config TARGET_P5040DS
bool "Support P5040DS"
select PHYS_64BIT
+ select ARCH_P5040
config TARGET_MPC8536DS
bool "Support MPC8536DS"
config ARCH_P5020
bool
+config ARCH_P5040
+ bool
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
obj-$(CONFIG_ARCH_P5020) += p5020_ids.o
-obj-$(CONFIG_PPC_P5040) += p5040_ids.o
+obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
obj-$(CONFIG_PPC_T4160) += t4240_ids.o
obj-$(CONFIG_PPC_T4080) += t4240_ids.o
obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o
-obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
+obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
serdes_corenet_t *srds2_regs;
#endif
int lane, bank, idx;
}
}
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
/*
* Lanes on bank 4 on P5040 are commented-out, but for some SERDES
* protocols, these lanes are routed to SATA. We use serdes_prtcl_map
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
-#elif defined(CONFIG_PPC_P5040)
+#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_SYS_PPC64
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#if defined(CONFIG_ARCH_P3041) || \
defined(CONFIG_ARCH_P4080) || \
defined(CONFIG_ARCH_P5020) || \
- defined(CONFIG_PPC_P5040) || \
+ defined(CONFIG_ARCH_P5040) || \
defined(CONFIG_ARCH_P2041)
#define CONFIG_FSL_TRUST_ARCH_v1
#endif
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_PPC_P5040)
+#if defined(CONFIG_ARCH_P5040)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
#define FIRST_PORT_ADDR 3
#define SECOND_PORT_ADDR 7
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
#define FIRST_PORT FM1_DTSEC5
#define SECOND_PORT FM2_DTSEC5
#else
fm_disable_port(i);
}
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
if (!IS_VALID_PORT(i))
fm_disable_port(i);
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,ARCH_P5040"
CONFIG_BOOTDELAY=10
CONFIG_CONSOLE_MUX=y
CONFIG_HUSH_PARSER=y
obj-$(CONFIG_ARCH_P3041) += p5020.o
obj-$(CONFIG_ARCH_P4080) += p4080.o
obj-$(CONFIG_ARCH_P5020) += p5020.o
-obj-$(CONFIG_PPC_P5040) += p5040.o
+obj-$(CONFIG_ARCH_P5040) += p5040.o
obj-$(CONFIG_PPC_T1040) += t1040.o
obj-$(CONFIG_PPC_T1042) += t1040.o
obj-$(CONFIG_PPC_T1020) += t1040.o
*
*/
#define CONFIG_P5040DS
-#define CONFIG_PPC_P5040
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_CYRUS
-#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_PPC_P5040)
+#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
#error Must call Cyrus CONFIG with a specific CPU enabled.
#endif
#if defined(CONFIG_ARCH_P5020)
#define CONFIG_SYS_CLK_FREQ 133000000
#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
-#elif defined(CONFIG_PPC_P5040)
+#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
#endif
CONFIG_PPC_B4420
CONFIG_PPC_B4860
CONFIG_PPC_CLUSTER_START
-CONFIG_PPC_P5040
CONFIG_PPC_SPINTABLE_COMPATIBLE
CONFIG_PPC_T1023
CONFIG_PPC_T1024