Add QC/A DRAM related reg defines, function prototypes and use defines from soc_commo...

diff --git a/u-boot/board/ar7240/common/common.c b/u-boot/board/ar7240/common/common.c
index b2aa70feb66760834d55fdecf42b3ebd9017196f..e572d25adc962baa45df44b851de8824564ec2d0 100644 (file)
--- a/u-boot/board/ar7240/common/common.c
+++ b/u-boot/board/ar7240/common/common.c
@@ -47,19 +47,19 @@ void print_board_info(void)
        printf("%" ALIGN_SIZE "s ", "RAM:");
        print_size(bd->bi_memsize, "");
 
-       switch (qca_mem_type()) {
-               case QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL:
-                       puts(" SDR\n");
-                       break;
-               case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL:
-                       puts(" DDR1\n");
-                       break;
-               case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL:
-                       puts(" DDR2\n");
-                       break;
-               default:
-                       puts("\n");
-                       break;
+       switch (qca_dram_type()) {
+       case RAM_MEMORY_TYPE_SDR:
+               puts(" SDR\n");
+               break;
+       case RAM_MEMORY_TYPE_DDR1:
+               puts(" DDR1\n");
+               break;
+       case RAM_MEMORY_TYPE_DDR2:
+               puts(" DDR2\n");
+               break;
+       default:
+               puts("\n");
+               break;
        }
 
        /* SPI NOR FLASH sizes and types */

diff --git a/u-boot/cpu/mips/ar7240/qca_common.c b/u-boot/cpu/mips/ar7240/qca_common.c
index 50116a7ef9d1a43e8ed6bddcfa83db636b3dcc09..791ff84a3f5f4b68b621219c86cb2f66af23b09c 100644 (file)
--- a/u-boot/cpu/mips/ar7240/qca_common.c
+++ b/u-boot/cpu/mips/ar7240/qca_common.c
@@ -26,10 +26,39 @@ inline u32 qca_xtal_is_40mhz(void)
 /*
  * Return memory type value from BOOT_STRAP register
  */
-inline u32 qca_mem_type(void)
+u32 qca_dram_type(void)
 {
-       return ((qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG) &
-                       QCA_RST_BOOTSTRAP_MEM_TYPE_MASK) >> QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT);
+#if defined(CONFIG_BOARD_CONST_DRAM_TYPE_SDR)
+       return RAM_MEMORY_TYPE_SDR;
+#elif defined(CONFIG_BOARD_CONST_DRAM_TYPE_DDR1)
+       return RAM_MEMORY_TYPE_DDR1;
+#elif defined(CONFIG_BOARD_CONST_DRAM_TYPE_DDR2)
+       return RAM_MEMORY_TYPE_DDR2;
+#else
+       static u32 dram_type = 0;
+
+       if (dram_type == 0) {
+               dram_type = ((qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG) &
+                                        QCA_RST_BOOTSTRAP_MEM_TYPE_MASK) >> QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT);
+
+               switch (dram_type) {
+               case QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL:
+                       dram_type = RAM_MEMORY_TYPE_SDR;
+                       break;
+               case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL:
+                       dram_type = RAM_MEMORY_TYPE_DDR1;
+                       break;
+               case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL:
+                       dram_type = RAM_MEMORY_TYPE_DDR2;
+                       break;
+               default:
+                       dram_type = RAM_MEMORY_TYPE_UNKNOWN;
+                       break;
+               }
+       }
+
+       return dram_type;
+#endif
 }
 
 /*

diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h
index 60010e79e16998fafb3dac786a3db8497abca68d..fc55f5abb525f925fda3abaf9e35d0e6bf8b6dc5 100644 (file)
--- a/u-boot/include/soc/qca_soc_common.h
+++ b/u-boot/include/soc/qca_soc_common.h
@@ -53,13 +53,15 @@
  */
 #define QCA_DDR_CFG_REG                                                        QCA_DDR_CTRL_BASE_REG + 0x000
 #define QCA_DDR_CFG2_REG                                               QCA_DDR_CTRL_BASE_REG + 0x004
-#define QCA_DDR_MODE_REG                                               QCA_DDR_CTRL_BASE_REG + 0x008
-#define QCA_DDR_EXTENDED_MODE_REG                              QCA_DDR_CTRL_BASE_REG + 0x00C
+#define QCA_DDR_MR_REG                                                 QCA_DDR_CTRL_BASE_REG + 0x008
+#define QCA_DDR_EMR_REG                                                        QCA_DDR_CTRL_BASE_REG + 0x00C
 #define QCA_DDR_CTRL_REG                                               QCA_DDR_CTRL_BASE_REG + 0x010
 #define QCA_DDR_REFRESH_REG                                            QCA_DDR_CTRL_BASE_REG + 0x014
 #define QCA_DDR_RD_DATA_THIS_CYCLE_REG                 QCA_DDR_CTRL_BASE_REG + 0x018
 #define QCA_DDR_TAP_CTRL_0_REG                                 QCA_DDR_CTRL_BASE_REG + 0x01C
 #define QCA_DDR_TAP_CTRL_1_REG                                 QCA_DDR_CTRL_BASE_REG + 0x020
+#define QCA_DDR_TAP_CTRL_2_REG                                 QCA_DDR_CTRL_BASE_REG + 0x024
+#define QCA_DDR_TAP_CTRL_3_REG                                 QCA_DDR_CTRL_BASE_REG + 0x028
 
 #if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_DDR_WB_FLUSH_GE0_REG                        QCA_DDR_CTRL_BASE_REG + 0x07C
@@ -100,6 +102,116 @@
        #define QCA_DDR_CFG3_REG                                        QCA_DDR_CTRL_BASE_REG + 0x15C
 #endif
 
+/*
+ * DDR registers BIT fields
+ */
+
+/* DDR_CONFIG register (DDR DRAM configuration) */
+#define QCA_DDR_CFG_TRAS_SHIFT                                 0
+#define QCA_DDR_CFG_TRAS_MASK                                  BITS(QCA_DDR_CFG_TRAS_SHIFT, 5)
+#define QCA_DDR_CFG_TRCD_SHIFT                                 5
+#define QCA_DDR_CFG_TRCD_MASK                                  BITS(QCA_DDR_CFG_TRCD_SHIFT, 4)
+#define QCA_DDR_CFG_TRP_SHIFT                                  9
+#define QCA_DDR_CFG_TRP_MASK                                   BITS(QCA_DDR_CFG_TRP_SHIFT, 4)
+#define QCA_DDR_CFG_TRRD_SHIFT                                 13
+#define QCA_DDR_CFG_TRRD_MASK                                  BITS(QCA_DDR_CFG_TRRD_SHIFT, 4)
+#define QCA_DDR_CFG_TRFC_SHIFT                                 17
+#define QCA_DDR_CFG_TRFC_MASK                                  BITS(QCA_DDR_CFG_TRFC_SHIFT, 6)
+#define QCA_DDR_CFG_TMRD_SHIFT                                 23
+#define QCA_DDR_CFG_TMRD_MASK                                  BITS(QCA_DDR_CFG_TMRD_SHIFT, 4)
+#define QCA_DDR_CFG_CAS_3LSB_SHIFT                             27
+#define QCA_DDR_CFG_CAS_3LSB_MASK                              BITS(QCA_DDR_CFG_CAS_3LSB_SHIFT, 3)
+#define QCA_DDR_CFG_OPEN_PAGE_SHIFT                            30
+#define QCA_DDR_CFG_OPEN_PAGE_MASK                             1 << QCA_DDR_CFG_OPEN_PAGE_SHIFT
+#define QCA_DDR_CFG_CAS_MSB_SHIFT                              31
+#define QCA_DDR_CFG_CAS_MSB_MASK                               1 << QCA_DDR_CFG_CAS_MSB_SHIFT
+
+/* DDR_CONFIG2 register (DDR DRAM configuration 2) */
+#define QCA_DDR_CFG2_BURST_LEN_SHIFT                   0
+#define QCA_DDR_CFG2_BURST_LEN_MASK                            BITS(QCA_DDR_CFG2_BURST_LEN_SHIFT, 4)
+#define QCA_DDR_CFG2_BURST_TYPE_SHIFT                  4
+#define QCA_DDR_CFG2_BURST_TYPE_MASK                   1 << QCA_DDR_CFG2_BURST_TYPE_SHIFT
+#define QCA_DDR_CFG2_CTRL_OE_EN_SHIFT                  5
+#define QCA_DDR_CFG2_CTRL_OE_EN_MASK                   1 << QCA_DDR_CFG2_CTRL_OE_EN_SHIFT
+#define QCA_DDR_CFG2_PHASE_SEL_SHIFT                   6
+#define QCA_DDR_CFG2_PHASE_SEL_MASK                            1 << QCA_DDR_CFG2_PHASE_SEL_SHIFT
+#define QCA_DDR_CFG2_CKE_SHIFT                                 7
+#define QCA_DDR_CFG2_CKE_MASK                                  1 << QCA_DDR_CFG2_CKE_SHIFT
+#define QCA_DDR_CFG2_TWR_SHIFT                                 8
+#define QCA_DDR_CFG2_TWR_MASK                                  BITS(QCA_DDR_CFG2_TWR_SHIFT, 4)
+#define QCA_DDR_CFG2_TRTW_SHIFT                                        12
+#define QCA_DDR_CFG2_TRTW_MASK                                 BITS(QCA_DDR_CFG2_TRTW_SHIFT, 5)
+#define QCA_DDR_CFG2_TRTP_SHIFT                                        17
+#define QCA_DDR_CFG2_TRTP_MASK                                 BITS(QCA_DDR_CFG2_TRTP_SHIFT, 4)
+#define QCA_DDR_CFG2_TWTR_SHIFT                                        21
+#define QCA_DDR_CFG2_TWTR_MASK                                 BITS(QCA_DDR_CFG2_TWTR_SHIFT, 5)
+#define QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT   26
+#define QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK            BITS(QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT, 4)
+#define QCA_DDR_CFG2_SWAP_A26_A27_SHIFT                        30
+#define QCA_DDR_CFG2_SWAP_A26_A27_MASK                 1 << QCA_DDR_CFG2_SWAP_A26_A27_SHIFT
+#define QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT              31
+#define QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK               1 << QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT
+
+/* DDR_MODE register (DDR mode register value) */
+#define QCA_DDR_MR_VALUE_SHIFT                                 0
+#define QCA_DDR_MR_VALUE_MASK                                  BITS(QCA_DDR_MR_VALUE_SHIFT, 14)
+
+
+/* DDR_EMR registers (DDR extended mode register 1/2/3 values) */
+#define QCA_DDR_EMR_VALUE_SHIFT                                        0
+#define QCA_DDR_EMR_VALUE_MASK                                 BITS(QCA_DDR_EMR_VALUE_SHIFT, 14)
+
+/* DDR_CONTROL register (DDR control) */
+#define QCA_DDR_CTRL_FORCE_MRS_SHIFT                   0
+#define QCA_DDR_CTRL_FORCE_MRS_MASK                            1 << QCA_DDR_CTRL_FORCE_MRS_SHIFT
+#define QCA_DDR_CTRL_FORCE_EMRS_SHIFT                  1
+#define QCA_DDR_CTRL_FORCE_EMRS_MASK                   1 << QCA_DDR_CTRL_FORCE_EMRS_SHIFT
+#define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT  2
+#define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK   1 << QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT
+#define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT 3
+#define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK  1 << QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT
+#define QCA_DDR_CTRL_FORCE_EMR2S_SHIFT                 4
+#define QCA_DDR_CTRL_FORCE_EMR2S_MASK                  1 << QCA_DDR_CTRL_FORCE_EMR2S_SHIFT
+#define QCA_DDR_CTRL_FORCE_EMR3S_SHIFT                 5
+#define QCA_DDR_CTRL_FORCE_EMR3S_MASK                  1 << QCA_DDR_CTRL_FORCE_EMR3S_SHIFT
+
+/* DDR_REFRESH register (DDR refresh control and configuration) */
+#define QCA_DDR_REFRESH_PERIOD_SHIFT                   0
+#define QCA_DDR_REFRESH_PERIOD_MASK                            BITS(QCA_DDR_REFRESH_PERIOD_SHIFT, 14)
+#define QCA_DDR_REFRESH_EN_SHIFT                               14
+#define QCA_DDR_REFRESH_EN_MASK                                        1 << QCA_DDR_REFRESH_EN_SHIFT
+
+/* DDR_RD_DATA_THIS_CYCLE register (DDR read data capture bit mask) */
+#define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT   0
+#define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_MASK            BITS(QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT, 32)
+
+/* TAP_CONTROL_X registers (DQS delay tap control for byte X) */
+#if (SOC_TYPE & QCA_AR933X_SOC) | \
+       (SOC_TYPE & QCA_AR934X_SOC)
+       #define QCA_DDR_TAP_CTRL_TAP_L_SHIFT            0
+       #define QCA_DDR_TAP_CTRL_TAP_L_MASK                     BITS(QCA_DDR_TAP_CTRL_TAP_L_SHIFT, 5)
+       #define QCA_DDR_TAP_CTRL_TAP_H_SHIFT            8
+       #define QCA_DDR_TAP_CTRL_TAP_H_MASK                     BITS(QCA_DDR_TAP_CTRL_TAP_H_SHIFT, 2)
+       #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT     16
+       #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_MASK      QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT
+#else
+       #define QCA_DDR_TAP_CTRL_TAP_SHIFT                      0
+       #define QCA_DDR_TAP_CTRL_TAP_MASK                       BITS(QCA_DDR_TAP_CTRL_TAP_SHIFT, 6)
+#endif
+
+/* DDR_DDR2_CONFIG register (DDR2 configuration) */
+#define QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT                 0
+#define QCA_DDR_DDR2_CFG_DDR2_EN_MASK                  1 << QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT
+#define QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT               2
+#define QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK                        BITS(QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT, 6)
+#if (SOC_TYPE & QCA_AR933X_SOC)
+       #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT         10
+       #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK          BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 3)
+#else
+       #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT         10
+       #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK          BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 4)
+#endif
+
 /*
  * Low-Speed UART registers
  */
@@ -468,7 +580,7 @@
        #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT   15
        #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_MASK    (1 << QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT)
        #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT   16
-       #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_MASK    BITS(QCA_GPIO_FUNC_2__SHIFT, 3)
+       #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_MASK    BITS(QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT, 3)
 #endif
 
 /*
@@ -1367,12 +1479,14 @@
 /* Magic flag for indication that PLL/clocks config is stored in FLASH */
 #define QCA_PLL_IN_FLASH_MAGIC         0x504C4C73
 
+/* Maximum DRAM size: 256 MB */
+#define QCA_DRAM_MAX_SIZE_VAL          (256 * 1024 * 1024)
+
 /*
  * Functions
  */
 #ifndef __ASSEMBLY__
 inline u32 qca_xtal_is_40mhz(void);
-inline u32 qca_mem_type(void);
 void   qca_soc_name_rev(char *buf);
 void   qca_full_chip_reset(void);
 void   qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk, u32 *spi_clk, u32 *ref_clk);
@@ -1381,6 +1495,9 @@ void   qca_sf_write_page(u32 bank, u32 address, u32 length, u8 *data);
 u32    qca_sf_sect_erase(u32 bank, u32 address, u32 sect_size, u8 erase_cmd);
 u32    qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_cmd);
 u32    qca_sf_jedec_id(u32 bank);
+u32    qca_dram_type(void);
+u32    qca_dram_size(void);
+void   qca_dram_init(void);
 #endif /* !__ASSEMBLY__ */
 
 /*