qe: add u-qe support to arm board
authorZhao Qiang <B45475@freescale.com>
Thu, 25 Sep 2014 05:52:25 +0000 (13:52 +0800)
committerYork Sun <yorksun@freescale.com>
Wed, 19 Nov 2014 20:55:45 +0000 (12:55 -0800)
ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
[York Sun: Fix compiling error caused by u_qe_init()]
Reviewed-by: York Sun <yorksun@freescale.com>
arch/arm/include/asm/arch-ls102xa/config.h
arch/arm/include/asm/global_data.h
drivers/Makefile
drivers/qe/Makefile
drivers/qe/fdt.c
drivers/qe/qe.c
drivers/qe/qe.h

index f2c9687df42cb9da9cc480cc0d35b5255a400c9e..fc6a4755f01c9be6808881c8664dcaa7fd6dbcad 100644 (file)
 
 #define DCU_LAYER_MAX_NUM                      16
 
+#define QE_MURAM_SIZE          0x6000UL
+#define MAX_QE_RISC            1
+#define QE_NUM_OF_SNUM         28
+
 #define CONFIG_SYS_FSL_SRDS_1
 
 #ifdef CONFIG_LS102XA
index c69d0646f58099caf2e9f664bcaf0ce4cc30fe7e..438f128326a67a6c5237df32a0f392efdabee1c7 100644 (file)
@@ -17,6 +17,14 @@ struct arch_global_data {
 #if defined(CONFIG_FSL_ESDHC)
        u32 sdhc_clk;
 #endif
+
+#if defined(CONFIG_U_QE)
+       u32 qe_clk;
+       u32 brg_clk;
+       uint mp_alloc_base;
+       uint mp_alloc_top;
+#endif /* CONFIG_U_QE */
+
 #ifdef CONFIG_AT91FAMILY
        /* "static data" needed by at91's clock.c */
        unsigned long   cpu_clk_rate_hz;
index 33227c8bd6de003d170962e7f7778ed1b091c460..3c96524de6336854347b5db2e255cb2e6198f7cb 100644 (file)
@@ -16,6 +16,7 @@ obj-y += twserial/
 obj-y += video/
 obj-y += watchdog/
 obj-$(CONFIG_QE) += qe/
+obj-$(CONFIG_U_QE) += qe/
 obj-y += memory/
 obj-y += pwm/
 obj-y += input/
index 7f1bd06922f4995b446581713c589d5b30ba670f..8fa48667ec7153d67a409f568f81c77e485c6b62 100644 (file)
@@ -4,5 +4,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y := qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_U_QE) += qe.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
index d9a7d8206ffa8e2a9304b028f0d9c19093d3337d..dfae4bf64defd63349833462d878027294e06afe 100644 (file)
@@ -12,6 +12,7 @@
 #include <fdt_support.h>
 #include "qe.h"
 
+#ifdef CONFIG_QE
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -72,3 +73,4 @@ void ft_qe_setup(void *blob)
                "clock-frequency", gd->arch.qe_clk / 2, 1);
        fdt_fixup_qe_firmware(blob);
 }
+#endif
index 4358a91adb5300911753416852654b63a1cc6faf..b545ec9df3f3851f2819f4ef029891f0fb09d628 100644 (file)
@@ -40,6 +40,7 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
        return;
 }
 
+#ifdef CONFIG_QE
 uint qe_muram_alloc(uint size, uint align)
 {
        uint    retloc;
@@ -70,6 +71,7 @@ uint qe_muram_alloc(uint size, uint align)
 
        return retloc;
 }
+#endif
 
 void *qe_muram_addr(uint offset)
 {
@@ -180,6 +182,17 @@ void qe_init(uint qe_base)
        qe_snums_init();
 }
 
+#ifdef CONFIG_U_QE
+void u_qe_init(void)
+{
+       uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */
+       qe_immr = (qe_map_t *)qe_base;
+
+       qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
+       out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+}
+#endif
+
 void qe_reset(void)
 {
        qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
@@ -212,6 +225,7 @@ void qe_assign_page(uint snum, uint para_ram_base)
 
 #define BRG_CLK                (gd->arch.brg_clk)
 
+#ifdef CONFIG_QE
 int qe_set_brg(uint brg, uint rate)
 {
        volatile uint   *bp;
@@ -239,6 +253,7 @@ int qe_set_brg(uint brg, uint rate)
 
        return 0;
 }
+#endif
 
 /* Set ethernet MII clock master
 */
index ebb7c5f12463239476167299e47756b88cbf2387..30484b8504e23aa3110ee2c2423b6bdf3018f27a 100644 (file)
@@ -275,6 +275,7 @@ void *qe_muram_addr(uint offset);
 int qe_get_snum(void);
 void qe_put_snum(u8 snum);
 void qe_init(uint qe_base);
+void u_qe_init(void);
 void qe_reset(void);
 void qe_assign_page(uint snum, uint para_ram_base);
 int qe_set_brg(uint brg, uint rate);