board: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not defined
authorYork Sun <york.sun@nxp.com>
Thu, 26 May 2016 20:59:03 +0000 (13:59 -0700)
committerYork Sun <york.sun@nxp.com>
Fri, 3 Jun 2016 21:12:48 +0000 (14:12 -0700)
U-Boot should continue to work without management complex (MC).
Fix compiling errors and warnings.

Signed-off-by: York Sun <york.sun@nxp.com>
board/freescale/ls2080aqds/ls2080aqds.c
board/freescale/ls2080ardb/ls2080ardb.c

index b3bd40afb77407d09c4a9f54d6b0428ad02ddbe3..897793d85b7db6dac3348e2e87245e6323010629 100644 (file)
@@ -282,7 +282,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
        int err;
+#endif
        u64 base[CONFIG_NR_DRAM_BANKS];
        u64 size[CONFIG_NR_DRAM_BANKS];
 
index fb39af64452f6a2edd743da2839edc009e10e4a6..52e5e3f516d341da0bc7b70e1093aa3d2f2044b0 100644 (file)
@@ -156,7 +156,9 @@ int board_init(void)
 {
        char *env_hwconfig;
        u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+#ifdef CONFIG_FSL_MC_ENET
        u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
        u32 val;
 
        init_final_memctl_regs();
@@ -178,8 +180,10 @@ int board_init(void)
 
        QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 
+#ifdef CONFIG_FSL_MC_ENET
        /* invert AQR405 IRQ pins polarity */
        out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+#endif
 
        return 0;
 }
@@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
        int err;
+#endif
        u64 base[CONFIG_NR_DRAM_BANKS];
        u64 size[CONFIG_NR_DRAM_BANKS];