Cosmetic: adjust PLL header files for tab size of 8

author Piotr Dymacz <pepe2k@gmail.com>

Thu, 17 Nov 2016 19:50:59 +0000 (20:50 +0100)

committer Piotr Dymacz <pepe2k@gmail.com>

Thu, 17 Nov 2016 19:50:59 +0000 (20:50 +0100)
author Piotr Dymacz <pepe2k@gmail.com>
Thu, 17 Nov 2016 19:50:59 +0000 (20:50 +0100)
committer Piotr Dymacz <pepe2k@gmail.com>
Thu, 17 Nov 2016 19:50:59 +0000 (20:50 +0100)
diff --git a/u-boot/include/soc/ar933x_pll_init.h b/u-boot/include/soc/ar933x_pll_init.h

index 657a0d46aab0127648dc0aa87874505c427cfc43..062708f7e91e4be6ac998f53694d2be4e725607f 100644 (file)
--- a/u-boot/include/soc/ar933x_pll_init.h
+++ b/u-boot/include/soc/ar933x_pll_init.h
@@ -15,318 +15,318 @@
  
  /* CPU_PLL_CONFIG */
  #define _ar933x_cpu_pll_cfg_reg_val(_nint,   \
-                                                                       _refdiv, \
-                                                                       _range,  \
-                                                                       _outdiv) \
-                                                                                        \
-               ((_nint   << QCA_PLL_CPU_PLL_CFG_NINT_SHIFT)   & QCA_PLL_CPU_PLL_CFG_NINT_MASK)   |\
-               ((_refdiv << QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK) |\
-               ((_range  << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)  & QCA_PLL_CPU_PLL_CFG_RANGE_MASK)  |\
-               ((_outdiv << QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK)
+                                   _refdiv, \
+                                   _range,  \
+                                   _outdiv) \
+                                            \
+       ((_nint   << QCA_PLL_CPU_PLL_CFG_NINT_SHIFT)   & QCA_PLL_CPU_PLL_CFG_NINT_MASK)   |\
+       ((_refdiv << QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK) |\
+       ((_range  << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)  & QCA_PLL_CPU_PLL_CFG_RANGE_MASK)  |\
+       ((_outdiv << QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK)
  
  /* CPU_CLOCK_CONTROL */
  #define _ar933x_cpu_clk_ctrl_reg_val(_cpudiv, \
-                                                                        _ddrdiv, \
-                                                                        _ahbdiv) \
-                                                                                         \
-               (((_cpudiv - 1) << QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT) &\
-                QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK) |\
-               (((_ddrdiv - 1) << QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT) &\
-                QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK) |\
-               (((_ahbdiv - 1) << QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT) &\
-                QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK)
+                                    _ddrdiv, \
+                                    _ahbdiv) \
+                                             \
+       (((_cpudiv - 1) << QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT) &\
+        QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK) |\
+       (((_ddrdiv - 1) << QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT) &\
+        QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK) |\
+       (((_ahbdiv - 1) << QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT) &\
+        QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK)
  
  /* PLL_DITHER_FRAC */
  #define _ar933x_cpu_pll_dither_frac_reg_val(_nfracmin) \
-               ((_nfracmin << QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT) &\
-                QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK)
+       ((_nfracmin << QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT) &\
+        QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK)
  
  /* SPI_CONTROL_ADDR */
  #define _ar933x_spi_ctrl_addr_reg_val(_clk_div,   \
-                                                                         _remap_dis, \
-                                                                         _reloc_spi) \
-                                                                                                 \
-               ((((_clk_div / 2) - 1) << QCA_SPI_CTRL_CLK_DIV_SHIFT) & QCA_SPI_CTRL_CLK_DIV_MASK) |\
-               ((_remap_dis << QCA_SPI_CTRL_REMAP_DIS_SHIFT)    & QCA_SPI_CTRL_REMAP_DIS_MASK)    |\
-               ((_reloc_spi << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) & QCA_SPI_CTRL_SPI_RELOCATE_MASK)
+                                     _remap_dis, \
+                                     _reloc_spi) \
+                                                 \
+       ((((_clk_div / 2) - 1) << QCA_SPI_CTRL_CLK_DIV_SHIFT) & QCA_SPI_CTRL_CLK_DIV_MASK) |\
+       ((_remap_dis << QCA_SPI_CTRL_REMAP_DIS_SHIFT)    & QCA_SPI_CTRL_REMAP_DIS_MASK)    |\
+       ((_reloc_spi << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) & QCA_SPI_CTRL_SPI_RELOCATE_MASK)
  
  /*
   * =============================
   * PLL configuration preset list
   * =============================
   */
-#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50)              /* Tested! */
+#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50)      /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(10, 1, 1, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(10, 1, 1, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
  
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80)            /* Tested! */
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80)    /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(16, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(16, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(17, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(17, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_410_410_205)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(820)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_420_420_210)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(33, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(33, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_430_430_215)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(34, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(34, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(410)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_440_440_220)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(35, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(35, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(205)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(22, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(22, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_450_450_225)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(45, 2, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(45, 2, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_460_460_230)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(820)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_470_470_235)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(37, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(37, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_480_480_240)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(38, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(38, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(410)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_490_490_245)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(39, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(39, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(205)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_510_510_255)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(820)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_520_520_260)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(41, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(41, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_530_265_132)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(42, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(42, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(410)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_540_270_135)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(43, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(43, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(205)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_275_137)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_560_280_140)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(820)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_570_285_142)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(45, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(45, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_580_290_145)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(46, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(46, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(410)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(29, 1, 0, 1)
-       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(29, 1, 0, 1)
+       #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
  
  #else
         #error "QCA PLL configuration not supported or not selected!"
@@ -336,15 +336,15 @@
   * Safe configuration, used in "O/C recovery" mode:
   * CPU/DDR/AHB/SPI: 400/400/200/20
   */
-#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25                                _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
-#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL25                       _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25                        _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
+#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL25               _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL25                _ar933x_cpu_pll_dither_frac_reg_val(0)
  
-#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40                                _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
-#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL40                       _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40                        _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
+#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL40               _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
  #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL40                _ar933x_cpu_pll_dither_frac_reg_val(0)
  
-#define QCA_SPI_CTRL_REG_VAL_SAFE                                                      _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+#define QCA_SPI_CTRL_REG_VAL_SAFE                              _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
  
  /*
   * Default values (if not defined above)
@@ -352,21 +352,21 @@
  
  /* Maximum clock for SPI NOR FLASH */
  #ifndef CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ
-       #define CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ    30
+       #define CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ            30
  #endif
  
  /* SPI_CONTROL_ADDR register value */
  #ifndef QCA_SPI_CTRL_REG_VAL
-       #define QCA_SPI_CTRL_REG_VAL                                    _ar933x_spi_ctrl_addr_reg_val(8, 1, 0)
+       #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(8, 1, 0)
  #endif
  
  /* CPU PLL dither register values */
  #ifndef QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25
-       #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25              _ar933x_cpu_pll_dither_frac_reg_val(0)
+       #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(0)
  #endif
  
  #ifndef QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40
-       #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40              _ar933x_cpu_pll_dither_frac_reg_val(0)
+       #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(0)
  #endif
  
  /* CPU PLL settle time */
diff --git a/u-boot/include/soc/qca95xx_pll_init.h b/u-boot/include/soc/qca95xx_pll_init.h

index 87c82ecf377317a8d914bf8db349ebe9bb5ab10f..5d9197b25ec390e7bdae81edef67852d99b105c6 100644 (file)
--- a/u-boot/include/soc/qca95xx_pll_init.h
+++ b/u-boot/include/soc/qca95xx_pll_init.h
@@ -15,1218 +15,1218 @@
  
  /* CPU_PLL_CONFIG */
  #define _qca95xx_cpu_pll_cfg_reg_val(_nint,   \
-                                                                        _refdiv, \
-                                                                        _range,  \
-                                                                        _outdiv, \
-                                                                        _dis)    \
-                                                                                         \
-               ((_nint   << QCA_PLL_CPU_PLL_CFG_NINT_SHIFT)   & QCA_PLL_CPU_PLL_CFG_NINT_MASK)   |\
-               ((_refdiv << QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK) |\
-               ((_range  << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)  & QCA_PLL_CPU_PLL_CFG_RANGE_MASK)  |\
-               ((_outdiv << QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK) |\
-               ((_dis    << QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT) & QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK)
+                                    _refdiv, \
+                                    _range,  \
+                                    _outdiv, \
+                                    _dis)    \
+                                             \
+       ((_nint   << QCA_PLL_CPU_PLL_CFG_NINT_SHIFT)   & QCA_PLL_CPU_PLL_CFG_NINT_MASK)   |\
+       ((_refdiv << QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK) |\
+       ((_range  << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)  & QCA_PLL_CPU_PLL_CFG_RANGE_MASK)  |\
+       ((_outdiv << QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK) |\
+       ((_dis    << QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT) & QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK)
  
  /* DDR_PLL_CONFIG */
  #define _qca95xx_ddr_pll_cfg_reg_val(_nint,   \
-                                                                        _refdiv, \
-                                                                        _range,  \
-                                                                        _outdiv, \
-                                                                        _dis)    \
-                                                                                         \
-               ((_nint   << QCA_PLL_DDR_PLL_CFG_NINT_SHIFT)   & QCA_PLL_DDR_PLL_CFG_NINT_MASK)   |\
-               ((_refdiv << QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_DDR_PLL_CFG_REFDIV_MASK) |\
-               ((_range  << QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT)  & QCA_PLL_DDR_PLL_CFG_RANGE_MASK)  |\
-               ((_outdiv << QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK) |\
-               ((_dis    << QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT) & QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK)
+                                    _refdiv, \
+                                    _range,  \
+                                    _outdiv, \
+                                    _dis)    \
+                                             \
+       ((_nint   << QCA_PLL_DDR_PLL_CFG_NINT_SHIFT)   & QCA_PLL_DDR_PLL_CFG_NINT_MASK)   |\
+       ((_refdiv << QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_DDR_PLL_CFG_REFDIV_MASK) |\
+       ((_range  << QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT)  & QCA_PLL_DDR_PLL_CFG_RANGE_MASK)  |\
+       ((_outdiv << QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK) |\
+       ((_dis    << QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT) & QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK)
  
  /* CPU_DDR_CLOCK_CONTROL */
  #define _qca95xx_cpu_ddr_clk_ctrl_reg_val(_cpudiv,          \
-                                                                                 _ddrdiv,          \
-                                                                                 _ahbdiv,          \
-                                                                                 _cpu_from_cpupll, \
-                                                                                 _ddr_from_ddrpll, \
-                                                                                 _ahb_from_ddrpll) \
-                                                                                                                       \
-               (((_cpudiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &\
-                QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) |\
-               (((_ddrdiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &\
-                QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) |\
-               (((_ahbdiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &\
-                QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) |\
-               ((_cpu_from_cpupll << QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT) &\
-                QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK) |\
-               ((_ddr_from_ddrpll << QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT) &\
-                QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK) |\
-               ((_ahb_from_ddrpll << QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT) &\
-                QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK)
+                                         _ddrdiv,          \
+                                         _ahbdiv,          \
+                                         _cpu_from_cpupll, \
+                                         _ddr_from_ddrpll, \
+                                         _ahb_from_ddrpll) \
+                                                           \
+       (((_cpudiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &\
+        QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) |\
+       (((_ddrdiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &\
+        QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) |\
+       (((_ahbdiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &\
+        QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) |\
+       ((_cpu_from_cpupll << QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT) &\
+        QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK) |\
+       ((_ddr_from_ddrpll << QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT) &\
+        QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK) |\
+       ((_ahb_from_ddrpll << QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT) &\
+        QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK)
  
  /* CPU/DDR_PLL_DITHER */
  #define _qca95xx_cpu_pll_dither_reg_val(_nfracmin)     \
-               ((_nfracmin << QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT) &\
-                QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK)
+       ((_nfracmin << QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT) &\
+        QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK)
  
  #define _qca95xx_ddr_pll_dither_reg_val(_nfracmin)     \
-               ((_nfracmin << QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT) &\
-                QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK)
+       ((_nfracmin << QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT) &\
+        QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK)
  
  /* SPI_CONTROL_ADDR */
  #define _qca95xx_spi_ctrl_addr_reg_val(_clk_div,   \
-                                                                          _remap_dis, \
-                                                                          _reloc_spi, \
-                                                                          _tshsl_cnt) \
-                                                                                                  \
-               ((((_clk_div / 2) - 1) << QCA_SPI_CTRL_CLK_DIV_SHIFT) & QCA_SPI_CTRL_CLK_DIV_MASK) |\
-               ((_remap_dis << QCA_SPI_CTRL_REMAP_DIS_SHIFT)    & QCA_SPI_CTRL_REMAP_DIS_MASK)    |\
-               ((_reloc_spi << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) & QCA_SPI_CTRL_SPI_RELOCATE_MASK) |\
-               ((_tshsl_cnt << QCA_SPI_CTRL_TSHSL_CNT_SHIFT)    & QCA_SPI_CTRL_TSHSL_CNT_MASK)
+                                      _remap_dis, \
+                                      _reloc_spi, \
+                                      _tshsl_cnt) \
+                                                  \
+       ((((_clk_div / 2) - 1) << QCA_SPI_CTRL_CLK_DIV_SHIFT) & QCA_SPI_CTRL_CLK_DIV_MASK) |\
+       ((_remap_dis << QCA_SPI_CTRL_REMAP_DIS_SHIFT)    & QCA_SPI_CTRL_REMAP_DIS_MASK)    |\
+       ((_reloc_spi << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) & QCA_SPI_CTRL_SPI_RELOCATE_MASK) |\
+       ((_tshsl_cnt << QCA_SPI_CTRL_TSHSL_CNT_SHIFT)    & QCA_SPI_CTRL_TSHSL_CNT_MASK)
  
  /*
   * =============================
   * PLL configuration preset list
   * =============================
   */
-#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100)             /* Tested! */
+#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100)     /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(28, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(28, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(35, 2, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(35, 2, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(25, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(25, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40           _qca95xx_cpu_pll_dither_reg_val(16)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1)
  
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80)            /* Tested! */
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80)    /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 1, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(26, 1, 0, 1, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 1, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(26, 1, 0, 1, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 1, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 1, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 1, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 1, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
  
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_170_170_85)            /* Tested! */
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_170_170_85)    /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(34, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(34, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(34, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(34, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 5, 10, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(17, 1, 0, 1, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(17, 1, 0, 1, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(17, 1, 0, 1, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(17, 1, 0, 1, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
  
-#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_180_180_90)            /* Tested! */
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_180_180_90)    /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 1, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 1, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 1, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 1, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(14, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(14, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(35, 4, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(35, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(35, 4, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(35, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_360_360_180)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_380_380_190)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(13)
         #define QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_ddr_pll_dither_reg_val(205)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(19, 1, 0, 1, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 1, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(19, 1, 0, 1, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 1, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(6,  1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(6,  1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_250)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_250)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_275)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 0)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_375_250)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(30, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(30, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_400_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_560_450_225)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(26)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_250)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_225)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_250)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_275)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_250)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_150)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_300)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_155)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_310)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_100)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_155)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_166)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_206)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_250)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_310)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_cpu_pll_dither_reg_val(52)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
  
-       #define QCA_SPI_CTRL_REG_VAL                                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                            _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_400_200)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40           _qca95xx_cpu_pll_dither_reg_val(16)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_420_210)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
         #define QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25           _qca95xx_ddr_pll_dither_reg_val(820)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(42, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(42, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40           _qca95xx_cpu_pll_dither_reg_val(16)
  
  #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_450_225)   /* Tested! */
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25                      _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25              _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
  
-       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0)
-       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40                      _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+       #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0)
+       #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40              _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
         #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40         _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
         #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40           _qca95xx_cpu_pll_dither_reg_val(16)
  
@@ -1238,19 +1238,19 @@
   * Safe configuration, used in "O/C recovery" mode:
   * CPU/DDR/AHB/SPI: 400/400/200/20
   */
-#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25                        _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
-#define QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL25                        _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25                _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+#define QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL25                _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
  #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_SAFE_XTAL25   _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL25             _qca95xx_cpu_pll_dither_reg_val(0)
-#define QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL25             _qca95xx_ddr_pll_dither_reg_val(0)
+#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL25     _qca95xx_cpu_pll_dither_reg_val(0)
+#define QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL25     _qca95xx_ddr_pll_dither_reg_val(0)
  
-#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40                        _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
-#define QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL40                        _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40                _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+#define QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL40                _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
  #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_SAFE_XTAL40   _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
-#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL40             _qca95xx_cpu_pll_dither_reg_val(0)
-#define QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL40             _qca95xx_ddr_pll_dither_reg_val(0)
+#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL40     _qca95xx_cpu_pll_dither_reg_val(0)
+#define QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL40     _qca95xx_ddr_pll_dither_reg_val(0)
  
-#define QCA_SPI_CTRL_REG_VAL_SAFE                                              _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+#define QCA_SPI_CTRL_REG_VAL_SAFE                      _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
  
  /*
   * Default values (if not defined above)
@@ -1263,7 +1263,7 @@
  
  /* SPI_CONTROL_ADDR register value */
  #ifndef QCA_SPI_CTRL_REG_VAL
-       #define QCA_SPI_CTRL_REG_VAL                                    _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2)
+       #define QCA_SPI_CTRL_REG_VAL                    _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2)
  #endif
  
  /* CPU PLL dither register values */
diff --git a/u-boot/include/soc/qca_pll_list.h b/u-boot/include/soc/qca_pll_list.h

index fe4c7aef0e61900a6a50f1940367d6be010826be..30c220b02dc63ffe280bfef2f6f98c588ee7541e 100644 (file)
--- a/u-boot/include/soc/qca_pll_list.h
+++ b/u-boot/include/soc/qca_pll_list.h
@@ -9,147 +9,147 @@
  #ifndef _QCA_PLL_LIST_H_
  #define _QCA_PLL_LIST_H_
  
-#define QCA_PLL_PRESET_25_25_12                        1
-#define QCA_PLL_PRESET_25_25_25                        2
-#define QCA_PLL_PRESET_50_50_25                        3
-#define QCA_PLL_PRESET_50_50_50                        4
-#define QCA_PLL_PRESET_75_75_25                        5
-#define QCA_PLL_PRESET_75_75_50                        6
-#define QCA_PLL_PRESET_75_75_75                        7
-#define QCA_PLL_PRESET_100_100_25              8
-#define QCA_PLL_PRESET_100_100_50              9
-#define QCA_PLL_PRESET_100_100_100             10
-#define QCA_PLL_PRESET_125_50_25               11
-#define QCA_PLL_PRESET_125_50_50               12
-#define QCA_PLL_PRESET_125_62_25               13
-#define QCA_PLL_PRESET_125_62_50               14
-#define QCA_PLL_PRESET_125_62_62               15
-#define QCA_PLL_PRESET_125_100_25              16
-#define QCA_PLL_PRESET_125_100_50              17
-#define QCA_PLL_PRESET_125_100_62              18
-#define QCA_PLL_PRESET_125_100_100             19
-#define QCA_PLL_PRESET_150_150_75              20
-#define QCA_PLL_PRESET_150_150_100             21
-#define QCA_PLL_PRESET_150_150_150             22
-#define QCA_PLL_PRESET_160_160_80              23
-#define QCA_PLL_PRESET_170_170_85              24
-#define QCA_PLL_PRESET_180_180_90              25
-#define QCA_PLL_PRESET_200_200_100             26
-#define QCA_PLL_PRESET_200_200_150             27
-#define QCA_PLL_PRESET_200_200_200             28
-#define QCA_PLL_PRESET_300_200_100             29
-#define QCA_PLL_PRESET_300_200_150             30
-#define QCA_PLL_PRESET_300_200_200             31
-#define QCA_PLL_PRESET_300_300_100             32
-#define QCA_PLL_PRESET_300_300_150             33
-#define QCA_PLL_PRESET_300_300_200             34
-#define QCA_PLL_PRESET_350_350_175             35
-#define QCA_PLL_PRESET_360_360_180             36
-#define QCA_PLL_PRESET_380_380_190             37
-#define QCA_PLL_PRESET_400_200_100             38
-#define QCA_PLL_PRESET_400_200_150             39
-#define QCA_PLL_PRESET_400_200_200             40
-#define QCA_PLL_PRESET_400_300_100             41
-#define QCA_PLL_PRESET_400_300_150             42
-#define QCA_PLL_PRESET_400_300_200             43
-#define QCA_PLL_PRESET_400_300_300             44
-#define QCA_PLL_PRESET_400_400_200             45
-#define QCA_PLL_PRESET_400_400_300             46
-#define QCA_PLL_PRESET_410_410_205             47
-#define QCA_PLL_PRESET_420_420_210             48
-#define QCA_PLL_PRESET_430_430_215             49
-#define QCA_PLL_PRESET_440_440_220             50
-#define QCA_PLL_PRESET_450_450_225             51
-#define QCA_PLL_PRESET_460_460_230             52
-#define QCA_PLL_PRESET_470_470_235             53
-#define QCA_PLL_PRESET_480_480_240             54
-#define QCA_PLL_PRESET_490_490_245             55
-#define QCA_PLL_PRESET_500_200_100             56
-#define QCA_PLL_PRESET_500_200_150             57
-#define QCA_PLL_PRESET_500_200_200             58
-#define QCA_PLL_PRESET_500_300_100             59
-#define QCA_PLL_PRESET_500_300_150             60
-#define QCA_PLL_PRESET_500_300_200             61
-#define QCA_PLL_PRESET_500_300_250             62
-#define QCA_PLL_PRESET_500_300_300             63
-#define QCA_PLL_PRESET_500_400_100             64
-#define QCA_PLL_PRESET_500_400_200             65
-#define QCA_PLL_PRESET_500_400_250             66
-#define QCA_PLL_PRESET_500_500_100             67
-#define QCA_PLL_PRESET_500_500_150             68
-#define QCA_PLL_PRESET_500_500_200             69
-#define QCA_PLL_PRESET_500_500_250             70
-#define QCA_PLL_PRESET_500_500_300             71
-#define QCA_PLL_PRESET_510_510_255             72
-#define QCA_PLL_PRESET_520_520_260             73
-#define QCA_PLL_PRESET_530_265_132             74
-#define QCA_PLL_PRESET_540_275_135             75
-#define QCA_PLL_PRESET_550_200_100             76
-#define QCA_PLL_PRESET_550_200_150             77
-#define QCA_PLL_PRESET_550_200_200             78
-#define QCA_PLL_PRESET_550_275_137             79
-#define QCA_PLL_PRESET_550_300_100             80
-#define QCA_PLL_PRESET_550_300_150             81
-#define QCA_PLL_PRESET_550_300_200             82
-#define QCA_PLL_PRESET_550_300_275             83
-#define QCA_PLL_PRESET_550_300_300             84
-#define QCA_PLL_PRESET_550_375_250             85
-#define QCA_PLL_PRESET_550_400_200             86
-#define QCA_PLL_PRESET_560_280_140             87
-#define QCA_PLL_PRESET_560_450_225             88
-#define QCA_PLL_PRESET_570_285_142             89
-#define QCA_PLL_PRESET_580_290_145             90
-#define QCA_PLL_PRESET_600_200_100             91
-#define QCA_PLL_PRESET_600_200_150             92
-#define QCA_PLL_PRESET_600_200_200             93
-#define QCA_PLL_PRESET_600_300_100             94
-#define QCA_PLL_PRESET_600_300_150             95
-#define QCA_PLL_PRESET_600_300_200             96
-#define QCA_PLL_PRESET_600_300_250             97
-#define QCA_PLL_PRESET_600_300_300             98
-#define QCA_PLL_PRESET_600_400_100             99
-#define QCA_PLL_PRESET_600_400_150             100
-#define QCA_PLL_PRESET_600_400_200             101
-#define QCA_PLL_PRESET_600_400_300             102
-#define QCA_PLL_PRESET_600_450_100             103
-#define QCA_PLL_PRESET_600_450_150             104
-#define QCA_PLL_PRESET_600_450_200             105
-#define QCA_PLL_PRESET_600_450_225             106
-#define QCA_PLL_PRESET_600_450_300             107
-#define QCA_PLL_PRESET_600_500_100             108
-#define QCA_PLL_PRESET_600_500_150             109
-#define QCA_PLL_PRESET_600_500_200             110
-#define QCA_PLL_PRESET_600_500_250             111
-#define QCA_PLL_PRESET_600_500_300             112
-#define QCA_PLL_PRESET_600_550_100             113
-#define QCA_PLL_PRESET_600_550_150             114
-#define QCA_PLL_PRESET_600_550_200             115
-#define QCA_PLL_PRESET_600_550_275             116
-#define QCA_PLL_PRESET_600_550_300             117
-#define QCA_PLL_PRESET_600_600_100             118
-#define QCA_PLL_PRESET_600_600_150             119
-#define QCA_PLL_PRESET_600_600_200             120
-#define QCA_PLL_PRESET_600_600_250             121
-#define QCA_PLL_PRESET_600_600_300             122
-#define QCA_PLL_PRESET_620_200_100             123
-#define QCA_PLL_PRESET_620_200_150             124
-#define QCA_PLL_PRESET_620_200_200             125
-#define QCA_PLL_PRESET_620_300_100             126
-#define QCA_PLL_PRESET_620_300_150             127
-#define QCA_PLL_PRESET_620_300_200             128
-#define QCA_PLL_PRESET_620_300_300             129
-#define QCA_PLL_PRESET_620_400_100             130
-#define QCA_PLL_PRESET_620_400_155             131
-#define QCA_PLL_PRESET_620_400_200             132
-#define QCA_PLL_PRESET_620_400_310             133
-#define QCA_PLL_PRESET_620_500_100             134
-#define QCA_PLL_PRESET_620_500_155             135
-#define QCA_PLL_PRESET_620_500_166             136
-#define QCA_PLL_PRESET_620_500_206             137
-#define QCA_PLL_PRESET_620_500_250             138
-#define QCA_PLL_PRESET_620_500_310             139
-#define QCA_PLL_PRESET_650_400_200             140
-#define QCA_PLL_PRESET_650_420_210             141
-#define QCA_PLL_PRESET_650_450_225             142
+#define QCA_PLL_PRESET_25_25_12                1
+#define QCA_PLL_PRESET_25_25_25                2
+#define QCA_PLL_PRESET_50_50_25                3
+#define QCA_PLL_PRESET_50_50_50                4
+#define QCA_PLL_PRESET_75_75_25                5
+#define QCA_PLL_PRESET_75_75_50                6
+#define QCA_PLL_PRESET_75_75_75                7
+#define QCA_PLL_PRESET_100_100_25      8
+#define QCA_PLL_PRESET_100_100_50      9
+#define QCA_PLL_PRESET_100_100_100     10
+#define QCA_PLL_PRESET_125_50_25       11
+#define QCA_PLL_PRESET_125_50_50       12
+#define QCA_PLL_PRESET_125_62_25       13
+#define QCA_PLL_PRESET_125_62_50       14
+#define QCA_PLL_PRESET_125_62_62       15
+#define QCA_PLL_PRESET_125_100_25      16
+#define QCA_PLL_PRESET_125_100_50      17
+#define QCA_PLL_PRESET_125_100_62      18
+#define QCA_PLL_PRESET_125_100_100     19
+#define QCA_PLL_PRESET_150_150_75      20
+#define QCA_PLL_PRESET_150_150_100     21
+#define QCA_PLL_PRESET_150_150_150     22
+#define QCA_PLL_PRESET_160_160_80      23
+#define QCA_PLL_PRESET_170_170_85      24
+#define QCA_PLL_PRESET_180_180_90      25
+#define QCA_PLL_PRESET_200_200_100     26
+#define QCA_PLL_PRESET_200_200_150     27
+#define QCA_PLL_PRESET_200_200_200     28
+#define QCA_PLL_PRESET_300_200_100     29
+#define QCA_PLL_PRESET_300_200_150     30
+#define QCA_PLL_PRESET_300_200_200     31
+#define QCA_PLL_PRESET_300_300_100     32
+#define QCA_PLL_PRESET_300_300_150     33
+#define QCA_PLL_PRESET_300_300_200     34
+#define QCA_PLL_PRESET_350_350_175     35
+#define QCA_PLL_PRESET_360_360_180     36
+#define QCA_PLL_PRESET_380_380_190     37
+#define QCA_PLL_PRESET_400_200_100     38
+#define QCA_PLL_PRESET_400_200_150     39
+#define QCA_PLL_PRESET_400_200_200     40
+#define QCA_PLL_PRESET_400_300_100     41
+#define QCA_PLL_PRESET_400_300_150     42
+#define QCA_PLL_PRESET_400_300_200     43
+#define QCA_PLL_PRESET_400_300_300     44
+#define QCA_PLL_PRESET_400_400_200     45
+#define QCA_PLL_PRESET_400_400_300     46
+#define QCA_PLL_PRESET_410_410_205     47
+#define QCA_PLL_PRESET_420_420_210     48
+#define QCA_PLL_PRESET_430_430_215     49
+#define QCA_PLL_PRESET_440_440_220     50
+#define QCA_PLL_PRESET_450_450_225     51
+#define QCA_PLL_PRESET_460_460_230     52
+#define QCA_PLL_PRESET_470_470_235     53
+#define QCA_PLL_PRESET_480_480_240     54
+#define QCA_PLL_PRESET_490_490_245     55
+#define QCA_PLL_PRESET_500_200_100     56
+#define QCA_PLL_PRESET_500_200_150     57
+#define QCA_PLL_PRESET_500_200_200     58
+#define QCA_PLL_PRESET_500_300_100     59
+#define QCA_PLL_PRESET_500_300_150     60
+#define QCA_PLL_PRESET_500_300_200     61
+#define QCA_PLL_PRESET_500_300_250     62
+#define QCA_PLL_PRESET_500_300_300     63
+#define QCA_PLL_PRESET_500_400_100     64
+#define QCA_PLL_PRESET_500_400_200     65
+#define QCA_PLL_PRESET_500_400_250     66
+#define QCA_PLL_PRESET_500_500_100     67
+#define QCA_PLL_PRESET_500_500_150     68
+#define QCA_PLL_PRESET_500_500_200     69
+#define QCA_PLL_PRESET_500_500_250     70
+#define QCA_PLL_PRESET_500_500_300     71
+#define QCA_PLL_PRESET_510_510_255     72
+#define QCA_PLL_PRESET_520_520_260     73
+#define QCA_PLL_PRESET_530_265_132     74
+#define QCA_PLL_PRESET_540_275_135     75
+#define QCA_PLL_PRESET_550_200_100     76
+#define QCA_PLL_PRESET_550_200_150     77
+#define QCA_PLL_PRESET_550_200_200     78
+#define QCA_PLL_PRESET_550_275_137     79
+#define QCA_PLL_PRESET_550_300_100     80
+#define QCA_PLL_PRESET_550_300_150     81
+#define QCA_PLL_PRESET_550_300_200     82
+#define QCA_PLL_PRESET_550_300_275     83
+#define QCA_PLL_PRESET_550_300_300     84
+#define QCA_PLL_PRESET_550_375_250     85
+#define QCA_PLL_PRESET_550_400_200     86
+#define QCA_PLL_PRESET_560_280_140     87
+#define QCA_PLL_PRESET_560_450_225     88
+#define QCA_PLL_PRESET_570_285_142     89
+#define QCA_PLL_PRESET_580_290_145     90
+#define QCA_PLL_PRESET_600_200_100     91
+#define QCA_PLL_PRESET_600_200_150     92
+#define QCA_PLL_PRESET_600_200_200     93
+#define QCA_PLL_PRESET_600_300_100     94
+#define QCA_PLL_PRESET_600_300_150     95
+#define QCA_PLL_PRESET_600_300_200     96
+#define QCA_PLL_PRESET_600_300_250     97
+#define QCA_PLL_PRESET_600_300_300     98
+#define QCA_PLL_PRESET_600_400_100     99
+#define QCA_PLL_PRESET_600_400_150     100
+#define QCA_PLL_PRESET_600_400_200     101
+#define QCA_PLL_PRESET_600_400_300     102
+#define QCA_PLL_PRESET_600_450_100     103
+#define QCA_PLL_PRESET_600_450_150     104
+#define QCA_PLL_PRESET_600_450_200     105
+#define QCA_PLL_PRESET_600_450_225     106
+#define QCA_PLL_PRESET_600_450_300     107
+#define QCA_PLL_PRESET_600_500_100     108
+#define QCA_PLL_PRESET_600_500_150     109
+#define QCA_PLL_PRESET_600_500_200     110
+#define QCA_PLL_PRESET_600_500_250     111
+#define QCA_PLL_PRESET_600_500_300     112
+#define QCA_PLL_PRESET_600_550_100     113
+#define QCA_PLL_PRESET_600_550_150     114
+#define QCA_PLL_PRESET_600_550_200     115
+#define QCA_PLL_PRESET_600_550_275     116
+#define QCA_PLL_PRESET_600_550_300     117
+#define QCA_PLL_PRESET_600_600_100     118
+#define QCA_PLL_PRESET_600_600_150     119
+#define QCA_PLL_PRESET_600_600_200     120
+#define QCA_PLL_PRESET_600_600_250     121
+#define QCA_PLL_PRESET_600_600_300     122
+#define QCA_PLL_PRESET_620_200_100     123
+#define QCA_PLL_PRESET_620_200_150     124
+#define QCA_PLL_PRESET_620_200_200     125
+#define QCA_PLL_PRESET_620_300_100     126
+#define QCA_PLL_PRESET_620_300_150     127
+#define QCA_PLL_PRESET_620_300_200     128
+#define QCA_PLL_PRESET_620_300_300     129
+#define QCA_PLL_PRESET_620_400_100     130
+#define QCA_PLL_PRESET_620_400_155     131
+#define QCA_PLL_PRESET_620_400_200     132
+#define QCA_PLL_PRESET_620_400_310     133
+#define QCA_PLL_PRESET_620_500_100     134
+#define QCA_PLL_PRESET_620_500_155     135
+#define QCA_PLL_PRESET_620_500_166     136
+#define QCA_PLL_PRESET_620_500_206     137
+#define QCA_PLL_PRESET_620_500_250     138
+#define QCA_PLL_PRESET_620_500_310     139
+#define QCA_PLL_PRESET_650_400_200     140
+#define QCA_PLL_PRESET_650_420_210     141
+#define QCA_PLL_PRESET_650_450_225     142
  
  #endif /* _QCA_PLL_LIST_H_ */
author	Piotr Dymacz <pepe2k@gmail.com>
	Thu, 17 Nov 2016 19:50:59 +0000 (20:50 +0100)
committer	Piotr Dymacz <pepe2k@gmail.com>
	Thu, 17 Nov 2016 19:50:59 +0000 (20:50 +0100)
u-boot/include/soc/ar933x_pll_init.h		patch \| blob \| history
u-boot/include/soc/qca95xx_pll_init.h		patch \| blob \| history
u-boot/include/soc/qca_pll_list.h		patch \| blob \| history