tegra2: spi: Add SPI driver for Tegra2 SOC
authorTom Warren <twarren.nvidia@gmail.com>
Sat, 5 Nov 2011 09:48:11 +0000 (09:48 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 24 Dec 2011 09:23:30 +0000 (10:23 +0100)
This driver supports SPI on Tegra2, running at 48MHz.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
arch/arm/include/asm/arch-tegra2/tegra2.h
arch/arm/include/asm/arch-tegra2/tegra2_spi.h [new file with mode: 0644]
board/nvidia/common/board.c
drivers/spi/Makefile
drivers/spi/tegra2_spi.c [new file with mode: 0644]

index 742a75a0dac3ab27163a2983db9e8ad4d2f6e0f9..8941443ad8e4edfda170e4865752e39e26d729af 100644 (file)
@@ -38,6 +38,7 @@
 #define NV_PA_APB_UARTC_BASE   (NV_PA_APB_MISC_BASE + 0x6200)
 #define NV_PA_APB_UARTD_BASE   (NV_PA_APB_MISC_BASE + 0x6300)
 #define NV_PA_APB_UARTE_BASE   (NV_PA_APB_MISC_BASE + 0x6400)
+#define TEGRA2_SPI_BASE                (NV_PA_APB_MISC_BASE + 0xC380)
 #define NV_PA_PMC_BASE         0x7000E400
 #define NV_PA_CSITE_BASE       0x70040000
 
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
new file mode 100644 (file)
index 0000000..ceec428
--- /dev/null
@@ -0,0 +1,76 @@
+/*
+ * NVIDIA Tegra2 SPI-FLASH controller
+ *
+ * Copyright 2010-2011 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_SPI_H_
+#define _TEGRA2_SPI_H_
+
+#include <asm/types.h>
+
+struct spi_tegra {
+       u32 command;    /* SPI_COMMAND_0 register  */
+       u32 status;     /* SPI_STATUS_0 register */
+       u32 rx_cmp;     /* SPI_RX_CMP_0 register  */
+       u32 dma_ctl;    /* SPI_DMA_CTL_0 register */
+       u32 tx_fifo;    /* SPI_TX_FIFO_0 register */
+       u32 rsvd[3];    /* offsets 0x14 to 0x1F reserved */
+       u32 rx_fifo;    /* SPI_RX_FIFO_0 register */
+};
+
+#define SPI_CMD_GO                     (1 << 30)
+#define SPI_CMD_ACTIVE_SCLK_SHIFT      26
+#define SPI_CMD_ACTIVE_SCLK_MASK       (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
+#define SPI_CMD_CK_SDA                 (1 << 21)
+#define SPI_CMD_ACTIVE_SDA_SHIFT       18
+#define SPI_CMD_ACTIVE_SDA_MASK                (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
+#define SPI_CMD_CS_POL                 (1 << 16)
+#define SPI_CMD_TXEN                   (1 << 15)
+#define SPI_CMD_RXEN                   (1 << 14)
+#define SPI_CMD_CS_VAL                 (1 << 13)
+#define SPI_CMD_CS_SOFT                        (1 << 12)
+#define SPI_CMD_CS_DELAY               (1 << 9)
+#define SPI_CMD_CS3_EN                 (1 << 8)
+#define SPI_CMD_CS2_EN                 (1 << 7)
+#define SPI_CMD_CS1_EN                 (1 << 6)
+#define SPI_CMD_CS0_EN                 (1 << 5)
+#define SPI_CMD_BIT_LENGTH             (1 << 4)
+#define SPI_CMD_BIT_LENGTH_MASK                0x0000001F
+
+#define SPI_STAT_BSY                   (1 << 31)
+#define SPI_STAT_RDY                   (1 << 30)
+#define SPI_STAT_RXF_FLUSH             (1 << 29)
+#define SPI_STAT_TXF_FLUSH             (1 << 28)
+#define SPI_STAT_RXF_UNR               (1 << 27)
+#define SPI_STAT_TXF_OVF               (1 << 26)
+#define SPI_STAT_RXF_EMPTY             (1 << 25)
+#define SPI_STAT_RXF_FULL              (1 << 24)
+#define SPI_STAT_TXF_EMPTY             (1 << 23)
+#define SPI_STAT_TXF_FULL              (1 << 22)
+#define SPI_STAT_SEL_TXRX_N            (1 << 16)
+#define SPI_STAT_CUR_BLKCNT            (1 << 15)
+
+#define SPI_TIMEOUT            1000
+#define TEGRA2_SPI_MAX_FREQ    52000000
+
+
+#endif /* _TEGRA2_SPI_H_ */
index 4c291673168428d16b1f0a0a6a671a8bab920d95..6a1312c5aae8890e92d093cc40660c54ea3f395b 100644 (file)
@@ -31,6 +31,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/uart.h>
+#include <spi.h>
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -114,6 +115,9 @@ int board_init(void)
        clock_init();
        clock_verify();
 
+#ifdef CONFIG_TEGRA2_SPI
+       spi_init();
+#endif
        /* boot param addr */
        gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
 
index 6f389f093498ae00c9758f7aac99a3c36e3b6228..c967d87834a43e6b47ed8c6d9601e18766da1d03 100644 (file)
@@ -43,6 +43,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
 COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
+COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c
new file mode 100644 (file)
index 0000000..fdcad09
--- /dev/null
@@ -0,0 +1,265 @@
+/*
+ * Copyright (c) 2010-2011 NVIDIA Corporation
+ * With help from the mpc8xxx SPI driver
+ * With more help from omap3_spi SPI driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra2_spi.h>
+
+struct tegra_spi_slave {
+       struct spi_slave slave;
+       struct spi_tegra *regs;
+       unsigned int freq;
+       unsigned int mode;
+};
+
+static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
+{
+       return container_of(slave, struct tegra_spi_slave, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       /* Tegra2 SPI-Flash - only 1 device ('bus/cs') */
+       if (bus != 0 || cs != 0)
+               return 0;
+       else
+               return 1;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+               unsigned int max_hz, unsigned int mode)
+{
+       struct tegra_spi_slave *spi;
+
+       if (!spi_cs_is_valid(bus, cs)) {
+               printf("SPI error: unsupported bus %d / chip select %d\n",
+                      bus, cs);
+               return NULL;
+       }
+
+       if (max_hz > TEGRA2_SPI_MAX_FREQ) {
+               printf("SPI error: unsupported frequency %d Hz. Max frequency"
+                       " is %d Hz\n", max_hz, TEGRA2_SPI_MAX_FREQ);
+               return NULL;
+       }
+
+       spi = malloc(sizeof(struct tegra_spi_slave));
+       if (!spi) {
+               printf("SPI error: malloc of SPI structure failed\n");
+               return NULL;
+       }
+       spi->slave.bus = bus;
+       spi->slave.cs = cs;
+       spi->freq = max_hz;
+       spi->regs = (struct spi_tegra *)TEGRA2_SPI_BASE;
+       spi->mode = mode;
+
+       return &spi->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+       free(spi);
+}
+
+void spi_init(void)
+{
+       /* do nothing */
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+       struct spi_tegra *regs = spi->regs;
+       u32 reg;
+
+       /* Change SPI clock to correct frequency, PLLP_OUT0 source */
+       clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq);
+
+       /* Clear stale status here */
+       reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
+               SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
+       writel(reg, &regs->status);
+       debug("spi_init: STATUS = %08x\n", readl(&regs->status));
+
+       /*
+        * Use sw-controlled CS, so we can clock in data after ReadID, etc.
+        */
+       reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
+       if (spi->mode & 2)
+               reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
+       clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
+               SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
+       debug("spi_init: COMMAND = %08x\n", readl(&regs->command));
+
+       /*
+        * SPI pins on Tegra2 are muxed - change pinmux later due to UART
+        * issue.
+        */
+       pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
+       pinmux_tristate_disable(PINGRP_LSPI);
+       return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+       /*
+        * We can't release UART_DISABLE and set pinmux to UART4 here since
+        * some code (e,g, spi_flash_probe) uses printf() while the SPI
+        * bus is held. That is arguably bad, but it has the advantage of
+        * already being in the source tree.
+        */
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+       /* CS is negated on Tegra, so drive a 1 to get a 0 */
+       setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+       /* CS is negated on Tegra, so drive a 0 to get a 1 */
+       clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+               const void *data_out, void *data_in, unsigned long flags)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+       struct spi_tegra *regs = spi->regs;
+       u32 reg, tmpdout, tmpdin = 0;
+       const u8 *dout = data_out;
+       u8 *din = data_in;
+       int num_bytes;
+       int ret;
+
+       debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
+             slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
+       if (bitlen % 8)
+               return -1;
+       num_bytes = bitlen / 8;
+
+       ret = 0;
+
+       reg = readl(&regs->status);
+       writel(reg, &regs->status);     /* Clear all SPI events via R/W */
+       debug("spi_xfer entry: STATUS = %08x\n", reg);
+
+       reg = readl(&regs->command);
+       reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
+       writel(reg, &regs->command);
+       debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
+
+       if (flags & SPI_XFER_BEGIN)
+               spi_cs_activate(slave);
+
+       /* handle data in 32-bit chunks */
+       while (num_bytes > 0) {
+               int bytes;
+               int is_read = 0;
+               int tm, i;
+
+               tmpdout = 0;
+               bytes = (num_bytes > 4) ?  4 : num_bytes;
+
+               if (dout != NULL) {
+                       for (i = 0; i < bytes; ++i)
+                               tmpdout = (tmpdout << 8) | dout[i];
+               }
+
+               num_bytes -= bytes;
+               if (dout)
+                       dout += bytes;
+
+               clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
+                               bytes * 8 - 1);
+               writel(tmpdout, &regs->tx_fifo);
+               setbits_le32(&regs->command, SPI_CMD_GO);
+
+               /*
+                * Wait for SPI transmit FIFO to empty, or to time out.
+                * The RX FIFO status will be read and cleared last
+                */
+               for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
+                       u32 status;
+
+                       status = readl(&regs->status);
+
+                       /* We can exit when we've had both RX and TX activity */
+                       if (is_read && (status & SPI_STAT_TXF_EMPTY))
+                               break;
+
+                       if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
+                                       SPI_STAT_RDY)
+                               tm++;
+
+                       else if (!(status & SPI_STAT_RXF_EMPTY)) {
+                               tmpdin = readl(&regs->rx_fifo);
+                               is_read = 1;
+
+                               /* swap bytes read in */
+                               if (din != NULL) {
+                                       for (i = bytes - 1; i >= 0; --i) {
+                                               din[i] = tmpdin & 0xff;
+                                               tmpdin >>= 8;
+                                       }
+                                       din += bytes;
+                               }
+                       }
+               }
+
+               if (tm >= SPI_TIMEOUT)
+                       ret = tm;
+
+               /* clear ACK RDY, etc. bits */
+               writel(readl(&regs->status), &regs->status);
+       }
+
+       if (flags & SPI_XFER_END)
+               spi_cs_deactivate(slave);
+
+       debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
+               tmpdin, readl(&regs->status));
+
+       if (ret) {
+               printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
+               return -1;
+       }
+
+       return 0;
+}