obj-$(CONFIG_LIBATA) += libata.o
obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
obj-$(CONFIG_MX51_PATA) += mxc_ata.o
-obj-$(CONFIG_PATA_BFIN) += pata_bfin.o
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
obj-$(CONFIG_SATA_DWC) += sata_dwc.o
obj-$(CONFIG_SATA_MV) += sata_mv.o
+++ /dev/null
-/*
- * Driver for Blackfin on-chip ATAPI controller.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (c) 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <config.h>
-#include <asm/byteorder.h>
-#include <asm/clock.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/pata.h>
-#include <ata.h>
-#include <sata.h>
-#include <libata.h>
-#include "pata_bfin.h"
-
-static struct ata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
-
-/**
- * PIO Mode - Frequency compatibility
- */
-/* mode: 0 1 2 3 4 */
-static const u32 pio_fsclk[] =
-{ 33333333, 33333333, 33333333, 33333333, 33333333 };
-
-/**
- * MDMA Mode - Frequency compatibility
- */
-/* mode: 0 1 2 */
-static const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 };
-
-/**
- * UDMA Mode - Frequency compatibility
- *
- * UDMA5 - 100 MB/s - SCLK = 133 MHz
- * UDMA4 - 66 MB/s - SCLK >= 80 MHz
- * UDMA3 - 44.4 MB/s - SCLK >= 50 MHz
- * UDMA2 - 33 MB/s - SCLK >= 40 MHz
- */
-/* mode: 0 1 2 3 4 5 */
-static const u32 udma_fsclk[] =
-{ 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 };
-
-/**
- * Register transfer timing table
- */
-/* mode: 0 1 2 3 4 */
-/* Cycle Time */
-static const u32 reg_t0min[] = { 600, 383, 330, 180, 120 };
-/* DIOR/DIOW to end cycle */
-static const u32 reg_t2min[] = { 290, 290, 290, 70, 25 };
-/* DIOR/DIOW asserted pulse width */
-static const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 };
-
-/**
- * PIO timing table
- */
-/* mode: 0 1 2 3 4 */
-/* Cycle Time */
-static const u32 pio_t0min[] = { 600, 383, 240, 180, 120 };
-/* Address valid to DIOR/DIORW */
-static const u32 pio_t1min[] = { 70, 50, 30, 30, 25 };
-/* DIOR/DIOW to end cycle */
-static const u32 pio_t2min[] = { 165, 125, 100, 80, 70 };
-/* DIOR/DIOW asserted pulse width */
-static const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 };
-/* DIOW data hold */
-static const u32 pio_t4min[] = { 30, 20, 15, 10, 10 };
-
-/* ******************************************************************
- * Multiword DMA timing table
- * ******************************************************************
- */
-/* mode: 0 1 2 */
-/* Cycle Time */
-static const u32 mdma_t0min[] = { 480, 150, 120 };
-/* DIOR/DIOW asserted pulse width */
-static const u32 mdma_tdmin[] = { 215, 80, 70 };
-/* DMACK to read data released */
-static const u32 mdma_thmin[] = { 20, 15, 10 };
-/* DIOR/DIOW to DMACK hold */
-static const u32 mdma_tjmin[] = { 20, 5, 5 };
-/* DIOR negated pulse width */
-static const u32 mdma_tkrmin[] = { 50, 50, 25 };
-/* DIOR negated pulse width */
-static const u32 mdma_tkwmin[] = { 215, 50, 25 };
-/* CS[1:0] valid to DIOR/DIOW */
-static const u32 mdma_tmmin[] = { 50, 30, 25 };
-/* DMACK to read data released */
-static const u32 mdma_tzmax[] = { 20, 25, 25 };
-
-/**
- * Ultra DMA timing table
- */
-/* mode: 0 1 2 3 4 5 */
-static const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 };
-static const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 };
-static const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 };
-static const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 };
-static const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 };
-
-
-static const u32 udma_tmlimin = 20;
-static const u32 udma_tzahmin = 20;
-static const u32 udma_tenvmin = 20;
-static const u32 udma_tackmin = 20;
-static const u32 udma_tssmin = 50;
-
-static void msleep(int count)
-{
- int i;
-
- for (i = 0; i < count; i++)
- udelay(1000);
-}
-
-/**
- *
- * Function: num_clocks_min
- *
- * Description:
- * calculate number of SCLK cycles to meet minimum timing
- */
-static unsigned short num_clocks_min(unsigned long tmin,
- unsigned long fsclk)
-{
- unsigned long tmp ;
- unsigned short result;
-
- tmp = tmin * (fsclk/1000/1000) / 1000;
- result = (unsigned short)tmp;
- if ((tmp*1000*1000) < (tmin*(fsclk/1000)))
- result++;
-
- return result;
-}
-
-/**
- * bfin_set_piomode - Initialize host controller PATA PIO timings
- * @ap: Port whose timings we are configuring
- * @pio_mode: mode
- *
- * Set PIO mode for device.
- *
- * LOCKING:
- * None (inherited from caller).
- */
-
-static void bfin_set_piomode(struct ata_port *ap, int pio_mode)
-{
- int mode = pio_mode - XFER_PIO_0;
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- unsigned int fsclk = get_sclk();
- unsigned short teoc_reg, t2_reg, teoc_pio;
- unsigned short t4_reg, t2_pio, t1_reg;
- unsigned short n0, n6, t6min = 5;
-
- /* the most restrictive timing value is t6 and tc, the DIOW - data hold
- * If one SCLK pulse is longer than this minimum value then register
- * transfers cannot be supported at this frequency.
- */
- n6 = num_clocks_min(t6min, fsclk);
- if (mode >= 0 && mode <= 4 && n6 >= 1) {
- debug("set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
- /* calculate the timing values for register transfers. */
- while (mode > 0 && pio_fsclk[mode] > fsclk)
- mode--;
-
- /* DIOR/DIOW to end cycle time */
- t2_reg = num_clocks_min(reg_t2min[mode], fsclk);
- /* DIOR/DIOW asserted pulse width */
- teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk);
- /* Cycle Time */
- n0 = num_clocks_min(reg_t0min[mode], fsclk);
-
- /* increase t2 until we meed the minimum cycle length */
- if (t2_reg + teoc_reg < n0)
- t2_reg = n0 - teoc_reg;
-
- /* calculate the timing values for pio transfers. */
-
- /* DIOR/DIOW to end cycle time */
- t2_pio = num_clocks_min(pio_t2min[mode], fsclk);
- /* DIOR/DIOW asserted pulse width */
- teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk);
- /* Cycle Time */
- n0 = num_clocks_min(pio_t0min[mode], fsclk);
-
- /* increase t2 until we meed the minimum cycle length */
- if (t2_pio + teoc_pio < n0)
- t2_pio = n0 - teoc_pio;
-
- /* Address valid to DIOR/DIORW */
- t1_reg = num_clocks_min(pio_t1min[mode], fsclk);
-
- /* DIOW data hold */
- t4_reg = num_clocks_min(pio_t4min[mode], fsclk);
-
- ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));
- ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));
- ATAPI_SET_PIO_TIM_1(base, teoc_pio);
- if (mode > 2) {
- ATAPI_SET_CONTROL(base,
- ATAPI_GET_CONTROL(base) | IORDY_EN);
- } else {
- ATAPI_SET_CONTROL(base,
- ATAPI_GET_CONTROL(base) & ~IORDY_EN);
- }
-
- /* Disable host ATAPI PIO interrupts */
- ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
- & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK));
- SSYNC();
- }
-}
-
-/**
- *
- * Function: wait_complete
- *
- * Description: Waits the interrupt from device
- *
- */
-static inline void wait_complete(void __iomem *base, unsigned short mask)
-{
- unsigned short status;
- unsigned int i = 0;
-
- for (i = 0; i < PATA_BFIN_WAIT_TIMEOUT; i++) {
- status = ATAPI_GET_INT_STATUS(base) & mask;
- if (status)
- break;
- }
-
- ATAPI_SET_INT_STATUS(base, mask);
-}
-
-/**
- *
- * Function: write_atapi_register
- *
- * Description: Writes to ATA Device Resgister
- *
- */
-
-static void write_atapi_register(void __iomem *base,
- unsigned long ata_reg, unsigned short value)
-{
- /* Program the ATA_DEV_TXBUF register with write data (to be
- * written into the device).
- */
- ATAPI_SET_DEV_TXBUF(base, value);
-
- /* Program the ATA_DEV_ADDR register with address of the
- * device register (0x01 to 0x0F).
- */
- ATAPI_SET_DEV_ADDR(base, ata_reg);
-
- /* Program the ATA_CTRL register with dir set to write (1)
- */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
-
- /* ensure PIO DMA is not set */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
-
- /* and start the transfer */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
-
- /* Wait for the interrupt to indicate the end of the transfer.
- * (We need to wait on and clear rhe ATA_DEV_INT interrupt status)
- */
- wait_complete(base, PIO_DONE_INT);
-}
-
-/**
- *
- * Function: read_atapi_register
- *
- *Description: Reads from ATA Device Resgister
- *
- */
-
-static unsigned short read_atapi_register(void __iomem *base,
- unsigned long ata_reg)
-{
- /* Program the ATA_DEV_ADDR register with address of the
- * device register (0x01 to 0x0F).
- */
- ATAPI_SET_DEV_ADDR(base, ata_reg);
-
- /* Program the ATA_CTRL register with dir set to read (0) and
- */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
-
- /* ensure PIO DMA is not set */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
-
- /* and start the transfer */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
-
- /* Wait for the interrupt to indicate the end of the transfer.
- * (PIO_DONE interrupt is set and it doesn't seem to matter
- * that we don't clear it)
- */
- wait_complete(base, PIO_DONE_INT);
-
- /* Read the ATA_DEV_RXBUF register with write data (to be
- * written into the device).
- */
- return ATAPI_GET_DEV_RXBUF(base);
-}
-
-/**
- *
- * Function: write_atapi_register_data
- *
- * Description: Writes to ATA Device Resgister
- *
- */
-
-static void write_atapi_data(void __iomem *base,
- int len, unsigned short *buf)
-{
- int i;
-
- /* Set transfer length to 1 */
- ATAPI_SET_XFER_LEN(base, 1);
-
- /* Program the ATA_DEV_ADDR register with address of the
- * ATA_REG_DATA
- */
- ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
-
- /* Program the ATA_CTRL register with dir set to write (1)
- */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
-
- /* ensure PIO DMA is not set */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
-
- for (i = 0; i < len; i++) {
- /* Program the ATA_DEV_TXBUF register with write data (to be
- * written into the device).
- */
- ATAPI_SET_DEV_TXBUF(base, buf[i]);
-
- /* and start the transfer */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
-
- /* Wait for the interrupt to indicate the end of the transfer.
- * (We need to wait on and clear rhe ATA_DEV_INT
- * interrupt status)
- */
- wait_complete(base, PIO_DONE_INT);
- }
-}
-
-/**
- *
- * Function: read_atapi_register_data
- *
- * Description: Reads from ATA Device Resgister
- *
- */
-
-static void read_atapi_data(void __iomem *base,
- int len, unsigned short *buf)
-{
- int i;
-
- /* Set transfer length to 1 */
- ATAPI_SET_XFER_LEN(base, 1);
-
- /* Program the ATA_DEV_ADDR register with address of the
- * ATA_REG_DATA
- */
- ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
-
- /* Program the ATA_CTRL register with dir set to read (0) and
- */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
-
- /* ensure PIO DMA is not set */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
-
- for (i = 0; i < len; i++) {
- /* and start the transfer */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
-
- /* Wait for the interrupt to indicate the end of the transfer.
- * (PIO_DONE interrupt is set and it doesn't seem to matter
- * that we don't clear it)
- */
- wait_complete(base, PIO_DONE_INT);
-
- /* Read the ATA_DEV_RXBUF register with write data (to be
- * written into the device).
- */
- buf[i] = ATAPI_GET_DEV_RXBUF(base);
- }
-}
-
-/**
- * bfin_check_status - Read device status reg & clear interrupt
- * @ap: port where the device is
- *
- * Note: Original code is ata_check_status().
- */
-
-static u8 bfin_check_status(struct ata_port *ap)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- return read_atapi_register(base, ATA_REG_STATUS);
-}
-
-/**
- * bfin_check_altstatus - Read device alternate status reg
- * @ap: port where the device is
- */
-
-static u8 bfin_check_altstatus(struct ata_port *ap)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- return read_atapi_register(base, ATA_REG_ALTSTATUS);
-}
-
-/**
- * bfin_ata_busy_wait - Wait for a port status register
- * @ap: Port to wait for.
- * @bits: bits that must be clear
- * @max: number of 10uS waits to perform
- *
- * Waits up to max*10 microseconds for the selected bits in the port's
- * status register to be cleared.
- * Returns final value of status register.
- *
- * LOCKING:
- * Inherited from caller.
- */
-static inline u8 bfin_ata_busy_wait(struct ata_port *ap, unsigned int bits,
- unsigned int max, u8 usealtstatus)
-{
- u8 status;
-
- do {
- udelay(10);
- if (usealtstatus)
- status = bfin_check_altstatus(ap);
- else
- status = bfin_check_status(ap);
- max--;
- } while (status != 0xff && (status & bits) && (max > 0));
-
- return status;
-}
-
-/**
- * bfin_ata_busy_sleep - sleep until BSY clears, or timeout
- * @ap: port containing status register to be polled
- * @tmout_pat: impatience timeout in msecs
- * @tmout: overall timeout in msecs
- *
- * Sleep until ATA Status register bit BSY clears,
- * or a timeout occurs.
- *
- * RETURNS:
- * 0 on success, -errno otherwise.
- */
-static int bfin_ata_busy_sleep(struct ata_port *ap,
- long tmout_pat, unsigned long tmout)
-{
- u8 status;
-
- status = bfin_ata_busy_wait(ap, ATA_BUSY, 300, 0);
- while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
- msleep(50);
- tmout_pat -= 50;
- status = bfin_ata_busy_wait(ap, ATA_BUSY, 3, 0);
- }
-
- if (status != 0xff && (status & ATA_BUSY))
- printf("port is slow to respond, please be patient "
- "(Status 0x%x)\n", status);
-
- while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
- msleep(50);
- tmout_pat -= 50;
- status = bfin_check_status(ap);
- }
-
- if (status == 0xff)
- return -ENODEV;
-
- if (status & ATA_BUSY) {
- printf("port failed to respond "
- "(%lu secs, Status 0x%x)\n",
- DIV_ROUND_UP(tmout, 1000), status);
- return -EBUSY;
- }
-
- return 0;
-}
-
-/**
- * bfin_dev_select - Select device 0/1 on ATA bus
- * @ap: ATA channel to manipulate
- * @device: ATA device (numbered from zero) to select
- *
- * Note: Original code is ata_sff_dev_select().
- */
-
-static void bfin_dev_select(struct ata_port *ap, unsigned int device)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- u8 tmp;
-
-
- if (device == 0)
- tmp = ATA_DEVICE_OBS;
- else
- tmp = ATA_DEVICE_OBS | ATA_DEV1;
-
- write_atapi_register(base, ATA_REG_DEVICE, tmp);
- udelay(1);
-}
-
-/**
- * bfin_devchk - PATA device presence detection
- * @ap: ATA channel to examine
- * @device: Device to examine (starting at zero)
- *
- * Note: Original code is ata_devchk().
- */
-
-static unsigned int bfin_devchk(struct ata_port *ap,
- unsigned int device)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- u8 nsect, lbal;
-
- bfin_dev_select(ap, device);
-
- write_atapi_register(base, ATA_REG_NSECT, 0x55);
- write_atapi_register(base, ATA_REG_LBAL, 0xaa);
-
- write_atapi_register(base, ATA_REG_NSECT, 0xaa);
- write_atapi_register(base, ATA_REG_LBAL, 0x55);
-
- write_atapi_register(base, ATA_REG_NSECT, 0x55);
- write_atapi_register(base, ATA_REG_LBAL, 0xaa);
-
- nsect = read_atapi_register(base, ATA_REG_NSECT);
- lbal = read_atapi_register(base, ATA_REG_LBAL);
-
- if ((nsect == 0x55) && (lbal == 0xaa))
- return 1; /* we found a device */
-
- return 0; /* nothing found */
-}
-
-/**
- * bfin_bus_post_reset - PATA device post reset
- *
- * Note: Original code is ata_bus_post_reset().
- */
-
-static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- unsigned int dev0 = devmask & (1 << 0);
- unsigned int dev1 = devmask & (1 << 1);
- long deadline;
-
- /* if device 0 was found in ata_devchk, wait for its
- * BSY bit to clear
- */
- if (dev0)
- bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
-
- /* if device 1 was found in ata_devchk, wait for
- * register access, then wait for BSY to clear
- */
- deadline = ATA_TMOUT_BOOT;
- while (dev1) {
- u8 nsect, lbal;
-
- bfin_dev_select(ap, 1);
- nsect = read_atapi_register(base, ATA_REG_NSECT);
- lbal = read_atapi_register(base, ATA_REG_LBAL);
- if ((nsect == 1) && (lbal == 1))
- break;
- if (deadline <= 0) {
- dev1 = 0;
- break;
- }
- msleep(50); /* give drive a breather */
- deadline -= 50;
- }
- if (dev1)
- bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
-
- /* is all this really necessary? */
- bfin_dev_select(ap, 0);
- if (dev1)
- bfin_dev_select(ap, 1);
- if (dev0)
- bfin_dev_select(ap, 0);
-}
-
-/**
- * bfin_bus_softreset - PATA device software reset
- *
- * Note: Original code is ata_bus_softreset().
- */
-
-static unsigned int bfin_bus_softreset(struct ata_port *ap,
- unsigned int devmask)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
-
- /* software reset. causes dev0 to be selected */
- write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
- udelay(20);
- write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg | ATA_SRST);
- udelay(20);
- write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
-
- /* spec mandates ">= 2ms" before checking status.
- * We wait 150ms, because that was the magic delay used for
- * ATAPI devices in Hale Landis's ATADRVR, for the period of time
- * between when the ATA command register is written, and then
- * status is checked. Because waiting for "a while" before
- * checking status is fine, post SRST, we perform this magic
- * delay here as well.
- *
- * Old drivers/ide uses the 2mS rule and then waits for ready
- */
- msleep(150);
-
- /* Before we perform post reset processing we want to see if
- * the bus shows 0xFF because the odd clown forgets the D7
- * pulldown resistor.
- */
- if (bfin_check_status(ap) == 0xFF)
- return 0;
-
- bfin_bus_post_reset(ap, devmask);
-
- return 0;
-}
-
-/**
- * bfin_softreset - reset host port via ATA SRST
- * @ap: port to reset
- *
- * Note: Original code is ata_sff_softreset().
- */
-
-static int bfin_softreset(struct ata_port *ap)
-{
- unsigned int err_mask;
-
- ap->dev_mask = 0;
-
- /* determine if device 0/1 are present.
- * only one device is supported on one port by now.
- */
- if (bfin_devchk(ap, 0))
- ap->dev_mask |= (1 << 0);
- else if (bfin_devchk(ap, 1))
- ap->dev_mask |= (1 << 1);
- else
- return -ENODEV;
-
- /* select device 0 again */
- bfin_dev_select(ap, 0);
-
- /* issue bus reset */
- err_mask = bfin_bus_softreset(ap, ap->dev_mask);
- if (err_mask) {
- printf("SRST failed (err_mask=0x%x)\n",
- err_mask);
- ap->dev_mask = 0;
- return -EIO;
- }
-
- return 0;
-}
-
-/**
- * bfin_irq_clear - Clear ATAPI interrupt.
- * @ap: Port associated with this ATA transaction.
- *
- * Note: Original code is ata_sff_irq_clear().
- */
-
-static void bfin_irq_clear(struct ata_port *ap)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
-
- ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
- | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
- | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
-}
-
-static u8 bfin_wait_for_irq(struct ata_port *ap, unsigned int max)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
-
- do {
- if (ATAPI_GET_INT_STATUS(base) & (ATAPI_DEV_INT
- | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
- | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT)) {
- break;
- }
- udelay(1000);
- max--;
- } while ((max > 0));
-
- return max == 0;
-}
-
-/**
- * bfin_ata_reset_port - initialize BFIN ATAPI port.
- */
-
-static int bfin_ata_reset_port(struct ata_port *ap)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- int count;
- unsigned short status;
-
- /* Disable all ATAPI interrupts */
- ATAPI_SET_INT_MASK(base, 0);
- SSYNC();
-
- /* Assert the RESET signal 25us*/
- ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);
- udelay(30);
-
- /* Negate the RESET signal for 2ms*/
- ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);
- msleep(2);
-
- /* Wait on Busy flag to clear */
- count = 10000000;
- do {
- status = read_atapi_register(base, ATA_REG_STATUS);
- } while (--count && (status & ATA_BUSY));
-
- /* Enable only ATAPI Device interrupt */
- ATAPI_SET_INT_MASK(base, 1);
- SSYNC();
-
- return !count;
-}
-
-/**
- *
- * Function: bfin_config_atapi_gpio
- *
- * Description: Configures the ATAPI pins for use
- *
- */
-static int bfin_config_atapi_gpio(struct ata_port *ap)
-{
- const unsigned short pins[] = {
- P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0,
- P_ATAPI_CS1, P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ,
- P_ATAPI_IORDY, P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A,
- P_ATAPI_D3A, P_ATAPI_D4A, P_ATAPI_D5A, P_ATAPI_D6A,
- P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, P_ATAPI_D10A,
- P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
- P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, 0,
- };
-
- peripheral_request_list(pins, "pata_bfin");
-
- return 0;
-}
-
-/**
- * bfin_atapi_probe - attach a bfin atapi interface
- * @pdev: platform device
- *
- * Register a bfin atapi interface.
- *
- *
- * Platform devices are expected to contain 2 resources per port:
- *
- * - I/O Base (IORESOURCE_IO)
- * - IRQ (IORESOURCE_IRQ)
- *
- */
-static int bfin_ata_probe_port(struct ata_port *ap)
-{
- if (bfin_config_atapi_gpio(ap)) {
- printf("Requesting Peripherals faild\n");
- return -EFAULT;
- }
-
- if (bfin_ata_reset_port(ap)) {
- printf("Fail to reset ATAPI device\n");
- return -EFAULT;
- }
-
- if (ap->ata_mode >= XFER_PIO_0 && ap->ata_mode <= XFER_PIO_4)
- bfin_set_piomode(ap, ap->ata_mode);
- else {
- printf("Given ATA data transfer mode is not supported.\n");
- return -EFAULT;
- }
-
- return 0;
-}
-
-#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
-
-static void bfin_ata_identify(struct ata_port *ap, int dev)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- u8 status = 0;
- static u16 iobuf[ATA_SECTOR_WORDS];
- u64 n_sectors = 0;
- hd_driveid_t *iop = (hd_driveid_t *)iobuf;
-
- memset(iobuf, 0, sizeof(iobuf));
-
- if (!(ap->dev_mask & (1 << dev)))
- return;
-
- debug("port=%d dev=%d\n", ap->port_no, dev);
-
- bfin_dev_select(ap, dev);
-
- status = 0;
- /* Device Identify Command */
- write_atapi_register(base, ATA_REG_CMD, ATA_CMD_ID_ATA);
- bfin_check_altstatus(ap);
- udelay(10);
-
- status = bfin_ata_busy_wait(ap, ATA_BUSY, 1000, 0);
- if (status & ATA_ERR) {
- printf("\ndevice not responding\n");
- ap->dev_mask &= ~(1 << dev);
- return;
- }
-
- read_atapi_data(base, ATA_SECTOR_WORDS, iobuf);
-
- ata_swap_buf_le16(iobuf, ATA_SECTOR_WORDS);
-
- /* we require LBA and DMA support (bits 8 & 9 of word 49) */
- if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
- printf("ata%u: no dma/lba\n", ap->port_no);
-
-#ifdef DEBUG
- ata_dump_id(iobuf);
-#endif
-
- n_sectors = ata_id_n_sectors(iobuf);
-
- if (n_sectors == 0) {
- ap->dev_mask &= ~(1 << dev);
- return;
- }
-
- ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].revision,
- ATA_ID_FW_REV, sizeof(sata_dev_desc[ap->port_no].revision));
- ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].vendor,
- ATA_ID_PROD, sizeof(sata_dev_desc[ap->port_no].vendor));
- ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].product,
- ATA_ID_SERNO, sizeof(sata_dev_desc[ap->port_no].product));
-
- if ((iop->config & 0x0080) == 0x0080)
- sata_dev_desc[ap->port_no].removable = 1;
- else
- sata_dev_desc[ap->port_no].removable = 0;
-
- sata_dev_desc[ap->port_no].lba = (u32) n_sectors;
- debug("lba=0x%lx\n", sata_dev_desc[ap->port_no].lba);
-
-#ifdef CONFIG_LBA48
- if (iop->command_set_2 & 0x0400)
- sata_dev_desc[ap->port_no].lba48 = 1;
- else
- sata_dev_desc[ap->port_no].lba48 = 0;
-#endif
-
- /* assuming HD */
- sata_dev_desc[ap->port_no].type = DEV_TYPE_HARDDISK;
- sata_dev_desc[ap->port_no].blksz = ATA_SECT_SIZE;
- sata_dev_desc[ap->port_no].log2blksz =
- LOG2(sata_dev_desc[ap->port_no].blksz);
- sata_dev_desc[ap->port_no].lun = 0; /* just to fill something in... */
-
- printf("PATA device#%d %s is found on ata port#%d.\n",
- ap->port_no%PATA_DEV_NUM_PER_PORT,
- sata_dev_desc[ap->port_no].vendor,
- ap->port_no/PATA_DEV_NUM_PER_PORT);
-}
-
-static void bfin_ata_set_Feature_cmd(struct ata_port *ap, int dev)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- u8 status = 0;
-
- if (!(ap->dev_mask & (1 << dev)))
- return;
-
- bfin_dev_select(ap, dev);
-
- write_atapi_register(base, ATA_REG_FEATURE, SETFEATURES_XFER);
- write_atapi_register(base, ATA_REG_NSECT, ap->ata_mode);
- write_atapi_register(base, ATA_REG_LBAL, 0);
- write_atapi_register(base, ATA_REG_LBAM, 0);
- write_atapi_register(base, ATA_REG_LBAH, 0);
-
- write_atapi_register(base, ATA_REG_DEVICE, ATA_DEVICE_OBS);
- write_atapi_register(base, ATA_REG_CMD, ATA_CMD_SET_FEATURES);
-
- udelay(50);
- msleep(150);
-
- status = bfin_ata_busy_wait(ap, ATA_BUSY, 5000, 0);
- if ((status & (ATA_BUSY | ATA_ERR))) {
- printf("Error : status 0x%02x\n", status);
- ap->dev_mask &= ~(1 << dev);
- }
-}
-
-int scan_sata(int dev)
-{
- /* dev is the index of each ata device in the system. one PATA port
- * contains 2 devices. one element in scan_done array indicates one
- * PATA port. device connected to one PATA port is selected by
- * bfin_dev_select() before access.
- */
- struct ata_port *ap = &port[dev];
- static int scan_done[(CONFIG_SYS_SATA_MAX_DEVICE+1)/PATA_DEV_NUM_PER_PORT];
-
- if (scan_done[dev/PATA_DEV_NUM_PER_PORT])
- return 0;
-
- /* Check for attached device */
- if (!bfin_ata_probe_port(ap)) {
- if (bfin_softreset(ap)) {
- /* soft reset failed, try a hard one */
- bfin_ata_reset_port(ap);
- if (bfin_softreset(ap))
- scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
- } else {
- scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
- }
- }
- if (scan_done[dev/PATA_DEV_NUM_PER_PORT]) {
- /* Probe device and set xfer mode */
- bfin_ata_identify(ap, dev%PATA_DEV_NUM_PER_PORT);
- bfin_ata_set_Feature_cmd(ap, dev%PATA_DEV_NUM_PER_PORT);
- part_init(&sata_dev_desc[dev]);
- return 0;
- }
-
- printf("PATA device#%d is not present on ATA port#%d.\n",
- ap->port_no%PATA_DEV_NUM_PER_PORT,
- ap->port_no/PATA_DEV_NUM_PER_PORT);
-
- return -1;
-}
-
-int init_sata(int dev)
-{
- struct ata_port *ap = &port[dev];
- static u8 init_done;
- int res = 1;
-
- if (init_done)
- return res;
-
- init_done = 1;
-
- switch (dev/PATA_DEV_NUM_PER_PORT) {
- case 0:
- ap->ioaddr.ctl_addr = ATAPI_CONTROL;
- ap->ata_mode = CONFIG_BFIN_ATA_MODE;
- break;
- default:
- printf("Tried to scan unknown port %d.\n", dev);
- return res;
- }
-
- if (ap->ata_mode < XFER_PIO_0 || ap->ata_mode > XFER_PIO_4) {
- ap->ata_mode = XFER_PIO_4;
- printf("DMA mode is not supported. Set to PIO mode 4.\n");
- }
-
- ap->port_no = dev;
- ap->ctl_reg = 0x8; /*Default value of control reg */
-
- res = 0;
- return res;
-}
-
-int reset_sata(int dev)
-{
- return 0;
-}
-
-/* Read up to 255 sectors
- *
- * Returns sectors read
-*/
-static u8 do_one_read(struct ata_port *ap, u64 blknr, u8 blkcnt, u16 *buffer,
- uchar lba48)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- u8 sr = 0;
- u8 status;
- u16 err = 0;
-
- if (!(bfin_check_status(ap) & ATA_DRDY)) {
- printf("Device ata%d not ready\n", ap->port_no);
- return 0;
- }
-
- /* Set up transfer */
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- write_atapi_register(base, ATA_REG_NSECT, 0);
- write_atapi_register(base, ATA_REG_LBAL, (blknr >> 24) & 0xFF);
- write_atapi_register(base, ATA_REG_LBAM, (blknr >> 32) & 0xFF);
- write_atapi_register(base, ATA_REG_LBAH, (blknr >> 40) & 0xFF);
- }
-#endif
- write_atapi_register(base, ATA_REG_NSECT, blkcnt);
- write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
- write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
- write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
-
-#ifdef CONFIG_LBA48
- if (lba48) {
- write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
- write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ_EXT);
- } else
-#endif
- {
- write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA | ((blknr >> 24) & 0xF));
- write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ);
- }
- status = bfin_ata_busy_wait(ap, ATA_BUSY, 500000, 1);
-
- if (status & (ATA_BUSY | ATA_ERR)) {
- printf("Device %d not responding status 0x%x.\n", ap->port_no, status);
- err = read_atapi_register(base, ATA_REG_ERR);
- printf("Error reg = 0x%x\n", err);
- return sr;
- }
-
- while (blkcnt--) {
- if (bfin_wait_for_irq(ap, 500)) {
- printf("ata%u irq failed\n", ap->port_no);
- return sr;
- }
-
- status = bfin_check_status(ap);
- if (status & ATA_ERR) {
- err = read_atapi_register(base, ATA_REG_ERR);
- printf("ata%u error %d\n", ap->port_no, err);
- return sr;
- }
- bfin_irq_clear(ap);
-
- /* Read one sector */
- read_atapi_data(base, ATA_SECTOR_WORDS, buffer);
- buffer += ATA_SECTOR_WORDS;
- sr++;
- }
-
- return sr;
-}
-
-ulong sata_read(int dev, ulong block, lbaint_t blkcnt, void *buff)
-{
- struct ata_port *ap = &port[dev];
- ulong n = 0, sread;
- u16 *buffer = (u16 *) buff;
- u8 status = 0;
- u64 blknr = (u64) block;
- unsigned char lba48 = 0;
-
-#ifdef CONFIG_LBA48
- if (blknr > 0xfffffff) {
- if (!sata_dev_desc[dev].lba48) {
- printf("Drive doesn't support 48-bit addressing\n");
- return 0;
- }
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
- bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
-
- while (blkcnt > 0) {
-
- if (blkcnt > 255)
- sread = 255;
- else
- sread = blkcnt;
-
- status = do_one_read(ap, blknr, sread, buffer, lba48);
- if (status != sread) {
- printf("Read failed\n");
- return n;
- }
-
- blkcnt -= sread;
- blknr += sread;
- n += sread;
- buffer += sread * ATA_SECTOR_WORDS;
- }
- return n;
-}
-
-ulong sata_write(int dev, ulong block, lbaint_t blkcnt, const void *buff)
-{
- struct ata_port *ap = &port[dev];
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- ulong n = 0;
- u16 *buffer = (u16 *) buff;
- unsigned char status = 0;
- u64 blknr = (u64) block;
-#ifdef CONFIG_LBA48
- unsigned char lba48 = 0;
-
- if (blknr > 0xfffffff) {
- if (!sata_dev_desc[dev].lba48) {
- printf("Drive doesn't support 48-bit addressing\n");
- return 0;
- }
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
-
- bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
-
- while (blkcnt-- > 0) {
- status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
- if (status & ATA_BUSY) {
- printf("ata%u failed to respond\n", ap->port_no);
- return n;
- }
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- write_atapi_register(base, ATA_REG_NSECT, 0);
- write_atapi_register(base, ATA_REG_LBAL,
- (blknr >> 24) & 0xFF);
- write_atapi_register(base, ATA_REG_LBAM,
- (blknr >> 32) & 0xFF);
- write_atapi_register(base, ATA_REG_LBAH,
- (blknr >> 40) & 0xFF);
- }
-#endif
- write_atapi_register(base, ATA_REG_NSECT, 1);
- write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
- write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
- write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
-#ifdef CONFIG_LBA48
- if (lba48) {
- write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
- write_atapi_register(base, ATA_REG_CMD,
- ATA_CMD_PIO_WRITE_EXT);
- } else
-#endif
- {
- write_atapi_register(base, ATA_REG_DEVICE,
- ATA_LBA | ((blknr >> 24) & 0xF));
- write_atapi_register(base, ATA_REG_CMD,
- ATA_CMD_PIO_WRITE);
- }
-
- /*may take up to 5 sec */
- status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
- if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
- printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
- ap->port_no, (ulong) blknr, status);
- return n;
- }
-
- write_atapi_data(base, ATA_SECTOR_WORDS, buffer);
- bfin_check_altstatus(ap);
- udelay(1);
-
- ++n;
- ++blknr;
- buffer += ATA_SECTOR_WORDS;
- }
- return n;
-}
+++ /dev/null
-/*
- * Driver for Blackfin on-chip ATAPI controller.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (c) 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef PATA_BFIN_H
-#define PATA_BFIN_H
-
-#include <asm/blackfin_local.h>
-
-struct ata_ioports {
- unsigned long cmd_addr;
- unsigned long data_addr;
- unsigned long error_addr;
- unsigned long feature_addr;
- unsigned long nsect_addr;
- unsigned long lbal_addr;
- unsigned long lbam_addr;
- unsigned long lbah_addr;
- unsigned long device_addr;
- unsigned long status_addr;
- unsigned long command_addr;
- unsigned long altstatus_addr;
- unsigned long ctl_addr;
- unsigned long bmdma_addr;
- unsigned long scr_addr;
-};
-
-struct ata_port {
- unsigned int port_no; /* primary=0, secondary=1 */
- struct ata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
- unsigned long flag;
- unsigned int ata_mode;
- unsigned char ctl_reg;
- unsigned char last_ctl;
- unsigned char dev_mask;
-};
-
-#define DRV_NAME "pata-bfin"
-#define DRV_VERSION "0.9"
-
-#define ATA_REG_CTRL 0x0E
-#define ATA_REG_ALTSTATUS ATA_REG_CTRL
-#define ATA_TMOUT_BOOT 30000
-#define ATA_TMOUT_BOOT_QUICK 7000
-
-#define PATA_BFIN_WAIT_TIMEOUT 10000
-#define PATA_DEV_NUM_PER_PORT 2
-
-/* These are the offset of the controller's registers */
-#define ATAPI_OFFSET_CONTROL 0x00
-#define ATAPI_OFFSET_STATUS 0x04
-#define ATAPI_OFFSET_DEV_ADDR 0x08
-#define ATAPI_OFFSET_DEV_TXBUF 0x0c
-#define ATAPI_OFFSET_DEV_RXBUF 0x10
-#define ATAPI_OFFSET_INT_MASK 0x14
-#define ATAPI_OFFSET_INT_STATUS 0x18
-#define ATAPI_OFFSET_XFER_LEN 0x1c
-#define ATAPI_OFFSET_LINE_STATUS 0x20
-#define ATAPI_OFFSET_SM_STATE 0x24
-#define ATAPI_OFFSET_TERMINATE 0x28
-#define ATAPI_OFFSET_PIO_TFRCNT 0x2c
-#define ATAPI_OFFSET_DMA_TFRCNT 0x30
-#define ATAPI_OFFSET_UMAIN_TFRCNT 0x34
-#define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38
-#define ATAPI_OFFSET_REG_TIM_0 0x40
-#define ATAPI_OFFSET_PIO_TIM_0 0x44
-#define ATAPI_OFFSET_PIO_TIM_1 0x48
-#define ATAPI_OFFSET_MULTI_TIM_0 0x50
-#define ATAPI_OFFSET_MULTI_TIM_1 0x54
-#define ATAPI_OFFSET_MULTI_TIM_2 0x58
-#define ATAPI_OFFSET_ULTRA_TIM_0 0x60
-#define ATAPI_OFFSET_ULTRA_TIM_1 0x64
-#define ATAPI_OFFSET_ULTRA_TIM_2 0x68
-#define ATAPI_OFFSET_ULTRA_TIM_3 0x6c
-
-
-#define ATAPI_GET_CONTROL(base)\
- bfin_read16(base + ATAPI_OFFSET_CONTROL)
-#define ATAPI_SET_CONTROL(base, val)\
- bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
-#define ATAPI_GET_STATUS(base)\
- bfin_read16(base + ATAPI_OFFSET_STATUS)
-#define ATAPI_GET_DEV_ADDR(base)\
- bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
-#define ATAPI_SET_DEV_ADDR(base, val)\
- bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
-#define ATAPI_GET_DEV_TXBUF(base)\
- bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
-#define ATAPI_SET_DEV_TXBUF(base, val)\
- bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
-#define ATAPI_GET_DEV_RXBUF(base)\
- bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
-#define ATAPI_SET_DEV_RXBUF(base, val)\
- bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
-#define ATAPI_GET_INT_MASK(base)\
- bfin_read16(base + ATAPI_OFFSET_INT_MASK)
-#define ATAPI_SET_INT_MASK(base, val)\
- bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
-#define ATAPI_GET_INT_STATUS(base)\
- bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
-#define ATAPI_SET_INT_STATUS(base, val)\
- bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
-#define ATAPI_GET_XFER_LEN(base)\
- bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
-#define ATAPI_SET_XFER_LEN(base, val)\
- bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
-#define ATAPI_GET_LINE_STATUS(base)\
- bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
-#define ATAPI_GET_SM_STATE(base)\
- bfin_read16(base + ATAPI_OFFSET_SM_STATE)
-#define ATAPI_GET_TERMINATE(base)\
- bfin_read16(base + ATAPI_OFFSET_TERMINATE)
-#define ATAPI_SET_TERMINATE(base, val)\
- bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
-#define ATAPI_GET_PIO_TFRCNT(base)\
- bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
-#define ATAPI_GET_DMA_TFRCNT(base)\
- bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
-#define ATAPI_GET_UMAIN_TFRCNT(base)\
- bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
-#define ATAPI_GET_UDMAOUT_TFRCNT(base)\
- bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
-#define ATAPI_GET_REG_TIM_0(base)\
- bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
-#define ATAPI_SET_REG_TIM_0(base, val)\
- bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
-#define ATAPI_GET_PIO_TIM_0(base)\
- bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
-#define ATAPI_SET_PIO_TIM_0(base, val)\
- bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
-#define ATAPI_GET_PIO_TIM_1(base)\
- bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
-#define ATAPI_SET_PIO_TIM_1(base, val)\
- bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
-#define ATAPI_GET_MULTI_TIM_0(base)\
- bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
-#define ATAPI_SET_MULTI_TIM_0(base, val)\
- bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
-#define ATAPI_GET_MULTI_TIM_1(base)\
- bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
-#define ATAPI_SET_MULTI_TIM_1(base, val)\
- bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
-#define ATAPI_GET_MULTI_TIM_2(base)\
- bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
-#define ATAPI_SET_MULTI_TIM_2(base, val)\
- bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
-#define ATAPI_GET_ULTRA_TIM_0(base)\
- bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
-#define ATAPI_SET_ULTRA_TIM_0(base, val)\
- bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
-#define ATAPI_GET_ULTRA_TIM_1(base)\
- bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
-#define ATAPI_SET_ULTRA_TIM_1(base, val)\
- bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
-#define ATAPI_GET_ULTRA_TIM_2(base)\
- bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
-#define ATAPI_SET_ULTRA_TIM_2(base, val)\
- bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
-#define ATAPI_GET_ULTRA_TIM_3(base)\
- bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
-#define ATAPI_SET_ULTRA_TIM_3(base, val)\
- bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
-
-#endif
endif
obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
-obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
obj-$(CONFIG_MMC_DAVINCI) += davinci_mmc.o
obj-$(CONFIG_MMC_DW) += dw_mmc.o
+++ /dev/null
-/*
- * Driver for Blackfin on-chip SDH controller
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <part.h>
-#include <mmc.h>
-
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/byteorder.h>
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/sdh.h>
-#include <asm/mach-common/bits/dma.h>
-
-#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF60x__)
-# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
-# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
-# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
-# define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
-# define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
-# define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
-# define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
-# define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
-# define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
-# define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
-# define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL
-# define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL
-# define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
-# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
-# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
-# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
-# if defined(__ADSPBF60x__)
-# define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ
-# define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ
-# define bfin_write_DMA_START_ADDR bfin_write_DMA10_START_ADDR
-# define bfin_write_DMA_X_COUNT bfin_write_DMA10_X_COUNT
-# define bfin_write_DMA_X_MODIFY bfin_write_DMA10_X_MODIFY
-# define bfin_write_DMA_CONFIG bfin_write_DMA10_CONFIG
-# else
-# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
-# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
-# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
-# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
-# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
-# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
-# endif
-# define PORTMUX_PINS \
- { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
-#elif defined(__ADSPBF54x__)
-# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
-# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
-# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
-# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
-# define PORTMUX_PINS \
- { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
-#else
-# error no support for this proc yet
-#endif
-
-static int
-sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
-{
- unsigned int status, timeout;
- int cmd = mmc_cmd->cmdidx;
- int flags = mmc_cmd->resp_type;
- int arg = mmc_cmd->cmdarg;
- int ret;
- u16 sdh_cmd;
-
- sdh_cmd = cmd | CMD_E;
- if (flags & MMC_RSP_PRESENT)
- sdh_cmd |= CMD_RSP;
- if (flags & MMC_RSP_136)
- sdh_cmd |= CMD_L_RSP;
-#ifdef RSI_BLKSZ
- sdh_cmd |= CMD_DATA0_BUSY;
-#endif
-
- bfin_write_SDH_ARGUMENT(arg);
- bfin_write_SDH_COMMAND(sdh_cmd);
-
- /* wait for a while */
- timeout = 0;
- do {
- if (++timeout > 1000000) {
- status = CMD_TIME_OUT;
- break;
- }
- udelay(1);
- status = bfin_read_SDH_STATUS();
- } while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
- CMD_CRC_FAIL)));
-
- if (flags & MMC_RSP_PRESENT) {
- mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
- if (flags & MMC_RSP_136) {
- mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
- mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
- mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
- }
- }
-
- if (status & CMD_TIME_OUT)
- ret = -ETIMEDOUT;
- else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
- ret = -ECOMM;
- else
- ret = 0;
-
- bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
- CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
-#ifdef RSI_BLKSZ
- /* wait till card ready */
- while (!(bfin_read_RSI_ESTAT() & SD_CARD_READY))
- continue;
- bfin_write_RSI_ESTAT(SD_CARD_READY);
-#endif
-
- return ret;
-}
-
-/* set data for single block transfer */
-static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
-{
- u16 data_ctl = 0;
- u16 dma_cfg = 0;
- unsigned long data_size = data->blocksize * data->blocks;
-
- /* Don't support write yet. */
- if (data->flags & MMC_DATA_WRITE)
- return -EOPNOTSUPP;
-#ifndef RSI_BLKSZ
- data_ctl |= ((ffs(data->blocksize) - 1) << 4);
-#else
- bfin_write_SDH_BLK_SIZE(data->blocksize);
-#endif
- data_ctl |= DTX_DIR;
- bfin_write_SDH_DATA_CTL(data_ctl);
- dma_cfg = WDSIZE_32 | PSIZE_32 | RESTART | WNR | DMAEN;
-
- bfin_write_SDH_DATA_TIMER(-1);
-
- blackfin_dcache_flush_invalidate_range(data->dest,
- data->dest + data_size);
- /* configure DMA */
- bfin_write_DMA_START_ADDR(data->dest);
- bfin_write_DMA_X_COUNT(data_size / 4);
- bfin_write_DMA_X_MODIFY(4);
- bfin_write_DMA_CONFIG(dma_cfg);
- bfin_write_SDH_DATA_LGTH(data_size);
- /* kick off transfer */
- bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
-
- return 0;
-}
-
-
-static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
-{
- u32 status;
- int ret = 0;
-
- if (data) {
- ret = sdh_setup_data(mmc, data);
- if (ret)
- return ret;
- }
-
- ret = sdh_send_cmd(mmc, cmd);
- if (ret) {
- bfin_write_SDH_COMMAND(0);
- bfin_write_DMA_CONFIG(0);
- bfin_write_SDH_DATA_CTL(0);
- SSYNC();
- printf("sending CMD%d failed\n", cmd->cmdidx);
- return ret;
- }
-
- if (data) {
- do {
- udelay(1);
- status = bfin_read_SDH_STATUS();
- } while (!(status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
- RX_OVERRUN)));
-
- if (status & DAT_TIME_OUT) {
- bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
- ret = -ETIMEDOUT;
- } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
- bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
- ret = -ECOMM;
- } else
- bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
-
- if (ret) {
- printf("tranfering data failed\n");
- return ret;
- }
- }
- return 0;
-}
-
-static void sdh_set_clk(unsigned long clk)
-{
- unsigned long sys_clk;
- unsigned long clk_div;
- u16 clk_ctl = 0;
-
- clk_ctl = bfin_read_SDH_CLK_CTL();
- if (clk) {
- /* setting SD_CLK */
- sys_clk = get_sclk();
- bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
- if (sys_clk % (2 * clk) == 0)
- clk_div = sys_clk / (2 * clk) - 1;
- else
- clk_div = sys_clk / (2 * clk);
-
- if (clk_div > 0xff)
- clk_div = 0xff;
- clk_ctl |= (clk_div & 0xff);
- clk_ctl |= CLK_E;
- bfin_write_SDH_CLK_CTL(clk_ctl);
- } else
- bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
-}
-
-static int bfin_sdh_set_ios(struct mmc *mmc)
-{
- u16 cfg = 0;
- u16 clk_ctl = 0;
-
- if (mmc->bus_width == 4) {
- cfg = bfin_read_SDH_CFG();
-#ifndef RSI_BLKSZ
- cfg &= ~PD_SDDAT3;
-#endif
- cfg |= PUP_SDDAT3;
- bfin_write_SDH_CFG(cfg);
- clk_ctl |= WIDE_BUS_4;
- }
- bfin_write_SDH_CLK_CTL(clk_ctl);
- sdh_set_clk(mmc->clock);
-
- return 0;
-}
-
-static int bfin_sdh_init(struct mmc *mmc)
-{
- const unsigned short pins[] = PORTMUX_PINS;
- int ret;
-
- /* Initialize sdh controller */
- ret = peripheral_request_list(pins, "bfin_sdh");
- if (ret < 0)
- return ret;
-#if defined(__ADSPBF54x__)
- bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
-#endif
- bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
- /* Disable card detect pin */
- bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
-#ifndef RSI_BLKSZ
- bfin_write_SDH_PWR_CTL(PWR_ON | ROD_CTL);
-#else
- bfin_write_SDH_CFG(bfin_read_SDH_CFG() | PWR_ON);
-#endif
- return 0;
-}
-
-static const struct mmc_ops bfin_mmc_ops = {
- .send_cmd = bfin_sdh_request,
- .set_ios = bfin_sdh_set_ios,
- .init = bfin_sdh_init,
-};
-
-static struct mmc_config bfin_mmc_cfg = {
- .name = "Blackfin SDH",
- .ops = &bfin_mmc_ops,
- .host_caps = MMC_MODE_4BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
-};
-
-int bfin_mmc_init(bd_t *bis)
-{
- struct mmc *mmc;
-
- bfin_mmc_cfg.f_max = get_sclk();
- bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9;
-
- mmc = mmc_create(&bfin_mmc_cfg, NULL);
- if (mmc == NULL)
- return -1;
-
- return 0;
-}
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
-obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
obj-$(CONFIG_NAND_DENALI) += denali.o
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
+++ /dev/null
-/*
- * Driver for Blackfin on-chip NAND controller.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/* TODO:
- * - move bit defines into mach-common/bits/nand.h
- * - try and replace all IRQSTAT usage with STAT polling
- * - have software ecc mode use same algo as hw ecc ?
- */
-
-#include <common.h>
-#include <console.h>
-#include <asm/io.h>
-
-#ifdef DEBUG
-# define pr_stamp() printf("%s:%s:%i: here i am\n", __FILE__, __func__, __LINE__)
-#else
-# define pr_stamp()
-#endif
-
-#include <nand.h>
-
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-
-/* Bit masks for NFC_CTL */
-
-#define WR_DLY 0xf /* Write Strobe Delay */
-#define RD_DLY 0xf0 /* Read Strobe Delay */
-#define NWIDTH 0x100 /* NAND Data Width */
-#define PG_SIZE 0x200 /* Page Size */
-
-/* Bit masks for NFC_STAT */
-
-#define NBUSY 0x1 /* Not Busy */
-#define WB_FULL 0x2 /* Write Buffer Full */
-#define PG_WR_STAT 0x4 /* Page Write Pending */
-#define PG_RD_STAT 0x8 /* Page Read Pending */
-#define WB_EMPTY 0x10 /* Write Buffer Empty */
-
-/* Bit masks for NFC_IRQSTAT */
-
-#define NBUSYIRQ 0x1 /* Not Busy IRQ */
-#define WB_OVF 0x2 /* Write Buffer Overflow */
-#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
-#define RD_RDY 0x8 /* Read Data Ready */
-#define WR_DONE 0x10 /* Page Write Done */
-
-#define NAND_IS_512() (CONFIG_BFIN_NFC_CTL_VAL & 0x200)
-
-/*
- * hardware specific access to control-lines
- */
-static void bfin_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- pr_stamp();
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- while (bfin_read_NFC_STAT() & WB_FULL)
- continue;
-
- if (ctrl & NAND_CLE)
- bfin_write_NFC_CMD(cmd);
- else
- bfin_write_NFC_ADDR(cmd);
- SSYNC();
-}
-
-static int bfin_nfc_devready(struct mtd_info *mtd)
-{
- pr_stamp();
- return (bfin_read_NFC_STAT() & NBUSY) ? 1 : 0;
-}
-
-/*
- * PIO mode for buffer writing and reading
- */
-static void bfin_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- pr_stamp();
-
- int i;
-
- /*
- * Data reads are requested by first writing to NFC_DATA_RD
- * and then reading back from NFC_READ.
- */
- for (i = 0; i < len; ++i) {
- while (bfin_read_NFC_STAT() & WB_FULL)
- if (ctrlc())
- return;
-
- /* Contents do not matter */
- bfin_write_NFC_DATA_RD(0x0000);
- SSYNC();
-
- while (!(bfin_read_NFC_IRQSTAT() & RD_RDY))
- if (ctrlc())
- return;
-
- buf[i] = bfin_read_NFC_READ();
-
- bfin_write_NFC_IRQSTAT(RD_RDY);
- }
-}
-
-static uint8_t bfin_nfc_read_byte(struct mtd_info *mtd)
-{
- pr_stamp();
-
- uint8_t val;
- bfin_nfc_read_buf(mtd, &val, 1);
- return val;
-}
-
-static void bfin_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
- pr_stamp();
-
- int i;
-
- for (i = 0; i < len; ++i) {
- while (bfin_read_NFC_STAT() & WB_FULL)
- if (ctrlc())
- return;
-
- bfin_write_NFC_DATA_WR(buf[i]);
- }
-
- /* Wait for the buffer to drain before we return */
- while (!(bfin_read_NFC_STAT() & WB_EMPTY))
- if (ctrlc())
- return;
-}
-
-/*
- * ECC functions
- * These allow the bfin to use the controller's ECC
- * generator block to ECC the data as it passes through
- */
-
-/*
- * ECC error correction function
- */
-static int bfin_nfc_correct_data_256(struct mtd_info *mtd, u_char *dat,
- u_char *read_ecc, u_char *calc_ecc)
-{
- u32 syndrome[5];
- u32 calced, stored;
- unsigned short failing_bit, failing_byte;
- u_char data;
-
- pr_stamp();
-
- calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
- stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
-
- syndrome[0] = (calced ^ stored);
-
- /*
- * syndrome 0: all zero
- * No error in data
- * No action
- */
- if (!syndrome[0] || !calced || !stored)
- return 0;
-
- /*
- * sysdrome 0: only one bit is one
- * ECC data was incorrect
- * No action
- */
- if (hweight32(syndrome[0]) == 1)
- return 1;
-
- syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
- syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
- syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
- syndrome[4] = syndrome[2] ^ syndrome[3];
-
- /*
- * sysdrome 0: exactly 11 bits are one, each parity
- * and parity' pair is 1 & 0 or 0 & 1.
- * 1-bit correctable error
- * Correct the error
- */
- if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
- failing_bit = syndrome[1] & 0x7;
- failing_byte = syndrome[1] >> 0x3;
- data = *(dat + failing_byte);
- data = data ^ (0x1 << failing_bit);
- *(dat + failing_byte) = data;
-
- return 0;
- }
-
- /*
- * sysdrome 0: random data
- * More than 1-bit error, non-correctable error
- * Discard data, mark bad block
- */
-
- return 1;
-}
-
-static int bfin_nfc_correct_data(struct mtd_info *mtd, u_char *dat,
- u_char *read_ecc, u_char *calc_ecc)
-{
- int ret;
-
- pr_stamp();
-
- ret = bfin_nfc_correct_data_256(mtd, dat, read_ecc, calc_ecc);
-
- /* If page size is 512, correct second 256 bytes */
- if (NAND_IS_512()) {
- dat += 256;
- read_ecc += 8;
- calc_ecc += 8;
- ret |= bfin_nfc_correct_data_256(mtd, dat, read_ecc, calc_ecc);
- }
-
- return ret;
-}
-
-static void reset_ecc(void)
-{
- bfin_write_NFC_RST(0x1);
- while (bfin_read_NFC_RST() & 1)
- continue;
-}
-
-static void bfin_nfc_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- reset_ecc();
-}
-
-static int bfin_nfc_calculate_ecc(struct mtd_info *mtd,
- const u_char *dat, u_char *ecc_code)
-{
- u16 ecc0, ecc1;
- u32 code[2];
- u8 *p;
-
- pr_stamp();
-
- /* first 4 bytes ECC code for 256 page size */
- ecc0 = bfin_read_NFC_ECC0();
- ecc1 = bfin_read_NFC_ECC1();
-
- code[0] = (ecc0 & 0x7FF) | ((ecc1 & 0x7FF) << 11);
-
- /* first 3 bytes in ecc_code for 256 page size */
- p = (u8 *) code;
- memcpy(ecc_code, p, 3);
-
- /* second 4 bytes ECC code for 512 page size */
- if (NAND_IS_512()) {
- ecc0 = bfin_read_NFC_ECC2();
- ecc1 = bfin_read_NFC_ECC3();
- code[1] = (ecc0 & 0x7FF) | ((ecc1 & 0x7FF) << 11);
-
- /* second 3 bytes in ecc_code for second 256
- * bytes of 512 page size
- */
- p = (u8 *) (code + 1);
- memcpy((ecc_code + 3), p, 3);
- }
-
- reset_ecc();
-
- return 0;
-}
-
-#ifdef CONFIG_BFIN_NFC_BOOTROM_ECC
-# define BOOTROM_ECC 1
-#else
-# define BOOTROM_ECC 0
-#endif
-
-static uint8_t bbt_pattern[] = { 0xff };
-
-static struct nand_bbt_descr bootrom_bbt = {
- .options = 0,
- .offs = 63,
- .len = 1,
- .pattern = bbt_pattern,
-};
-
-static struct nand_ecclayout bootrom_ecclayout = {
- .eccbytes = 24,
- .eccpos = {
- 0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2,
- 0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2,
- 0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2,
- 0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2,
- 0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2,
- 0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2,
- 0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2,
- 0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2
- },
- .oobfree = {
- { 0x8 * 0 + 3, 5 },
- { 0x8 * 1 + 3, 5 },
- { 0x8 * 2 + 3, 5 },
- { 0x8 * 3 + 3, 5 },
- { 0x8 * 4 + 3, 5 },
- { 0x8 * 5 + 3, 5 },
- { 0x8 * 6 + 3, 5 },
- { 0x8 * 7 + 3, 5 },
- }
-};
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - cmd_ctrl: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
- * only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- * read regs (tR)
- * - options: various chip options. They can partly be set to inform
- * nand_scan about special functionality. See the defines for further
- * explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *chip)
-{
- const unsigned short pins[] = {
- P_NAND_CE, P_NAND_RB, P_NAND_D0, P_NAND_D1, P_NAND_D2,
- P_NAND_D3, P_NAND_D4, P_NAND_D5, P_NAND_D6, P_NAND_D7,
- P_NAND_WE, P_NAND_RE, P_NAND_CLE, P_NAND_ALE, 0,
- };
-
- pr_stamp();
-
- /* set width/ecc/timings/etc... */
- bfin_write_NFC_CTL(CONFIG_BFIN_NFC_CTL_VAL);
-
- /* clear interrupt status */
- bfin_write_NFC_IRQMASK(0x0);
- bfin_write_NFC_IRQSTAT(0xffff);
-
- /* enable GPIO function enable register */
- peripheral_request_list(pins, "bfin_nand");
-
- chip->cmd_ctrl = bfin_nfc_cmd_ctrl;
- chip->read_buf = bfin_nfc_read_buf;
- chip->write_buf = bfin_nfc_write_buf;
- chip->read_byte = bfin_nfc_read_byte;
-
-#ifdef CONFIG_BFIN_NFC_NO_HW_ECC
-# define ECC_HW 0
-#else
-# define ECC_HW 1
-#endif
- if (ECC_HW) {
- if (BOOTROM_ECC) {
- chip->badblock_pattern = &bootrom_bbt;
- chip->ecc.layout = &bootrom_ecclayout;
- }
- if (!NAND_IS_512()) {
- chip->ecc.bytes = 3;
- chip->ecc.size = 256;
- chip->ecc.strength = 1;
- } else {
- chip->ecc.bytes = 6;
- chip->ecc.size = 512;
- chip->ecc.strength = 2;
- }
- chip->ecc.mode = NAND_ECC_HW;
- chip->ecc.calculate = bfin_nfc_calculate_ecc;
- chip->ecc.correct = bfin_nfc_correct_data;
- chip->ecc.hwctl = bfin_nfc_enable_hwecc;
- } else
- chip->ecc.mode = NAND_ECC_SOFT;
- chip->dev_ready = bfin_nfc_devready;
- chip->chip_delay = 0;
-
- return 0;
-}
obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
-obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
obj-$(CONFIG_CS8900) += cs8900.o
obj-$(CONFIG_TULIP) += dc2114x.o
+++ /dev/null
-/*
- * Driver for Blackfin On-Chip MAC device
- *
- * Copyright (c) 2005-2008 Analog Device, Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <net.h>
-#include <netdev.h>
-#include <command.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <linux/mdio.h>
-#include <linux/mii.h>
-
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/dma.h>
-#include <asm/mach-common/bits/emac.h>
-#include <asm/mach-common/bits/pll.h>
-
-#include "bfin_mac.h"
-
-#ifndef CONFIG_PHY_ADDR
-# define CONFIG_PHY_ADDR 1
-#endif
-#ifndef CONFIG_PHY_CLOCK_FREQ
-# define CONFIG_PHY_CLOCK_FREQ 2500000
-#endif
-
-#ifdef CONFIG_POST
-#include <post.h>
-#endif
-
-#define RXBUF_BASE_ADDR 0xFF900000
-#define TXBUF_BASE_ADDR 0xFF800000
-#define TX_BUF_CNT 1
-
-#define TOUT_LOOP 1000000
-
-static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
-static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
-static u16 txIdx; /* index of the current RX buffer */
-static u16 rxIdx; /* index of the current TX buffer */
-
-/* DMAx_CONFIG values at DMA Restart */
-static const union {
- u16 data;
- ADI_DMA_CONFIG_REG reg;
-} txdmacfg = {
- .reg = {
- .b_DMA_EN = 1, /* enabled */
- .b_WNR = 0, /* read from memory */
- .b_WDSIZE = 2, /* wordsize is 32 bits */
- .b_DMA2D = 0,
- .b_RESTART = 0,
- .b_DI_SEL = 0,
- .b_DI_EN = 0, /* no interrupt */
- .b_NDSIZE = 5, /* 5 half words is desc size */
- .b_FLOW = 7 /* large desc flow */
- },
-};
-
-static int bfin_miiphy_wait(void)
-{
- /* poll the STABUSY bit */
- while (bfin_read_EMAC_STAADD() & STABUSY)
- continue;
- return 0;
-}
-
-static int bfin_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- ushort val = 0;
- if (bfin_miiphy_wait())
- return 1;
- bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
- if (bfin_miiphy_wait())
- return 1;
- val = bfin_read_EMAC_STADAT();
- return val;
-}
-
-static int bfin_miiphy_write(struct mii_dev *bus, int addr, int devad,
- int reg, u16 val)
-{
- if (bfin_miiphy_wait())
- return 1;
- bfin_write_EMAC_STADAT(val);
- bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
- return 0;
-}
-
-int bfin_EMAC_initialize(bd_t *bis)
-{
- struct eth_device *dev;
- dev = malloc(sizeof(*dev));
- if (dev == NULL)
- hang();
-
- memset(dev, 0, sizeof(*dev));
- strcpy(dev->name, "bfin_mac");
-
- dev->iobase = 0;
- dev->priv = 0;
- dev->init = bfin_EMAC_init;
- dev->halt = bfin_EMAC_halt;
- dev->send = bfin_EMAC_send;
- dev->recv = bfin_EMAC_recv;
- dev->write_hwaddr = bfin_EMAC_setup_addr;
-
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = bfin_miiphy_read;
- mdiodev->write = bfin_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-
- dev->priv = mdiodev;
-#endif
-
- return 0;
-}
-
-static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length)
-{
- int i;
- int result = 0;
-
- if (length <= 0) {
- printf("Ethernet: bad packet size: %d\n", length);
- goto out;
- }
-
- if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
- printf("Ethernet: tx DMA error\n");
- goto out;
- }
-
- for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
- if (i > TOUT_LOOP) {
- puts("Ethernet: tx time out\n");
- goto out;
- }
- }
- txbuf[txIdx]->FrmData->NoBytes = length;
- memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
- txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
- bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
- bfin_write_DMA2_CONFIG(txdmacfg.data);
- bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
-
- for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
- if (i > TOUT_LOOP) {
- puts("Ethernet: tx error\n");
- goto out;
- }
- }
- result = txbuf[txIdx]->StatusWord;
- txbuf[txIdx]->StatusWord = 0;
- if ((txIdx + 1) >= TX_BUF_CNT)
- txIdx = 0;
- else
- txIdx++;
- out:
- debug("BFIN EMAC send: length = %d\n", length);
- return result;
-}
-
-static int bfin_EMAC_recv(struct eth_device *dev)
-{
- int length = 0;
-
- for (;;) {
- if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
- length = -1;
- break;
- }
- if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
- printf("Ethernet: rx dma overrun\n");
- break;
- }
- if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
- printf("Ethernet: rx error\n");
- break;
- }
- length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
- if (length <= 4) {
- printf("Ethernet: bad frame\n");
- break;
- }
-
- debug("%s: len = %d\n", __func__, length - 4);
-
- net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
- net_process_received_packet(net_rx_packets[rxIdx], length - 4);
- bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
- rxbuf[rxIdx]->StatusWord = 0x00000000;
- if ((rxIdx + 1) >= PKTBUFSRX)
- rxIdx = 0;
- else
- rxIdx++;
- }
-
- return length;
-}
-
-/**************************************************************
- *
- * Ethernet Initialization Routine
- *
- *************************************************************/
-
-/* MDC = SCLK / MDC_freq / 2 - 1 */
-#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
-
-#ifndef CONFIG_BFIN_MAC_PINS
-# ifdef CONFIG_RMII
-# define CONFIG_BFIN_MAC_PINS P_RMII0
-# else
-# define CONFIG_BFIN_MAC_PINS P_MII0
-# endif
-#endif
-
-static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
-{
- const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
- int phydat;
- size_t count;
- struct mii_dev *mdiodev = dev->priv;
-
- /* Enable PHY output */
- bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
-
- /* Set all the pins to peripheral mode */
- peripheral_request_list(pins, "bfin_mac");
-
- /* Odd word alignment for Receive Frame DMA word */
- /* Configure checksum support and rcve frame word alignment */
- bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
-
- /* turn on auto-negotiation and wait for link to come up */
- bfin_miiphy_write(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE, MII_BMCR,
- BMCR_ANENABLE);
- count = 0;
- while (1) {
- ++count;
- phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR,
- MDIO_DEVAD_NONE, MII_BMSR);
- if (phydat < 0)
- return phydat;
- if (phydat & BMSR_LSTATUS)
- break;
- if (count > 30000) {
- printf("%s: link down, check cable\n", dev->name);
- return -1;
- }
- udelay(100);
- }
-
- /* see what kind of link we have */
- phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE,
- MII_LPA);
- if (phydat < 0)
- return phydat;
- if (phydat & LPA_DUPLEX)
- *opmode = FDMODE;
- else
- *opmode = 0;
-
- bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
- bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
- bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);
-
- /* Initialize the TX DMA channel registers */
- bfin_write_DMA2_X_COUNT(0);
- bfin_write_DMA2_X_MODIFY(4);
- bfin_write_DMA2_Y_COUNT(0);
- bfin_write_DMA2_Y_MODIFY(0);
-
- /* Initialize the RX DMA channel registers */
- bfin_write_DMA1_X_COUNT(0);
- bfin_write_DMA1_X_MODIFY(4);
- bfin_write_DMA1_Y_COUNT(0);
- bfin_write_DMA1_Y_MODIFY(0);
-
- return 0;
-}
-
-static int bfin_EMAC_setup_addr(struct eth_device *dev)
-{
- bfin_write_EMAC_ADDRLO(
- dev->enetaddr[0] |
- dev->enetaddr[1] << 8 |
- dev->enetaddr[2] << 16 |
- dev->enetaddr[3] << 24
- );
- bfin_write_EMAC_ADDRHI(
- dev->enetaddr[4] |
- dev->enetaddr[5] << 8
- );
- return 0;
-}
-
-static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
-{
- u32 opmode;
- int dat;
- int i;
- debug("Eth_init: ......\n");
-
- txIdx = 0;
- rxIdx = 0;
-
- /* Initialize System Register */
- if (bfin_miiphy_init(dev, &dat) < 0)
- return -1;
-
- /* Initialize EMAC address */
- bfin_EMAC_setup_addr(dev);
-
- /* Initialize TX and RX buffer */
- for (i = 0; i < PKTBUFSRX; i++) {
- rxbuf[i] = SetupRxBuffer(i);
- if (i > 0) {
- rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
- if (i == (PKTBUFSRX - 1))
- rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
- }
- }
- for (i = 0; i < TX_BUF_CNT; i++) {
- txbuf[i] = SetupTxBuffer(i);
- if (i > 0) {
- txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
- if (i == (TX_BUF_CNT - 1))
- txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
- }
- }
-
- /* Set RX DMA */
- bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
- bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
-
- /* Wait MII done */
- bfin_miiphy_wait();
-
- /* We enable only RX here */
- /* ASTP : Enable Automatic Pad Stripping
- PR : Promiscuous Mode for test
- PSF : Receive frames with total length less than 64 bytes.
- FDMODE : Full Duplex Mode
- LB : Internal Loopback for test
- RE : Receiver Enable */
- if (dat == FDMODE)
- opmode = ASTP | FDMODE | PSF;
- else
- opmode = ASTP | PSF;
- opmode |= RE;
-#ifdef CONFIG_RMII
- opmode |= TE | RMII;
-#endif
- /* Turn on the EMAC */
- bfin_write_EMAC_OPMODE(opmode);
- return 0;
-}
-
-static void bfin_EMAC_halt(struct eth_device *dev)
-{
- debug("Eth_halt: ......\n");
- /* Turn off the EMAC */
- bfin_write_EMAC_OPMODE(0);
- /* Turn off the EMAC RX DMA */
- bfin_write_DMA1_CONFIG(0);
- bfin_write_DMA2_CONFIG(0);
-}
-
-ADI_ETHER_BUFFER *SetupRxBuffer(int no)
-{
- ADI_ETHER_FRAME_BUFFER *frmbuf;
- ADI_ETHER_BUFFER *buf;
- int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
- int total_size = nobytes_buffer + RECV_BUFSIZE;
-
- buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
- frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
-
- memset(buf, 0x00, nobytes_buffer);
- buf->FrmData = frmbuf;
- memset(frmbuf, 0xfe, RECV_BUFSIZE);
-
- /* set up first desc to point to receive frame buffer */
- buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
- buf->Dma[0].START_ADDR = (u32) buf->FrmData;
- buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
- buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
- buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
- buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
- buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
-
- /* set up second desc to point to status word */
- buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
- buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
- buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
- buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
- buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
- buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
- buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
- buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
-
- return buf;
-}
-
-ADI_ETHER_BUFFER *SetupTxBuffer(int no)
-{
- ADI_ETHER_FRAME_BUFFER *frmbuf;
- ADI_ETHER_BUFFER *buf;
- int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
- int total_size = nobytes_buffer + RECV_BUFSIZE;
-
- buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
- frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
-
- memset(buf, 0x00, nobytes_buffer);
- buf->FrmData = frmbuf;
- memset(frmbuf, 0x00, RECV_BUFSIZE);
-
- /* set up first desc to point to receive frame buffer */
- buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
- buf->Dma[0].START_ADDR = (u32) buf->FrmData;
- buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
- buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
- buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
- buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
- buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
-
- /* set up second desc to point to status word */
- buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
- buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
- buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
- buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
- buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
- buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
- buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
- buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
-
- return buf;
-}
-
-#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
-int ether_post_test(int flags)
-{
- uchar buf[64];
- int i, value = 0;
- int length;
- uint addr;
-
- printf("\n--------");
- bfin_EMAC_init(NULL, NULL);
- /* construct the package */
- addr = bfin_read_EMAC_ADDRLO();
- buf[0] = buf[6] = addr;
- buf[1] = buf[7] = addr >> 8;
- buf[2] = buf[8] = addr >> 16;
- buf[3] = buf[9] = addr >> 24;
- addr = bfin_read_EMAC_ADDRHI();
- buf[4] = buf[10] = addr;
- buf[5] = buf[11] = addr >> 8;
- buf[12] = 0x08; /* Type: ARP */
- buf[13] = 0x06;
- buf[14] = 0x00; /* Hardware type: Ethernet */
- buf[15] = 0x01;
- buf[16] = 0x08; /* Protocal type: IP */
- buf[17] = 0x00;
- buf[18] = 0x06; /* Hardware size */
- buf[19] = 0x04; /* Protocol size */
- buf[20] = 0x00; /* Opcode: request */
- buf[21] = 0x01;
-
- for (i = 0; i < 42; i++)
- buf[i + 22] = i;
- printf("--------Send 64 bytes......\n");
- bfin_EMAC_send(NULL, buf, 64);
- for (i = 0; i < 100; i++) {
- udelay(10000);
- if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
- value = 1;
- break;
- }
- }
- if (value == 0) {
- printf("--------EMAC can't receive any data\n");
- eth_halt();
- return -1;
- }
- length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
- for (i = 0; i < length; i++) {
- if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
- printf("--------EMAC receive error data!\n");
- eth_halt();
- return -1;
- }
- }
- printf("--------receive %d bytes, matched\n", length);
- bfin_EMAC_halt(NULL);
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * bfin_mac.h - some defines/structures for the Blackfin on-chip MAC.
- *
- * Copyright (c) 2005-2008 Analog Device, Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MAC_H__
-#define __BFIN_MAC_H__
-
-#define RECV_BUFSIZE (0x614)
-
-typedef struct ADI_DMA_CONFIG_REG {
- u16 b_DMA_EN:1; /* 0 Enabled */
- u16 b_WNR:1; /* 1 Direction */
- u16 b_WDSIZE:2; /* 2:3 Transfer word size */
- u16 b_DMA2D:1; /* 4 DMA mode */
- u16 b_RESTART:1; /* 5 Retain FIFO */
- u16 b_DI_SEL:1; /* 6 Data interrupt timing select */
- u16 b_DI_EN:1; /* 7 Data interrupt enabled */
- u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */
- u16 b_FLOW:3; /* 12:14Flow */
-} ADI_DMA_CONFIG_REG;
-
-typedef struct adi_ether_frame_buffer {
- u16 NoBytes; /* the no. of following bytes */
- u8 Dest[6]; /* destination MAC address */
- u8 Srce[6]; /* source MAC address */
- u16 LTfield; /* length/type field */
- u8 Data[0]; /* payload bytes */
-} ADI_ETHER_FRAME_BUFFER;
-/* 16 bytes/struct */
-
-typedef struct dma_descriptor {
- struct dma_descriptor *NEXT_DESC_PTR;
- u32 START_ADDR;
- union {
- u16 CONFIG_DATA;
- ADI_DMA_CONFIG_REG CONFIG;
- };
-} DMA_DESCRIPTOR;
-/* 10 bytes/struct in 12 bytes */
-
-typedef struct adi_ether_buffer {
- DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */
- ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
- struct adi_ether_buffer *pNext; /* next buffer */
- struct adi_ether_buffer *pPrev; /* prev buffer */
- u16 IPHdrChksum; /* the IP header checksum */
- u16 IPPayloadChksum; /* the IP header and payload checksum */
- volatile u32 StatusWord; /* the frame status word */
-} ADI_ETHER_BUFFER;
-/* 40 bytes/struct in 44 bytes */
-
-static ADI_ETHER_BUFFER *SetupRxBuffer(int no);
-static ADI_ETHER_BUFFER *SetupTxBuffer(int no);
-
-static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd);
-static void bfin_EMAC_halt(struct eth_device *dev);
-static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length);
-static int bfin_EMAC_recv(struct eth_device *dev);
-static int bfin_EMAC_setup_addr(struct eth_device *dev);
-
-#endif
obj-$(CONFIG_DM_RTC) += rtc-uclass.o
obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o
-obj-$(CONFIG_RTC_BFIN) += bfin_rtc.o
obj-y += date.o
obj-$(CONFIG_RTC_DAVINCI) += davinci.o
obj-$(CONFIG_RTC_DS1302) += ds1302.o
+++ /dev/null
-/*
- * Copyright (c) 2004-2008 Analog Devices Inc.
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <rtc.h>
-
-#if defined(CONFIG_CMD_DATE)
-
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/rtc.h>
-
-#define pr_stamp() debug("%s:%s:%i: here i am\n", __FILE__, __func__, __LINE__)
-
-#define MIN_TO_SECS(x) (60 * (x))
-#define HRS_TO_SECS(x) (60 * MIN_TO_SECS(x))
-#define DAYS_TO_SECS(x) (24 * HRS_TO_SECS(x))
-
-#define NUM_SECS_IN_MIN MIN_TO_SECS(1)
-#define NUM_SECS_IN_HR HRS_TO_SECS(1)
-#define NUM_SECS_IN_DAY DAYS_TO_SECS(1)
-
-/* Enable the RTC prescaler enable register */
-void rtc_init(void)
-{
- if (!(bfin_read_RTC_PREN() & 0x1))
- bfin_write_RTC_PREN(0x1);
-}
-
-/* Our on-chip RTC has no notion of "reset" */
-void rtc_reset(void)
-{
- rtc_init();
-}
-
-/* Wait for pending writes to complete */
-static void wait_for_complete(void)
-{
- pr_stamp();
- while (!(bfin_read_RTC_ISTAT() & WRITE_COMPLETE))
- if (!(bfin_read_RTC_ISTAT() & WRITE_PENDING))
- break;
- bfin_write_RTC_ISTAT(WRITE_COMPLETE);
-}
-
-/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
- * based on this value.
- */
-int rtc_set(struct rtc_time *tmp)
-{
- unsigned long remain, days, hrs, mins, secs;
-
- pr_stamp();
-
- if (tmp == NULL) {
- puts("Error setting the date/time\n");
- return -1;
- }
-
- rtc_init();
- wait_for_complete();
-
- /* Calculate number of seconds this incoming time represents */
- remain = rtc_mktime(tmp);
-
- /* Figure out how many days since epoch */
- days = remain / NUM_SECS_IN_DAY;
-
- /* From the remaining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */
- remain = remain % NUM_SECS_IN_DAY;
- hrs = remain / NUM_SECS_IN_HR;
- remain = remain % NUM_SECS_IN_HR;
- mins = remain / NUM_SECS_IN_MIN;
- secs = remain % NUM_SECS_IN_MIN;
-
- /* Encode these time values into our RTC_STAT register */
- bfin_write_RTC_STAT(SET_ALARM(days, hrs, mins, secs));
-
- return 0;
-}
-
-/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */
-int rtc_get(struct rtc_time *tmp)
-{
- uint32_t cur_rtc_stat;
- int time_in_sec;
- int tm_sec, tm_min, tm_hr, tm_day;
-
- pr_stamp();
-
- if (tmp == NULL) {
- puts("Error getting the date/time\n");
- return -1;
- }
-
- rtc_init();
- wait_for_complete();
-
- /* Read the RTC_STAT register */
- cur_rtc_stat = bfin_read_RTC_STAT();
-
- /* Convert our encoded format into actual time values */
- tm_sec = (cur_rtc_stat & RTC_SEC) >> RTC_SEC_P;
- tm_min = (cur_rtc_stat & RTC_MIN) >> RTC_MIN_P;
- tm_hr = (cur_rtc_stat & RTC_HR ) >> RTC_HR_P;
- tm_day = (cur_rtc_stat & RTC_DAY) >> RTC_DAY_P;
-
- /* Calculate the total number of seconds since epoch */
- time_in_sec = (tm_sec) + MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hr) + DAYS_TO_SECS(tm_day);
- rtc_to_tm(time_in_sec, tmp);
-
- return 0;
-}
-
-#endif
endif
obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
-obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o
+++ /dev/null
-/*
- * watchdog.c - driver for Blackfin on-chip watchdog
- *
- * Copyright (c) 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/mach-common/bits/watchdog.h>
-
-void hw_watchdog_reset(void)
-{
- bfin_write_WDOG_STAT(0);
-}
-
-void hw_watchdog_init(void)
-{
- bfin_write_WDOG_CTL(WDDIS);
- SSYNC();
- bfin_write_WDOG_CNT(CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000 * get_sclk());
- hw_watchdog_reset();
- bfin_write_WDOG_CTL(WDEN);
-}
projects / oweals / u-boot.git / commitdiff