tsec: Fix eTSEC2 link problem on P2020RDB
authorFelix Radensky <felix@embedded-sol.com>
Sun, 27 Jun 2010 22:57:39 +0000 (01:57 +0300)
committerWolfgang Denk <wd@denx.de>
Tue, 29 Jun 2010 19:02:16 +0000 (21:02 +0200)
On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII.
Current TBI PHY settings for SGMII mode cause link problems on
this platform, link never comes up.

Fix this by making TBI PHY settings configurable and add a working
configuration for P2020RDB.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Acked-by: Andy Fleming <afleming@freescale.com>
drivers/net/tsec.c
include/configs/P1_P2_RDB.h

index 3e4c3bd31b98231ce83f3bc2bba74865d4acadca..5fa6f6100836b1bc5b3c9cb9ffeaa046c5d4ec4e 100644 (file)
@@ -281,12 +281,16 @@ static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs,
                | TBIANA_FULL_DUPLEX \
                )
 
-/* Force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
+/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
+#ifndef CONFIG_TSEC_TBICR_SETTINGS
 #define TBICR_SETTINGS ( \
                TBICR_PHY_RESET \
                | TBICR_FULL_DUPLEX \
                | TBICR_SPEED1_SET \
                )
+#else
+#define TBICR_SETTINGS CONFIG_TSEC_TBICR_SETTINGS
+#endif /* CONFIG_TSEC_TBICR_SETTINGS */
 
 /* Configure the TBI for SGMII operation */
 static void tsec_configure_serdes(struct tsec_private *priv)
index 125911f2f853a868baeacea749254a4e5274b096..b8917307897423021cb3e46335bbe172e8bb86b1 100644 (file)
@@ -425,6 +425,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_ETHPRIME                "eTSEC1"
 
 #define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
+
+/* TBI PHY configuration for SGMII mode */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+               TBICR_PHY_RESET \
+               | TBICR_ANEG_ENABLE \
+               | TBICR_FULL_DUPLEX \
+               | TBICR_SPEED1_SET \
+               )
+
 #endif /* CONFIG_TSEC_ENET */
 
 /*