at91: Add support for the AT91 slow clock controller

This is available on AT91SAM9G45. Add the peripheral address and flag
definitions.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/include/mach/at91_sck.h b/arch/arm/mach-at91/include/mach/at91_sck.h
new file mode 100644 (file)
index 0000000..ce8e577
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_sck.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef AT91_SCK_H
+#define AT91_SCK_H
+
+/*
+ * SCKCR flags
+ */
+#define AT91SAM9G45_SCKCR_RCEN     (1 << 0)    /* RC Oscillator Enable */
+#define AT91SAM9G45_SCKCR_OSC32EN   (1 << 1)   /* 32kHz Oscillator Enable */
+#define AT91SAM9G45_SCKCR_OSC32BYP  (1 << 2)   /* 32kHz Oscillator Bypass */
+#define AT91SAM9G45_SCKCR_OSCSEL    (1 << 3)   /* Slow Clock Selector */
+#define                AT91SAM9G45_SCKCR_OSCSEL_RC     (0 << 3)
+#define                AT91SAM9G45_SCKCR_OSCSEL_32     (1 << 3)
+
+#endif

diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index cf1c73f3d986219e3aa3fb3a212299fc0928a750..5c32e24ed0f24559f2cf66124752053b25fc1351 100644 (file)
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -109,6 +109,7 @@
 #define ATMEL_BASE_RTT         0xfffffd20
 #define ATMEL_BASE_PIT         0xfffffd30
 #define ATMEL_BASE_WDT         0xfffffd40
+#define ATMEL_BASE_SCKCR       0xfffffd50
 #define ATMEL_BASE_GPBR                0xfffffd60
 #define ATMEL_BASE_RTC         0xfffffdb0
 /* Reserved:   0xfffffdc0 - 0xffffffff */