Adjust QC/A SOC related code to the new bitmask SOC_TYPE values

diff --git a/u-boot/cpu/mips/ar7240/qca_clocks.c b/u-boot/cpu/mips/ar7240/qca_clocks.c
index e52be09a220225859dd1dc7091f089a8dc49130e..19fd3e565b72d4fc28409829ab69027de6c1ac7d 100644 (file)
--- a/u-boot/cpu/mips/ar7240/qca_clocks.c
+++ b/u-boot/cpu/mips/ar7240/qca_clocks.c
@@ -65,7 +65,7 @@ void qca_sys_clocks(u32 *cpu_clk,
                                        u32 *ref_clk)
 {
        u32 cpu_pll;
-#if (SOC_TYPE != QCA_AR933X_SOC)
+#if (SOC_TYPE & (~QCA_AR933X_SOC))
        u32 ddr_pll;
 #endif
        u32 outdiv;
@@ -82,7 +82,7 @@ void qca_sys_clocks(u32 *cpu_clk,
                qca_ref_clk = VAL_25MHz;
        }
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        /*
         * Main AR933x CPU PLL clock calculation:
         *

diff --git a/u-boot/cpu/mips/ar7240/qca_common.c b/u-boot/cpu/mips/ar7240/qca_common.c
index e1f9d9af5d23fe73e3d21bdf62336c627318de45..50116a7ef9d1a43e8ed6bddcfa83db636b3dcc09 100644 (file)
--- a/u-boot/cpu/mips/ar7240/qca_common.c
+++ b/u-boot/cpu/mips/ar7240/qca_common.c
@@ -51,7 +51,7 @@ void qca_soc_name_rev(char *buf)
        rev = id & QCA_RST_REVISION_ID_REV_MASK;
 
        switch (major) {
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        case QCA_RST_REVISION_ID_MAJOR_AR9330_VAL:
                sprintf(buf, "AR9330 rev. %d", rev);
                break;
@@ -59,17 +59,15 @@ void qca_soc_name_rev(char *buf)
                sprintf(buf, "AR9331 rev. %d", rev);
                break;
 #endif
-#if (SOC_TYPE == QCA_AR9341_SOC)
+#if (SOC_TYPE & QCA_AR934X_SOC)
        case QCA_RST_REVISION_ID_MAJOR_AR9341_VAL:
                sprintf(buf, "AR9341 rev. %d", rev);
                break;
-#endif
-#if (SOC_TYPE == QCA_AR9344_SOC)
        case QCA_RST_REVISION_ID_MAJOR_AR9344_VAL:
                sprintf(buf, "AR9344 rev. %d", rev);
                break;
 #endif
-#if (SOC_TYPE == QCA_QCA9531_SOC || SOC_TYPE == QCA_QCA9533_SOC)
+#if (SOC_TYPE & QCA_QCA953X_SOC)
        case QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL:
                sprintf(buf, "QCA953x ver. 1 rev. %d", rev);
                break;
@@ -77,7 +75,7 @@ void qca_soc_name_rev(char *buf)
                sprintf(buf, "QCA953x ver. 2 rev. %d", rev);
                break;
 #endif
-#if (SOC_TYPE == QCA_QCA9558_SOC)
+#if (SOC_TYPE & QCA_QCA955X_SOC)
        case QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL:
                sprintf(buf, "QCA9558 rev. %d", rev);
                break;

diff --git a/u-boot/cpu/mips/ar7240/qca_hs_uart.c b/u-boot/cpu/mips/ar7240/qca_hs_uart.c
index 7d094fcdf33e67acf5b8d310b01f957325512c63..dae53da1a250f23b3fe5419be37d357e12820a2d 100644 (file)
--- a/u-boot/cpu/mips/ar7240/qca_hs_uart.c
+++ b/u-boot/cpu/mips/ar7240/qca_hs_uart.c
@@ -95,7 +95,7 @@ int serial_init(void)
 {
        u32 uart_cs;
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        /*
         * Set GPIO10 (UART_SO) as output and enable UART,
         * BIT(15) in GPIO_FUNCTION_1 register must be written with 1