powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.h

B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.

Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index dd683351d4697d5eae065cda8c3ef0410ba34075..1009a31b33954693fc2de55a5636dee22f9ea2a1 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -556,19 +556,15 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 
-#elif defined(CONFIG_PPC_B4420)
+#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
+#define CONFIG_E6500
 #define CONFIG_SYS_PPC64               /* 64-bit core */
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
-#define CONFIG_MAX_CPUS                        2
-#define CONFIG_SYS_FSL_NUM_CC_PLLS     4
 #define CONFIG_SYS_FSL_NUM_LAWS                32
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_SYS_NUM_FMAN            1
-#define CONFIG_SYS_NUM_FM1_DTSEC       4
-#define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
@@ -579,32 +575,24 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 
-#elif defined(CONFIG_PPC_B4860)
-#define CONFIG_SYS_PPC64               /* 64-bit core */
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
+#ifdef CONFIG_PPC_B4860
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
-#define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #define CONFIG_MAX_CPUS                        4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     4
-#define CONFIG_SYS_FSL_NUM_LAWS                32
-#define CONFIG_SYS_FSL_SEC_COMPAT      4
-#define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_NUM_FM1_DTSEC       6
 #define CONFIG_SYS_NUM_FM1_10GEC       2
 #define CONFIG_NUM_DDR_CONTROLLERS     2
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
-#define CONFIG_SYS_FMAN_V3
-#define CONFIG_SYS_FM_MURAM_SIZE       0x60000
-#define CONFIG_SYS_FSL_TBCLK_DIV       16
-#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_ERRATUM_A_004934
-#define CONFIG_SYS_FSL_ERRATUM_A005871
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
+#else
+#define CONFIG_MAX_CPUS                        2
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
+#define CONFIG_SYS_FSL_NUM_CC_PLLS     4
+#define CONFIG_SYS_NUM_FM1_DTSEC       4
+#define CONFIG_SYS_NUM_FM1_10GEC       0
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#endif
 
 #elif defined(CONFIG_PPC_T1040)
 #define CONFIG_E5500

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index cfab1e8140c336ea3b092ea96c9ba07ed0ac592e..65f8a2209ea344301f4e70089acf7d3bf04013d5 100644 (file)
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -36,7 +36,6 @@
 
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
-#define CONFIG_E6500
 #define CONFIG_E500                    /* BOOKE e500 family */
 #define CONFIG_E500MC                  /* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */