davinci: add support for printing clock frequency
authorHadli, Manjunath <manjunath.hadli@ti.com>
Mon, 6 Feb 2012 00:30:44 +0000 (00:30 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sun, 12 Feb 2012 09:11:32 +0000 (10:11 +0100)
add support for printing various clock frequency info found
in SOC such as ARM core frequency, DSP core frequency and DDR
frequency as part of bdinfo command.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
20 files changed:
arch/arm/cpu/arm926ejs/davinci/cpu.c
arch/arm/include/asm/u-boot.h
arch/arm/lib/board.c
common/cmd_bdinfo.c
include/common.h
include/configs/cam_enc_4xx.h
include/configs/da830evm.h
include/configs/da850evm.h
include/configs/davinci_dm355evm.h
include/configs/davinci_dm355leopard.h
include/configs/davinci_dm365evm.h
include/configs/davinci_dm6467Tevm.h
include/configs/davinci_dm6467evm.h
include/configs/davinci_dvevm.h
include/configs/davinci_schmoogie.h
include/configs/davinci_sffsdr.h
include/configs/davinci_sonata.h
include/configs/ea20.h
include/configs/enbw_cmc.h
include/configs/hawkboard.h

index 17355552267d7e88b16b6a146bcb7ec62100c8eb..b3c9fb7b6991da12818f0aa6e8311b6684d2fb1a 100644 (file)
@@ -25,6 +25,8 @@
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* offsets from PLL controller base */
 #define PLLC_PLLCTL    0x100
 #define PLLC_PLLM      0x110
@@ -187,6 +189,36 @@ unsigned int davinci_clk_get(unsigned int div)
 #endif
 #endif /* !CONFIG_SOC_DA8XX */
 
+int set_cpu_clk_info(void)
+{
+#ifdef CONFIG_SOC_DA8XX
+       gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
+       /* DDR PHY uses an x2 input clock */
+       gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000;
+#else
+
+       unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
+#if defined(CONFIG_SOC_DM365)
+       pllbase = DAVINCI_PLL_CNTRL1_BASE;
+#endif
+       gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
+
+#ifdef DSP_PLLDIV
+       gd->bd->bi_dsp_freq =
+               pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
+#else
+       gd->bd->bi_dsp_freq = 0;
+#endif
+
+       pllbase = DAVINCI_PLL_CNTRL1_BASE;
+#if defined(CONFIG_SOC_DM365)
+       pllbase = DAVINCI_PLL_CNTRL0_BASE;
+#endif
+       gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
+#endif
+       return 0;
+}
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
index f30b9fc96f0be9a1d6328bd6206cc3cf988b4c84..20e165393020e91625168638fbea8c005bebf698 100644 (file)
@@ -41,6 +41,9 @@ typedef struct bd_info {
     unsigned long      bi_ip_addr;     /* IP Address */
     ulong              bi_arch_number; /* unique id for this board */
     ulong              bi_boot_params; /* where this board expects params */
+       unsigned long   bi_arm_freq; /* arm frequency */
+       unsigned long   bi_dsp_freq; /* dsp core frequency */
+       unsigned long   bi_ddr_freq; /* ddr frequency */
     struct                             /* RAM configuration */
     {
        ulong start;
index 3d7827407206b86b02542b72d076737abf66869d..500e2164ce4b85d2606b26a596c195ab7216fed4 100644 (file)
@@ -463,7 +463,15 @@ void board_init_r(gd_t *id, ulong dest_addr)
 
        debug("monitor flash len: %08lX\n", monitor_flash_len);
        board_init();   /* Setup chipselects */
-
+       /*
+        * TODO: printing of the clock inforamtion of the board is now
+        * implemented as part of bdinfo command. Currently only support for
+        * davinci SOC's is added. Remove this check once all the board
+        * implement this.
+        */
+#ifdef CONFIG_CLOCKS
+       set_cpu_clk_info(); /* Setup clock information */
+#endif
 #ifdef CONFIG_SERIAL_MULTI
        serial_initialize();
 #endif
index 97f29456f97e7454813e88e84096d5ee4cd3dd32..5359a47859b98fb431e3d99a9a3c36a6f10ff404 100644 (file)
@@ -370,6 +370,15 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        print_num("irq_sp", gd->irq_sp);        /* irq stack pointer */
        print_num("sp start ", gd->start_addr_sp);
        print_num("FB base  ", gd->fb_base);
+       /*
+        * TODO: Currently only support for davinci SOC's is added.
+        * Remove this check once all the board implement this.
+        */
+#ifdef CONFIG_CLOCKS
+       printf("ARM frequency = %ld MHz\n", gd->bd->bi_arm_freq);
+       printf("DSP frequency = %ld MHz\n", gd->bd->bi_dsp_freq);
+       printf("DDR frequency = %ld MHz\n", gd->bd->bi_ddr_freq);
+#endif
        return 0;
 }
 
index 7a9b3a2381994343795cbdf25a2c37e1ad3dde37..a2c6b27d43cce33d1a00a033e4b33c895c4e1d8d 100644 (file)
@@ -285,6 +285,7 @@ int last_stage_init(void);
 extern ulong monitor_flash_len;
 int mac_read_from_eeprom(void);
 extern u8 _binary_dt_dtb_start[];      /* embedded device tree blob */
+int set_cpu_clk_info(void);
 
 /*
  * Called when console output is requested before the console is available.
index bca9841a171a88d0ef38d7a912090c50aaecceb4..79a8611f821b755c79f1b84f6f49a72a40d204b0 100644 (file)
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #ifdef CONFIG_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_EXT2
index e8c021262ac4b747363cc6a013df7d4f89316203..4532e4f4fdd18fe6b2322654a65cb3a87ddb295a 100644 (file)
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #ifndef CONFIG_DRIVER_TI_EMAC
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_DHCP
index 220890dfd9750c6633360a802a4c60798f4fd072..f32bd34add328cc429dbea76321e1e359350b69d 100644 (file)
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_MEMORY
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #ifndef CONFIG_DRIVER_TI_EMAC
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_DHCP
index 8578730baba58f007f2b905b412bc4c09f8fc2a0..42caf1e42a467d32e7358a32b8036036ea4a6350 100644 (file)
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #ifdef CONFIG_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_EXT2
index 803e8578fcf02cb9292615cecf2167e8a300e20f..b05cfbaa8e8b122b3e0380ea42d2f7d45cea5344 100644 (file)
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #ifdef CONFIG_NAND_DAVINCI
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_MTD_PARTITIONS
index cb6ed24a80015dc5d6d4962cc0cbd78d5d613ba8..a75bce675b48a3924027f79119f28073f445b1cc 100644 (file)
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #ifdef CONFIG_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_EXT2
index f7c994eba94c8336e28ce5861a5e90123f6c38f1..0cbdec86813ecceede0545af8e1c970faf180156 100644 (file)
@@ -152,6 +152,10 @@ extern unsigned int davinci_arm_clk_get(void);
 #define CONFIG_CMD_NAND
 #endif
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #define CONFIG_MAX_RAM_BANK_SIZE       (256 << 20)     /* 256 MB */
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
index ddfd3ed39b09afcf4f6b82488e48b3fbfa0b780a..e0fe6b5c248ec618744744dd62b9b40dde5c280c 100644 (file)
@@ -150,6 +150,10 @@ extern unsigned int davinci_arm_clk_get(void);
 #define CONFIG_CMD_NAND
 #endif
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #define CONFIG_MAX_RAM_BANK_SIZE       (256 << 20)     /* 256 MB */
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
index a2aa3c3fce0101ac70d4a78df30558124d81c96d..310d5770dec4889c81389e4765ae21312e109e9c 100644 (file)
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_BDI
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR
 #ifdef CONFIG_SYS_USE_NAND
index e0a8ee9a9597ae3031618930ecbd9995ee31e8ef..949174a1637193504bd36607395b4a7d0c4afdbe 100644 (file)
 #undef CONFIG_CMD_FLASH
 #undef CONFIG_CMD_IMLS
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #define CONFIG_MAX_RAM_BANK_SIZE       (256 << 20)     /* 256 MB */
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
index a2da65a762b87a8f9d158611dfdeea60c97e1d7a..c931ede85cfd7d79851fc6f0b03248ac421f526d 100644 (file)
 #undef CONFIG_CMD_FLASH
 #undef CONFIG_CMD_IMLS
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #define CONFIG_MAX_RAM_BANK_SIZE       (256 << 20)     /* 256 MB */
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
index db4796624d40fe3d7cf144cd096328190054551b..854099b2a26f500b353eb4fac961e0a96a1b564c 100644 (file)
 #error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
 #endif
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #define CONFIG_MAX_RAM_BANK_SIZE       (256 << 20)     /* 256 MB */
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
index cc0f5b05cd63538eaebef8533b04d7f029dc15c1..b4610d9474faf2d6c2eb5a3806f24eff9c6df464 100644 (file)
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_I2C
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #ifndef CONFIG_DRIVER_TI_EMAC
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_DHCP
index 9cffaee1108cd524831a761ca99ef443a42a40fd..9fd6a4f183a190edd81ffbe403c7774f8c5aab73 100644 (file)
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_CACHE
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #ifndef CONFIG_DRIVER_TI_EMAC
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_DHCP
index fa214941afbf8f52438e0fc02483b522a1d6e7ed..21f7b9b7e318425ab987d4a2abe4a7c58febf2e9 100644 (file)
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_MEMORY
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
 #ifdef CONFIG_SYS_USE_NAND
 #undef CONFIG_CMD_FLASH
 #undef CONFIG_CMD_IMLS