OMAP5: palmas: Configure nominal opp vdd values

The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.

Also used the right sequence to enable the vcores as per
a previous patch from Nishant Menon, which can be dropped now.
	http://lists.denx.de/pipermail/u-boot/2012-March/119151.html

Signed-off-by: R Sricharan <r.sricharan@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index e96a430f74c667f8c503f1a376eeffd2a5e57af9..10d286a6d4d84435fe485c20e618b25e75519705 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -397,23 +397,16 @@ void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv)
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
 {
        u32 offset_code;
-       u32 step = 12660; /* 12.66 mV represented in uV */
        u32 offset = volt_mv;
 
        /* convert to uV for better accuracy in the calculations */
        offset *= 1000;
 
-       if (omap_revision() == OMAP4430_ES1_0)
-               offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
-       else
-               offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
-
-       offset_code = (offset + step - 1) / step;
-       /* The code starts at 1 not 0 */
-       offset_code++;
+       offset_code = get_offset_code(offset);
 
        debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
                offset_code);
+
        if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
                                vcore_reg, offset_code))
                printf("Scaling voltage failed for 0x%x\n", vcore_reg);

diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index b6b3f7e195e5733b6d4cd9b0e4143bea22bdc574..dd694c409f827eaf24f856369816bd89533ade4e 100644 (file)
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -326,6 +326,21 @@ void scale_vcores(void)
        }
 }
 
+u32 get_offset_code(u32 offset)
+{
+       u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
+
+       if (omap_revision() == OMAP4430_ES1_0)
+               offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
+       else
+               offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
+
+       offset_code = (offset + step - 1) / step;
+
+       /* The code starts at 1 not 0 */
+       return ++offset_code;
+}
+
 /*
  * Enable essential clock domains, modules and
  * do some additional special settings needed

diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c
index 722916e036eed26d875c495f2e727d5fd59070a6..1a59f265f7b00ca6bc020f77428eee4bb454b640 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -264,17 +264,31 @@ void scale_vcores(void)
 
        omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
 
-       /* Enable 1.22V from TPS for vdd_mpu */
-       volt = 1220;
-       do_scale_tps62361(-1, TPS62361_REG_ADDR_SET1, volt);
+       /* Palmas settings */
+       volt = VDD_CORE;
+       do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt);
 
-       /* VCORE 1 - for vdd_core */
-       volt = 1000;
-       do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+       volt = VDD_MPU;
+       do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt);
 
-       /* VCORE 2 - for vdd_MM */
-       volt = 1125;
-       do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+       volt = VDD_MM;
+       do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt);
+
+}
+
+u32 get_offset_code(u32 volt_offset)
+{
+       u32 offset_code, step = 10000; /* 10 mV represented in uV */
+
+       volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
+
+       offset_code = (volt_offset + step - 1) / step;
+
+       /*
+        * Offset codes 1-6 all give the base voltage in Palmas
+        * Offset code 0 switches OFF the SMPS
+        */
+       return offset_code + 6;
 }
 
 /*

diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index 62a339f184d5f1171881fa7beed5e1780bac7625..617729c32b7675f1bdd4c7793618b0a6b1119a1b 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -741,6 +741,7 @@ extern const u32 sys_clk_array[8];
 
 void scale_vcores(void);
 void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
+u32 get_offset_code(u32 offset);
 u32 omap_ddr_clk(void);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
 void setup_post_dividers(u32 *const base, const struct dpll_params *params);

diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index cf6022da2f971951f528da6bd5960e07694dd92b..f32cf3eeef7beb8e79ef791b3945dc3155291087 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -633,12 +633,17 @@ struct omap5_prcm_regs {
 
 /* SMPS */
 #define SMPS_I2C_SLAVE_ADDR    0x12
-#define SMPS_REG_ADDR_VCORE1   0x55
-#define SMPS_REG_ADDR_VCORE2   0x5B
-#define SMPS_REG_ADDR_VCORE3   0x61
+#define SMPS_REG_ADDR_12_MPU   0x23
+#define SMPS_REG_ADDR_45_IVA   0x2B
+#define SMPS_REG_ADDR_8_CORE   0x37
 
-#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV             607700
-#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
+/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
+#define VDD_MPU                1000
+#define VDD_MM         1000
+#define VDD_CORE       1040
+
+/* Standard offset is 0.5v expressed in uv */
+#define PALMAS_SMPS_BASE_VOLT_UV 500000
 
 /* TPS */
 #define TPS62361_I2C_SLAVE_ADDR                0x60
@@ -700,6 +705,7 @@ extern const u32 sys_clk_array[8];
 
 void scale_vcores(void);
 void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
+u32 get_offset_code(u32 offset);
 u32 omap_ddr_clk(void);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
 void setup_post_dividers(u32 *const base, const struct dpll_params *params);