arm64: zynqmp: Get rid of emulation platforms
authorMichal Simek <michal.simek@xilinx.com>
Mon, 14 May 2018 13:33:22 +0000 (15:33 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Thu, 31 May 2018 11:50:39 +0000 (13:50 +0200)
ZynqMP emulation platforms are no longer tested and supported that's why
remove macros and code around.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/cpu/armv8/zynqmp/clk.c
arch/arm/cpu/armv8/zynqmp/cpu.c
arch/arm/include/asm/arch-zynqmp/hardware.h

index 13e1977bfa1abf5aed60058ed9271673adb70efa..0593b6310fd5b1ea2e37a657e08d5f57f5d90fe5 100644 (file)
@@ -16,10 +16,6 @@ unsigned long zynqmp_get_system_timer_freq(void)
        u32 ver = zynqmp_get_silicon_version();
 
        switch (ver) {
-       case ZYNQMP_CSU_VERSION_VELOCE:
-               return 10000;
-       case ZYNQMP_CSU_VERSION_EP108:
-               return 4000000;
        case ZYNQMP_CSU_VERSION_QEMU:
                return 50000000;
        }
@@ -40,11 +36,7 @@ int set_cpu_clk_info(void)
 {
        gd->cpu_clk = get_tbclk();
 
-       /* Support Veloce to show at least 1MHz via bdi */
-       if (gd->cpu_clk > 1000000)
-               gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
-       else
-               gd->bd->bi_arm_freq = 1;
+       gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
 
        gd->bd->bi_dsp_freq = 0;
 
index 2748d65d14b4f3b94746d95ec2dc32001689612f..792a3e1b655fadeca3280f019caf94adee49f50d 100644 (file)
@@ -135,12 +135,8 @@ unsigned int zynqmp_get_silicon_version(void)
        gd->cpu_clk = get_tbclk();
 
        switch (gd->cpu_clk) {
-       case 0 ... 1000000:
-               return ZYNQMP_CSU_VERSION_VELOCE;
        case 50000000:
                return ZYNQMP_CSU_VERSION_QEMU;
-       case 4000000:
-               return ZYNQMP_CSU_VERSION_EP108;
        }
 
        return ZYNQMP_CSU_VERSION_SILICON;
index f31725030b55dcaad46aa38332f22c3b252cbf5e..8a505edab3cc32b4cf809bce878adab97beab883 100644 (file)
@@ -130,8 +130,6 @@ struct apu_regs {
 /* Board version value */
 #define ZYNQMP_CSU_BASEADDR            0xFFCA0000
 #define ZYNQMP_CSU_VERSION_SILICON     0x0
-#define ZYNQMP_CSU_VERSION_EP108       0x1
-#define ZYNQMP_CSU_VERSION_VELOCE      0x2
 #define ZYNQMP_CSU_VERSION_QEMU                0x3
 
 #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT         20