pinctrl: uniphier: introduce capability flag
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Thu, 24 Mar 2016 13:32:44 +0000 (22:32 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Thu, 31 Mar 2016 15:54:00 +0000 (00:54 +0900)
The core part of the UniPhier pinctrl driver needs to support a new
capability for upcoming UniPhier ARMv8 SoCs.  This sometimes happens
because pinctrl drivers include really SoC-specific stuff.

This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding new ones.  Having flags would be better than
adding new members every time a new SoC-specific capability comes up.

At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
This capability (I'd say rather quirk) was added for PH1-Pro4 and
PH1-Pro5 as requirement from our customer.  For those SoCs, one pin-mux
setting is controlled by the combination of two separate registers; the
LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
Because it is impossible to update two separate registers atomically,
the LOAD_PINCTRL register should be set in order to make the pin-mux
settings really effective.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
drivers/pinctrl/uniphier/pinctrl-uniphier.h

index ac3a06c191a9cd7267fed8a4f3d4c95e5c51e69b..bb7a0887466e6c0148aa26c3d2638a1d41153d2c 100644 (file)
@@ -68,14 +68,33 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
                                    unsigned muxval)
 {
        struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
-       unsigned mux_bits = priv->socdata->mux_bits;
-       unsigned reg_stride = priv->socdata->reg_stride;
-       unsigned reg, reg_end, shift, mask;
+       unsigned mux_bits, reg_stride, reg, reg_end, shift, mask;
+       bool load_pinctrl;
        u32 tmp;
 
        /* some pins need input-enabling */
        uniphier_pinconf_input_enable(dev, pin);
 
+       if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
+               /*
+                *  Mode       offset        bit
+                *  Normal     4 * n     shift+3:shift
+                *  Debug      4 * n     shift+7:shift+4
+                */
+               mux_bits = 4;
+               reg_stride = 8;
+               load_pinctrl = true;
+       } else {
+               /*
+                *  Mode       offset           bit
+                *  Normal     8 * n        shift+3:shift
+                *  Debug      8 * n + 4    shift+3:shift
+                */
+               mux_bits = 8;
+               reg_stride = 4;
+               load_pinctrl = false;
+       }
+
        reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
        reg_end = reg + reg_stride;
        shift = pin * mux_bits % 32;
@@ -94,7 +113,7 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
                muxval >>= mux_bits;
        }
 
-       if (priv->socdata->load_pinctrl)
+       if (load_pinctrl)
                writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX);
 }
 
index b3d47f091537d5aec3d6ccdf3cfeb3ba2a193d3d..8f7574e2aa86bf482695d4ad2faefa77d808ae3c 100644 (file)
@@ -107,9 +107,6 @@ static struct uniphier_pinctrl_socdata ph1_ld4_pinctrl_socdata = {
        .groups_count = ARRAY_SIZE(ph1_ld4_groups),
        .functions = ph1_ld4_functions,
        .functions_count = ARRAY_SIZE(ph1_ld4_functions),
-       .mux_bits = 8,
-       .reg_stride = 4,
-       .load_pinctrl = false,
 };
 
 static int ph1_ld4_pinctrl_probe(struct udevice *dev)
index 8703a215e489dc06ccb80d940de10e3db1e711cc..2a5d5f3ad412dff7a7c3c0112d436c5d021dfb57 100644 (file)
@@ -107,9 +107,6 @@ static struct uniphier_pinctrl_socdata ph1_ld6b_pinctrl_socdata = {
        .groups_count = ARRAY_SIZE(ph1_ld6b_groups),
        .functions = ph1_ld6b_functions,
        .functions_count = ARRAY_SIZE(ph1_ld6b_functions),
-       .mux_bits = 8,
-       .reg_stride = 4,
-       .load_pinctrl = false,
 };
 
 static int ph1_ld6b_pinctrl_probe(struct udevice *dev)
index b3eaf138f76b183421355fc9a062d6ceabe059e8..60fbbafe781268710eb14fb808cfe887ac42dbab 100644 (file)
@@ -103,9 +103,7 @@ static struct uniphier_pinctrl_socdata ph1_pro4_pinctrl_socdata = {
        .groups_count = ARRAY_SIZE(ph1_pro4_groups),
        .functions = ph1_pro4_functions,
        .functions_count = ARRAY_SIZE(ph1_pro4_functions),
-       .mux_bits = 4,
-       .reg_stride = 8,
-       .load_pinctrl = true,
+       .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
 };
 
 static int ph1_pro4_pinctrl_probe(struct udevice *dev)
index 3749250066978c008e629ef9a68fa6d5263207ff..30c9b4d556cce7de0aea99003ba2800ff9bc5171 100644 (file)
@@ -117,9 +117,7 @@ static struct uniphier_pinctrl_socdata ph1_pro5_pinctrl_socdata = {
        .groups_count = ARRAY_SIZE(ph1_pro5_groups),
        .functions = ph1_pro5_functions,
        .functions_count = ARRAY_SIZE(ph1_pro5_functions),
-       .mux_bits = 4,
-       .reg_stride = 8,
-       .load_pinctrl = true,
+       .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
 };
 
 static int ph1_pro5_pinctrl_probe(struct udevice *dev)
index 2cca69d5148ea431be65b5c9fafe67fb72f259f2..976bb2f4a45ce4a9e93032c0b6128e8acb74ed9d 100644 (file)
@@ -114,9 +114,6 @@ static struct uniphier_pinctrl_socdata proxstream2_pinctrl_socdata = {
        .groups_count = ARRAY_SIZE(proxstream2_groups),
        .functions = proxstream2_functions,
        .functions_count = ARRAY_SIZE(proxstream2_functions),
-       .mux_bits = 8,
-       .reg_stride = 4,
-       .load_pinctrl = false,
 };
 
 static int proxstream2_pinctrl_probe(struct udevice *dev)
index 5fafdb610011da95c43ed107f4a70bea0320b21c..6cbf21526cc705014f4a9ff1ef15a0ca824b52b7 100644 (file)
@@ -115,9 +115,6 @@ static struct uniphier_pinctrl_socdata ph1_sld8_pinctrl_socdata = {
        .groups_count = ARRAY_SIZE(ph1_sld8_groups),
        .functions = ph1_sld8_functions,
        .functions_count = ARRAY_SIZE(ph1_sld8_functions),
-       .mux_bits = 8,
-       .reg_stride = 4,
-       .load_pinctrl = false,
 };
 
 static int ph1_sld8_pinctrl_probe(struct udevice *dev)
index 6bdebf28cd59de02ffd7d72d56d1d6d5bd28d1a6..d58231729152a69492bc6e3f1ae9bc38e67ecfa5 100644 (file)
@@ -7,6 +7,7 @@
 #ifndef __PINCTRL_UNIPHIER_H__
 #define __PINCTRL_UNIPHIER_H__
 
+#include <linux/bitops.h>
 #include <linux/bug.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
@@ -59,8 +60,7 @@ struct uniphier_pinctrl_group {
  * @functions_count: number of pinmux functions
  * @mux_bits: bit width of each pinmux register
  * @reg_stride: stride of pinmux register address
- * @load_pinctrl: if true, LOAD_PINMUX register must be set to one for new
- *               values in pinmux registers to become really effective
+ * @caps: SoC-specific capability flag
  */
 struct uniphier_pinctrl_socdata {
        const struct uniphier_pinctrl_pin *pins;
@@ -69,9 +69,8 @@ struct uniphier_pinctrl_socdata {
        int groups_count;
        const char * const *functions;
        int functions_count;
-       unsigned mux_bits;
-       unsigned reg_stride;
-       bool load_pinctrl;
+       unsigned caps;
+#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE  BIT(0)
 };
 
 #define UNIPHIER_PINCTRL_PIN(a, b)                                     \