unsigned muxval)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
- unsigned mux_bits = priv->socdata->mux_bits;
- unsigned reg_stride = priv->socdata->reg_stride;
- unsigned reg, reg_end, shift, mask;
+ unsigned mux_bits, reg_stride, reg, reg_end, shift, mask;
+ bool load_pinctrl;
u32 tmp;
/* some pins need input-enabling */
uniphier_pinconf_input_enable(dev, pin);
+ if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
+ /*
+ * Mode offset bit
+ * Normal 4 * n shift+3:shift
+ * Debug 4 * n shift+7:shift+4
+ */
+ mux_bits = 4;
+ reg_stride = 8;
+ load_pinctrl = true;
+ } else {
+ /*
+ * Mode offset bit
+ * Normal 8 * n shift+3:shift
+ * Debug 8 * n + 4 shift+3:shift
+ */
+ mux_bits = 8;
+ reg_stride = 4;
+ load_pinctrl = false;
+ }
+
reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
reg_end = reg + reg_stride;
shift = pin * mux_bits % 32;
muxval >>= mux_bits;
}
- if (priv->socdata->load_pinctrl)
+ if (load_pinctrl)
writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX);
}
.groups_count = ARRAY_SIZE(ph1_ld4_groups),
.functions = ph1_ld4_functions,
.functions_count = ARRAY_SIZE(ph1_ld4_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
};
static int ph1_ld4_pinctrl_probe(struct udevice *dev)
.groups_count = ARRAY_SIZE(ph1_ld6b_groups),
.functions = ph1_ld6b_functions,
.functions_count = ARRAY_SIZE(ph1_ld6b_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
};
static int ph1_ld6b_pinctrl_probe(struct udevice *dev)
.groups_count = ARRAY_SIZE(ph1_pro4_groups),
.functions = ph1_pro4_functions,
.functions_count = ARRAY_SIZE(ph1_pro4_functions),
- .mux_bits = 4,
- .reg_stride = 8,
- .load_pinctrl = true,
+ .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
};
static int ph1_pro4_pinctrl_probe(struct udevice *dev)
.groups_count = ARRAY_SIZE(ph1_pro5_groups),
.functions = ph1_pro5_functions,
.functions_count = ARRAY_SIZE(ph1_pro5_functions),
- .mux_bits = 4,
- .reg_stride = 8,
- .load_pinctrl = true,
+ .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
};
static int ph1_pro5_pinctrl_probe(struct udevice *dev)
.groups_count = ARRAY_SIZE(proxstream2_groups),
.functions = proxstream2_functions,
.functions_count = ARRAY_SIZE(proxstream2_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
};
static int proxstream2_pinctrl_probe(struct udevice *dev)
.groups_count = ARRAY_SIZE(ph1_sld8_groups),
.functions = ph1_sld8_functions,
.functions_count = ARRAY_SIZE(ph1_sld8_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
};
static int ph1_sld8_pinctrl_probe(struct udevice *dev)
#ifndef __PINCTRL_UNIPHIER_H__
#define __PINCTRL_UNIPHIER_H__
+#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/types.h>
* @functions_count: number of pinmux functions
* @mux_bits: bit width of each pinmux register
* @reg_stride: stride of pinmux register address
- * @load_pinctrl: if true, LOAD_PINMUX register must be set to one for new
- * values in pinmux registers to become really effective
+ * @caps: SoC-specific capability flag
*/
struct uniphier_pinctrl_socdata {
const struct uniphier_pinctrl_pin *pins;
int groups_count;
const char * const *functions;
int functions_count;
- unsigned mux_bits;
- unsigned reg_stride;
- bool load_pinctrl;
+ unsigned caps;
+#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
};
#define UNIPHIER_PINCTRL_PIN(a, b) \