The SPI NOR nWP line is connected to GPIO PF7 on the SoM,
pull the GPIO line high by default to clear SPI NOR WP.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
};
};
+&gpiof {
+ snor-nwp {
+ gpio-hog;
+ gpios = <7 0>;
+ output-high;
+ line-name = "spi-nor-nwp";
+ };
+};
+
&i2c4 {
u-boot,dm-pre-reloc;
};
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_VIRT=y
+CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
CONFIG_DM_I2C=y