* Patch by Yuli Barcohen, 08 Nov 2004:

  Add support for Analogue & Micro Rattler boards.
  Tested on Rattler8248.

* Patch by Andre Renaud, 08 Nov 2004:
  Fix watchdog support in common/lcd.c

* Patch by Marc Leeman, 05 Nov 2003:
  Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU
  bug only affects the XPC8245 processors

diff --git a/CHANGELOG b/CHANGELOG
index c96d0cc8237afd2df25e42bcee2f6bf43cbf353d..e690bdd8a649303d8874ea67dc0b412de454f6fe 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,17 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Patch by Yuli Barcohen, 08 Nov 2004:
+  Add support for Analogue & Micro Rattler boards.
+  Tested on Rattler8248.
+
+* Patch by Andre Renaud, 08 Nov 2004:
+  Fix watchdog support in common/lcd.c
+
+* Patch by Marc Leeman, 05 Nov 2003:
+  Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU
+  bug only affects the XPC8245 processors
+
 * Patches by Josef Wagner, 29 Oct 2004:
   - Add support for MicroSys CPU87 board
   - Add support for MicroSys PM854 board

diff --git a/CREDITS b/CREDITS
index 7b4dfad8d52c574e8c1f642f73cc5085006201f0..252a4b2e7f667f2a097724ed6add0539e65013a7 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -40,6 +40,7 @@ D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
 D: Support for Zephyr Engineering ZPC.1900 board.
 D: Support for Interphase iSPAN boards.
 D: Support for Analogue&Micro Adder boards.
+D: Support for Analogue&Micro Rattler boards.
 W: http://www.arabellasw.com
 
 N: Jerry van Baren

diff --git a/MAINTAINERS b/MAINTAINERS
index 1434f8c83e532f7a3b28d65c4a2d3b118c17b34b..411512759381872a1a45df778c7217d7aad9b867 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -34,6 +34,7 @@ Yuli Barcohen <yuli@arabellasw.com>
        Adder                   MPC87x/MPC852T
        ISPAN                   MPC8260
        MPC8260ADS              MPC826x/MPC827x/MPC8280
+       Rattler                 MPC8248
        ZPC1900                 MPC8265
 
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>

diff --git a/MAKEALL b/MAKEALL
index 46fd95e81872e7454bb8bf92c8fbbf0bd72a248b..85c1de933a44e0a18c8cccd4072fa95ad04ef94e 100644 (file)
--- a/MAKEALL
+++ b/MAKEALL
@@ -98,11 +98,12 @@ LIST_824x=" \
 
 LIST_8260="    \
        atc             cogent_mpc8260  CPU86           CPU87           \
-       ep8260          gw8260          hymod           IPHASE4539      
+       ep8260          gw8260          hymod           IPHASE4539      \
        ISPAN           MPC8260ADS      MPC8266ADS      MPC8272ADS      \
-       PM826           PM828           ppmc8260        RPXsuper        \
-       rsdproto        sacsng          sbc8260         SCM             \
-       TQM8260_AC      TQM8260_AD      TQM8260_AE      ZPC1900         \
+       PM826           PM828           ppmc8260        Rattler8248     \
+       RPXsuper        rsdproto        sacsng          sbc8260         \
+       SCM             TQM8260_AC      TQM8260_AD      TQM8260_AE      \
+       ZPC1900                                                         \
 "
 
 #########################################################################

diff --git a/Makefile b/Makefile
index e6a7bef6e552c73b8be3fd376de307f4ef9ae4be..71ab9933aefea7eee57f7248ac50b9a059b9de14 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -972,7 +972,6 @@ CPU87_ROMBOOT_config: unconfig
        fi; \
        echo "export CONFIG_BOOT_ROM" >> config.mk;
 
-       
 ep8260_config: unconfig
        @./mkconfig $(@:_config=) ppc mpc8260 ep8260
 
@@ -1067,6 +1066,12 @@ PM828_ROMBOOT_PCI_config:        unconfig
 ppmc8260_config:       unconfig
        @./mkconfig $(@:_config=) ppc mpc8260 ppmc8260
 
+Rattler8248_config     \
+Rattler_config:                unconfig
+       $(if $(findstring 8248,$@), \
+       @echo "#define CONFIG_MPC8248" > include/config.h)
+       @./mkconfig -a Rattler ppc mpc8260 rattler
+
 RPXsuper_config:       unconfig
        @./mkconfig $(@:_config=) ppc mpc8260 rpxsuper
 

diff --git a/board/pm854/flash.c b/board/pm854/flash.c
index 73941e893e9663a1f6db3da6cd64bfac4dfed745..d714589280f1a2fceefaa36100044f91ae2038fc 100644 (file)
--- a/board/pm854/flash.c
+++ b/board/pm854/flash.c
@@ -134,7 +134,7 @@ void flash_print_info  (flash_info_t *info)
                                break;
        case FLASH_28F128J3A:   printf ("28F128J3A (128 Mbit, 128 x 128K)\n");
                                break;
-       
+
        default:                printf ("Unknown Chip Type\n");
                                break;
        }
@@ -224,14 +224,14 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
                info->size = 0x01000000;
                sector_offset = 0x40000;
                break;                          /* => 2x8 MB             */
-       
+
        case (INTEL_ID_28F128J3A):
                info->flash_id += FLASH_28F128J3A;
                info->sector_count = 128;
                info->size = 0x02000000;
                sector_offset = 0x40000;
                break;                          /* => 2x16 MB             */
-       
+
 
        case SHARP_ID_28F016SCL:
        case SHARP_ID_28F016SCZ:
@@ -325,7 +325,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
                        asm("sync");
 
                        last = start = get_timer (0);
-                       
+
                        /* Disable interrupts which might cause a timeout here */
                        flag = disable_interrupts();
 
@@ -367,7 +367,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
                                        last = now;
                                }
                        }
-                       
+
                        /* reset to read mode */
                        *addr = 0xFFFFFFFF;
                        asm("sync");

diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c
index 3eaf93e35e6a1a1e91638f5b45f605b639f276d8..94c492f7821483f0f0670bbdfe9b97fd87b52228 100644 (file)
--- a/board/pm854/pm854.c
+++ b/board/pm854/pm854.c
@@ -87,9 +87,9 @@ initdram(int board_type)
        {
            volatile ccsr_gur_t *gur= &immap->im_gur;
            int i,x;
-           
+
            x = 10;
-           
+
            /*
             * Work around to stabilize DDR DLL
             */
@@ -106,7 +106,7 @@ initdram(int board_type)
                asm("sync;isync;msync");
                x++;
            }
-       }       
+       }
 #endif
 
 #if defined(CONFIG_SPD_EEPROM)

diff --git a/board/rattler/Makefile b/board/rattler/Makefile
new file mode 100644 (file)
index 0000000..52f0fd6
--- /dev/null
+++ b/board/rattler/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   := $(BOARD).o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

diff --git a/board/rattler/config.mk b/board/rattler/config.mk
new file mode 100644 (file)
index 0000000..5fca8c7
--- /dev/null
+++ b/board/rattler/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2001-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Rattler series boards by Analogue & Micro
+#
+
+TEXT_BASE = 0xFE000000

diff --git a/board/rattler/rattler.c b/board/rattler/rattler.c
new file mode 100644 (file)
index 0000000..be7977d
--- /dev/null
+++ b/board/rattler/rattler.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Rattler boards family.
+ * Tested on Rattler8248.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {  /*            conf      ppar psor pdir podr pdat */
+       /* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
+       /* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
+       /* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
+       /* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
+       /* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
+       /* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
+       /* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
+       /* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
+       /* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
+       /* PA22 */ { 1,          0,   0,   1,   0,   1 }, /* Eth PHYs reset  */
+       /* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+       /* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+       /* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+       /* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+       /* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+       /* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+       /* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+       /* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+       /* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
+       /* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
+       /* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
+       /* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
+       /* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
+       /* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
+       /* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
+       /* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
+       /* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
+       /* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
+       /* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
+       /* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
+       /* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
+       /* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
+    },
+
+    /* Port B */
+    {   /*           conf      ppar psor pdir podr pdat */
+       /* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+       /* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+       /* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+       /* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+       /* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+       /* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+       /* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+       /* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+       /* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+       /* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+       /* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+       /* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+       /* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+       /* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+       /* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    },
+
+    /* Port C */
+    {   /*           conf      ppar psor pdir podr pdat */
+       /* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
+       /* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
+       /* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
+       /* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
+       /* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
+       /* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
+       /* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
+       /* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
+       /* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
+       /* PC22 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK10) */
+       /* PC21 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK11) */
+       /* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
+       /* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19            */
+       /* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
+       /* PC17 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK15) */
+       /* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
+       /* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
+       /* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
+       /* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
+       /* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
+       /* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
+       /* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
+       /* PC9  */ { 1,          0,   0,   1,   0,   1 }, /* MDIO            */
+       /* PC8  */ { 1,          0,   0,   1,   0,   1 }, /* MDC             */
+       /* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
+       /* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
+       /* PC5  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 TxD        */
+       /* PC4  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 RxD        */
+       /* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
+       /* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
+       /* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
+       /* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
+    },
+
+    /* Port D */
+    {   /*           conf      ppar psor pdir podr pdat */
+       /* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RxD        */
+       /* PD30 */ { 1,          1,   1,   1,   0,   0 }, /* SCC1 TxD        */
+       /* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
+       /* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
+       /* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
+       /* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
+       /* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
+       /* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
+       /* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
+       /* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22            */
+       /* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21            */
+       /* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20            */
+       /* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
+       /* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
+       /* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
+       /* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
+       /* PD15 */ { 0,          0,   0,   0,   0,   0 }, /* PD15            */
+       /* PD14 */ { 0,          0,   0,   0,   0,   0 }, /* PD14            */
+       /* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
+       /* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
+       /* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
+       /* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
+       /* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
+       /* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
+       /* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
+       /* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
+       /* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
+       /* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
+       /* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+       /* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    }
+};
+
+long int initdram(int board_type)
+{
+       long int msize = CFG_SDRAM_SIZE;
+
+#ifndef CFG_RAMBOOT
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
+       volatile memctl8260_t *memctl = &immap->im_memctl;
+       vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
+       uchar c = 0xFF;
+       uint psdmr = CFG_PSDMR;
+       int i;
+
+       immap->im_siu_conf.sc_ppc_acr  = 0x02;
+       immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
+       immap->im_siu_conf.sc_tescr1   = 0x00004000;
+
+       memctl->memc_mptpr = CFG_MPTPR;
+
+       /* Initialise 60x bus SDRAM */
+       memctl->memc_psrt = CFG_PSRT;
+       memctl->memc_or1  = CFG_SDRAM_OR;
+       memctl->memc_br1  = CFG_SDRAM_BR;
+       memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+       *ramaddr = c;
+       memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+       for (i = 0; i < 8; i++)
+               *ramaddr = c;
+       memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+       *ramaddr = c;
+       memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+       *ramaddr = c;
+#endif /* !CFG_RAMBOOT */
+
+       /* Return total 60x bus SDRAM size */
+       return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+       vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+       printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40);
+       return 0;
+}

diff --git a/board/rattler/u-boot.lds b/board/rattler/u-boot.lds
new file mode 100644 (file)
index 0000000..a0c0863
--- /dev/null
+++ b/board/rattler/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)              }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)              }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)               }
+  .rela.got      : { *(.rela.got)              }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)               }
+  .rela.bss      : { *(.rela.bss)              }
+  .rel.plt       : { *(.rel.plt)               }
+  .rela.plt      : { *(.rela.plt)              }
+  .init          : { *(.init)  }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o        (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)

diff --git a/common/lcd.c b/common/lcd.c
index d3ecd925fcfe5c792111f6057cfab7eed3c469ff..9713ea30819fcc21162790266c7d847f43611392 100644 (file)
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -40,13 +40,13 @@
 #include <post.h>
 #endif
 #include <lcd.h>
+#include <watchdog.h>
 
 #if defined(CONFIG_PXA250)
 #include <asm/byteorder.h>
 #endif
 
 #if defined(CONFIG_MPC823)
-#include <watchdog.h>
 #include <lcdvideo.h>
 #endif
 

diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c
index 965f4fd5ed230fe0f84aa454a18f26a1bd33a2bf..7871031b9709610ac9fa805992b1260af8172902 100644 (file)
--- a/cpu/mpc824x/cpu_init.c
+++ b/cpu/mpc824x/cpu_init.c
@@ -106,6 +106,21 @@ cpu_init_f (void)
        CONFIG_READ_BYTE(AMBOR,val);
        CONFIG_WRITE_BYTE(AMBOR,val|0x1);
 
+#if 0
+       /*
+        * The following bug only affects older (XPC8245) processors.
+        * DMA transfers initiated by external devices get corrupted due
+        * to a hardware scheduling problem.
+        *
+        * The effect is:
+        * when transferring X words, the first 32 words are transferred
+        * OK, the next 3 x 32 words are 'old' data (from previous DMA)
+        * while the rest of the X words is xferred fine.
+        *
+        * Disabling 3 of the 4 32 word hardware buffers solves the problem
+        * with no significant performance loss.
+        */
+
        CONFIG_READ_BYTE(PCMBCR,val);
        /* in order not to corrupt data which is being read over the PCI bus
        * with the PPC as slave, we need to reduce the number of PCMRBs to 1,
@@ -117,10 +132,8 @@ cpu_init_f (void)
 #else
        CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
        CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
-       /* default, 4 PCMRBs are used, so don't change the
-        * register is this is _really_ what you want: data
-        * corruption with no performance gain
-        */
+       /* default, 4 PCMRBs are used */
+#endif
 #endif
 #endif
 

diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 6b12258445e6d3f2c8099bc048017e74746962c4..0e0876f807d58e95ab6a0589121bf8c12443592a 100644 (file)
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -113,8 +113,6 @@
 
 #define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
 
-#undef CONFIG_CLOCKS_IN_MHZ            
-
 #define CONFIG_PREBOOT                                                         \
        "echo; "                                                                \
        "echo Type \"run flash_nfs\" to mount root filesystem over NFS; "       \

diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index bf7eb8e97a776b98f35211160b17dc8c7fe07a14..69e1bafcfda61a82afd8eedc7e10f1adc795c46a 100644 (file)
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -144,19 +144,14 @@
 #undef CFG_RAMBOOT
 #endif
 
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-
 /*
  * Local Bus Definitions
  */
- 
 #define CFG_LBC_LCRR           0x00030004    /* LB clock ratio reg */
 #define CFG_LBC_LBCR           0x00000000    /* LB config reg */
 #define CFG_LBC_LSRT           0x20000000    /* LB sdram refresh timer */
 #define CFG_LBC_MRTPR          0x20000000    /* LB refresh timer prescal*/
- 
+
 
 #define CONFIG_L1_INIT_RAM
 #define CFG_INIT_RAM_LOCK      1

diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
new file mode 100644 (file)
index 0000000..46dc78b
--- /dev/null
+++ b/include/configs/Rattler.h
@@ -0,0 +1,272 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * U-Boot configuration for Analogue&Micro Rattler boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_MPC8248
+#define CPU_ID_STR             "MPC8248"
+#else
+#define CONFIG_MPC8260
+#define CPU_ID_STR             "MPC8250"
+#endif /* CONFIG_MPC8248 */
+
+#define CONFIG_RATTLER                 /* Analogue&Micro Rattler board */
+
+#undef DEBUG
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define        CONFIG_CONS_ON_SMC              /* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC             /* It's not on SCC           */
+#undef CONFIG_CONS_NONE                /* It's not on external UART */
+#define CONFIG_CONS_INDEX      1       /* SMC1 is used for console  */
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CFG_CMD_NET must
+ * be removed from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC            /* Ethernet is on FCC     */
+#undef CONFIG_ETHER_NONE               /* No external Ethernet   */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#define CONFIG_ETHER_INDEX     1       /* FCC1 is used for Ethernet */
+
+#if   (CONFIG_ETHER_INDEX == 1)
+
+/* - Rx clock is CLK11
+ * - Tx clock is CLK10
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CFG_CMXFCR_MASK        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CFG_CMXFCR_VALUE       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
+#define CFG_CPMFCR_RAMTYPE     0
+#define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#elif (CONFIG_ETHER_INDEX == 2)
+
+/* - Rx clock is CLK15
+ * - Tx clock is CLK14
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CFG_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
+#define CFG_CPMFCR_RAMTYPE     0
+#define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII                     /* MII PHY management        */
+#define CONFIG_BITBANGMII              /* Bit-banged MDIO interface */
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT              2       /* Port C */
+#define MDIO_ACTIVE            (iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE          (iop->pdir &= ~0x00400000)
+#define MDIO_READ              ((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)              if(bit) iop->pdat |=  0x00400000; \
+                               else    iop->pdat &= ~0x00400000
+
+#define MDC(bit)               if(bit) iop->pdat |=  0x00800000; \
+                               else    iop->pdat &= ~0x00800000
+
+#define MIIDELAY               udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN      100000000       /* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE                38400
+
+#define CONFIG_COMMANDS                (CONFIG_CMD_DFL   \
+                               | CFG_CMD_DHCP    \
+                               | CFG_CMD_ECHO    \
+                               | CFG_CMD_IMMAP   \
+                               | CFG_CMD_JFFS2   \
+                               | CFG_CMD_MII     \
+                               | CFG_CMD_PING    \
+                               )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND     "bootm FE040000"        /* autoboot command */
+#define CONFIG_BOOTARGS                "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC             /* define if kgdb on SCC */
+#undef CONFIG_KGDB_NONE                /* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX      2       /* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE   115200  /* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2   /* include support for bzip2 compressed images */
+#undef CONFIG_WATCHDOG                 /* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2    "> "
+#define CFG_LONGHELP                   /* undef to save memory     */
+#define CFG_PROMPT             "=> "   /* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE             1024    /* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE             256     /* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size  */
+#define CFG_MAXARGS            16              /* max number of command args */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size  */
+
+#define CFG_MEMTEST_START      0x00100000      /* memtest works on */
+#define CFG_MEMTEST_END                0x00f00000      /* 1 ... 15 MB in DRAM  */
+
+#define CFG_LOAD_ADDR          0x100000        /* default load address */
+
+#define CFG_HZ                 1000    /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_FLASH_BASE         0xFE000000
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS    1       /* max num of flash banks       */
+#define CFG_MAX_FLASH_SECT     256     /* max num of sects on one chip */
+
+#define        CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_FIRST_BANK   0
+#define CFG_JFFS2_NUM_BANKS    CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_FIRST_SECTOR  16
+#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#define CFG_MONITOR_BASE       TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN                (192 << 10)     /* Reserve 192 kB for Monitor   */
+
+#define CFG_ENV_IS_IN_FLASH
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE      0x10000
+#define CFG_ENV_ADDR           (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+#define CFG_DEFAULT_IMMR       0xFF010000
+
+#define CFG_IMMR               0xF0000000
+
+#define CFG_INIT_RAM_ADDR      CFG_IMMR
+#define CFG_INIT_RAM_END       0x2000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE      128     /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_SDRAM_SIZE         32
+#define CFG_SDRAM_BR           (CFG_SDRAM_BASE | 0x00000041)
+#define CFG_SDRAM_OR           0xFE002EC0
+
+#define CFG_BCSR               0xFC000000
+
+/* Hard reset configuration word */
+#define CFG_HRCW_MASTER                0x0A06875A /* Not used - provided by FPGA */
+/* No slaves */
+#define CFG_HRCW_SLAVE1        0
+#define CFG_HRCW_SLAVE2        0
+#define CFG_HRCW_SLAVE3        0
+#define CFG_HRCW_SLAVE4        0
+#define CFG_HRCW_SLAVE5        0
+#define CFG_HRCW_SLAVE6        0
+#define CFG_HRCW_SLAVE7        0
+
+#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM          0x02    /* Software reboot                  */
+
+#define CFG_MALLOC_LEN         (4096 << 10)    /* Reserve 4 MB for malloc()    */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+
+#define CFG_CACHELINE_SIZE     32      /* For MPC8260 CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT          0
+#define CFG_HID0_FINAL         (HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CFG_HID2               0
+
+#define CFG_SIUMCR             0x0E04C000
+#define CFG_SYPCR              0xFFFFFFC3
+#define CFG_BCR                        0x00000000
+#define CFG_SCCR               SCCR_DFBRG01
+
+#define CFG_RMR                        RMR_CSRE
+#define CFG_TMCNTSC            (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CFG_PISCR              (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CFG_RCCR               0
+
+#define CFG_PSDMR              0x8249A452
+#define CFG_PSRT               0x1F
+#define CFG_MPTPR              0x2000
+
+#define CFG_BR0_PRELIM         (CFG_FLASH_BASE | 0x00001001)
+#define CFG_OR0_PRELIM         0xFF001ED6
+#define CFG_BR7_PRELIM         (CFG_BCSR | 0x00000801)
+#define CFG_OR7_PRELIM         0xFFFF87F6
+
+#define CFG_RESET_ADDRESS      0xC0000000
+
+#endif /* __CONFIG_H */