arm: ls102xa: Add NAND boot support for LS1021AQDS board

This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 704d683e83380fe6adb156b8552d89b6bc9583b7..ef775cf606ecde0fb96c967ed5adcdba8252e408 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -15,6 +15,8 @@
 #define CONFIG_SYS_IMMR                                0x01000000
 #define CONFIG_SYS_DCSRBAR                     0x20000000
 
+#define CONFIG_SYS_DCSR_DCFG_ADDR      (CONFIG_SYS_DCSRBAR + 0x00220000)
+
 #define CONFIG_SYS_FSL_DDR_ADDR                        (CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_CCI400_ADDR                 (CONFIG_SYS_IMMR + 0x00180000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x00530000)

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 98b268dffeb0a0a5fb948e9147792a50b3b8414b..5abc3a196eb572262d3d9399050c1e87993fb4e0 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -29,6 +29,11 @@
 #define ARCH_TIMER_CTRL_ENABLE         (1 << 0)
 #define SYS_COUNTER_CTRL_ENABLE                (1 << 24)
 
+#define DCFG_CCSR_PORSR1_RCW_MASK      0xff800000
+#define DCFG_CCSR_PORSR1_RCW_SRC_I2C   0x24800000
+
+#define DCFG_DCSR_PORCR1               0
+
 struct sys_info {
        unsigned long freq_processor[CONFIG_MAX_CPUS];
        unsigned long freq_systembus;

diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS
index 7a704cf25fbc9172791b543c0a9e285a0b1ef705..638833dc4126fd0a8dbdfde9fbedd020bcc1b736 100644 (file)
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -8,3 +8,4 @@ F:      configs/ls1021aqds_ddr4_nor_defconfig
 F:     configs/ls1021aqds_nor_SECURE_BOOT_defconfig
 F:     configs/ls1021aqds_sdcard_defconfig
 F:     configs/ls1021aqds_qspi_defconfig
+F:     configs/ls1021aqds_nand_defconfig

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 9fcd12988394e2224eaa354a4c329c938303a1f0..691e828c020242b805e995baff43afbec155ed1b 100644 (file)
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -187,6 +187,22 @@ void board_init_f(ulong dummy)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 
+#ifdef CONFIG_NAND_BOOT
+       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+       u32 porsr1, pinctl;
+
+       /*
+        * There is LS1 SoC issue where NOR, FPGA are inaccessible during
+        * NAND boot because IFC signals > IFC_AD7 are not enabled.
+        * This workaround changes RCW source to make all signals enabled.
+        */
+       porsr1 = in_be32(&gur->porsr1);
+       pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
+                DCFG_CCSR_PORSR1_RCW_SRC_I2C);
+       out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+                pinctl);
+#endif
+
        /* Set global data pointer */
        gd = &gdata;
 

diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
new file mode 100644 (file)
index 0000000..222c71d
--- /dev/null
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0608000a 00000000 00000000 00000000
+60000000 00407900 e0106a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000

diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
new file mode 100644 (file)
index 0000000..dad5274
--- /dev/null
+++ b/configs/ls1021aqds_nand_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021AQDS=y

diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index e336cb1c94b2c9a7d37a2ba168c45d5790f57b0b..fb827c5e74e096a37f71dcbdade8a5a350be6aaf 100644 (file)
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -254,3 +254,13 @@ void nand_boot(void)
        uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
        uboot();
 }
+
+#ifndef CONFIG_SPL_NAND_INIT
+void nand_init(void)
+{
+}
+
+void nand_deselect(void)
+{
+}
+#endif

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 6f8b43f351ea0ab809e3bbc1490974e11ebd8308..536d9f3a58bb0dffeb6413b7229b806e1aa912ba 100644 (file)
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -84,6 +84,39 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NO_FLASH
 #endif
 
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT    "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE           0x10000000
+#define CONFIG_SPL_MAX_SIZE            0x1a000
+#define CONFIG_SPL_STACK               0x1001d000
+#define CONFIG_SPL_PAD_TO              0x1c000
+#define CONFIG_SYS_TEXT_BASE           0x82000000
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    (400 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_PAGE_SIZE      2048
+#define CONFIG_SYS_NAND_U_BOOT_DST     CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_SPL_MALLOC_START    0x80200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000
+#define CONFIG_SPL_BSS_START_ADDR      0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x80000
+#define CONFIG_SYS_MONITOR_LEN         0x80000
+#endif
+
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE           0x67f80000
 #endif
@@ -261,6 +294,40 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FPGA_FTIM3          0x0
 #endif
 
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0              CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0               CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0           CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2               CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR3_EXT           CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3               CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3              CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3               CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0           CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1           CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2           CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3           CONFIG_SYS_FPGA_FTIM3
+#else
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK0              CONFIG_SYS_NOR_AMASK
@@ -293,6 +360,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1           CONFIG_SYS_FPGA_FTIM1
 #define CONFIG_SYS_CS3_FTIM2           CONFIG_SYS_FPGA_FTIM2
 #define CONFIG_SYS_CS3_FTIM3           CONFIG_SYS_FPGA_FTIM3
+#endif
 
 /*
  * Serial Port
@@ -492,6 +560,10 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE                        0x2000          /* 8KB */
 #define CONFIG_ENV_OFFSET              0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE           0x10000
+#elif defined(CONFIG_NAND_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE                        0x2000
+#define CONFIG_ENV_OFFSET              (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)