arm: dts: split mtk-reset.h into per-chip header

This follows the linux header rules to avoid conflict bitfields.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>

diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 3a868ea2ee85e22edd25f2a6f4db3c6c62df96d4..1135b1e1ae02657c19583079a4b98363c4846d55 100644 (file)
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -11,7 +11,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt7623-power.h>
-#include <dt-bindings/reset/mtk-reset.h>
+#include <dt-bindings/reset/mt7623-reset.h>
 #include "skeleton.dtsi"
 
 / {

diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index 8ff19162f06312a65a6abc79b98b52f36c5e7b25..b0c843bafdeadbc8f23910862cf11ceb522323c3 100644 (file)
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -10,7 +10,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/mt7629-power.h>
-#include <dt-bindings/reset/mtk-reset.h>
+#include <dt-bindings/reset/mt7629-reset.h>
 #include "skeleton.dtsi"
 
 / {

diff --git a/include/dt-bindings/reset/mt7623-reset.h b/include/dt-bindings/reset/mt7623-reset.h
new file mode 100644 (file)
index 0000000..a859a5b
--- /dev/null
+++ b/include/dt-bindings/reset/mt7623-reset.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MTK_RESET_H_
+#define _DT_BINDINGS_MTK_RESET_H_
+
+/* ETHSYS resets */
+#define ETHSYS_PPE_RST                 31
+#define ETHSYS_GMAC_RST                        23
+#define ETHSYS_FE_RST                  6
+#define ETHSYS_MCM_RST                 2
+#define ETHSYS_SYS_RST                 0
+
+/* HIFSYS resets */
+#define HIFSYS_PCIE2_RST               26
+#define HIFSYS_PCIE1_RST               25
+#define HIFSYS_PCIE0_RST               24
+#define HIFSYS_UPHY1_RST               22
+#define HIFSYS_UPHY0_RST               21
+#define HIFSYS_UHOST1_RST              4
+#define HIFSYS_UHOST0_RST              3
+
+#endif /* _DT_BINDINGS_MTK_RESET_H_ */

diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h
new file mode 100644 (file)
index 0000000..8f1634f
--- /dev/null
+++ b/include/dt-bindings/reset/mt7629-reset.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MTK_RESET_H_
+#define _DT_BINDINGS_MTK_RESET_H_
+
+/* PCIe Subsystem resets */
+#define PCIE1_CORE_RST                 19
+#define PCIE1_MMIO_RST                 20
+#define PCIE1_HRST                     21
+#define PCIE1_USER_RST                 22
+#define PCIE1_PIPE_RST                 23
+#define PCIE0_CORE_RST                 27
+#define PCIE0_MMIO_RST                 28
+#define PCIE0_HRST                     29
+#define PCIE0_USER_RST                 30
+#define PCIE0_PIPE_RST                 31
+
+/* SSUSB Subsystem resets */
+#define SSUSB_PHY_PWR_RST              3
+#define SSUSB_MAC_PWR_RST              4
+
+/* ETH Subsystem resets */
+#define ETHSYS_SYS_RST                 0
+#define ETHSYS_MCM_RST                 2
+#define ETHSYS_HSDMA_RST               5
+#define ETHSYS_FE_RST                  6
+#define ETHSYS_ESW_RST                 16
+#define ETHSYS_GMAC_RST                        23
+#define ETHSYS_EPHY_RST                        24
+#define ETHSYS_CRYPTO_RST              29
+#define ETHSYS_PPE_RST                 31
+
+#endif /* _DT_BINDINGS_MTK_RESET_H_ */

diff --git a/include/dt-bindings/reset/mtk-reset.h b/include/dt-bindings/reset/mtk-reset.h
deleted file mode 100644 (file)
index 78fcdab..0000000
--- a/include/dt-bindings/reset/mtk-reset.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 MediaTek Inc.
- */
-
-#ifndef _DT_BINDINGS_MTK_RESET_H_
-#define _DT_BINDINGS_MTK_RESET_H_
-
-/* ETHSYS */
-#define ETHSYS_PPE_RST                 31
-#define ETHSYS_EPHY_RST                        24
-#define ETHSYS_GMAC_RST                        23
-#define ETHSYS_ESW_RST                 16
-#define ETHSYS_FE_RST                  6
-#define ETHSYS_MCM_RST                 2
-#define ETHSYS_SYS_RST                 0
-
-/* HIFSYS resets */
-#define HIFSYS_PCIE2_RST               26
-#define HIFSYS_PCIE1_RST               25
-#define HIFSYS_PCIE0_RST               24
-#define HIFSYS_UPHY1_RST               22
-#define HIFSYS_UPHY0_RST               21
-#define HIFSYS_UHOST1_RST              4
-#define HIFSYS_UHOST0_RST              3
-
-#endif /* _DT_BINDINGS_MTK_RESET_H_ */