#define UART_TXCTRL_TXEN 0x1
#define UART_RXCTRL_RXEN 0x1
+/* IP register */
+#define UART_IP_RXWM 0x2
+
struct uart_sifive {
u32 txfifo;
u32 rxfifo;
struct sifive_uart_platdata {
unsigned long clock;
- int saved_input_char;
struct uart_sifive *regs;
};
return -EAGAIN;
ch &= UART_RXFIFO_DATA;
- return (!ch) ? -EAGAIN : ch;
+ return ch;
}
static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
if (gd->flags & GD_FLG_RELOC)
return 0;
- platdata->saved_input_char = 0;
_sifive_serial_init(platdata->regs);
return 0;
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
struct uart_sifive *regs = platdata->regs;
- if (platdata->saved_input_char > 0) {
- c = platdata->saved_input_char;
- platdata->saved_input_char = 0;
- return c;
- }
-
while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ;
return c;
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
struct uart_sifive *regs = platdata->regs;
- if (input) {
- if (platdata->saved_input_char > 0)
- return 1;
- platdata->saved_input_char = _sifive_serial_getc(regs);
- return (platdata->saved_input_char > 0) ? 1 : 0;
- } else {
+ if (input)
+ return (readl(®s->ip) & UART_IP_RXWM);
+ else
return !!(readl(®s->txfifo) & UART_TXFIFO_FULL);
- }
}
static int sifive_serial_ofdata_to_platdata(struct udevice *dev)