meesc ARM926EJS (AT91SAM9263 SoC)
+Sedji Gaouaou<sedji.gaouaou@atmel.com>
+ at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC)
+ at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC)
+
Marius Gröger <mag@sysgo.de>
impa7 ARM720T (EP7211)
## AT91 Systems
#########################################################################
-LIST_at91=" \
- afeb9260 \
- at91cap9adk \
- at91rm9200dk \
- at91rm9200ek \
- at91sam9260ek \
- at91sam9261ek \
- at91sam9263ek \
- at91sam9g20ek \
- at91sam9rlek \
- cmc_pu2 \
- csb637 \
- kb9202 \
- meesc \
- mp2usb \
- m501sk \
- pm9261 \
- pm9263 \
+LIST_at91=" \
+ afeb9260 \
+ at91cap9adk \
+ at91rm9200dk \
+ at91rm9200ek \
+ at91sam9260ek \
+ at91sam9261ek \
+ at91sam9263ek \
+ at91sam9g10ek \
+ at91sam9g20ek \
+ at91sam9m10g45ek \
+ at91sam9rlek \
+ cmc_pu2 \
+ csb637 \
+ kb9202 \
+ meesc \
+ mp2usb \
+ m501sk \
+ pm9261 \
+ pm9263 \
"
#########################################################################
sh7763rdp \
sh7785lcr \
ap325rxa \
+ espt \
"
LIST_sh=" \
$(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT)
$(GEN_UBOOT)
ifeq ($(CONFIG_KALLSYMS),y)
- smap=`$(call SYSTEM_MAP,u-boot) | awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\0"}'` ; \
+ smap=`$(call SYSTEM_MAP,u-boot) | awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
$(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" -c common/system_map.c -o $(obj)common/system_map.o
$(GEN_UBOOT) $(obj)common/system_map.o
endif
at91sam9261ek_nandflash_config \
at91sam9261ek_dataflash_cs0_config \
at91sam9261ek_dataflash_cs3_config \
-at91sam9261ek_config : unconfig
- @mkdir -p $(obj)include
+at91sam9261ek_config \
+at91sam9g10ek_nandflash_config \
+at91sam9g10ek_dataflash_cs0_config \
+at91sam9g10ek_dataflash_cs3_config \
+at91sam9g10ek_config : unconfig
+ @mkdir -p $(obj)include
+ @if [ "$(findstring 9g10,$@)" ] ; then \
+ echo "#define CONFIG_AT91SAM9G10EK 1" >>$(obj)include/config.h ; \
+ $(XECHO) "... 9G10 Variant" ; \
+ else \
+ echo "#define CONFIG_AT91SAM9261EK 1" >>$(obj)include/config.h ; \
+ fi;
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
- elif [ "$(findstring dataflash_cs3,$@)" ] ; then \
+ elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_DATAFLASH_CS3 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in SPI DATAFLASH CS3" ; \
else \
pm9261_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9261 ronetix at91
+at91sam9m10g45ek_nandflash_config \
+at91sam9m10g45ek_dataflash_config \
+at91sam9m10g45ek_dataflash_cs0_config \
+at91sam9m10g45ek_config \
+at91sam9g45ekes_nandflash_config \
+at91sam9g45ekes_dataflash_config \
+at91sam9g45ekes_dataflash_cs0_config \
+at91sam9g45ekes_config : unconfig
+ @mkdir -p $(obj)include
+ @if [ "$(findstring 9m10,$@)" ] ; then \
+ echo "#define CONFIG_AT91SAM9M10G45EK 1" >>$(obj)include/config.h ; \
+ $(XECHO) "... 9M10G45 Variant" ; \
+ else \
+ echo "#define CONFIG_AT91SAM9G45EKES 1" >>$(obj)include/config.h ; \
+ fi;
+
+ @if [ "$(findstring _nandflash,$@)" ] ; then \
+ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
+ $(XECHO) "... with environment variable in NAND FLASH" ; \
+ else \
+ echo "#define CONFIG_ATMEL_SPI 1" >>$(obj)include/config.h ; \
+ $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+ fi;
+ @$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91
+
pm9263_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
xtract_sh7785lcr = $(subst _32bit,,$(subst _config,,$1))
sh7785lcr_32bit_config \
sh7785lcr_config : unconfig
- @ >include/config.h
- @echo "#define CONFIG_SH7785LCR 1" >> include/config.h
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/renesas/sh7785lcr
+ @echo "#define CONFIG_SH7785LCR 1" > $(obj)include/config.h
@if [ "$(findstring 32bit, $@)" ] ; then \
echo "#define CONFIG_SH_32BIT 1" >> $(obj)include/config.h ; \
- cp $(obj)board/renesas/sh7785lcr/u-boot_32bit \
- $(obj)board/renesas/sh7785lcr/u-boot.lds ; \
echo "TEXT_BASE = 0x8ff80000" > \
$(obj)board/renesas/sh7785lcr/config.tmp ; \
$(XECHO) " ... enable 32-Bit Address Extended Mode" ; \
- else \
- cp $(obj)board/renesas/sh7785lcr/u-boot_29bit \
- $(obj)board/renesas/sh7785lcr/u-boot.lds ; \
fi
@$(MKCONFIG) -a $(call xtract_sh7785lcr,$@) sh sh4 sh7785lcr renesas
@echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa renesas
+espt_config : unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_ESPT 1" > $(obj)include/config.h
+ @$(MKCONFIG) -a $(@:_config=) sh sh4 espt
+
#========================================================================
# SPARC
#========================================================================
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
- @[ ! -d $(obj)api_examples ] || find $(obj)api_examples -name "*" -type l -print | xargs rm -f
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
-crc32.c
-ctype.c
demo
demo.bin
-ppcstring.S
-string.c
-vsprintf.c
include $(TOPDIR)/config.mk
-ELF-$(CONFIG_API) += demo
-BIN-$(CONFIG_API) += demo.bin
-ELF := $(ELF-y)
-BIN := $(BIN-y)
-
-#CFLAGS += -v
-
-COBJS-$(CONFIG_API) += $(ELF:=.o)
-SOBJS-$(CONFIG_API) += crt0.o
+# Resulting ELF and binary exectuables will be named demo and demo.bin
+OUTPUT-$(CONFIG_API) = $(obj)demo
+OUTPUT = $(OUTPUT-y)
+
+# Source files located in the api_examples directory
+SOBJ_FILES-$(CONFIG_API) += crt0.o
+COBJ_FILES-$(CONFIG_API) += demo.o
+COBJ_FILES-$(CONFIG_API) += glue.o
+COBJ_FILES-$(CONFIG_API) += libgenwrap.o
+
+# Source files which exist outside the api_examples directory
+EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/crc32.o
+EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/ctype.o
+EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/string.o
+EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/vsprintf.o
ifeq ($(ARCH),ppc)
-SOBJS-$(CONFIG_API) += ppcstring.o
+EXT_SOBJ_FILES-$(CONFIG_API) += lib_ppc/ppcstring.o
endif
-COBJS := $(COBJS-y)
-SOBJS := $(SOBJS-y)
-
-LIB = $(obj)libglue.a
-LIBCOBJS-$(CONFIG_API) += glue.o crc32.o ctype.o string.o vsprintf.o \
- libgenwrap.o
-LIBCOBJS := $(LIBCOBJS-y)
-LIBOBJS = $(addprefix $(obj),$(SOBJS) $(LIBCOBJS))
+# Create a list of source files so their dependencies can be auto-generated
+SRCS += $(addprefix $(SRCTREE)/,$(EXT_COBJ_FILES-y:.o=.c))
+SRCS += $(addprefix $(SRCTREE)/,$(EXT_SOBJ_FILES-y:.o=.S))
+SRCS += $(addprefix $(SRCTREE)/api_examples/,$(COBJ_FILES-y:.o=.c))
+SRCS += $(addprefix $(SRCTREE)/api_examples/,$(SOBJ_FILES-y:.o=.S))
-SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(SOBJS:.o=.S)
-OBJS := $(addprefix $(obj),$(COBJS))
-ELF := $(addprefix $(obj),$(ELF))
-BIN := $(addprefix $(obj),$(BIN))
+# Create a list of object files to be compiled
+OBJS += $(addprefix $(obj),$(SOBJ_FILES-y))
+OBJS += $(addprefix $(obj),$(COBJ_FILES-y))
+OBJS += $(addprefix $(obj),$(notdir $(EXT_COBJ_FILES-y)))
+OBJS += $(addprefix $(obj),$(notdir $(EXT_SOBJ_FILES-y)))
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
CPPFLAGS += -I..
-all: $(obj).depend $(OBJS) $(LIB) $(ELF) $(BIN)
+all: $(obj).depend $(OUTPUT)
#########################################################################
-$(LIB): $(obj).depend $(LIBOBJS)
- $(AR) $(ARFLAGS) $@ $(LIBOBJS)
-
-$(ELF):
-$(obj)%: $(obj)%.o $(LIB)
- $(LD) $(obj)crt0.o -Ttext $(LOAD_ADDR) \
- -o $@ $< $(LIB) \
- -L$(gcclibdir) -lgcc
-
-$(BIN):
-$(obj)%.bin: $(obj)%
- $(OBJCOPY) -O binary $< $@ 2>/dev/null
-$(obj)crc32.c:
- @rm -f $(obj)crc32.c
- ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c
+$(OUTPUT): $(OBJS)
+ $(LD) -Ttext $(LOAD_ADDR) -o $@ $^ -L$(gcclibdir) -lgcc
+ $(OBJCOPY) -O binary $@ $(OUTPUT).bin 2>/dev/null
-$(obj)ctype.c:
- @rm -f $(obj)ctype.c
- ln -s $(src)../lib_generic/ctype.c $(obj)ctype.c
+# Rule to build generic library C files
+$(obj)%.o: $(SRCTREE)/lib_generic/%.c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
-$(obj)string.c:
- @rm -f $(obj)string.c
- ln -s $(src)../lib_generic/string.c $(obj)string.c
-
-$(obj)vsprintf.c:
- @rm -f $(obj)vsprintf.c
- ln -s $(src)../lib_generic/vsprintf.c $(obj)vsprintf.c
-
-ifeq ($(ARCH),ppc)
-$(obj)ppcstring.S:
- @rm -f $(obj)ppcstring.S
- ln -s $(src)../lib_ppc/ppcstring.S $(obj)ppcstring.S
-endif
+# Rule to build architecture-specific library assembly files
+$(obj)%.o: $(SRCTREE)/lib_$(ARCH)/%.S
+ $(CC) -g $(CFLAGS) -c -o $@ $<
#########################################################################
LIB = $(obj)lib$(BOARD).a
-COBJS := versatile.o flash.o
+COBJS := versatile.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Board support for 1 or 2 flash devices */
-#define FLASH_PORT_WIDTH32
-#undef FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#define SWAP(x) __swab16(x)
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#define SWAP(x) __swab32(x)
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-
-/* Flash Organization Structure */
-typedef struct OrgDef {
- unsigned int sector_number;
- unsigned int sector_size;
-} OrgDef;
-
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256K3[] = {
- {256, 128 * 1024}, /* 256 * 128kBytes sectors */
-};
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-unsigned long flash_init (void);
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-void flash_print_info (flash_info_t * info);
-void flash_unprotect_sectors (FPWV * addr);
-int flash_erase (flash_info_t * info, int s_first, int s_last);
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-
-/*-----------------------------------------------------------------------
- */
-
-static void flash_vpp(int on)
-{
- unsigned int tmp;
-
- tmp = *(unsigned int *)(VERSATILE_FLASHCTRL);
-
- if (on)
- tmp |= VERSATILE_FLASHPROG_FLVPPEN;
- else
- tmp &= ~VERSATILE_FLASHPROG_FLVPPEN;
-
- *(unsigned int *)(VERSATILE_FLASHCTRL) = tmp;
-}
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_vpp(1);
- flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- flash_vpp(0);
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
- OrgDef *pOrgDef;
-
- pOrgDef = OrgIntel_28F256K3;
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- if (i > 255) {
- info->start[i] = base + (i * 0x8000);
- info->protect[i] = 0;
- } else {
- info->start[i] = base +
- (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F256L18T:
- printf ("FLASH 28F256L18T\n");
- break;
- case FLASH_28F256K3:
- printf ("FLASH 28F256K3\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
- volatile FPW value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = (FPW) 0x00AA00AA;
- addr[0x2AAA] = (FPW) 0x00550055;
- addr[0x5555] = (FPW) 0x00900090;
-
- mb ();
- value = addr[0];
- switch (value) {
-
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[1]; /* device ID */
- switch (value) {
-
- case (FPW) (INTEL_ID_28F256L18T):
- info->flash_id += FLASH_28F256L18T;
- info->sector_count = 259;
- info->size = 0x02000000;
- break; /* => 32 MB */
-
- case (FPW)(INTEL_ID_28F256K3):
- info->flash_id += FLASH_28F256K3;
- info->sector_count = 256;
- info->size = 0x02000000;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/* unprotects a sector for write and erase
- * on some intel parts, this unprotects the entire chip, but it
- * wont hurt to call this additional times per sector...
- */
-void flash_unprotect_sectors (FPWV * addr)
-{
-#define PD_FINTEL_WSMS_READY_MASK 0x0080
-
- *addr = (FPW) 0x00500050; /* clear status register */
-
- /* this sends the clear lock bit command */
- *addr = (FPW) 0x00600060;
- *addr = (FPW) 0x00D000D0;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type, start, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- flash_vpp(1);
-
- start = get_timer (0);
- last = start;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- flash_unprotect_sectors (addr);
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
-
- *addr = (FPW) 0x00500050;/* clear status register */
- *addr = (FPW) 0x00200020;/* erase setup */
- *addr = (FPW) 0x00D000D0;/* erase confirm */
-
- while (((status =
- *addr) & (FPW) 0x00800080) !=
- (FPW) 0x00800080) {
- if (get_timer_masked () >
- CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- /* suspend erase */
- *addr = (FPW) 0x00B000B0;
- /* reset to read mode */
- *addr = (FPW) 0x00FF00FF;
- rcode = 1;
- break;
- }
- }
-
- /* clear status register cmd. */
- *addr = (FPW) 0x00500050;
- *addr = (FPW) 0x00FF00FF;/* resest to read mode */
- printf (" done\n");
- }
- }
-
- flash_vpp(0);
-
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
-
- flash_vpp(1);
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- flash_vpp(0);
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- flash_vpp(0);
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- flash_vpp(0);
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- rc = write_data (info, wp, SWAP (data));
-
- flash_vpp(0);
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr);
- return (2);
- }
-
- flash_vpp(1);
-
- flash_unprotect_sectors (addr);
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
-
- /* wait while polling the status register */
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- flash_vpp(0);
- return (1);
- }
- }
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- flash_vpp(0);
- return (0);
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
+#ifdef CONFIG_AT91SAM9G10EK
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+#else
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+#endif
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
static void at91sam9261ek_dm9000_hw_init(void)
{
/* Configure SMC CS2 for DM9000 */
+#ifdef CONFIG_AT91SAM9G10EK
+ at91_sys_write(AT91_SMC_SETUP(2),
+ AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(3) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(2),
+ AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(8) |
+ AT91_SMC_NRDPULSE_(6) | AT91_SMC_NCS_RDPULSE_(8));
+ at91_sys_write(AT91_SMC_CYCLE(2),
+ AT91_SMC_NWECYCLE_(20) | AT91_SMC_NRDCYCLE_(20));
+ at91_sys_write(AT91_SMC_MODE(2),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+ AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
+ AT91_SMC_TDF_(1));
+#else
at91_sys_write(AT91_SMC_SETUP(2),
AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
AT91_SMC_TDF_(1));
+#endif
/* Configure Reset signal as output */
at91_set_gpio_output(AT91_PIN_PC10, 0);
at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
+#ifdef CONFIG_AT91SAM9G10EK
+ gd->fb_base = CONFIG_AT91SAM9G10_LCD_BASE;
+#else
gd->fb_base = AT91SAM9261_SRAM_BASE;
+#endif
}
#ifdef CONFIG_LCD_INFO
/* Enable Ctrlc */
console_init_f();
+#ifdef CONFIG_AT91SAM9G10EK
+ /* arch number of AT91SAM9G10EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
+#else
/* arch number of AT91SAM9261EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
+#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
--- /dev/null
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += at91sam9m10g45ek.o
+COBJS-y += led.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9m10g45ek_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ at91_sys_write(AT91_MATRIX_EBICSA,
+ csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_DBW_8 |
+#endif
+ AT91_SMC_TDF_(3));
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9m10g45ek_macb_hw_init(void)
+{
+ unsigned long rstc;
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA15) => PHY normal mode (not Test mode)
+ * ERX0 (PA12) => PHY ADDR0
+ * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA12) |
+ pin_to_mask(AT91_PIN_PA13),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+ rstc = at91_sys_read(AT91_RSTC_MR);
+
+ /* Need to reset PHY -> 500ms reset */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ (AT91_RSTC_ERSTL & (0x0D << 8)) |
+ AT91_RSTC_URSTEN);
+
+ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+ /* Wait for end hardware reset */
+ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+ /* Restore NRST value */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ (rstc) |
+ AT91_RSTC_URSTEN);
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA12) |
+ pin_to_mask(AT91_PIN_PA13),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+
+vidinfo_t panel_info = {
+ vl_col: 480,
+ vl_row: 272,
+ vl_clk: 9000000,
+ vl_sync: ATMEL_LCDC_INVLINE_NORMAL |
+ ATMEL_LCDC_INVFRAME_NORMAL,
+ vl_bpix: 3,
+ vl_tft: 1,
+ vl_hsync_len: 45,
+ vl_left_margin: 1,
+ vl_right_margin:1,
+ vl_vsync_len: 1,
+ vl_upper_margin:40,
+ vl_lower_margin:1,
+ mmio: AT91SAM9G45_LCDC_BASE,
+};
+
+
+void lcd_enable(void)
+{
+ at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
+}
+
+static void at91sam9m10g45ek_lcd_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
+ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
+ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
+ at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
+ at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
+
+ at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
+ at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
+ at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
+ at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
+ at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
+ at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
+ at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
+ at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
+ at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
+ at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
+ at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
+ at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
+ at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
+ at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
+ at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
+ at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
+ at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
+ at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
+ at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
+ at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
+ at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
+ at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
+ at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
+ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
+
+ gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+ int i;
+ char temp[32];
+
+ lcd_printf ("%s\n", U_BOOT_VERSION);
+ lcd_printf ("(C) 2008 ATMEL Corp\n");
+ lcd_printf ("at91support@atmel.com\n");
+ lcd_printf ("%s CPU at %s MHz\n",
+ AT91_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+ lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
+ dram_size >> 20,
+ nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+
+ /* arch number of AT91SAM9M10G45EK-Board */
+#ifdef CONFIG_AT91SAM9M10G45EK
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
+#elif defined CONFIG_AT91SAM9G45EKES
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
+#endif
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+ at91sam9m10g45ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+ at91sam9m10g45ek_macb_hw_init();
+#endif
+
+#ifdef CONFIG_LCD
+ at91sam9m10g45ek_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch(slave->cs) {
+ case 1:
+ at91_set_gpio_output(AT91_PIN_PB18, 0);
+ break;
+ case 0:
+ default:
+ at91_set_gpio_output(AT91_PIN_PB3, 0);
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch(slave->cs) {
+ case 1:
+ at91_set_gpio_output(AT91_PIN_PB18, 1);
+ break;
+ case 0:
+ default:
+ at91_set_gpio_output(AT91_PIN_PB3, 1);
+ break;
+ }
+}
+#endif /* CONFIG_ATMEL_SPI */
--- /dev/null
+TEXT_BASE = 0x73f00000
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
+
+ at91_set_gpio_output(CONFIG_RED_LED, 1);
+ at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
--- /dev/null
+#
+# Copyright (C) 2009 Renesas Solutions Corp.
+# Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+#
+# board/espt/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := espt.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# board/espt/config.mk
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000
--- /dev/null
+/*
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/espt/espt.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+ puts("BOARD: ESPT-GIGA\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
--- /dev/null
+/*
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/espt/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ write32 WDTCSR_A, WDTCSR_D
+
+ write32 WDTST_A, WDTST_D
+
+ write32 WDTBST_A, WDTBST_D
+
+ write32 CCR_A, CCR_CACHE_ICI_D
+
+ write32 MMUCR_A, MMU_CONTROL_TI_D
+
+ write32 MSTPCR0_A, MSTPCR0_D
+
+ write32 MSTPCR1_A, MSTPCR1_D
+
+ write32 RAMCR_A, RAMCR_D
+
+ /*
+ * Setting infomation from
+ * original ESPT-GIGA bootloader register
+ */
+ write32 MMSEL_A, MMSEL_D
+
+ /* dummy */
+ mov.l @r1, r2
+ mov.l @r1, r2
+ synco
+
+ write32 BCR_A, BCR_D
+
+ write32 CS0BCR_A, CS0BCR_D
+
+ write32 CS0WCR_A, CS0WCR_D
+
+ /*
+ * DDR-SDRAM setting
+ */
+
+ /* set DDR-SDRAM dummy read */
+ write32 MMSEL_A, MMSEL_D
+
+ mov.l MMSEL_A, r0
+ synco
+ mov.l @r0, r1
+ synco
+
+ mov.l CS0_A, r0
+ synco
+ mov.l @r0, r1
+ synco
+
+ /* set DDR-SDRAM bus/endian etc */
+ write32 MIM_U_A, MIM_U_D
+
+ write32 MIM_L_A, MIM_L_D0
+
+ write32 SDR_L_A, SDR_L_A_D0
+
+ write32 STR_L_A, STR_L_A_D0
+
+ /* DDR-SDRAM access control */
+ write32 MIM_L_A, MIM_L_D1
+
+ write32 SCR_L_A, SCR_L_A_D0
+
+ write32 SCR_L_A, SCR_L_A_D1
+
+ write32 EMRS_A, EMRS_D
+
+ write32 MRS1_A, MRS1_D
+
+ write32 MIM_U_A, MIM_U_D
+
+ write32 MIM_L_A, MIM_L_A_D2
+
+ write32 SCR_L_A, SCR_L_A_D2
+
+ write32 SCR_L_A, SCR_L_A_D2
+
+ write32 MRS2_A, MRS2_D
+
+ /* wait 200us */
+ wait_timer REPEAT_R3
+
+ /* GPIO setting */
+ write16 PSEL0_A, PSEL0_D
+
+ write16 PSEL1_A, PSEL1_D
+
+ write16 PSEL2_A, PSEL2_D
+
+ write16 PSEL3_A, PSEL3_D
+
+ write16 PSEL4_A, PSEL4_D
+
+ write8 PADR_A, PADR_D
+
+ write16 PACR_A, PACR_D
+
+ write8 PBDR_A, PBDR_D
+
+ write16 PBCR_A, PBCR_D
+
+ write8 PCDR_A, PCDR_D
+
+ write16 PCCR_A, PCCR_D
+
+ write8 PDDR_A, PDDR_D
+
+ write16 PDCR_A, PDCR_D
+
+ write16 PECR_A, PECR_D
+
+ write16 PFCR_A, PFCR_D
+
+ write16 PGCR_A, PGCR_D
+
+ write16 PHCR_A, PHCR_D
+
+ write16 PICR_A, PICR_D
+
+ write8 PJDR_A, PJDR_D
+
+ write16 PJCR_A, PJCR_D
+
+ /* wait 50us */
+ wait_timer REPEAT_R3
+
+ write8 PKDR_A, PKDR_D
+
+ write16 PKCR_A, PKCR_D
+
+ write16 PLCR_A, PLCR_D
+
+ write16 PMCR_A, PMCR_D
+
+ write16 PNCR_A, PNCR_D
+
+ write16 POCR_A, POCR_D
+
+
+ /* ICR0 ,ICR1 */
+ write32 ICR0_A, ICR0_D
+
+ write32 ICR1_A, ICR1_D
+
+ /* USB Host */
+ write32 USB_USBHSC_A, USB_USBHSC_D
+
+ write32 CCR_A, CCR_CACHE_D_2
+
+ rts
+ nop
+
+ .align 2
+
+/* GPIO Crontrol Register */
+PACR_A: .long 0xFFEF0000
+PBCR_A: .long 0xFFEF0002
+PCCR_A: .long 0xFFEF0004
+PDCR_A: .long 0xFFEF0006
+PECR_A: .long 0xFFEF0008
+PFCR_A: .long 0xFFEF000A
+PGCR_A: .long 0xFFEF000C
+PHCR_A: .long 0xFFEF000E
+PICR_A: .long 0xFFEF0010
+PJCR_A: .long 0xFFEF0012
+PKCR_A: .long 0xFFEF0014
+PLCR_A: .long 0xFFEF0016
+PMCR_A: .long 0xFFEF0018
+PNCR_A: .long 0xFFEF001A
+POCR_A: .long 0xFFEF001C
+
+/* GPIO Data Register */
+PADR_A: .long 0xFFEF0020
+PBDR_A: .long 0xFFEF0022
+PCDR_A: .long 0xFFEF0024
+PDDR_A: .long 0xFFEF0026
+PJDR_A: .long 0xFFEF0032
+PKDR_A: .long 0xFFEF0034
+
+/* GPIO Set data */
+PADR_D: .long 0x00000000
+PACR_D: .long 0x00001400
+PBDR_D: .long 0x00000000
+PBCR_D: .long 0x0000555A
+PCDR_D: .long 0x00000000
+PCCR_D: .long 0x00005555
+PDDR_D: .long 0x00000000
+PDCR_D: .long 0x00000155
+PECR_D: .long 0x00000000
+PFCR_D: .long 0x00000000
+PGCR_D: .long 0x00000000
+PHCR_D: .long 0x00000000
+PICR_D: .long 0x00000800
+PJDR_D: .long 0x00000006
+PJCR_D: .long 0x00005A57
+PKDR_D: .long 0x00000000
+PKCR_D: .long 0x0000FFF9
+PLCR_D: .long 0x0000C330
+PMCR_D: .long 0x0000FFFF
+PNCR_D: .long 0x00000242
+POCR_D: .long 0x00000000
+
+/* Pin Select */
+PSEL0_A: .long 0xFFEF0070
+PSEL1_A: .long 0xFFEF0072
+PSEL2_A: .long 0xFFEF0074
+PSEL3_A: .long 0xFFEF0076
+PSEL4_A: .long 0xFFEF0078
+PSEL0_D: .long 0x0001
+PSEL1_D: .long 0x2400
+PSEL2_D: .long 0x0000
+PSEL3_D: .long 0x2421
+PSEL4_D: .long 0x0000
+
+MMSEL_A: .long 0xFE600020
+BCR_A: .long 0xFF801000
+CS0BCR_A: .long 0xFF802000
+CS0WCR_A: .long 0xFF802008
+ICR0_A: .long 0xFFD00000
+ICR1_A: .long 0xFFD0001C
+
+MMSEL_D: .long 0xA5A50000
+BCR_D: .long 0x05000000
+CS0BCR_D: .long 0x232306F0
+CS0WCR_D: .long 0x00011104
+ICR0_D: .long 0x80C00000
+ICR1_D: .long 0x00020000
+
+/* RWBT Address */
+WDTST_A: .long 0xFFCC0000
+WDTCSR_A: .long 0xFFCC0004
+WDTBST_A: .long 0xFFCC0008
+/* RWBT Data */
+WDTST_D: .long 0x5A000FFF
+WDTCSR_D: .long 0xA5000000
+WDTBST_D: .long 0x55000000
+
+/* Cache Address */
+CCR_A: .long 0xFF00001C
+MMUCR_A: .long 0xFF000010
+RAMCR_A: .long 0xFF000074
+
+/* Cache Data */
+CCR_CACHE_ICI_D:.long 0x00000800
+CCR_CACHE_D_2: .long 0x00000103
+MMU_CONTROL_TI_D:.long 0x00000004
+RAMCR_D: .long 0x00000200
+
+/* Low power mode control Address */
+MSTPCR0_A: .long 0xFFC80030
+MSTPCR1_A: .long 0xFFC80038
+/* Low power mode control Data */
+MSTPCR0_D: .long 0x00000000
+MSTPCR1_D: .long 0x00000000
+
+REPEAT0_R3: .long 0x00002000
+REPEAT_R3: .long 0x00000200
+CS0_A: .long 0xA8000000
+
+MIM_U_A: .long 0xFE800008
+MIM_L_A: .long 0xFE80000C
+SCR_U_A: .long 0xFE800010
+SCR_L_A: .long 0xFE800014
+STR_U_A: .long 0xFE800018
+STR_L_A: .long 0xFE80001C
+SDR_U_A: .long 0xFE800030
+SDR_L_A: .long 0xFE800034
+EMRS_A: .long 0xFE902000
+MRS1_A: .long 0xFE900B08
+MRS2_A: .long 0xFE900308
+
+MIM_U_D: .long 0x00000000
+MIM_L_D0: .long 0x04100008
+MIM_L_D1: .long 0x02EE0009
+MIM_L_D2: .long 0x02EE0209
+
+SDR_L_A_D0: .long 0x00000300
+STR_L_A_D0: .long 0x00010040
+MIM_L_A_D1: .long 0x04100009
+SCR_L_A_D0: .long 0x00000003
+SCR_L_A_D1: .long 0x00000002
+MIM_L_A_D2: .long 0x04100209
+SCR_L_A_D2: .long 0x00000004
+
+SCR_L_NORMAL: .long 0x00000000
+SCR_L_NOP: .long 0x00000001
+SCR_L_PALL: .long 0x00000002
+SCR_L_CKE_EN: .long 0x00000003
+SCR_L_CBR: .long 0x00000004
+
+STR_L_D: .long 0x000F3980
+SDR_L_D: .long 0x00000400
+EMRS_D: .long 0x00000000
+MRS1_D: .long 0x00000000
+MRS2_D: .long 0x00000000
+
+/* USB */
+USB_USBHSC_A: .long 0xFFEC80F0
+USB_USBHSC_D: .long 0x00000000
+++ /dev/null
-/*
- * Copyright (C) 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- Base address of internal SDRAM is 0x8C000000.
- U-Boot resides in the last 256 kB of the 64 MB.
-
- NOTE: This address must match with the definition of
- TEXT_BASE in config.mk (in this directory).
-
- */
- . = 0x8C000000 + (64*1024*1024) - (256*1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh3/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
+++ /dev/null
-/*
- * Copyrigth (c) 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * Copyrigth (c) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- Base address of internal SDRAM is 0x0C000000.
- Although size of SDRAM can be either 16 or 32 MBytes,
- we assume 16 MBytes (ie ignore upper half if the full
- 32 MBytes is present).
-
- NOTE: This address must match with the definition of
- TEXT_BASE in config.mk (in this directory).
-
- */
- . = 0x8C000000 + (64*1024*1024) - (256*1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh3/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
+++ /dev/null
-/*
- * Copyrigth (c) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- Base address of internal SDRAM is 0x0C000000.
- Although size of SDRAM can be either 16 or 32 MBytes,
- we assume 16 MBytes (ie ignore upper half if the full
- 32 MBytes is present).
-
- NOTE: This address must match with the definition of
- TEXT_BASE in config.mk (in this directory).
-
- */
- . = 0x8C000000 + (64*1024*1024) - (256*1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh4/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss (NOLOAD) :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
+++ /dev/null
-/*
- * Copyrigth (c) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- Base address of internal SDRAM is 0x0C000000.
- Although size of SDRAM can be either 16 or 32 MBytes,
- we assume 16 MBytes (ie ignore upper half if the full
- 32 MBytes is present).
-
- NOTE: This address must match with the definition of
- TEXT_BASE in config.mk (in this directory).
-
- */
- . = 0x8C000000 + (64*1024*1024) - (256*1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh4/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss (NOLOAD) :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1))\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1))\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0))\
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
/*GPIO based game buttons*/\
- MUX_VAL(CP(CAM_XCLKA), (IEN | PTU | DIS | M4)) /*GPIO_96 - LEFT*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M4)) /*GPIO_97 - L2*/\
- MUX_VAL(CP(CAM_FLD), (IEN | PTU | DIS | M4)) /*GPIO_98 - RIGHT*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTU | DIS | M4)) /*GPIO_99 - MENU*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTU | DIS | M4)) /*GPIO_100 - START*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTU | DIS | M4)) /*GPIO_101 - Y*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTU | DIS | M4)) /*GPIO_102 - L1*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTU | DIS | M4)) /*GPIO_103 - DOWN*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTU | DIS | M4)) /*GPIO_104 - SELECT*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTU | DIS | M4)) /*GPIO_105 - R1*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTU | DIS | M4)) /*GPIO_106 - B*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTU | DIS | M4)) /*GPIO_107 - R2*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTU | DIS | M4)) /*GPIO_109 - X*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTU | DIS | M4)) /*GPIO_110 - UP*/\
- MUX_VAL(CP(CAM_XCLKB), (IEN | PTU | DIS | M4)) /*GPIO_111 - A*/\
+ MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | DIS | M4)) /*GPIO_96 - LEFT*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M4)) /*GPIO_97 - L2*/\
+ MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 - RIGHT*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M4)) /*GPIO_99 - MENU*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M4)) /*GPIO_100 - START*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M4)) /*GPIO_101 - Y*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M4)) /*GPIO_102 - L1*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M4)) /*GPIO_103 - DOWN*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M4)) /*GPIO_104 - SELECT*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M4)) /*GPIO_105 - R1*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M4)) /*GPIO_106 - B*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M4)) /*GPIO_107 - R2*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109 - X*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M4)) /*GPIO_110 - UP*/\
+ MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M4)) /*GPIO_111 - A*/\
/*Audio Interface To External DAC (Headphone, Speakers)*/\
MUX_VAL(CP(MCBSP2_FSX), (IDIS | PTD | DIS | M0)) /*McBSP2_FSX*/\
MUX_VAL(CP(MCBSP2_CLKX), (IDIS | PTD | DIS | M0)) /*McBSP2_CLKX*/\
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | DIS | M0)) /*McBSP_CLKS*/\
MUX_VAL(CP(MCBSP2_DR), (IDIS | PTD | DIS | M4)) /*GPIO_118*/\
/* - nPOWERDOWN_DAC*/\
/*Expansion card 1*/\
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M0)) /*McBSP4_DX*/\
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
/*GPIO definitions for muxed pins on AV connector*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)) /*GPIO_144,*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M4)) /*GPIO_144,*/\
/*UART2_CTS*/\
- MUX_VAL(CP(UART2_RTS), (IEN | PTU | DIS | M4)) /*GPIO_145,*/\
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)) /*GPIO_145,*/\
/*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IEN | PTU | EN | M4)) /*GPIO_146,*/\
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)) /*GPIO_146,*/\
/*UART2_TX*/\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147,*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)) /*GPIO_147,*/\
/*UART2_RX*/\
/*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\
MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
/* - LED_WIFI*/\
/*Switches*/\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /*GPIO_176*/\
/* - nHOLD_SWITCH*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTU | DIS | M4)) /*GPIO_108*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M4)) /*GPIO_108*/\
/* - nLID_SWITCH*/\
/*External IRQs*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M4)) /*GPIO_94*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTD | DIS | M4)) /*GPIO_94*/\
/* - nTOUCH_IRQ*/\
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M4)) /*GPIO_21*/\
/* - WIFI_IRQ*/\
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\
/* - nIRQ_NUB1*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTU | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
/* - nIRQ_NUB2*/\
/*Various other stuff*/\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M4)) /*GPIO_95*/\
- /* - nTOUCH_BUSY*/\
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | DIS | M4)) /*GPIO_163*/\
/* - nOC_USB5*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
- /* - START_ADC*/\
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M4)) /*GPIO_22*/\
/* - MSECURE*/\
- MUX_VAL(CP(CAM_STROBE), (IEN | PTU | DIS | M4)) /*GPIO_126*/\
- /* - HP_DETECT*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M4)) /*GPIO_115*/\
+ /* - POP_OVERHEAT*/\
/*External Resets and Enables*/\
MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_14*/\
/* - nHDPHN_SHUTDOWN*/\
/* - nLCD_RESET*/\
MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
/* - RESET_NUBS*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M4)) /*GPIO_164*/\
/* - EN_USB_5V*/\
- /*Unused*/\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO - NC*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0 - NC*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0 - NC*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1 - NC*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1 - NC*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL - NC*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA - NC*/\
+ /*Spare GPIOs*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | EN | M4)) /*GPIO_58*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M4)) /*GPIO_64*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | EN | M4)) /*GPIO_65*/\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) /*GPIO_95*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /*GPIO_170*/\
/*HS USB OTG Port (connects to HSUSB0)*/\
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8*/\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /*SYS_CLKOUT1 - NC*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M4)) /*SYS_CLKOUT2 - NC*/\
/*JTAG*/\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
#endif
+++ /dev/null
-/*
- * Copyrigth (c) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- Base address of internal SDRAM is 0x0C000000.
- Although size of SDRAM can be either 16 or 32 MBytes,
- we assume 16 MBytes (ie ignore upper half if the full
- 32 MBytes is present).
-
- NOTE: This address must match with the definition of
- TEXT_BASE in config.mk (in this directory).
-
- */
- . = 0x8C000000 + (64*1024*1024) - (256*1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh4/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
+++ /dev/null
-/*
- * Copyrigth (c) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- Base address of internal SDRAM is 0x88000000.
- Although size of SDRAM can be either 16 or 32 MBytes,
- we assume 16 MBytes (ie ignore upper half if the full
- 32 MBytes is present).
-
- NOTE: This address must match with the definition of
- TEXT_BASE in config.mk (in this directory).
-
- */
- . = 0x88000000 + (128*1024*1024) - (256*1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh4/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
+++ /dev/null
-/*
- * Copyrigth (c) 2007,2008
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- Base address of internal SDRAM is 0x0C000000.
- Although size of SDRAM can be either 16 or 32 MBytes,
- we assume 16 MBytes (ie ignore upper half if the full
- 32 MBytes is present).
-
- NOTE: This address must match with the definition of
- TEXT_BASE in config.mk (in this directory).
-
- */
- . = 0x0C000000 + (64*1024*1024) - (256*1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh4/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
+++ /dev/null
-/*
- * Copyrigth (c) 2007,2008
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- Base address of internal SDRAM is 0x0C000000.
- Although size of SDRAM can be either 16 or 32 MBytes,
- we assume 16 MBytes (ie ignore upper half if the full
- 32 MBytes is present).
-
- NOTE: This address must match with the definition of
- TEXT_BASE in config.mk (in this directory).
-
- */
- . = 0x08000000 + (128*1024*1024) - (256*1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh4/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
+++ /dev/null
-/*
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- * Base address of internal SDRAM is 0x0C000000.
- *
- * NOTE: This address must match with the definition of
- *TEXT_BASE in config.mk (in this directory).
- */
-
- . = 0x0C000000 + (8*1024*1024) - (256*1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh2/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
+++ /dev/null
-/*
- * Copyrigth (c) 2007,2008
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- Base address of internal SDRAM is 0x0C000000.
- Although size of SDRAM can be either 16 or 32 MBytes,
- we assume 16 MBytes (ie ignore upper half if the full
- 32 MBytes is present).
-
- NOTE: This address must match with the definition of
- TEXT_BASE in config.mk (in this directory).
-
- */
- . = 0x8C000000 + (64*1024*1024) - (256*1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh4/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
COBJS := sh7785lcr.o selfcheck.o rtl8169_mac.o
SOBJS := lowlevel_init.o
WAIT_200US: .long 33333
/*------- GPIO -------*/
-#define GPIO_BASE 0xffe70000
-PACR_A: .long GPIO_BASE + 0x00
-PBCR_A: .long GPIO_BASE + 0x02
-PCCR_A: .long GPIO_BASE + 0x04
-PDCR_A: .long GPIO_BASE + 0x06
-PECR_A: .long GPIO_BASE + 0x08
-PFCR_A: .long GPIO_BASE + 0x0a
-PGCR_A: .long GPIO_BASE + 0x0c
-PHCR_A: .long GPIO_BASE + 0x0e
-PJCR_A: .long GPIO_BASE + 0x10
-PKCR_A: .long GPIO_BASE + 0x12
-PLCR_A: .long GPIO_BASE + 0x14
-PMCR_A: .long GPIO_BASE + 0x16
-PNCR_A: .long GPIO_BASE + 0x18
-PPCR_A: .long GPIO_BASE + 0x1a
-PQCR_A: .long GPIO_BASE + 0x1c
-PRCR_A: .long GPIO_BASE + 0x1e
-PEPUPR_A: .long GPIO_BASE + 0x48
-PHPUPR_A: .long GPIO_BASE + 0x4e
-PJPUPR_A: .long GPIO_BASE + 0x50
-PKPUPR_A: .long GPIO_BASE + 0x52
-PLPUPR_A: .long GPIO_BASE + 0x54
-PMPUPR_A: .long GPIO_BASE + 0x56
-PNPUPR_A: .long GPIO_BASE + 0x58
-PPUPR1_A: .long GPIO_BASE + 0x60
-PPUPR2_A: .long GPIO_BASE + 0x62
-P1MSELR_A: .long GPIO_BASE + 0x80
-P2MSELR_A: .long GPIO_BASE + 0x82
-
PACR_D: .long 0x0000
PBCR_D: .long 0x0000
PCCR_D: .long 0x0000
P1MSELR_D: .long 0x3780
P2MSELR_D: .long 0x0000
+#define GPIO_BASE 0xffe70000
+PACR_A: .long GPIO_BASE + 0x00
+PBCR_A: .long GPIO_BASE + 0x02
+PCCR_A: .long GPIO_BASE + 0x04
+PDCR_A: .long GPIO_BASE + 0x06
+PECR_A: .long GPIO_BASE + 0x08
+PFCR_A: .long GPIO_BASE + 0x0a
+PGCR_A: .long GPIO_BASE + 0x0c
+PHCR_A: .long GPIO_BASE + 0x0e
+PJCR_A: .long GPIO_BASE + 0x10
+PKCR_A: .long GPIO_BASE + 0x12
+PLCR_A: .long GPIO_BASE + 0x14
+PMCR_A: .long GPIO_BASE + 0x16
+PNCR_A: .long GPIO_BASE + 0x18
+PPCR_A: .long GPIO_BASE + 0x1a
+PQCR_A: .long GPIO_BASE + 0x1c
+PRCR_A: .long GPIO_BASE + 0x1e
+PEPUPR_A: .long GPIO_BASE + 0x48
+PHPUPR_A: .long GPIO_BASE + 0x4e
+PJPUPR_A: .long GPIO_BASE + 0x50
+PKPUPR_A: .long GPIO_BASE + 0x52
+PLPUPR_A: .long GPIO_BASE + 0x54
+PMPUPR_A: .long GPIO_BASE + 0x56
+PNPUPR_A: .long GPIO_BASE + 0x58
+PPUPR1_A: .long GPIO_BASE + 0x60
+PPUPR2_A: .long GPIO_BASE + 0x62
+P1MSELR_A: .long GPIO_BASE + 0x80
+P2MSELR_A: .long GPIO_BASE + 0x82
+
/*------- LBSC -------*/
PASCR_A: .long 0xff000070
PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
+++ /dev/null
-/*
- * Copyrigth (c) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyrigth (c) 2008-2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- . = 0x88000000 + (128 * 1024 * 1024) - (512 * 1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh4/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
+++ /dev/null
-/*
- * Copyrigth (c) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyrigth (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- . = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh4/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(.rodata)
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
+++ /dev/null
-/*
- * Copyrigth (c) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyrigth (c) 2008-2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- . = 0x88000000 + (128 * 1024 * 1024) - (512 * 1024);
-
- PROVIDE (reloc_dst = .);
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- cpu/sh4/start.o (.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(.rodata)
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
- }
- PROVIDE (__u_boot_cmd_end = .);
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (_end = .);
-}
return err ? err : count_save - size;
}
-static int ubi_dev_scan(struct mtd_info *info, char *ubidev)
+static int ubi_dev_scan(struct mtd_info *info, char *ubidev,
+ const char *vid_header_offset)
{
struct mtd_device *dev;
struct part_info *part;
struct mtd_partition mtd_part;
+ char ubi_mtd_param_buffer[80];
u8 pnum;
int err;
mtd_part.offset = part->offset;
add_mtd_partitions(info, &mtd_part, 1);
- err = ubi_mtd_param_parse(buffer, NULL);
+ strcpy(ubi_mtd_param_buffer, buffer);
+ if (vid_header_offset)
+ sprintf(ubi_mtd_param_buffer, "mtd=%d,%s", pnum,
+ vid_header_offset);
+ err = ubi_mtd_param_parse(ubi_mtd_param_buffer, NULL);
if (err) {
del_mtd_partitions(info);
return err;
char mtd_dev[16];
struct mtd_device *dev;
struct part_info *part;
+ const char *vid_header_offset = NULL;
u8 pnum;
/* Print current partition */
ubi_dev.selected = 1;
+ if (argc > 3)
+ vid_header_offset = argv[3];
strcpy(ubi_dev.part_name, argv[2]);
- err = ubi_dev_scan(ubi_dev.mtd_info, ubi_dev.part_name);
+ err = ubi_dev_scan(ubi_dev.mtd_info, ubi_dev.part_name,
+ vid_header_offset);
if (err) {
printf("UBI init error %d\n", err);
ubi_dev.selected = 0;
U_BOOT_CMD(ubi, 6, 1, do_ubi,
"ubi commands",
- "part [part]"
- " - Show or set current partition\n"
+ "part [part] [offset]\n"
+ " - Show or set current partition (with optional VID"
+ " header offset)\n"
"ubi info [l[ayout]]"
" - Display volume and ubi layout information\n"
"ubi create[vol] volume [size] [type]"
char *vol_name;
int ret;
+ if (argc != 2) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
vol_name = argv[1];
debug("Using volume %s\n", vol_name);
int do_ubifs_load(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *filename;
+ char *endp;
int ret;
u32 addr;
u32 size = 0;
}
if (argc < 3) {
- printf("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return -1;
}
- addr = simple_strtoul(argv[1], NULL, 16);
+ addr = simple_strtoul(argv[1], &endp, 16);
+ if (endp == argv[1]) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
filename = argv[2];
- if (argc == 4)
- size = simple_strtoul(argv[3], NULL, 16);
+ if (argc == 4) {
+ size = simple_strtoul(argv[3], &endp, 16);
+ if (endp == argv[3]) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+ }
debug("Loading file '%s' to address 0x%08x (size %d)\n", filename, addr, size);
ret = ubifs_load(filename, addr, size);
U_BOOT_CMD(
ubifsmount, 2, 0, do_ubifs_mount,
"mount UBIFS volume",
- ""
+ "<volume-name>\n"
+ " - mount 'volume-name' volume"
);
U_BOOT_CMD(ubifsls, 2, 0, do_ubifs_ls,
COBJS-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o
COBJS-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o
COBJS-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o
+COBJS-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o
COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o
COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o
+COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
COBJS-$(CONFIG_AT91_LED) += led.o
COBJS-y += clock.o
COBJS-y += cpu.o
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void at91_serial0_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
+ at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0);
+}
+
+void at91_serial1_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
+ at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1);
+}
+
+void at91_serial2_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PD6, 1); /* TXD2 */
+ at91_set_A_periph(AT91_PIN_PD7, 0); /* RXD2 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2);
+}
+
+void at91_serial3_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
+ at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);;
+}
+
+void at91_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+ at91_serial0_hw_init();
+#endif
+
+#ifdef CONFIG_USART1
+ at91_serial1_hw_init();
+#endif
+
+#ifdef CONFIG_USART2
+ at91_serial2_hw_init();
+#endif
+
+#ifdef CONFIG_USART3 /* DBGU */
+ at91_serial3_hw_init();
+#endif
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+ at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
+ at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
+ at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0);
+
+ if (cs_mask & (1 << 0)) {
+ at91_set_A_periph(AT91_PIN_PB3, 0);
+ }
+ if (cs_mask & (1 << 1)) {
+ at91_set_B_periph(AT91_PIN_PB18, 0);
+ }
+ if (cs_mask & (1 << 2)) {
+ at91_set_B_periph(AT91_PIN_PB19, 0);
+ }
+ if (cs_mask & (1 << 3)) {
+ at91_set_B_periph(AT91_PIN_PD27, 0);
+ }
+ if (cs_mask & (1 << 4)) {
+ at91_set_gpio_output(AT91_PIN_PB3, 0);
+ }
+ if (cs_mask & (1 << 5)) {
+ at91_set_gpio_output(AT91_PIN_PB18, 0);
+ }
+ if (cs_mask & (1 << 6)) {
+ at91_set_gpio_output(AT91_PIN_PB19, 0);
+ }
+ if (cs_mask & (1 << 7)) {
+ at91_set_gpio_output(AT91_PIN_PD27, 0);
+ }
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+ at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
+ at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
+ at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1);
+
+ if (cs_mask & (1 << 0)) {
+ at91_set_A_periph(AT91_PIN_PB17, 0);
+ }
+ if (cs_mask & (1 << 1)) {
+ at91_set_B_periph(AT91_PIN_PD28, 0);
+ }
+ if (cs_mask & (1 << 2)) {
+ at91_set_A_periph(AT91_PIN_PD18, 0);
+ }
+ if (cs_mask & (1 << 3)) {
+ at91_set_A_periph(AT91_PIN_PD19, 0);
+ }
+ if (cs_mask & (1 << 4)) {
+ at91_set_gpio_output(AT91_PIN_PB17, 0);
+ }
+ if (cs_mask & (1 << 5)) {
+ at91_set_gpio_output(AT91_PIN_PD28, 0);
+ }
+ if (cs_mask & (1 << 6)) {
+ at91_set_gpio_output(AT91_PIN_PD18, 0);
+ }
+ if (cs_mask & (1 << 7)) {
+ at91_set_gpio_output(AT91_PIN_PD19, 0);
+ }
+
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
+ at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
+ at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
+ at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
+ at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
+ at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
+ at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
+ at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
+ at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
+ at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
+#ifndef CONFIG_RMII
+ at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
+ at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
+ at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
+ at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
+ at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
+ at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
+ at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
+ at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
+#endif
+}
+#endif
* For now, assume this parentage won't change.
*/
mckr = at91_sys_read(AT91_PMC_MCKR);
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+ /* plla divisor by 2 */
+ plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+#endif
freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS);
+
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
#if defined(CONFIG_AT91RM9200)
mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
#elif defined(CONFIG_AT91SAM9G20)
mck_rate_hz = (mckr & AT91_PMC_MDIV) ?
- freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
+ freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
if (mckr & AT91_PMC_PDIV)
- freq /= 2; /* processor clock division */
+ freq /= 2; /* processor clock division */
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+ mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
+ freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
#else
mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
#endif
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
/* Configure interface. */
- setbits_be32((void *)ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
+ setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
/* Wait for clock to stabilize */
do {
- temp = in_be32((void *)ehci->control);
+ temp = in_be32(&ehci->control);
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
#endif
*/
int __pci_pre_init(struct pci_controller *hose)
{
+#if defined (CONFIG_405EP)
+ /*
+ * Enable the internal PCI arbiter by default.
+ *
+ * On 405EP CPUs the internal arbiter can be controlled
+ * by the I2C strapping EEPROM. If you want to do so
+ * or if you want to disable the arbiter pci_pre_init()
+ * must be reimplemented without enabling the arbiter.
+ * The arbiter is enabled in this place because of
+ * compatibility reasons.
+ */
+ mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_ARBIT_EN);
+#endif /* CONFIG_405EP */
+
return 1;
}
int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
}
#endif
-#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
- pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
+#if defined(CONFIG_405EP)
+ /*
+ * on ppc405ep vendor/device id is not set
+ * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
+ * are the correct values.
+ */
+ pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
+ pci_write_config_word(PCIDEVID_405GP,
+ PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
#endif
/*
* Set EMAC noise filter bits
*/
mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
-
- /*
- * Enable the internal PCI arbiter
- */
- mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
#endif /* CONFIG_405EP */
#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
--- /dev/null
+/*
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ * entry and reloct_dst will be provided via ldflags
+ */
+ . = .;
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh2/start.o (.text)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenv)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
--- /dev/null
+/*
+ * Copyright (C) 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ * entry and reloct_dst will be provided via ldflags
+ */
+ . = .;
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh3/start.o (.text)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenv)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
--- /dev/null
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2008-2009
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ * entry and reloct_dst will be provided via ldflags
+ */
+ . = .;
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenv)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss (NOLOAD) :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
------------------------------------------------------------------------------
-AT91SAM9261EK
+AT91SAM9261EK, AT91SAM9G10EK
------------------------------------------------------------------------------
Memory map
make at91sam9263ek_norflash_boot_config - boot from nor falsh
+------------------------------------------------------------------------------
+AT91SAM9M10G45EK
+------------------------------------------------------------------------------
+
+Memory map
+ 0x20000000 - 23FFFFFF SDRAM (64 MB)
+ 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J12)
+
+Environment variables
+
+ U-Boot environment variables can be stored at different places:
+ - Dataflash on SPI chip select 0 (dataflash card)
+ - Nand flash.
+
+ You can choose your storage location at config step (here for at91sam9m10g45ek) :
+ make at91sam9m10g45ek_config - use data flash (spi cs0) (default)
+ make at91sam9m10g45ek_nandflash_config - use nand flash
+ make at91sam9m10g45ek_dataflash_cs0_config - use data flash (spi cs0)
+
+
------------------------------------------------------------------------------
AT91SAM9RLEK
------------------------------------------------------------------------------
break;
case CFI_CMDSET_AMD_EXTENDED:
case CFI_CMDSET_AMD_STANDARD:
-#ifdef CONFIG_FLASH_CFI_LEGACY
- case CFI_CMDSET_AMD_LEGACY:
-#endif
sect = find_sector(info, dest);
flash_unlock_seq (info, sect);
flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE);
sect_found = 1;
break;
+#ifdef CONFIG_FLASH_CFI_LEGACY
+ case CFI_CMDSET_AMD_LEGACY:
+ sect = find_sector(info, dest);
+ flash_unlock_seq (info, 0);
+ flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE);
+ sect_found = 1;
+ break;
+#endif
}
switch (info->portwidth) {
COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/kirkwood.h>
+#include <nand.h>
+
+/* NAND Flash Soc registers */
+struct kwnandf_registers {
+ u32 rd_params; /* 0x10418 */
+ u32 wr_param; /* 0x1041c */
+ u8 pad[0x10470 - 0x1041c - 4];
+ u32 ctrl; /* 0x10470 */
+};
+
+static struct kwnandf_registers *nf_reg =
+ (struct kwnandf_registers *)KW_NANDF_BASE;
+
+/*
+ * hardware specific access to control-lines/bits
+ */
+#define NAND_ACTCEBOOT_BIT 0x02
+
+static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
+{
+ struct nand_chip *nc = mtd->priv;
+ u32 offs;
+
+ if (cmd == NAND_CMD_NONE)
+ return;
+
+ if (ctrl & NAND_CLE)
+ offs = (1 << 0); /* Commands with A[1:0] == 01 */
+ else if (ctrl & NAND_ALE)
+ offs = (1 << 1); /* Addresses with A[1:0] == 10 */
+ else
+ return;
+
+ writeb(cmd, nc->IO_ADDR_W + offs);
+}
+
+void kw_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ u32 data;
+
+ data = readl(&nf_reg->ctrl);
+ data |= NAND_ACTCEBOOT_BIT;
+ writel(data, &nf_reg->ctrl);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = kw_nand_hwcontrol;
+ nand->chip_delay = 30;
+ nand->select_chip = kw_nand_select_chip;
+ return 0;
+}
/* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_RMII
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
- defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
+ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
+ defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, 0);
#endif
#else
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
- defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
+ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
+ defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
macb_writel(macb, USRIO, MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, MACB_BIT(MII));
COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
+COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
struct usb_ehci *ehci;
ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
- hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength);
+ hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
hcor = (struct ehci_hcor *)((uint32_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
/* Set to Host mode */
- setbits_le32((void *)ehci->usbmode, CM_HOST);
+ setbits_le32(&ehci->usbmode, CM_HOST);
- out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB);
- out_be32((void *)ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
+ out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
+ out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
/* Init phy */
if (!strcmp(getenv("usb_phy_type"), "utmi"))
out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI);
/* Enable interface. */
- setbits_be32((void *)ehci->control, USB_EN);
+ setbits_be32(&ehci->control, USB_EN);
- out_be32((void *)ehci->prictrl, 0x0000000c);
- out_be32((void *)ehci->age_cnt_limit, 0x00000040);
- out_be32((void *)ehci->sictrl, 0x00000001);
+ out_be32(&ehci->prictrl, 0x0000000c);
+ out_be32(&ehci->age_cnt_limit, 0x00000040);
+ out_be32(&ehci->sictrl, 0x00000001);
- in_le32((void *)ehci->usbmode);
+ in_le32(&ehci->usbmode);
return 0;
}
goto unknown;
}
/* unblock posted writes */
- ehci_readl(&hcor->or_usbcmd);
+ (void) ehci_readl(&hcor->or_usbcmd);
break;
case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
reg = ehci_readl(status_reg);
}
ehci_writel(status_reg, reg);
/* unblock posted write */
- ehci_readl(&hcor->or_usbcmd);
+ (void) ehci_readl(&hcor->or_usbcmd);
break;
default:
debug("Unknown request\n");
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <usb.h>
+#include "ehci.h"
+#include "ehci-core.h"
+#include <asm/arch/kirkwood.h>
+
+#define rdl(off) readl(KW_USB20_BASE + (off))
+#define wrl(off, val) writel((val), KW_USB20_BASE + (off))
+
+#define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
+#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
+#define USB_TARGET_DRAM 0x0
+
+/*
+ * USB 2.0 Bridge Address Decoding registers setup
+ */
+static void usb_brg_adrdec_setup(void)
+{
+ int i;
+ u32 size, attrib;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+
+ /* Enable DRAM bank */
+ switch (i) {
+ case 0:
+ attrib = KWCPU_ATTR_DRAM_CS0;
+ break;
+ case 1:
+ attrib = KWCPU_ATTR_DRAM_CS1;
+ break;
+ case 2:
+ attrib = KWCPU_ATTR_DRAM_CS2;
+ break;
+ case 3:
+ attrib = KWCPU_ATTR_DRAM_CS3;
+ break;
+ default:
+ /* invalide bank, disable access */
+ attrib = 0;
+ break;
+ }
+
+ size = kw_sdram_bs(i);
+ if ((size) && (attrib))
+ wrl(USB_WINDOW_CTRL(i),
+ KWCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
+ attrib, KWCPU_WIN_ENABLE));
+ else
+ wrl(USB_WINDOW_CTRL(i), KWCPU_WIN_DISABLE);
+
+ wrl(USB_WINDOW_BASE(i), kw_sdram_bar(i));
+ }
+}
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+ usb_brg_adrdec_setup();
+
+ hccr = (struct ehci_hccr *)(KW_USB20_BASE + 0x100);
+ hcor = (struct ehci_hcor *)((uint32_t) hccr
+ + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ debug("Kirkwood-ehci: init hccr %x and hcor %x hc_length %d\n",
+ (uint32_t)hccr, (uint32_t)hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(void)
+{
+ return 0;
+}
+
extern void write_fifo(u8 ep, u32 length, void *fifo_data);
extern void read_fifo(u8 ep, u32 length, void *fifo_data);
-/* extern functions */
-extern inline void musb_writew(u32 offset, u16 value);
-extern inline void musb_writeb(u32 offset, u8 value);
-extern inline u16 musb_readw(u32 offset);
-extern inline u8 musb_readb(u32 offset);
-
#endif /* __MUSB_HDRC_DEFS_H__ */
{
u16 csr;
int result = 1;
+ int timeout = CONFIG_MUSB_TIMEOUT;
while (result > 0) {
csr = readw(&musbr->txcsr);
}
break;
}
+
+ /* Check the timeout */
+ if (--timeout)
+ udelay(1);
+ else {
+ dev->status = USB_ST_CRC_ERR;
+ result = -1;
+ break;
+ }
}
+
return result;
}
static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
{
u16 csr;
+ int timeout = CONFIG_MUSB_TIMEOUT;
do {
if (check_stall(ep, 1)) {
dev->status = USB_ST_CRC_ERR;
return 0;
}
+
+ /* Check the timeout */
+ if (--timeout)
+ udelay(1);
+ else {
+ dev->status = USB_ST_CRC_ERR;
+ return -1;
+ }
+
} while (csr & MUSB_TXCSR_TXPKTRDY);
return 1;
}
static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
{
u16 csr;
+ int timeout = CONFIG_MUSB_TIMEOUT;
do {
if (check_stall(ep, 0)) {
dev->status = USB_ST_CRC_ERR;
return 0;
}
+
+ /* Check the timeout */
+ if (--timeout)
+ udelay(1);
+ else {
+ dev->status = USB_ST_CRC_ERR;
+ return -1;
+ }
+
} while (!(csr & MUSB_RXCSR_RXPKTRDY));
return 1;
}
extern unsigned char new[];
#endif
+#ifndef CONFIG_MUSB_TIMEOUT
+# define CONFIG_MUSB_TIMEOUT 100000
+#endif
+
/* This defines the endpoint number used for control transfers */
#define MUSB_CONTROL_EP 0
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
+#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
#define AT91SAM9_PMC_MDIV_6 (3 << 8)
#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
#define AT91_PMC_PDIV_1 (0 << 12)
#include <asm/arch/at91sam9rl_matrix.h>
#elif defined(CONFIG_AT91CAP9)
#include <asm/arch/at91cap9_matrix.h>
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#include <asm/arch/at91sam9g45_matrix.h>
#else
#error "Unsupported AT91SAM9/CAP9 processor"
#endif
--- /dev/null
+/*
+ * Chip-specific header file for the AT91SAM9M1x family
+ *
+ * Copyright (C) 2008 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91SAM9G45 preliminary datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9G45_H
+#define AT91SAM9G45_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS 1 /* System Controller Interrupt */
+#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
+#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
+#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
+#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */
+#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */
+#define AT91SAM9G45_ID_US0 7 /* USART 0 */
+#define AT91SAM9G45_ID_US1 8 /* USART 1 */
+#define AT91SAM9G45_ID_US2 9 /* USART 2 */
+#define AT91SAM9G45_ID_US3 10 /* USART 3 */
+#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
+#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */
+#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */
+#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */
+#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */
+#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */
+#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */
+#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */
+#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */
+#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */
+#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */
+#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */
+#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */
+#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */
+#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */
+#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */
+#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
+#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
+#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */
+#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9G45_BASE_UDPHS 0xfff78000
+#define AT91SAM9G45_BASE_TC0 0xfff7c000
+#define AT91SAM9G45_BASE_TC1 0xfff7c040
+#define AT91SAM9G45_BASE_TC2 0xfff7c080
+#define AT91SAM9G45_BASE_MCI0 0xfff80000
+#define AT91SAM9G45_BASE_TWI0 0xfff84000
+#define AT91SAM9G45_BASE_TWI1 0xfff88000
+#define AT91SAM9G45_BASE_US0 0xfff8c000
+#define AT91SAM9G45_BASE_US1 0xfff90000
+#define AT91SAM9G45_BASE_US2 0xfff94000
+#define AT91SAM9G45_BASE_US3 0xfff98000
+#define AT91SAM9G45_BASE_SSC0 0xfff9c000
+#define AT91SAM9G45_BASE_SSC1 0xfffa0000
+#define AT91SAM9G45_BASE_SPI0 0xfffa4000
+#define AT91SAM9G45_BASE_SPI1 0xfffa8000
+#define AT91SAM9G45_BASE_AC97C 0xfffac000
+#define AT91SAM9G45_BASE_TSC 0xfffb0000
+#define AT91SAM9G45_BASE_ISI 0xfffb4000
+#define AT91SAM9G45_BASE_PWMC 0xfffb8000
+#define AT91SAM9G45_BASE_EMAC 0xfffbc000
+#define AT91SAM9G45_BASE_AES 0xfffc0000
+#define AT91SAM9G45_BASE_TDES 0xfffc4000
+#define AT91SAM9G45_BASE_SHA 0xfffc8000
+#define AT91SAM9G45_BASE_TRNG 0xfffcc000
+#define AT91SAM9G45_BASE_MCI1 0xfffd0000
+#define AT91SAM9G45_BASE_TC3 0xfffd4000
+#define AT91SAM9G45_BASE_TC4 0xfffd4040
+#define AT91SAM9G45_BASE_TC5 0xfffd4080
+#define AT91_BASE_SYS 0xffffe200
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
+#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
+#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
+#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
+#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
+#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
+#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
+#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
+#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
+#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
+
+#define AT91_USART0 AT91SAM9G45_BASE_US0
+#define AT91_USART1 AT91SAM9G45_BASE_US1
+#define AT91_USART2 AT91SAM9G45_BASE_US2
+#define AT91_USART3 AT91SAM9G45_BASE_US3
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */
+#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */
+
+#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */
+#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
+
+#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */
+#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
+#define AT91SAM9G45_HCI_BASE 0x00700000 /* USB Host controller (OHCI) */
+#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
+#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
+
+#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
+
+/*
+ * Cpu Name
+ */
+#define AT91_CPU_NAME "AT91SAM9G45"
+
+#endif
--- /dev/null
+/*
+ * Matrix-centric header file for the AT91SAM9M1x family
+ *
+ * Copyright (C) 2008 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9G45 preliminary datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9G45_MATRIX_H
+#define AT91SAM9G45_MATRIX_H
+
+#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
+#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
+#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
+#define AT91_MATRIX_ULBT_128 (7 << 0)
+
+#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+
+#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
+#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
+#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
+#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
+#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
+#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
+
+#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
+#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91_MATRIX_RCB2 (1 << 2)
+#define AT91_MATRIX_RCB3 (1 << 3)
+#define AT91_MATRIX_RCB4 (1 << 4)
+#define AT91_MATRIX_RCB5 (1 << 5)
+#define AT91_MATRIX_RCB6 (1 << 6)
+#define AT91_MATRIX_RCB7 (1 << 7)
+#define AT91_MATRIX_RCB8 (1 << 8)
+#define AT91_MATRIX_RCB9 (1 << 9)
+#define AT91_MATRIX_RCB10 (1 << 10)
+#define AT91_MATRIX_RCB11 (1 << 11)
+
+#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */
+#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
+#define AT91_MATRIX_ITCM_0 (0 << 0)
+#define AT91_MATRIX_ITCM_32 (6 << 0)
+#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
+#define AT91_MATRIX_DTCM_0 (0 << 4)
+#define AT91_MATRIX_DTCM_32 (6 << 4)
+#define AT91_MATRIX_DTCM_64 (7 << 4)
+#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
+#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
+#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
+
+#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */
+#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
+#define AT91C_VDEC_SEL_OFF (0 << 0)
+#define AT91C_VDEC_SEL_ON (1 << 0)
+
+#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
+#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
+#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
+#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
+#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
+#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
+#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
+#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
+#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
+#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
+#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
+#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
+#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
+
+#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
+#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
+#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
+#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
+#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
+
+#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
+#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
+#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
+#define AT91_MATRIX_WPSR_WPV (1 << 0)
+#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
+
+#endif
return get_mck_clk_rate();
}
+static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
+{
+ return get_mck_clk_rate();
+}
+
static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
{
return get_mck_clk_rate();
#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0
#define AT91_ID_UHP AT91SAM9260_ID_UHP
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
-#elif defined(CONFIG_AT91SAM9261)
+#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
#include <asm/arch/at91sam9261.h>
#define AT91_BASE_SPI AT91SAM9261_BASE_SPI0
#define AT91_ID_UHP AT91SAM9261_ID_UHP
#include <asm/arch/at91sam9rl.h>
#define AT91_BASE_SPI AT91SAM9RL_BASE_SPI
#define AT91_ID_UHP AT91SAM9RL_ID_UHP
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#include <asm/arch/at91sam9g45.h>
+#define AT91_BASE_EMAC AT91SAM9G45_BASE_EMAC
+#define AT91_BASE_SPI AT91SAM9G45_BASE_SPI0
+#define AT91_ID_UHP AT91SAM9G45_ID_UHPHS
+#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
#elif defined(CONFIG_AT91CAP9)
#include <asm/arch/at91cap9.h>
#define AT91_BASE_SPI AT91CAP9_BASE_SPI0
#define USART1_BASE AT91_USART1
#define USART2_BASE AT91_USART2
#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU)
+#define SPI0_BASE AT91_BASE_SPI
#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */
#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
#define KW_UART0_BASE (KW_REGISTER(0x12000))
-#define KW_UART1_BASE (KW_REGISTER(0x13000))
+#define KW_UART1_BASE (KW_REGISTER(0x12100))
#define KW_MPP_BASE (KW_REGISTER(0x10000))
#define KW_GPIO0_BASE (KW_REGISTER(0x10100))
#define KW_GPIO1_BASE (KW_REGISTER(0x10140))
#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
-#define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */
-#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */
-#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */
-#define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */
-#define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */
-#define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */
+#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */
+#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */
+#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */
+#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */
+#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */
+#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */
+#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */
#else /* if defined CONFIG_CPU_MONAHANS */
--- /dev/null
+/*
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_SH_CLK_H__
+#define __ASM_SH_CLK_H__
+
+static inline unsigned long get_peripheral_clk_rate(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+static inline unsigned long get_tmu0_clk_rate(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+#endif /* __ASM_SH_CLK_H__ */
.macro write16, addr, data
mov.l \addr ,r1
- mov.l \data ,r0
+ mov.w \data ,r0
mov.w r0, @r1
.endm
void pciinfo (int, int);
#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
- int pci_pre_init (struct pci_controller * );
+ int pci_pre_init (struct pci_controller *);
+ int is_pci_host (struct pci_controller *);
#endif
#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX))
# if defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init (struct pci_controller *);
# endif
- int is_pci_host (struct pci_controller *);
#if defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
#define PCI_ENET1_MEMADDR 0x81000000
#define CONFIG_RTL8139
-#define _IO_BASE 0x00000000
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x) (x)
+
/* Make sure the ethaddr can be overwritten
TODO: Remove this on final product
*/
# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
-# define _IO_BASE 0
#endif
#define CONFIG_NET_MULTI 1
#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
-#define _IO_BASE 0
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
-#define _IO_BASE 0
/* Realtime clock */
#define CONFIG_MCFRTC
#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
#endif
-#define _IO_BASE 0x00000000 /* points to PCI I/O space */
-
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#ifdef CONFIG_RTL8139
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x) (x)
-#endif
-
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR 0x00000000
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
#undef CONFIG_TULIP
#undef CONFIG_RTL8139
-#ifdef CONFIG_RTL8139
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
-#define _IO_BASE 0x00000000
-#endif
-
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
#undef CONFIG_TULIP
#define CONFIG_RTL8139
-#ifdef CONFIG_RTL8139
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x) (x)
-#define _IO_BASE 0x00000000
-#endif
-
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
#undef CONFIG_TULIP
#undef CONFIG_RTL8139
-#ifdef CONFIG_RTL8139
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x) (x)
-#define _IO_BASE 0x00000000
-#endif
-
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-/* For RTL8139 */
-#define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); })
-#define _IO_BASE 0x00000000
-
/* controller 1, Base address 0xa000 */
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
| CONFIG_SYS_PHYS_ADDR_HIGH)
#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */
-/* For RTL8139 */
-#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
-#define _IO_BASE 0x00000000
-
#ifdef CONFIG_PHYS_64BIT
/*
* Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT.
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
-#define _IO_BASE 0x00000000
-
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 3
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_HZ 1000
#endif /* __MIGO_R_H */
#undef CONFIG_TULIP
#define CONFIG_RTL8139
-#ifdef CONFIG_RTL8139
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x) (x)
-#define _IO_BASE 0x00000000
-#endif
-
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_HZ 1000
#endif /* __AP325RXA_H */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#ifdef CONFIG_AT91SAM9G10EK
+#define CONFIG_AT91SAM9G10 1 /* It's an Atmel AT91SAM9G10 SoC*/
+#else
#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/
-#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */
+#endif
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_LCD_INFO_BELOW_LOGO 1
#define CONFIG_SYS_WHITE_ON_BLACK 1
#define CONFIG_ATMEL_LCD 1
+#ifdef CONFIG_AT91SAM9261EK
#define CONFIG_ATMEL_LCD_BGR555 1
+#else
+#define CONFIG_AT91SAM9G10_LCD_BASE 0x23E00000 /* LCD is no more in SRAM */
+#endif
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/* LED */
#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
+#ifdef CONFIG_AT91SAM9G10EK
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10"
+#else
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
+#endif
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE 1
#define CONFIG_CMD_FAT 1
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#ifdef CONFIG_AT91SAM9M10G45EK
+#define CONFIG_AT91SAM9M10G45 1 /* It's an Atmel AT91SAM9M10G45 SoC*/
+#else
+#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/
+#endif
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+/* LCD */
+#define CONFIG_LCD 1
+#define LCD_BPP LCD_COLOR8
+#define CONFIG_LCD_LOGO 1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO 1
+#define CONFIG_LCD_INFO_BELOW_LOGO 1
+#define CONFIG_SYS_WHITE_ON_BLACK 1
+#define CONFIG_ATMEL_LCD 1
+#define CONFIG_ATMEL_LCD_RGB565 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */
+#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_USB 1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x70000000
+#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+
+/* DataFlash */
+#ifdef CONFIG_ATMEL_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_SPI_FLASH_ATMEL 1
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
+#endif
+
+/* NOR flash, if populated */
+#ifndef CONFIG_CMD_NAND
+#define CONFIG_SYS_NO_FLASH 1
+#else
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define PHYS_FLASH_1 0x10000000
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#endif
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MAX_CHIPS 1
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_RMII 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END 0x23e00000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400)
+#define CONFIG_ENV_OFFSET 0x4200
+#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x4200
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock0 " \
+ "mtdparts=at91_nand:-(root) "\
+ "rw rootfstype=jffs2"
+
+#else /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_OFFSET 0x60000
+#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock5 " \
+ "mtdparts=at91_nand:128k(bootstrap)ro, \
+ 256k(uboot)ro,128k(env1)ro,128k(env2)ro, \
+ 2M(linux),-(root) " \
+ "rw rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
#endif
#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x40000
-#define ENV_IS_EMBEDDED_CUSTOM
/*
* SDRAM settings & memory map
* Serial Flash Infomation
*/
#define CONFIG_BFIN_SPI
-/* For the M25P64 SCK Should be Kept < 20Mhz */
-#define CONFIG_ENV_SPI_MAX_HZ 20000000
-#define CONFIG_SF_DEFAULT_SPEED 20000000
+/* For the M25P64 SCK Should be Kept < 15Mhz */
+#define CONFIG_ENV_SPI_MAX_HZ 15000000
+#define CONFIG_SF_DEFAULT_SPEED 15000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
+/* The next 2 lines are for use with DEV-BF5xx */
#define CONFIG_DRIVER_SMC91111 1
#define CONFIG_SMC91111_BASE 0x28000300
+/* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */
+/* #define CONFIG_DRIVER_SMC911X 1 */
+/* #define CONFIG_DRIVER_SMC911X_BASE 0x24080000 // AMS1 */
+/* #define CONFIG_DRIVER_SMC911X_32_BIT 1 */
#define CONFIG_HOSTNAME cm-bf561
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:cf */
--- /dev/null
+/*
+ * Configuation settings for the ESPT-GIGA board
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ESPT_H
+#define __ESPT_H
+
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_CPU_SH7763 1
+#define CONFIG_ESPT 1
+#define __LITTLE_ENDIAN 1
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_BOOTDELAY -1
+#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
+#define CONFIG_ENV_OVERWRITE 1
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_SCIF0 1
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
+#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments
+ passed to kernel */
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
+ settings for this board */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
+#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Flash(NOR) S29JL064H */
+#define CONFIG_SYS_FLASH_BASE (0xA0000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
+#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+#define CONFIG_SYS_MAX_FLASH_SECT (150)
+
+/* U-boot setting */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE (256)
+#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#undef CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
+/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef CONFIG_SYS_FLASH_PROTECTION
+#undef CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+
+/* Clock */
+#define CONFIG_SYS_CLK_FREQ 66666666
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#define CONFIG_SYS_HZ 1000
+
+/* Ether */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT (1)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
+
+#endif /* __SH7763RDP_H */
/* Networking Configuration */
-#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */
-
#define CONFIG_TSI108_ETH
#define CONFIG_TSI108_ETH_NUM_PORTS 2
#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */
-#define _IO_BASE 0x00000000 /* points to PCI I/O space */
-
/* PCI Config Space mapping */
#define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */
#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */
/* Clocks */
#define CONFIG_SYS_CLK_FREQ 24000000
-#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_HZ 1000
/* UART */
#define CONFIG_SCIF_CONSOLE 1
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_HZ 1000
/* PCMCIA */
#define CONFIG_IDE_PCMCIA 1
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_HZ 1000
#endif /* __MS7722SE_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER 4
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#define CONFIG_SYS_HZ 1000
#endif /* __MS7750SE_H */
* SuperH Clock setting
*/
#define CONFIG_SYS_CLK_FREQ 60000000
-#define TMU_CLK_DIVIDER 4
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
/*
*/
#define CONFIG_NET_MULTI
#define CONFIG_RTL8139
-#define _IO_BASE 0x00000000
-#define KSEG1ADDR(x) (x)
#endif /* __CONFIG_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER 4
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#define CONFIG_SYS_HZ 1000
/* PCI Controller */
#if defined(CONFIG_CMD_PCI)
#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
+#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
#endif /* CONFIG_CMD_PCI */
#if defined(CONFIG_CMD_NET)
/* Clock */
#define CONFIG_SYS_CLK_FREQ 66666666
-#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_HZ 1000
/* Ether */
#define CONFIG_NET_MULTI 1
/* Board Clock */
/* The SCIF used external clock. system clock only used timer. */
#define CONFIG_SYS_CLK_FREQ 50000000
-#define TMU_CLK_DIVIDER 4
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#define CONFIG_SYS_HZ 1000
#endif /* __SH7785LCR_H */
#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */
#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
+#ifndef CONFIG_ARCH_VERSATILE_AB /* AB */
+#define CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
+#endif
+
#define CONFIG_SYS_MEMTEST_START 0x100000
#define CONFIG_SYS_MEMTEST_END 0x10000000
#define CONFIG_SYS_HZ (1000000 / 256)
/*
* Command line configuration.
*/
-
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FLASH
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "Versatile # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Monitor Command Prompt */
+#ifdef CONFIG_ARCH_VERSATILE_AB
+# define CONFIG_SYS_PROMPT "VersatileAB # "
+#else
+# define CONFIG_SYS_PROMPT "VersatilePB # "
+#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-
-#define CONFIG_SYS_FLASH_BASE 0x34000000
+#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
-
+/*
+ * Use the CFI flash driver for ease of use
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_ENV_IS_IN_FLASH 1
+/*
+ * System control register
+ */
#define VERSATILE_SYS_BASE 0x10000000
#define VERSATILE_SYS_FLASH_OFFSET 0x4C
#define VERSATILE_FLASHCTRL \
/* Enable writing to flash */
#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0)
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */
/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Erase Timeout */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (20 * CONFIG_SYS_HZ) /* Write Timeout */
-#define CONFIG_SYS_MAX_FLASH_SECT (256)
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
+
+/*
+ * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block
+ * i.e.
+ * the bottom "sector" (bottom boot), or top "sector"
+ * (top boot), is a seperate erase region divided into
+ * 4 (equal) smaller sectors. This, notionally, allows
+ * quicker erase/rewrire of the most frequently changed
+ * area......
+ * CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4
+ */
+
+#ifdef CONFIG_ARCH_VERSATILE_AB
+#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */
+#define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE)
+#define CONFIG_SYS_MAX_FLASH_SECT (520)
+#endif
+
+#ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
+#define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
+#define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT (260)
+#endif
+
+#define CONFIG_SYS_FLASH_BASE 0x34000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+#define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE)
+
+/* The ARM Boot Monitor is shipped in the lowest sector of flash */
-#define PHYS_FLASH_1 (CONFIG_SYS_FLASH_BASE)
+#define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE)
+#define CONFIG_ENV_SIZE 8192
+#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_IS_IN_FLASH 1 /* env in flash */
-#define CONFIG_ENV_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
-#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment */
-#define CONFIG_ENV_OFFSET 0x01f00000 /* environment starts */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_H */
#define PCI_DEVICE_ID_AUREAL_VORTEX_1 0x0001
#define PCI_DEVICE_ID_AUREAL_VORTEX_2 0x0002
+#define PCI_VENDOR_ID_ESDGMBH 0x12fe
+
#define PCI_VENDOR_ID_CBOARDS 0x1307
#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001
#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
-#if defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC83xx)
#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
#elif defined(CONFIG_MPC85xx)
#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
COBJS-y += boot.o
COBJS-y += cache.o
COBJS-y += clocks.o
+COBJS-$(CONFIG_CMD_CACHE_DUMP) += cmd_cache_dump.o
COBJS-y += muldi3.o
COBJS-$(CONFIG_POST) += post.o tests.o
COBJS-y += string.o
--- /dev/null
+/*
+ * U-boot - cmd_cache_dump.c
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
+
+static int check_limit(const char *type, size_t start_limit, size_t end_limit, size_t start, size_t end)
+{
+ if (start >= start_limit && start <= end_limit && \
+ end <= end_limit && end >= start_limit && \
+ start <= end)
+ return 0;
+
+ printf("%s limit violation: %zu <= (user:%zu) <= (user:%zu) <= %zu\n",
+ type, start_limit, start, end, end_limit);
+ return 1;
+}
+
+int do_icache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int cache_status = icache_status();
+
+ if (cache_status)
+ icache_disable();
+
+ uint32_t cmd_base, tag, cache_upper, cache_lower;
+
+ size_t way, way_start = 0, way_end = 3;
+ size_t sbnk, sbnk_start = 0, sbnk_end = 3;
+ size_t set, set_start = 0, set_end = 31;
+ size_t dw;
+
+ if (argc > 1) {
+ way_start = way_end = simple_strtoul(argv[1], NULL, 10);
+ if (argc > 2) {
+ sbnk_start = sbnk_end = simple_strtoul(argv[2], NULL, 10);
+ if (argc > 3)
+ set_start = set_end = simple_strtoul(argv[3], NULL, 10);
+ }
+ }
+
+ if (check_limit("way", 0, 3, way_start, way_end) || \
+ check_limit("subbank", 0, 3, sbnk_start, sbnk_end) || \
+ check_limit("set", 0, 31, set_start, set_end))
+ return 1;
+
+ puts("Way:Subbank:Set: [valid-tag lower upper] {invalid-tag lower upper}...\n");
+
+ for (way = way_start; way <= way_end; ++way) {
+ for (sbnk = sbnk_start; sbnk <= sbnk_end; ++sbnk) {
+ for (set = set_start; set <= set_end; ++set) {
+ printf("%zu:%zu:%2zu: ", way, sbnk, set);
+ for (dw = 0; dw < 4; ++dw) {
+ if (ctrlc())
+ return 1;
+
+ cmd_base = \
+ (way << 26) | \
+ (sbnk << 16) | \
+ (set << 5) | \
+ (dw << 3);
+
+ /* first read the tag */
+ bfin_write_ITEST_COMMAND(cmd_base | 0x0);
+ SSYNC();
+ tag = bfin_read_ITEST_DATA0();
+ printf("%c%08x ", (tag & 0x1 ? ' ' : '{'), tag);
+
+ /* grab the data at this loc */
+ bfin_write_ITEST_COMMAND(cmd_base | 0x4);
+ SSYNC();
+ cache_lower = bfin_read_ITEST_DATA0();
+ cache_upper = bfin_read_ITEST_DATA1();
+ printf("%08x %08x%c ", cache_lower, cache_upper, (tag & 0x1 ? ' ' : '}'));
+ }
+ puts("\n");
+ }
+ }
+ }
+
+ if (cache_status)
+ icache_enable();
+
+ return 0;
+}
+
+U_BOOT_CMD(icache_dump, 4, 0, do_icache_dump,
+ "icache_dump - dump current instruction cache\n",
+ "[way] [subbank] [set]");
+
+int do_dcache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u32 way, bank, subbank, set;
+ u32 status, addr;
+ u32 dmem_ctl = bfin_read_DMEM_CONTROL();
+
+ for (bank = 0; bank < 2; ++bank) {
+ if (!(dmem_ctl & (1 << (DMC1_P - bank))))
+ continue;
+
+ for (way = 0; way < 2; ++way)
+ for (subbank = 0; subbank < 4; ++subbank) {
+ printf("%i:%i:%i:\t", bank, way, subbank);
+ for (set = 0; set < 64; ++set) {
+
+ if (ctrlc())
+ return 1;
+
+ /* retrieve a cache tag */
+ bfin_write_DTEST_COMMAND(
+ way << 26 |
+ bank << 23 |
+ subbank << 16 |
+ set << 5
+ );
+ CSYNC();
+ status = bfin_read_DTEST_DATA0();
+
+ /* construct the address using the tag */
+ addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
+
+ /* show it */
+ if (set && !(set % 4))
+ puts("\n\t");
+ printf("%c%08x%c%08x%c ", (status & 0x1 ? '[' : '{'), status, (status & 0x2 ? 'd' : ' '), addr, (status & 0x1 ? ']' : '}'));
+ }
+ puts("\n");
+ }
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(dcache_dump, 4, 0, do_dcache_dump,
+ "dcache_dump - dump current data cache\n",
+ "[bank] [way] [subbank] [set]");
/*
+ * (C) Copyright 2009
+ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
* (C) Copyright 2007-2008
* Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
*/
#include <common.h>
+#include <div64.h>
#include <asm/processor.h>
+#include <asm/clk.h>
#include <asm/io.h>
#define TMU_MAX_COUNTER (~0UL)
-static int clk_adj = 1;
+
+static ulong timer_freq;
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, timer_freq);
+
+ return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+ usec *= timer_freq;
+ do_div(usec, 1000000);
+
+ return usec;
+}
static void tmu_timer_start (unsigned int timer)
{
int timer_init (void)
{
- /* Divide clock by TMU_CLK_DIVIDER */
+ /* Divide clock by CONFIG_SYS_TMU_CLK_DIV */
u16 bit = 0;
- switch (TMU_CLK_DIVIDER) {
+ switch (CONFIG_SYS_TMU_CLK_DIV) {
case 1024:
bit = 4;
break;
break;
case 4:
default:
- bit = 0;
break;
}
writew(readw(TCR0) | bit, TCR0);
- /* Clock adjustment calc */
- clk_adj = (int)(1.0 / ((1.0 / CONFIG_SYS_HZ) * 1000000));
- if (clk_adj < 1)
- clk_adj = 1;
+ /* Calc clock rate */
+ timer_freq = get_tmu0_clk_rate() >> ((bit + 1) * 2);
tmu_timer_stop(0);
tmu_timer_start(0);
return 0 - readl(TCNT0);
}
-static unsigned long get_usec (void)
-{
- return (0 - readl(TCNT0));
-}
-
void udelay (unsigned long usec)
{
- unsigned int start = get_usec();
- unsigned int end = start + (usec * clk_adj);
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = usec_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
- while (get_usec() < end)
- continue;
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
}
unsigned long get_timer (unsigned long base)
{
/* return msec */
- return ((get_usec() / clk_adj) / 1000) - base;
+ return tick_to_time(get_ticks()) - base;
}
void set_timer (unsigned long t)
unsigned long get_tbclk (void)
{
- return CONFIG_SYS_HZ;
+ return timer_freq;
}
#
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
+PLATFORM_LDFLAGS += -e $(TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE)
+
+LDSCRIPT := $(SRCTREE)/cpu/$(CPU)/u-boot.lds
projects / oweals / u-boot.git / commitdiff