x86: Disable microcode section for FSP2

At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 44f7f0ab03ece4250cad3edbe9762a394dcd1046..64f167306b0eea56bfba4e4fc6ea1c96e469abbc 100644 (file)
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -588,6 +588,10 @@ config HAVE_REFCODE
           broadwell) U-Boot will be missing some critical setup steps.
           Various peripherals may fail to work.
 
+config HAVE_MICROCODE
+       bool
+       default y if !FSP_VERSION2
+
 config SMP
        bool "Enable Symmetric Multiprocessing"
        default n

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 33441c7c807a2a7ae1a1f0a224a0f62e4becfd0e..850fe3ac11ae72dae3bcab8de791afed3f1495d0 100644 (file)
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -37,11 +37,13 @@
        };
 #endif
 #ifdef CONFIG_TPL
+#ifdef CONFIG_HAVE_MICROCODE
        u-boot-tpl-with-ucode-ptr {
                offset = <CONFIG_TPL_TEXT_BASE>;
        };
        u-boot-tpl-dtb {
        };
+#endif
        u-boot-spl {
                offset = <CONFIG_SPL_TEXT_BASE>;
        };
@@ -77,11 +79,16 @@
                offset = <CONFIG_SYS_TEXT_BASE>;
        };
 #endif
+#ifdef CONFIG_HAVE_MICROCODE
        u-boot-dtb-with-ucode {
        };
        u-boot-ucode {
                align = <16>;
        };
+#else
+       u-boot-dtb {
+       };
+#endif
 #ifdef CONFIG_HAVE_X86_FIT
        intel-fit {
        };