Replace CONFIG_MPC837x with a proper CONFIG_ARCH_MPC837X Kconfig option.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
config TARGET_MPC837XEMDS
bool "Support MPC837XEMDS"
+ select ARCH_MPC837X
select BOARD_EARLY_INIT_F
imply CMD_SATA
imply FSL_SATA
config TARGET_MPC837XERDB
bool "Support MPC837XERDB"
+ select ARCH_MPC837X
select BOARD_EARLY_INIT_F
config TARGET_IDS8313
config ARCH_MPC8360
bool
+config ARCH_MPC837X
+ bool
+
source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8308rdb/Kconfig"
source "board/freescale/mpc8313erdb/Kconfig"
u32 csb_clk;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
u32 brg_clk;
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
u32 sata_clk;
#endif
sccr = im->clk.sccr;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
tsec1_clk = 0;
#endif
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
case 0:
usbdr_clk = 0;
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
i2c1_clk = sdhc_clk;
-#elif defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC837X)
i2c1_clk = enc_clk;
#elif defined(CONFIG_ARCH_MPC8309)
i2c1_clk = csb_clk;
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
pciexp1_clk = 0;
}
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
case 0:
sata_clk = 0;
gd->arch.csb_clk = csb_clk;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
gd->arch.tsec1_clk = tsec1_clk;
gd->arch.tsec2_clk = tsec2_clk;
gd->arch.usbdr_clk = usbdr_clk;
gd->arch.brg_clk = brg_clk;
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC837X)
gd->arch.pciexp1_clk = pciexp1_clk;
gd->arch.pciexp2_clk = pciexp2_clk;
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
gd->arch.sata_clk = sata_clk;
#endif
gd->pci_clk = pci_sync_in;
strmhz(buf, gd->arch.sdhc_clk));
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
printf(" TSEC1: %-4s MHz\n",
strmhz(buf, gd->arch.tsec1_clk));
printf(" TSEC2: %-4s MHz\n",
strmhz(buf, gd->arch.usbmph_clk));
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC837X)
printf(" PCIEXP1: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp1_clk));
printf(" PCIEXP2: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp2_clk));
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
printf(" SATA: %-4s MHz\n",
strmhz(buf, gd->arch.sata_clk));
#endif
#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_ARCH_MPC8315)
#define MPC83XX_GPIO_CTRLRS 1
-#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
#define MPC83XX_GPIO_CTRLRS 2
#else
#define MPC83XX_GPIO_CTRLRS 0
/* There are other clocks in the MPC83XX */
u32 csb_clk;
# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
u32 lbiu_clk;
u32 lclk_clk;
# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
# endif
-# if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
+# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
u32 sata_clk;
# endif
# if defined(CONFIG_ARCH_MPC8360)
u8 res12[0x1CF00];
} immap_t;
-#elif defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC837X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
defined(CONFIG_ARCH_MPC8313) || \
defined(CONFIG_ARCH_MPC8315) || \
defined(CONFIG_ARCH_MPC834X) || \
- defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC837X)
typedef struct spi8xxx {
u8 res0[0x20]; /* 0x0-0x01f reserved */
switch (odt_rd_cfg) {
case ODT_RD_ONLY_OTHER_DIMM:
if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
return -EINVAL;
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
return -EINVAL;
switch (odt_wr_cfg) {
case ODT_WR_ONLY_OTHER_DIMM:
if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
return -EINVAL;
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
return -EINVAL;
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XERDB 1
#define CONFIG_HWCONFIG
#define SPCR_TSEC2EP_SHIFT (31-31)
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_MPC837x)
-/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
+ defined(CONFIG_ARCH_MPC837X)
+/* SPCR bits - MPC8308, MPC831x and MPC837X specific */
/* TSEC data priority */
#define SPCR_TSECDP 0x00003000
#define SPCR_TSECDP_SHIFT (31-19)
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_MPC837x)
-/* SICRL bits - MPC837x specific */
+#elif defined(CONFIG_ARCH_MPC837X)
+/* SICRL bits - MPC837X specific */
#define SICRL_USB_A 0xC0000000
#define SICRL_USB_B 0x30000000
#define SICRL_USB_B_SD 0x20000000
#define SICRL_LDP_A 0x00000002
#define SICRL_LDP_B 0x00000001
-/* SICRH bits - MPC837x specific */
+/* SICRH bits - MPC837X specific */
#define SICRH_DDR 0x80000000
#define SICRH_TSEC1_A 0x10000000
#define SICRH_TSEC1_B 0x08000000
#define HRCWL_SVCOD_DIV_8 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
-#elif defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC837X)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_4 0x00000000
#if defined(CONFIG_ARCH_MPC834X)
#define HRCWH_ROM_LOC_PCI2 0x00200000
#endif
-#if defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC837X)
#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC837X)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
* RSR - Reset Status Register
*/
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_MPC837x)
+ defined(CONFIG_ARCH_MPC837X)
#define RSR_RSTSRC 0xF0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 28
#else
#define SCCR_TDMCM_2 0x00000020
#define SCCR_TDMCM_3 0x00000030
-#elif defined(CONFIG_MPC837x)
-/* SCCR bits - MPC837x specific */
+#elif defined(CONFIG_ARCH_MPC837X)
+/* SCCR bits - MPC837X specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
#elif defined(CONFIG_ARCH_MPC832X)
#define CSCONFIG_ODT_RD_CFG 0x00400000
#define CSCONFIG_ODT_WR_CFG 0x00040000
-#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
CONFIG_MPC8349ITX
CONFIG_MPC837XEMDS
CONFIG_MPC837XERDB
-CONFIG_MPC837x
CONFIG_MPC83XX_GPIO
CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION
CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN