ppc4xx: Sequoia coding style cleanup and beautification
authorMatthias Fuchs <matthias.fuchs@esd-electronics.com>
Wed, 16 Jan 2008 09:33:46 +0000 (10:33 +0100)
committerStefan Roese <sr@denx.de>
Wed, 16 Jan 2008 10:24:28 +0000 (11:24 +0100)
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
board/amcc/sequoia/init.S
board/amcc/sequoia/sequoia.c

index 306c92c157ed8c3406e0c2bffc2b2cf7f3a5d990..46a37c6a20175acc01c1273ef528f7147d18b06c 100644 (file)
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,7 +25,7 @@
 #include <asm-ppc/mmu.h>
 #include <config.h>
 
-/**************************************************************************
+/*
  * TLB TABLE
  *
  * This table is used by the cpu boot code to setup the initial tlb
@@ -31,8 +33,7 @@
  * this table lets each board set things up however they like.
  *
  *  Pointer to the table is returned in r1
- *
- *************************************************************************/
+ */
     .section .bootpg,"ax"
     .globl tlbtab
 
index e46efef10a725b5e81ad60dd684090bff59a1fb8..ce0537f220684b97f4ddb360a81377ca4076418f 100644 (file)
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2006
  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel,           AMCC/IBM, alain.saurel@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
 #include <asm/gpio.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#include <asm/bitops.h>
 #include <asm/ppc4xx-intvec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips   */
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 ulong flash_get_size (ulong base, int banknum);
 
@@ -46,9 +47,9 @@ int board_early_init_f(void)
        mtdcr(ebccfga, xbcfg);
        mtdcr(ebccfgd, 0xb8400000);
 
-       /*--------------------------------------------------------------------
+       /*
         * Setup the interrupt controller polarities, triggers, etc.
-        *-------------------------------------------------------------------*/
+        */
        mtdcr(uic0sr, 0xffffffff);      /* clear all */
        mtdcr(uic0er, 0x00000000);      /* disable all */
        mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
@@ -87,9 +88,11 @@ int board_early_init_f(void)
 
        /* select Ethernet pins */
        mfsdr(SDR0_PFC1, sdr0_pfc1);
-       sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
+       sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+               SDR0_PFC1_SELECT_CONFIG_4;
        mfsdr(SDR0_PFC2, sdr0_pfc2);
-       sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
+       sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+               SDR0_PFC2_SELECT_CONFIG_4;
        mtsdr(SDR0_PFC2, sdr0_pfc2);
        mtsdr(SDR0_PFC1, sdr0_pfc1);
 
@@ -109,9 +112,6 @@ int board_early_init_f(void)
        return 0;
 }
 
-/*---------------------------------------------------------------------------+
-  | misc_init_r.
-  +---------------------------------------------------------------------------*/
 int misc_init_r(void)
 {
        uint pbcr;
@@ -124,11 +124,7 @@ int misc_init_r(void)
        char *act = getenv("usbact");
 #endif
 
-       /*
-        * FLASH stuff...
-        */
-
-       /* Re-do sizing to get full correct info */
+       /* Re-do flash sizing to get full correct info */
 
        /* adjust flash start and offset */
        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@@ -140,32 +136,7 @@ int misc_init_r(void)
        mtdcr(ebccfga, pb0cr);
 #endif
        pbcr = mfdcr(ebccfgd);
-       switch (gd->bd->bi_flashsize) {
-       case 1 << 20:
-               size_val = 0;
-               break;
-       case 2 << 20:
-               size_val = 1;
-               break;
-       case 4 << 20:
-               size_val = 2;
-               break;
-       case 8 << 20:
-               size_val = 3;
-               break;
-       case 16 << 20:
-               size_val = 4;
-               break;
-       case 32 << 20:
-               size_val = 5;
-               break;
-       case 64 << 20:
-               size_val = 6;
-               break;
-       case 128 << 20:
-               size_val = 7;
-               break;
-       }
+        size_val = ffs(gd->bd->bi_flashsize) - 21;
        pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
        mtdcr(ebccfga, pb3cr);
@@ -197,7 +168,7 @@ int misc_init_r(void)
         * USB suff...
         */
 #ifdef CONFIG_440EPX
-       if (act == NULL || strcmp(act, "hostdev") == 0) {
+       if (act == NULL || strcmp(act, "hostdev") == 0) {
                /* SDR Setting */
                mfsdr(SDR0_PFC1, sdr0_pfc1);
                mfsdr(SDR0_USB2D0CR, usb2d0cr);
@@ -205,27 +176,32 @@ int misc_init_r(void)
                mfsdr(SDR0_USB2H0CR, usb2h0cr);
 
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;    /*1*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;         /*0*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;          /*1*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;          /*1*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 
-               /* An 8-bit/60MHz interface is the only possible alternative
-                  when connecting the Device to the PHY */
+               /*
+                * An 8-bit/60MHz interface is the only possible alternative
+                * when connecting the Device to the PHY
+                */
                usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-               usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;        /*1*/
+               usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
 
-               /* To enable the USB 2.0 Device function through the UTMI interface */
+               /*
+                * To enable the USB 2.0 Device function
+                * through the UTMI interface
+                */
                usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-               usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;          /*1*/
+               usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
 
                sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-               sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;                /*0*/
+               sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
 
                mtsdr(SDR0_PFC1, sdr0_pfc1);
                mtsdr(SDR0_USB2D0CR, usb2d0cr);
@@ -245,13 +221,13 @@ int misc_init_r(void)
                mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;         /*0*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;          /*1*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;          /*1*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
                mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 
                udelay (1000);
@@ -276,31 +252,31 @@ int misc_init_r(void)
                mfsdr(SDR0_PFC1, sdr0_pfc1);
 
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;     /*0*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;          /*1*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;           /*0*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;           /*0*/
+               usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
 
                usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-               usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;         /*0*/
+               usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
 
                usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-               usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;              /*0*/
+               usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
 
                sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-               sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;                /*1*/
+               sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
 
                mtsdr(SDR0_USB2H0CR, usb2h0cr);
                mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
                mtsdr(SDR0_USB2D0CR, usb2d0cr);
                mtsdr(SDR0_PFC1, sdr0_pfc1);
 
-               /*clear resets*/
+               /* clear resets */
                udelay (1000);
                mtsdr(SDR0_SRST1, 0x00000000);
                udelay (1000);
@@ -398,43 +374,42 @@ void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 }
 #endif
 
-/*************************************************************************
- *  pci_pre_init
- *
- *  This routine is called just prior to registering the hose and gives
- *  the board the opportunity to check things. Returning a value of zero
- *  indicates that things are bad & PCI initialization should be aborted.
+/*
+ * pci_pre_init
  *
- *     Different boards may wish to customize the pci controller structure
- *     (add regions, override default access routines, etc) or perform
- *     certain pre-initialization actions.
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
  *
- ************************************************************************/
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
 #if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
        unsigned long addr;
 
-       /*-------------------------------------------------------------------------+
-         | Set priority for all PLB3 devices to 0.
-         | Set PLB3 arbiter to fair mode.
-         +-------------------------------------------------------------------------*/
+       /*
+        * Set priority for all PLB3 devices to 0.
+        * Set PLB3 arbiter to fair mode.
+        */
        mfsdr(sdr_amp1, addr);
        mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
        addr = mfdcr(plb3_acr);
        mtdcr(plb3_acr, addr | 0x80000000);
 
-       /*-------------------------------------------------------------------------+
-         | Set priority for all PLB4 devices to 0.
-         +-------------------------------------------------------------------------*/
+       /*
+        * Set priority for all PLB4 devices to 0.
+        */
        mfsdr(sdr_amp0, addr);
        mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
        addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
        mtdcr(plb4_acr, addr);
 
-       /*-------------------------------------------------------------------------+
-         | Set Nebula PLB4 arbiter to fair mode.
-         +-------------------------------------------------------------------------*/
+       /*
+        * Set Nebula PLB4 arbiter to fair mode.
+        */
        /* Segment0 */
        addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
        addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
@@ -456,47 +431,51 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
+/*
+ * pci_target_init
  *
- ************************************************************************/
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
-       /*--------------------------------------------------------------------------+
+       /*
         * Set up Direct MMIO registers
-        *--------------------------------------------------------------------------*/
-       /*--------------------------------------------------------------------------+
-         | PowerPC440EPX PCI Master configuration.
-         | Map one 1Gig range of PLB/processor addresses to PCI memory space.
-         |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
-         |   Use byte reversed out routines to handle endianess.
-         | Make this region non-prefetchable.
-         +--------------------------------------------------------------------------*/
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+        */
+       /*
+        * PowerPC440EPX PCI Master configuration.
+        * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+        * PLB address 0xA0000000-0xDFFFFFFF
+        *     ==> PCI address 0xA0000000-0xDFFFFFFF
+        * Use byte reversed out routines to handle endianess.
+        * Make this region non-prefetchable.
+        */
+       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
+                                               /* - disabled b4 setting */
        out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
+       out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
        out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
+                                               /* and enable region */
 
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
+                                               /* - disabled b4 setting */
        out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
+       out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
        out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
+                                               /* and enable region */
 
        out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
+       out32r(PCIX0_PTM1LA, 0);                /* Local Addr. Reg */
+       out32r(PCIX0_PTM2MS, 0);                /* Memory Size/Attribute */
+       out32r(PCIX0_PTM2LA, 0);                /* Local Addr. Reg */
 
-       /*--------------------------------------------------------------------------+
+       /*
         * Set up Configuration registers
-        *--------------------------------------------------------------------------*/
+        */
 
        /* Program the board's subsystem id/vendor id */
        pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
@@ -515,51 +494,46 @@ void pci_target_init(struct pci_controller *hose)
        pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
 }
-#endif                         /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 
-/*************************************************************************
- *  pci_master_init
- *
- ************************************************************************/
 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
        unsigned short temp_short;
 
-       /*--------------------------------------------------------------------------+
-         | Write the PowerPC440 EP PCI Configuration regs.
-         |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
-         |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
-         +--------------------------------------------------------------------------*/
+       /*
+        * Write the PowerPC440 EP PCI Configuration regs.
+        * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+        * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+        */
        pci_read_config_word(0, PCI_COMMAND, &temp_short);
        pci_write_config_word(0, PCI_COMMAND,
                              temp_short | PCI_COMMAND_MASTER |
                              PCI_COMMAND_MEMORY);
 }
-#endif                         /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 
-/*************************************************************************
- *  is_pci_host
- *
- *     This routine is called to determine if a pci scan should be
- *     performed. With various hardware environments (especially cPCI and
- *     PPMC) it's insufficient to depend on the state of the arbiter enable
- *     bit in the strap register, or generic host/adapter assumptions.
- *
- *     Rather than hard-code a bad assumption in the general 440 code, the
- *     440 pci code requires the board to decide at runtime.
+/*
+ * is_pci_host
  *
- *     Return 0 for adapter mode, non-zero for host (monarch) mode.
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
  *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
  *
- ************************************************************************/
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
 #if defined(CONFIG_PCI)
 int is_pci_host(struct pci_controller *hose)
 {
        /* Cactus is always configured as host. */
        return (1);
 }
-#endif                         /* defined(CONFIG_PCI) */
+#endif /* defined(CONFIG_PCI) */
+
 #if defined(CONFIG_POST)
 /*
  * Returns 1 if keys pressed to start the power-on long-running tests