fix riscv64 a_cas inline asm operand sign extension

This patch adds an explicit cast to the int arguments passed to the
inline asm used in the RISC-V's implementation of `a_cas`, to ensure
that they are properly sign extended to 64 bits. They aren't
automatically sign extended by Clang, and GCC technically also doesn't
guarantee that they will be sign extended.

diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h
index 41ad4d04907cb2627c484da9eb756a9f635134a5..0c382588686c48ed5af2b8dcf9f816c0aacbea9e 100644 (file)
--- a/arch/riscv64/atomic_arch.h
+++ b/arch/riscv64/atomic_arch.h
@@ -15,7 +15,7 @@ static inline int a_cas(volatile int *p, int t, int s)
                "       bnez %1, 1b\n"
                "1:"
                : "=&r"(old), "=&r"(tmp)
-               : "r"(p), "r"(t), "r"(s)
+               : "r"(p), "r"((long)t), "r"((long)s)
                : "memory");
        return old;
 }