am33xx: convert defines from am33xx-specific to generic names
authorMatt Porter <mporter@ti.com>
Fri, 15 Mar 2013 10:07:02 +0000 (10:07 +0000)
committerTom Rini <trini@ti.com>
Sun, 24 Mar 2013 16:49:11 +0000 (12:49 -0400)
Eliminate AM33xx specific names to prepare for TI814x support
within AM33xx-land.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/include/asm/arch-am33xx/hardware.h
board/phytec/pcm051/board.c
board/ti/am335x/board.c

index e35a3e3a704e122ca381eae766dbe9e78f2cc565..885fb2d20e5a516432ed07a8ecce327dded9edb0 100644 (file)
@@ -141,11 +141,11 @@ int arch_misc_init(void)
 {
 #ifdef CONFIG_AM335X_USB0
        musb_register(&otg0_plat, &otg0_board_data,
-               (void *)AM335X_USB0_OTG_BASE);
+               (void *)USB0_OTG_BASE);
 #endif
 #ifdef CONFIG_AM335X_USB1
        musb_register(&otg1_plat, &otg1_board_data,
-               (void *)AM335X_USB1_OTG_BASE);
+               (void *)USB1_OTG_BASE);
 #endif
        return 0;
 }
index 6dd3296907acce5671364bc09b8b6b65824108f0..7016e25a41d197174e3533b66fab81df343db1b9 100644 (file)
 #define GPMC_BASE                      0x50000000
 
 /* CPSW Config space */
-#define AM335X_CPSW_BASE               0x4A100000
-#define AM335X_CPSW_MDIO_BASE          0x4A101000
+#define CPSW_BASE                      0x4A100000
+#define CPSW_MDIO_BASE                 0x4A101000
 
 /* RTC base address */
-#define AM335X_RTC_BASE                        0x44E3E000
+#define RTC_BASE                       0x44E3E000
 
 /* OTG */
-#define AM335X_USB0_OTG_BASE           0x47401000
-#define AM335X_USB1_OTG_BASE           0x47401800
+#define USB0_OTG_BASE                  0x47401000
+#define USB1_OTG_BASE                  0x47401800
 
 #endif /* __AM33XX_HARDWARE_H */
index 55bc01871457a716afe152e6d1a85128e1a6423c..471725a2fa71587d4b4ef3479e0a78b6c0410eb6 100644 (file)
@@ -61,7 +61,7 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
 static void rtc32k_enable(void)
 {
-       struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
        /*
         * Unlock the RTC's registers.  For more details please see the
@@ -199,8 +199,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 };
 
 static struct cpsw_platform_data cpsw_data = {
-       .mdio_base              = AM335X_CPSW_MDIO_BASE,
-       .cpsw_base              = AM335X_CPSW_BASE,
+       .mdio_base              = CPSW_MDIO_BASE,
+       .cpsw_base              = CPSW_BASE,
        .mdio_div               = 0xff,
        .channels               = 8,
        .cpdma_reg_ofs          = 0x800,
index 2e230f456f41145006f71415b790f57fb81f3140..758ba15430509b15c0f018ce52b93dfc4a8ff9e0 100644 (file)
@@ -134,7 +134,7 @@ static int read_eeprom(void)
 
 static void rtc32k_enable(void)
 {
-       struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
        /*
         * Unlock the RTC's registers.  For more details please see the
@@ -414,8 +414,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 };
 
 static struct cpsw_platform_data cpsw_data = {
-       .mdio_base              = AM335X_CPSW_MDIO_BASE,
-       .cpsw_base              = AM335X_CPSW_BASE,
+       .mdio_base              = CPSW_MDIO_BASE,
+       .cpsw_base              = CPSW_BASE,
        .mdio_div               = 0xff,
        .channels               = 8,
        .cpdma_reg_ofs          = 0x800,