arm: socfpga: sysmgr: Add FPGA bits into system manager

Add missing system manager bits from Altera U-Boot to make the code
comparable. These are the bits which depend on the FPGA manager.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c
index 07c72e49e0f018f06c83e897d22c6704261509fd..11f7badbf212168e9d76aa3c6b01af55ab619379 100644 (file)
--- a/arch/arm/cpu/armv7/socfpga/system_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -14,6 +14,43 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct socfpga_system_manager *sysmgr_regs =
        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
+/*
+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
+ */
+static void populate_sysmgr_fpgaintf_module(void)
+{
+       uint32_t handoff_val = 0;
+
+       /* ISWGRP_HANDOFF_FPGAINTF */
+       writel(0, &sysmgr_regs->iswgrp_handoff[2]);
+
+       /* Enable the signal for those HPS peripherals that use FPGA. */
+       if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+               handoff_val |= SYSMGR_FPGAINTF_NAND;
+       if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+               handoff_val |= SYSMGR_FPGAINTF_EMAC1;
+       if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+               handoff_val |= SYSMGR_FPGAINTF_SDMMC;
+       if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+               handoff_val |= SYSMGR_FPGAINTF_EMAC0;
+       if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+               handoff_val |= SYSMGR_FPGAINTF_SPIM0;
+       if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+               handoff_val |= SYSMGR_FPGAINTF_SPIM1;
+
+       /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
+       based on pinmux setting */
+       setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
+
+       handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
+       if (fpgamgr_test_fpga_ready()) {
+               /* Enable the required signals only */
+               writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
+       }
+}
+
 /*
  * Configure all the pin muxes
  */
@@ -26,4 +63,6 @@ void sysmgr_pinmux_init(void)
                writel(sys_mgr_init_table[i], regs);
                regs += sizeof(regs);
        }
+
+       populate_sysmgr_fpgaintf_module();
 }