void reset_cpu(ulong ignored)
{
- at91_st_t *st = (at91_st_t *) AT91_ST_BASE;
+ at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST;
#if defined(CONFIG_AT91RM9200_USART)
/*shutdown the console to avoid strange chars during reset */
serial_exit();
#include <common.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_tc.h>
#include <asm/arch/at91_pmc.h>
int timer_init(void)
{
- at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
/* enables TC1.0 clock */
- writel(1 << AT91_ID_TC0, &pmc->pcer); /* enable clock */
+ writel(1 << ATMEL_ID_TC0, &pmc->pcer); /* enable clock */
writel(0, &tc->bcr);
writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
void reset_timer_masked(void)
{
/* reset time */
- at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
+ at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
gd->lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
gd->tbl = 0;
}
ulong get_timer_raw(void)
{
- at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
+ at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
u32 now;
now = readl(&tc->tc[0].cv) & 0x0000ffff;
#ifndef AT91_MC_H
#define AT91_MC_H
-#define AT91_ASM_MC_EBI_CSA (AT91_MC_BASE + 0x60)
-#define AT91_ASM_MC_EBI_CFG (AT91_MC_BASE + 0x64)
-#define AT91_ASM_MC_SMC_CSR0 (AT91_MC_BASE + 0x70)
-#define AT91_ASM_MC_SDRAMC_MR (AT91_MC_BASE + 0x90)
-#define AT91_ASM_MC_SDRAMC_TR (AT91_MC_BASE + 0x94)
-#define AT91_ASM_MC_SDRAMC_CR (AT91_MC_BASE + 0x98)
+#define AT91_ASM_MC_EBI_CSA (ATMEL_BASE_MC + 0x60)
+#define AT91_ASM_MC_EBI_CFG (ATMEL_BASE_MC + 0x64)
+#define AT91_ASM_MC_SMC_CSR0 (ATMEL_BASE_MC + 0x70)
+#define AT91_ASM_MC_SDRAMC_MR (ATMEL_BASE_MC + 0x90)
+#define AT91_ASM_MC_SDRAMC_TR (ATMEL_BASE_MC + 0x94)
+#define AT91_ASM_MC_SDRAMC_CR (ATMEL_BASE_MC + 0x98)
#ifndef __ASSEMBLY__
#ifndef AT91_PMC_H
#define AT91_PMC_H
-#define AT91_ASM_PMC_MOR (AT91_PMC_BASE + 0x20)
-#define AT91_ASM_PMC_PLLAR (AT91_PMC_BASE + 0x28)
-#define AT91_ASM_PMC_PLLBR (AT91_PMC_BASE + 0x2c)
-#define AT91_ASM_PMC_MCKR (AT91_PMC_BASE + 0x30)
-#define AT91_ASM_PMC_SR (AT91_PMC_BASE + 0x68)
+#define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20)
+#define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28)
+#define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c)
+#define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30)
+#define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68)
#ifndef __ASSEMBLY__
#ifndef __AT91RM9200_H__
#define __AT91RM9200_H__
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
+#define CONFIG_ARM920T /* This is an ARM920T Core */
+
/* Periperial Identifiers */
-#define AT91_ID_SYS 1 /* System Peripheral */
-#define AT91_ID_PIOA 2 /* PIO port A */
-#define AT91_ID_PIOB 3 /* PIO port B */
-#define AT91_ID_PIOC 4 /* PIO port C */
-#define AT91_ID_PIOD 5 /* PIO port D BGA only */
-#define AT91_ID_USART0 6 /* USART 0 */
-#define AT91_ID_USART1 7 /* USART 1 */
-#define AT91_ID_USART2 8 /* USART 2 */
-#define AT91_ID_USART3 9 /* USART 3 */
-#define AT91_ID_MCI 10 /* Multimedia Card Interface */
-#define AT91_ID_UDP 11 /* USB Device Port */
-#define AT91_ID_TWI 12 /* Two Wire Interface */
-#define AT91_ID_SPI 13 /* Serial Peripheral Interface */
-#define AT91_ID_SSC0 14 /* Synch. Serial Controller 0 */
-#define AT91_ID_SSC1 15 /* Synch. Serial Controller 1 */
-#define AT91_ID_SSC2 16 /* Synch. Serial Controller 2 */
-#define AT91_ID_TC0 17 /* Timer Counter 0 */
-#define AT91_ID_TC1 18 /* Timer Counter 1 */
-#define AT91_ID_TC2 19 /* Timer Counter 2 */
-#define AT91_ID_TC3 20 /* Timer Counter 3 */
-#define AT91_ID_TC4 21 /* Timer Counter 4 */
-#define AT91_ID_TC5 22 /* Timer Counter 5 */
-#define AT91_ID_UHP 23 /* OHCI USB Host Port */
-#define AT91_ID_EMAC 24 /* Ethernet MAC */
-#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller */
-#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller */
-#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller */
-#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller */
-#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller */
-#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller */
-#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller */
-
-#define AT91_USB_HOST_BASE 0x00300000
-
-#define AT91_TC_BASE 0xFFFA0000
-#define AT91_UDP_BASE 0xFFFB0000
-#define AT91_MCI_BASE 0xFFFB4000
-#define AT91_TWI_BASE 0xFFFB8000
-#define AT91_EMAC_BASE 0xFFFBC000
-#define AT91_USART_BASE 0xFFFC0000 /* 4x 0x4000 Offset */
-#define AT91_SCC_BASE 0xFFFD0000 /* 4x 0x4000 Offset */
-#define AT91_SPI_BASE 0xFFFE0000
-
-#define AT91_AIC_BASE 0xFFFFF000
-#define AT91_DBGU_BASE 0xFFFFF200
-#define AT91_PIO_BASE 0xFFFFF400 /* 4x 0x200 Offset */
-#define AT91_PMC_BASE 0xFFFFFC00
-#define AT91_ST_BASE 0xFFFFFD00
-#define AT91_ST_BASE 0xFFFFFD00
-#define AT91_RTC_BASE 0xFFFFFE00
-#define AT91_MC_BASE 0xFFFFFF00
+#define ATMEL_ID_SYS 1 /* System Peripheral */
+#define ATMEL_ID_PIOA 2 /* PIO port A */
+#define ATMEL_ID_PIOB 3 /* PIO port B */
+#define ATMEL_ID_PIOC 4 /* PIO port C */
+#define ATMEL_ID_PIOD 5 /* PIO port D BGA only */
+#define ATMEL_ID_USART0 6 /* USART 0 */
+#define ATMEL_ID_USART1 7 /* USART 1 */
+#define ATMEL_ID_USART2 8 /* USART 2 */
+#define ATMEL_ID_USART3 9 /* USART 3 */
+#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */
+#define ATMEL_ID_UDP 11 /* USB Device Port */
+#define ATMEL_ID_TWI 12 /* Two Wire Interface */
+#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */
+#define ATMEL_ID_SSC0 14 /* Synch. Serial Controller 0 */
+#define ATMEL_ID_SSC1 15 /* Synch. Serial Controller 1 */
+#define ATMEL_ID_SSC2 16 /* Synch. Serial Controller 2 */
+#define ATMEL_ID_TC0 17 /* Timer Counter 0 */
+#define ATMEL_ID_TC1 18 /* Timer Counter 1 */
+#define ATMEL_ID_TC2 19 /* Timer Counter 2 */
+#define ATMEL_ID_TC3 20 /* Timer Counter 3 */
+#define ATMEL_ID_TC4 21 /* Timer Counter 4 */
+#define ATMEL_ID_TC5 22 /* Timer Counter 5 */
+#define ATMEL_ID_UHP 23 /* OHCI USB Host Port */
+#define ATMEL_ID_EMAC 24 /* Ethernet MAC */
+#define ATMEL_ID_IRQ0 25 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ1 26 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ2 27 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ3 28 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ4 29 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ5 30 /* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ6 31 /* Advanced Interrupt Controller */
+
+#define ATMEL_USB_HOST_BASE 0x00300000
+
+#define ATMEL_BASE_TC 0xFFFA0000
+#define ATMEL_BASE_UDP 0xFFFB0000
+#define ATMEL_BASE_MCI 0xFFFB4000
+#define ATMEL_BASE_TWI 0xFFFB8000
+#define ATMEL_BASE_EMAC 0xFFFBC000
+#define ATMEL_BASE_USART 0xFFFC0000 /* 4x 0x4000 Offset */
+#define ATMEL_BASE_USART0 ATMEL_BASE_USART
+#define ATMEL_BASE_USART1 (ATMEL_BASE_USART + 0x4000)
+#define ATMEL_BASE_USART2 (ATMEL_BASE_USART + 0x8000)
+#define ATMEL_BASE_USART3 (ATMEL_BASE_USART + 0xC000)
+
+#define ATMEL_BASE_SCC 0xFFFD0000 /* 4x 0x4000 Offset */
+#define ATMEL_BASE_SPI 0xFFFE0000
+
+#define ATMEL_BASE_AIC 0xFFFFF000
+#define ATMEL_BASE_DBGU 0xFFFFF200
+#define ATMEL_BASE_PIO 0xFFFFF400 /* 4x 0x200 Offset */
+#define ATMEL_BASE_PMC 0xFFFFFC00
+#define ATMEL_BASE_ST 0xFFFFFD00
+#define ATMEL_BASE_RTC 0xFFFFFE00
+#define ATMEL_BASE_MC 0xFFFFFF00
+#define AT91_PIO_BASE ATMEL_BASE_PIO
/* AT91RM9200 Periperial Multiplexing A */
/* Port A */
-#define AT91_PMX_AA_EREFCK 0x00000080
-#define AT91_PMX_AA_ETXCK 0x00000080
-#define AT91_PMX_AA_ETXEN 0x00000100
-#define AT91_PMX_AA_ETX0 0x00000200
-#define AT91_PMX_AA_ETX1 0x00000400
-#define AT91_PMX_AA_ECRS 0x00000800
-#define AT91_PMX_AA_ECRSDV 0x00000800
-#define AT91_PMX_AA_ERX0 0x00001000
-#define AT91_PMX_AA_ERX1 0x00002000
-#define AT91_PMX_AA_ERXER 0x00004000
-#define AT91_PMX_AA_EMDC 0x00008000
-#define AT91_PMX_AA_EMDIO 0x00010000
-
-#define AT91_PMX_AA_TXD2 0x00810000
-
-#define AT91_PMX_AA_TWD 0x02000000
-#define AT91_PMX_AA_TWCK 0x04000000
+#define ATMEL_PMX_AA_EREFCK 0x00000080
+#define ATMEL_PMX_AA_ETXCK 0x00000080
+#define ATMEL_PMX_AA_ETXEN 0x00000100
+#define ATMEL_PMX_AA_ETX0 0x00000200
+#define ATMEL_PMX_AA_ETX1 0x00000400
+#define ATMEL_PMX_AA_ECRS 0x00000800
+#define ATMEL_PMX_AA_ECRSDV 0x00000800
+#define ATMEL_PMX_AA_ERX0 0x00001000
+#define ATMEL_PMX_AA_ERX1 0x00002000
+#define ATMEL_PMX_AA_ERXER 0x00004000
+#define ATMEL_PMX_AA_EMDC 0x00008000
+#define ATMEL_PMX_AA_EMDIO 0x00010000
+
+#define ATMEL_PMX_AA_TXD2 0x00810000
+
+#define ATMEL_PMX_AA_TWD 0x02000000
+#define ATMEL_PMX_AA_TWCK 0x04000000
/* Port B */
-#define AT91_PMX_BA_ERXCK 0x00080000
-#define AT91_PMX_BA_ECOL 0x00040000
-#define AT91_PMX_BA_ERXDV 0x00020000
-#define AT91_PMX_BA_ERX3 0x00010000
-#define AT91_PMX_BA_ERX2 0x00008000
-#define AT91_PMX_BA_ETXER 0x00004000
-#define AT91_PMX_BA_ETX3 0x00002000
-#define AT91_PMX_BA_ETX2 0x00001000
+#define ATMEL_PMX_BA_ERXCK 0x00080000
+#define ATMEL_PMX_BA_ECOL 0x00040000
+#define ATMEL_PMX_BA_ERXDV 0x00020000
+#define ATMEL_PMX_BA_ERX3 0x00010000
+#define ATMEL_PMX_BA_ERX2 0x00008000
+#define ATMEL_PMX_BA_ETXER 0x00004000
+#define ATMEL_PMX_BA_ETX3 0x00002000
+#define ATMEL_PMX_BA_ETX2 0x00001000
/* Port B */
-#define AT91_PMX_CA_BFCK 0x00000001
-#define AT91_PMX_CA_BFRDY 0x00000002
-#define AT91_PMX_CA_SMOE 0x00000002
-#define AT91_PMX_CA_BFAVD 0x00000004
-#define AT91_PMX_CA_BFBAA 0x00000008
-#define AT91_PMX_CA_SMWE 0x00000008
-#define AT91_PMX_CA_BFOE 0x00000010
-#define AT91_PMX_CA_BFWE 0x00000020
-#define AT91_PMX_CA_NWAIT 0x00000040
-#define AT91_PMX_CA_A23 0x00000080
-#define AT91_PMX_CA_A24 0x00000100
-#define AT91_PMX_CA_A25 0x00000200
-#define AT91_PMX_CA_CFRNW 0x00000200
-#define AT91_PMX_CA_NCS4 0x00000400
-#define AT91_PMX_CA_CFCS 0x00000400
-#define AT91_PMX_CA_NCS5 0x00000800
-#define AT91_PMX_CA_CFCE1 0x00001000
-#define AT91_PMX_CA_NCS6 0x00001000
-#define AT91_PMX_CA_CFCE2 0x00002000
-#define AT91_PMX_CA_NCS7 0x00002000
-#define AT91_PMX_CA_D16_31 0xFFFF0000
-
-#define CONFIG_SYS_AT91_CPU_NAME "AT91RM9200"
+#define ATMEL_PMX_CA_BFCK 0x00000001
+#define ATMEL_PMX_CA_BFRDY 0x00000002
+#define ATMEL_PMX_CA_SMOE 0x00000002
+#define ATMEL_PMX_CA_BFAVD 0x00000004
+#define ATMEL_PMX_CA_BFBAA 0x00000008
+#define ATMEL_PMX_CA_SMWE 0x00000008
+#define ATMEL_PMX_CA_BFOE 0x00000010
+#define ATMEL_PMX_CA_BFWE 0x00000020
+#define ATMEL_PMX_CA_NWAIT 0x00000040
+#define ATMEL_PMX_CA_A23 0x00000080
+#define ATMEL_PMX_CA_A24 0x00000100
+#define ATMEL_PMX_CA_A25 0x00000200
+#define ATMEL_PMX_CA_CFRNW 0x00000200
+#define ATMEL_PMX_CA_NCS4 0x00000400
+#define ATMEL_PMX_CA_CFCS 0x00000400
+#define ATMEL_PMX_CA_NCS5 0x00000800
+#define ATMEL_PMX_CA_CFCE1 0x00001000
+#define ATMEL_PMX_CA_NCS6 0x00001000
+#define ATMEL_PMX_CA_CFCE2 0x00002000
+#define ATMEL_PMX_CA_NCS7 0x00002000
+#define ATMEL_PMX_CA_D16_31 0xFFFF0000
+
+#define ATMEL_PIO_PORTS 4 /* theese SoCs have 4 PIO */
+#define ATMEL_PMC_UHP AT91RM9200_PMC_UHP
+
+#define CONFIG_SYS_ATMEL_CPU_NAME "AT91RM9200"
#endif
int board_init(void)
{
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
/* Enable Ctrlc */
console_init_f();
/* Correct IRDA resistor problem / Set PA23_TXD in Output */
- writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
+ writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
/* adress of boot parameters */
int board_eth_init(bd_t *bis)
{
int rc = 0;
- rc = at91emac_register(bis, (u32) AT91_EMAC_BASE);
+ rc = at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
return rc;
}
#endif
void cpux9k2_nand_hw_init(void)
{
unsigned long csr;
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
- at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
/* Setup Smart Media, fitst enable the address range of CS3 */
writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa);
AT91_SMC_CSR_WSEN;
writel(csr, &mc->smc.csr[3]);
- writel(AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, &pio->pioc.asr);
- writel(AT91_PMX_CA_BFCK | AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE,
+ writel(ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE, &pio->pioc.asr);
+ writel(ATMEL_PMX_CA_BFCK | ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE,
&pio->pioc.pdr);
/* Configure PC2 as input (signal Nand READY ) */
- writel(AT91_PMX_CA_BFAVD, &pio->pioc.per);
- writel(AT91_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
- writel(AT91_PMX_CA_BFCK, &pio->pioc.codr);
+ writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.per);
+ writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
+ writel(ATMEL_PMX_CA_BFCK, &pio->pioc.codr);
/* PIOC clock enabling */
- writel(1 << AT91_ID_PIOC, &pmc->pcer);
+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
}
static void board_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
static int board_nand_dev_ready(struct mtd_info *mtd)
{
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0);
}
#endif
char *s;
unsigned long csr;
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
- at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
printf("Init Video as ");
s = getenv("displaywidth");
AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
writel(csr, &mc->smc.csr[2]);
- writel(1 << AT91_ID_PIOB, &pmc->pcer);
+ writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
vcxk_init(display_width, display_height);
#ifdef CONFIG_SPLASH_SCREEN
void i2c_init_board(void)
{
u32 pin;
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- writel(1 << AT91_ID_PIOA, &pmc->pcer);
- pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
+ writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
+ pin = ATMEL_PMX_AA_TWD | ATMEL_PMX_AA_TWCK;
writel(pin, &pio->pioa.idr);
writel(pin, &pio->pioa.pudr);
writel(pin, &pio->pioa.per);
void __led_toggle(led_id_t mask)
{
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
if (readl(&pio->piod.odsr) & mask)
writel(mask, &pio->piod.codr);
void __led_init(led_id_t mask, int state)
{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- writel(1 << AT91_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */
+ writel(1 << ATMEL_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */
/* Disable peripherals on LEDs */
writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per);
/* Enable pins as outputs */
void __led_set(led_id_t mask, int state)
{
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
if (state == STATUS_LED_ON)
writel(mask, &pio->piod.codr);
else
* Correct IRDA resistor problem
* Set PA23_TXD in Output
*/
- writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
+ writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
/* arch number of AT91RM9200EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
- return at91emac_register(bis, (u32) AT91_EMAC_BASE);
+ return at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
}
#endif
*/
#include <common.h>
-#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
/* bit mask in PIO port B */
#define GREEN_LED (1<<0)
void green_LED_on(void)
{
- at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
writel(GREEN_LED, &pio->piob.codr);
}
void yellow_LED_on(void)
{
- at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
writel(YELLOW_LED, &pio->piob.codr);
}
void red_LED_on(void)
{
- at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
writel(RED_LED, &pio->piob.codr);
}
void green_LED_off(void)
{
- at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
writel(GREEN_LED, &pio->piob.sodr);
}
void yellow_LED_off(void)
{
- at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
writel(YELLOW_LED, &pio->piob.sodr);
}
void red_LED_off(void)
{
- at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
writel(RED_LED, &pio->piob.sodr);
}
void coloured_LED_init (void)
{
- at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
- at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
/* Enable PIOB clock */
- writel(1 << AT91_ID_PIOB, &pmc->pcer);
+ writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
/* Disable peripherals on LEDs */
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
u32 value;
emac_device *dev;
at91_emac_t *emac;
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
emac = (at91_emac_t *) netdev->iobase;
dev = (emac_device *) netdev->priv;
/* PIO Disable Register */
- value = AT91_PMX_AA_EMDIO | AT91_PMX_AA_EMDC |
- AT91_PMX_AA_ERXER | AT91_PMX_AA_ERX1 |
- AT91_PMX_AA_ERX0 | AT91_PMX_AA_ECRS |
- AT91_PMX_AA_ETX1 | AT91_PMX_AA_ETX0 |
- AT91_PMX_AA_ETXEN | AT91_PMX_AA_EREFCK;
+ value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC |
+ ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 |
+ ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS |
+ ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 |
+ ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK;
writel(value, &pio->pioa.pdr);
writel(value, &pio->pioa.asr);
#ifdef CONFIG_RMII
- value = AT91_PMX_BA_ERXCK;
+ value = ATMEL_PMX_BA_ERXCK;
#else
- value = AT91_PMX_BA_ERXCK | AT91_PMX_BA_ECOL |
- AT91_PMX_BA_ERXDV | AT91_PMX_BA_ERX3 |
- AT91_PMX_BA_ERX2 | AT91_PMX_BA_ETXER |
- AT91_PMX_BA_ETX3 | AT91_PMX_BA_ETX2;
+ value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL |
+ ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 |
+ ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER |
+ ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2;
#endif
writel(value, &pio->piob.pdr);
writel(value, &pio->piob.bsr);
- writel(1 << AT91_ID_EMAC, &pmc->pcer);
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
/* Init Ethernet buffers */
{
emac_device *dev;
at91_emac_t *emac;
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
emac = (at91_emac_t *) netdev->iobase;
dev = (emac_device *) netdev->priv;
- writel(1 << AT91_ID_EMAC, &pmc->pcer);
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))),
cpu_to_le32(*((u32 *)netdev->enetaddr)));
struct eth_device *dev;
if (iobase == 0)
- iobase = AT91_EMAC_BASE;
+ iobase = ATMEL_BASE_EMAC;
emac = malloc(sizeof(*emac)+512);
if (emac == NULL)
return -1;
#define CONFIG_SYS_HZ 1000
/* CPU configuration */
-#define CONFIG_ARM920T
#define CONFIG_AT91RM9200
#define CONFIG_AT91RM9200EK
#define CONFIG_CPUAT91
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_AT91FAMILY
-
/*
* Memory Configuration
*/
#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
+#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
/*--------------------------------------------------------------------------*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
-#define CONFIG_EB_CPUX9K2 1 /* on an EP+CPUX9K2 Board */
-#define USE_920T_MMU 1
+#define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */
+#define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */
+#define USE_920T_MMU
-#define CONFIG_VERSION_VARIABLE 1
+#define CONFIG_VERSION_VARIABLE
#define CONFIG_IDENT_STRING " on EB+CPUx9K2"
#include <asm/arch/hardware.h> /* needed for port definitions */
#define CONFIG_SYS_I2C_INIT_BOARD
#define I2C_INIT i2c_init_board();
-#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
-#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
-#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
+#define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
+#define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
+#define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
#define I2C_SDA(bit) \
if (bit) \
- writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
+ writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \
else \
- writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
+ writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
#define I2C_SCL(bit) \
if (bit) \
- writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
+ writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \
else \
- writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
+ writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
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