85xx: Add eSDHC support for 8536 DS
authorAndy Fleming <afleming@freescale.com>
Thu, 30 Oct 2008 21:51:33 +0000 (16:51 -0500)
committerAndy Fleming <afleming@freescale.com>
Tue, 17 Feb 2009 00:07:43 +0000 (18:07 -0600)
Signed-off-by: Andy Fleming <afleming@freescale.com>
board/freescale/mpc8536ds/mpc8536ds.c
cpu/mpc85xx/cpu.c
include/asm-ppc/immap_85xx.h
include/configs/MPC8536DS.h

index bddc78f3b9feda6847b2464b91feb94d871ee179..31c1e1503af36e2d876932763b5ff5964e4a431e 100644 (file)
 
 phys_size_t fixed_sdram(void);
 
+int board_early_init_f (void)
+{
+#ifdef CONFIG_MMC
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+       setbits_be32(&gur->pmuxcr,
+                       (MPC85xx_PMUXCR_SD_DATA |
+                        MPC85xx_PMUXCR_SDHC_CD |
+                        MPC85xx_PMUXCR_SDHC_WP));
+
+#endif
+       return 0;
+}
+
 int checkboard (void)
 {
        printf ("Board: MPC8536DS, System ID: 0x%02x, "
index c9598fade4dc200f036f4e63c663cb264b694494..7c50c2fea8512484aab079a0a8af02ed69e46779 100644 (file)
@@ -31,6 +31,7 @@
 #include <command.h>
 #include <tsec.h>
 #include <netdev.h>
+#include <fsl_esdhc.h>
 #include <asm/cache.h>
 #include <asm/io.h>
 
@@ -394,5 +395,19 @@ int cpu_eth_init(bd_t *bis)
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
        tsec_standard_init(bis);
 #endif
+
        return 0;
 }
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+       return fsl_esdhc_mmc_init(bis);
+#else
+       return 0;
+#endif
+}
index ed8ddeda1cc90db85b436381ba96abd3931b0363..7b97fe0bddbcdaed87cf301742b6a1782664b4c1 100644 (file)
@@ -1614,6 +1614,9 @@ typedef struct ccsr_gur {
        uint    gpindr;         /* 0xe0050 - General-purpose input data register */
        char    res5[12];
        uint    pmuxcr;         /* 0xe0060 - Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_SD_DATA         0x80000000
+#define MPC85xx_PMUXCR_SDHC_CD         0x40000000
+#define MPC85xx_PMUXCR_SDHC_WP         0x20000000
        char    res6[12];
        uint    devdisr;        /* 0xe0070 - Device disable control */
 #define MPC85xx_DEVDISR_PCI1           0x80000000
index e379d5327d9acbb709045312bc98567cf4f4f16e..bbb448d55fdf9572092e57da5648750c69c1a96c 100644 (file)
@@ -72,6 +72,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_L2_CACHE                        /* toggle L2 cache */
 #define CONFIG_BTB                     /* toggle branch predition */
 
+#define CONFIG_BOARD_EARLY_INIT_F      1       /* Call board_pre_init */
+
 #define CONFIG_ENABLE_36BIT_PHYS       1
 
 #define CONFIG_SYS_MEMTEST_START       0x00000000      /* memtest works on */
@@ -528,6 +530,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled */
 
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /*
  * Miscellaneous configurable options
  */