dm: x86: pci: Convert coreboot to use driver model for pci

Move coreboot-x86 over to driver model for PCI.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index c9983f15889e4cdab4a55c41973c8aaba530a287..fa415dd42be6814be9a851c9c950b8baacbde6f7 100644 (file)
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -10,58 +10,27 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
 #include <pci.h>
+#include <asm/io.h>
 #include <asm/pci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
-                             struct pci_config_table *table)
-{
-       u8 secondary;
-       hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
-       hose->last_busno = max(hose->last_busno, (int)secondary);
-       pci_hose_scan_bus(hose, secondary);
-}
-
-static struct pci_config_table pci_coreboot_config_table[] = {
-       /* vendor, device, class, bus, dev, func */
-       { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
-               PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
-       {}
+static const struct dm_pci_ops pci_x86_ops = {
+       .read_config    = pci_x86_read_config,
+       .write_config   = pci_x86_write_config,
 };
 
-void board_pci_setup_hose(struct pci_controller *hose)
-{
-       hose->config_table = pci_coreboot_config_table;
-       hose->first_busno = 0;
-       hose->last_busno = 0;
-
-       /* PCI memory space */
-       pci_set_region(hose->regions + 0,
-                      CONFIG_PCI_MEM_BUS,
-                      CONFIG_PCI_MEM_PHYS,
-                      CONFIG_PCI_MEM_SIZE,
-                      PCI_REGION_MEM);
-
-       /* PCI IO space */
-       pci_set_region(hose->regions + 1,
-                      CONFIG_PCI_IO_BUS,
-                      CONFIG_PCI_IO_PHYS,
-                      CONFIG_PCI_IO_SIZE,
-                      PCI_REGION_IO);
-
-       pci_set_region(hose->regions + 2,
-                      CONFIG_PCI_PREF_BUS,
-                      CONFIG_PCI_PREF_PHYS,
-                      CONFIG_PCI_PREF_SIZE,
-                      PCI_REGION_PREFETCH);
-
-       pci_set_region(hose->regions + 3,
-                      0,
-                      0,
-                      gd->ram_size,
-                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+static const struct udevice_id pci_x86_ids[] = {
+       { .compatible = "pci-x86" },
+       { }
+};
 
-       hose->region_count = 4;
-}
+U_BOOT_DRIVER(pci_x86_drv) = {
+       .name           = "pci_x86",
+       .id             = UCLASS_PCI,
+       .of_match       = pci_x86_ids,
+       .ops            = &pci_x86_ops,
+};

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 45ada610b348e84fd2b80f463a3aaedd6d6ebc88..cdbdb6827e432831992d83a69a98d93b4502f20f 100644 (file)
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -172,6 +172,13 @@
        };
 
        pci {
+               compatible = "intel,pci-ivybridge", "pci-x86";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               u-boot,dm-pre-reloc;
+               ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
+                       0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+                       0x01000000 0x0 0x1000 0x1000 0 0xefff>;
                sata {
                        compatible = "intel,pantherpoint-ahci";
                        intel,sata-mode = "ahci";

diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 9978e92006d92068ae2b0ce0a8aa6b25fbd91415..8c04cb82802fc9b47bd84b56751e714904d6c00b 100644 (file)
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <cros_ec.h>
+#include <dm.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/pci.h>
@@ -13,6 +14,14 @@
 
 int arch_early_init_r(void)
 {
+       struct udevice *dev;
+       int ret;
+
+       /* Make sure the platform controller hub is up and running */
+       ret = uclass_get_device(UCLASS_PCH, 0, &dev);
+       if (ret)
+               return ret;
+
        if (cros_ec_board_init())
                return -1;
 

diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 3cc034a98bbb7508cb95d722036ccb57782321f9..0249172feb309feb15400bd5daf9c77db16855cb 100644 (file)
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -2,3 +2,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x01110000"
 CONFIG_X86=y
 CONFIG_TARGET_COREBOOT=y
 CONFIG_OF_CONTROL=y
+CONFIG_DM_PCI=y

diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 0b6e85037abfd488bcc58bfafb13cd82832a33a0..047ac1504dba3ba37027b494a8976437c802ecf0 100644 (file)
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -37,6 +37,7 @@ enum uclass_id {
        UCLASS_MOD_EXP,         /* RSA Mod Exp device */
        UCLASS_PCI,             /* PCI bus */
        UCLASS_PCI_GENERIC,     /* Generic PCI bus device */
+       UCLASS_PCH,             /* x86 platform controller hub */
 
        UCLASS_COUNT,
        UCLASS_INVALID = -1,