* Vince Husovsky, 7 Nov 2002: LABEL_2002_11_10_2310
authorwdenk <wdenk>
Sun, 10 Nov 2002 22:06:23 +0000 (22:06 +0000)
committerwdenk <wdenk>
Sun, 10 Nov 2002 22:06:23 +0000 (22:06 +0000)
  Add "-n" to linker options to get rid of "Not enough room for
  program headers" problem

* Patch by David Müller, 05 Nov 2002
  Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
  so we can use an already existing name

* Patch by Pierre Aubert, 05 Nov 2002
  Hardware related improvements in FDC boot code

* Patch by Holger Schurig, 5 Nov 2002:
  Make the PXA really change it's frequency

* Patch by Pierre Aubert, 05 Nov 2002
  Add support for slave serial Spartan 2 FPGAs

* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet
  drivers

17 files changed:
CHANGELOG
README
common/cmd_fdc.c
common/devices.c
common/spartan2.c
config.mk
cpu/arm920t/speed.c
cpu/mpc8xx/fec.c
cpu/mpc8xx/scc.c
cpu/xscale/start.S
include/common.h
include/configs/smdk2400.h
include/configs/smdk2410.h
include/configs/trab.h
include/spartan2.h
net/eth.c
ppc_config.mk

index 37ff332ad5885feaa3da640a1aa101a0c32b98e9..4427c35903996e5c6711897e4f54179f75a5eeb0 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,26 @@
 Changes since for U-Boot 0.1.0:
 ======================================================================
 
+* Vince Husovsky, 7 Nov 2002:
+  Add "-n" to linker options to get rid of "Not enough room for
+  program headers" problem
+
+* Patch by David Müller, 05 Nov 2002
+  Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
+  so we can use an already existing name
+
+* Patch by Pierre Aubert, 05 Nov 2002
+  Hardware relatied improvments in FDC boot code
+
+* Patch by Holger Schurig, 5 Nov 2002:
+  Make the PXA really change it's frequency
+
+* Patch by Pierre Aubert, 05 Nov 2002
+  Add support for slave serial Spartan 2 FPGAs
+
+* Fix uninitialized memory (MAC  address)  in  8xx  SCC/FEC  ethernet
+  drivers
+
 * Add support for log buffer which can be passed to Linux kernel's
   syslog mechanism; used especially for POST results.
 
diff --git a/README b/README
index 66cbd604331a7b146ca8a369959b218be40f4e6f..24ad20a980081820c46102b4438d0e11fc241f7a 100644 (file)
--- a/README
+++ b/README
@@ -266,6 +266,11 @@ Example: For a TQM823L module, all configuration settings are in
 "include/configs/TQM823L.h".
 
 
+Many of the options are named exactly as the corresponding Linux
+kernel configuration options. The intention is to make it easier to
+build a config tool - later.
+
+
 The following options need to be configured:
 
 - CPU Type:    Define exactly one of
@@ -1523,10 +1528,6 @@ Note2: you must edit your u-boot.lds file to reflect this
 configuration.
 
 
-Many of the options are named exactly as the corresponding Linux
-kernel configuration options. The intention is to make it easier to
-build a config tool - later.
-
 Low Level (hardware related) configuration options:
 
 - CFG_CACHELINE_SIZE:
@@ -1538,6 +1539,32 @@ Low Level (hardware related) configuration options:
                to be able to adjust the position of the IMMR
                register after a reset.
 
+- Floppy Disk Support:
+               CFG_FDC_DRIVE_NUMBER
+
+               the default drive number (default value 0)
+
+               CFG_ISA_IO_STRIDE
+
+               defines the spacing between fdc chipset registers
+               (default value 1)
+
+               CFG_ISA_IO_OFFSET
+
+                defines the offset of register from address. It
+                depends on which part of the data bus is connected to
+                the fdc chipset. (default value 0)
+
+                If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and
+                CFG_FDC_DRIVE_NUMBER are undefined, they take their
+                default value.
+
+                if CFG_FDC_HW_INIT is defined, then the function
+                fdc_hw_init() is called at the beginning of the FDC
+                setup. fdc_hw_init() must be provided by the board
+                source code. It is used to make hardware dependant
+                initializations.
+
 - CFG_IMMR:    Physical address of the Internal Memory Mapped
                Register; DO NOT CHANGE! (11-4)
                [MPC8xx systems only]
index 712c14b57c7837fe85786fb2f31b56265f868cd0..8e6b7350c230d123fb6e69e5704256402b382849 100644 (file)
@@ -173,19 +173,35 @@ const static FD_GEO_STRUCT floppy_type[2] = {
 
 static FDC_COMMAND_STRUCT cmd; /* global command struct */
 
+/* If the boot drive number is undefined, we assume it's drive 0             */
+#ifndef CFG_FDC_DRIVE_NUMBER
+#define CFG_FDC_DRIVE_NUMBER 0
+#endif
+
+/* Hardware access */
+#ifndef CFG_ISA_IO_STRIDE
+#define CFG_ISA_IO_STRIDE 1
+#endif
+
+#ifndef CFG_ISA_IO_OFFSET
+#define CFG_ISA_IO_OFFSET 0
+#endif
+
+
 /* Supporting Functions */
 /* reads a Register of the FDC */
 unsigned char read_fdc_reg(unsigned int addr)
 {
-       volatile unsigned char *val = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS | addr);
-       return val[0];
+       volatile unsigned char *val = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS + (addr * CFG_ISA_IO_STRIDE) + CFG_ISA_IO_OFFSET);
+        
+       return val [0];
 }
 
 /* writes a Register of the FDC */
 void write_fdc_reg(unsigned int addr, unsigned char val)
 {
-               volatile unsigned char *tmp = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS | addr);
-               tmp[0]=val;
+        volatile unsigned char *tmp = (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS + (addr * CFG_ISA_IO_STRIDE) + CFG_ISA_IO_OFFSET);
+       tmp[0]=val;
 }
 
 /* waits for an interrupt (polling) */
@@ -263,7 +279,8 @@ int fdc_issue_cmd(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
        head = sect / pFG->sect; /* head nr */
        sect =  sect % pFG->sect; /* remaining blocks */
        sect++; /* sectors are 1 based */
-       PRINTF("Track %ld, Head %ld, Sector %ld, Drive %d (blnr %ld)\n",track,head,sect,pCMD->drive,pCMD->blnr);
+       PRINTF("Cmd 0x%02x Track %ld, Head %ld, Sector %ld, Drive %d (blnr %ld)\n",pCMD->cmd[0],track,head,sect,pCMD->drive,pCMD->blnr);
+
        if(head|=0) { /* max heads = 2 */
                pCMD->cmd[DRIVE]=pCMD->drive | 0x04; /* head 1 */
                pCMD->cmd[HEAD]=(unsigned char) head; /* head register */
@@ -538,20 +555,20 @@ int fdc_check_drive(FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
                select_fdc_drive(pCMD);
                pCMD->blnr=0; /* set to the 1st block */
                if(fdc_recalibrate(pCMD,pFG)==FALSE)
-                       break;
+                       continue;
                if((pCMD->result[STATUS_0]&0x10)==0x10)
-                       break;
+                       continue;
                /* ok drive connected check for disk */
                state|=(1<<drives);
                pCMD->blnr=pFG->size; /* set to the last block */
                if(fdc_seek(pCMD,pFG)==FALSE)
-                       break;
+                       continue;
                pCMD->blnr=0; /* set to the 1st block */
                if(fdc_recalibrate(pCMD,pFG)==FALSE)
-                       break;
+                       continue;
                pCMD->cmd[COMMAND]=FDC_CMD_READ_ID;
                if(fdc_issue_cmd(pCMD,pFG)==FALSE)
-                       break;
+                       continue;
                state|=(0x10<<drives);
        }
        stop_fdc_drive(pCMD);
@@ -575,12 +592,16 @@ int fdc_setup(FDC_COMMAND_STRUCT *pCMD,   FD_GEO_STRUCT *pFG)
 {
 
        int i;
+
+#ifdef CFG_FDC_HW_INIT
+        fdc_hw_init ();
+#endif
        /* first, we reset the FDC via the DOR */
        write_fdc_reg(FDC_DOR,0x00);
        for(i=0; i<255; i++) /* then we wait some time */
                udelay(500);
        /* then, we clear the reset in the DOR */
-       pCMD->drive=0;
+       pCMD->drive=CFG_FDC_DRIVE_NUMBER;
        select_fdc_drive(pCMD);
        /* initialize the CCR */
        write_fdc_reg(FDC_CCR,pFG->rate);
@@ -602,7 +623,7 @@ int fdc_setup(FDC_COMMAND_STRUCT *pCMD,     FD_GEO_STRUCT *pFG)
        }
        /* assuming drive 0 for rest of configuration
         * issue the configure command */
-       pCMD->drive=0;
+       pCMD->drive=CFG_FDC_DRIVE_NUMBER;
        select_fdc_drive(pCMD);
        pCMD->cmd[COMMAND]=FDC_CMD_CONFIGURE;
        if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
@@ -641,11 +662,11 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        switch (argc) {
        case 1:
                addr = CFG_LOAD_ADDR;
-               boot_drive=0; /* default boot from drive 0 */
+               boot_drive=CFG_FDC_DRIVE_NUMBER; 
                break;
        case 2:
                addr = simple_strtoul(argv[1], NULL, 16);
-               boot_drive=0; /* default boot from drive 0 */
+               boot_drive=CFG_FDC_DRIVE_NUMBER;
                break;
        case 3:
                addr = simple_strtoul(argv[1], NULL, 16);
index 8207f834fee014ac4d3a90d0a8c87a31ceaf73d5..7489eac41eccae4904f08b45ffe50b20604e9cf8 100644 (file)
 #include <stdarg.h>
 #include <malloc.h>
 #include <devices.h>
+#ifdef CONFIG_LOGBUFFER
+#include <logbuff.h>
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
 #include <i2c.h>
+#endif
 
 list_t devlist = 0;
 device_t *stdio_devices[] = { NULL, NULL, NULL };
index 9ac1e137786f05820cb9e00f228bee50b6bbaa75..dcda0c4948054a241d615c8be19740f54fa54901 100644 (file)
@@ -35,7 +35,7 @@
 #endif
 
 #undef CFG_FPGA_CHECK_BUSY
-#define CFG_FPGA_PROG_FEEDBACK
+#undef CFG_FPGA_PROG_FEEDBACK
 
 /* Note: The assumption is that we cannot possibly run fast enough to
  * overrun the device (the Slave Parallel mode can free run at 50MHz).
@@ -438,14 +438,150 @@ static int Spartan2_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
 
 static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
 {
-       printf ("%s: Slave Serial Loading is still unsupported\n",
-                       __FUNCTION__);
-       return FPGA_FAIL;
+        int ret_val = FPGA_FAIL;       /* assume the worst */
+       Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
+        int i;
+        char  val;
+        
+       PRINTF ("%s: start with interface functions @ 0x%p\n",
+                       __FUNCTION__, fn);
+
+       if (fn) {
+               size_t bytecount = 0;
+               unsigned char *data = (unsigned char *) buf;
+               int cookie = desc->cookie;      /* make a local copy */
+               unsigned long ts;               /* timestamp */
+
+               PRINTF ("%s: Function Table:\n"
+                               "ptr:\t0x%p\n"
+                               "struct: 0x%p\n"
+                               "pgm:\t0x%p\n"
+                               "init:\t0x%p\n"
+                               "clk:\t0x%p\n"
+                               "wr:\t0x%p\n"
+                               "done:\t0x%p\n\n",
+                               __FUNCTION__, &fn, fn, fn->pgm, fn->init, 
+                               fn->clk, fn->wr, fn->done); 
+#ifdef CFG_FPGA_PROG_FEEDBACK
+               printf ("Loading FPGA Device %d...\n", cookie);
+#endif
+
+               /*
+                * Run the pre configuration function if there is one.
+                */
+               if (*fn->pre) {
+                       (*fn->pre) (cookie);
+               }
+
+               /* Establish the initial state */
+               (*fn->pgm) (TRUE, TRUE, cookie);        /* Assert the program, commit */
+
+                /* Wait for INIT state (init low)                            */
+               ts = get_timer (0);             /* get current time */
+               do {
+                       CONFIG_FPGA_DELAY ();
+                       if (get_timer (ts) > CFG_FPGA_WAIT) {   /* check the time */
+                               puts ("** Timeout waiting for INIT to start.\n");
+                               return FPGA_FAIL;
+                       }
+               } while (!(*fn->init) (cookie));
+                
+               /* Get ready for the burn */
+               CONFIG_FPGA_DELAY ();
+               (*fn->pgm) (FALSE, TRUE, cookie);       /* Deassert the program, commit */
+
+               ts = get_timer (0);             /* get current time */
+               /* Now wait for INIT to go high */
+               do {
+                       CONFIG_FPGA_DELAY ();
+                       if (get_timer (ts) > CFG_FPGA_WAIT) {   /* check the time */
+                               puts ("** Timeout waiting for INIT to clear.\n");
+                               return FPGA_FAIL;
+                       }
+               } while ((*fn->init) (cookie));
+
+               /* Load the data */
+               while (bytecount < bsize) {
+                    
+                        /* Xilinx detects an error if INIT goes low (active)
+                           while DONE is low (inactive) */
+                        if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
+                                puts ("** CRC error during FPGA load.\n");
+                                return (FPGA_FAIL);
+                        }
+                        val = data [bytecount ++];
+                        i = 8;
+                        do {
+                                /* Deassert the clock */
+                                (*fn->clk) (FALSE, TRUE, cookie);
+                                CONFIG_FPGA_DELAY ();
+                                /* Write data */
+                                (*fn->wr) ((val < 0), TRUE, cookie);
+                                CONFIG_FPGA_DELAY ();
+                                /* Assert the clock */
+                                (*fn->clk) (TRUE, TRUE, cookie);
+                                CONFIG_FPGA_DELAY ();
+                                val <<= 1;
+                                i --;
+                        } while (i > 0);
+                        
+#ifdef CFG_FPGA_PROG_FEEDBACK
+                       if (bytecount % (bsize / 40) == 0)
+                               putc ('.');             /* let them know we are alive */
+#endif
+               }
+
+               CONFIG_FPGA_DELAY ();
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+               putc ('\n');                    /* terminate the dotted line */
+#endif
+
+               /* now check for done signal */
+               ts = get_timer (0);             /* get current time */
+               ret_val = FPGA_SUCCESS;
+                (*fn->wr) (TRUE, TRUE, cookie);
+
+               while (! (*fn->done) (cookie)) {
+                       /* XXX - we should have a check in here somewhere to
+                        * make sure we aren't busy forever... */
+
+                       CONFIG_FPGA_DELAY ();
+                       (*fn->clk) (FALSE, TRUE, cookie);       /* Deassert the clock pin */
+                       CONFIG_FPGA_DELAY ();
+                       (*fn->clk) (TRUE, TRUE, cookie);        /* Assert the clock pin */
+
+                        putc ('*');
+                        
+                       if (get_timer (ts) > CFG_FPGA_WAIT) {   /* check the time */
+                               puts ("** Timeout waiting for DONE to clear.\n");
+                               ret_val = FPGA_FAIL;
+                               break;
+                       }
+               }
+               putc ('\n');                    /* terminate the dotted line */
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+               if (ret_val == FPGA_SUCCESS) {
+                       puts ("Done.\n");
+               }
+               else {
+                       puts ("Fail.\n");
+               }
+#endif
+
+       } else {
+               printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+       }
+
+       return ret_val;
 }
 
 static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 {
-       printf ("%s: Slave Serial Dumping is still unsupported\n",
+        /* Readback is only available through the Slave Parallel and         */
+        /* boundary-scan interfaces.                                         */
+       printf ("%s: Slave Serial Dumping is unavailable\n",
                        __FUNCTION__);
        return FPGA_FAIL;
 }
@@ -453,12 +589,59 @@ static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
 {
        int ret_val = FPGA_FAIL;        /* assume the worst */
-       Xilinx_Spartan2_Slave_Serial_fns *fn =
+       Xilinx_Spartan2_Slave_Serial_fns *fn_r, *fn =
                        (Xilinx_Spartan2_Slave_Serial_fns *) (desc->iface_fns);
 
        if (fn) {
-               printf ("%s: Slave Serial Loading is still unsupported\n",
-                               __FUNCTION__);
+               ulong addr;
+
+               /* Get the relocated table address */
+               addr = (ulong) fn + reloc_offset;
+               fn_r = (Xilinx_Spartan2_Slave_Serial_fns *) addr;
+
+               if (!fn_r->relocated) {
+
+                       if (memcmp (fn_r, fn,
+                                               sizeof (Xilinx_Spartan2_Slave_Serial_fns))
+                               == 0) {
+                               /* good copy of the table, fix the descriptor pointer */
+                               desc->iface_fns = fn_r;
+                       } else {
+                               PRINTF ("%s: Invalid function table at 0x%p\n",
+                                               __FUNCTION__, fn_r);
+                               return FPGA_FAIL;
+                       }
+
+                       PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
+                                       desc);
+
+                       addr = (ulong) (fn->pre) + reloc_offset;
+                       fn_r->pre = (Xilinx_pre_fn) addr;
+
+                       addr = (ulong) (fn->pgm) + reloc_offset;
+                       fn_r->pgm = (Xilinx_pgm_fn) addr;
+
+                       addr = (ulong) (fn->init) + reloc_offset;
+                       fn_r->init = (Xilinx_init_fn) addr;
+
+                       addr = (ulong) (fn->done) + reloc_offset;
+                       fn_r->done = (Xilinx_done_fn) addr;
+
+                       addr = (ulong) (fn->clk) + reloc_offset;
+                       fn_r->clk = (Xilinx_clk_fn) addr;
+
+                       addr = (ulong) (fn->wr) + reloc_offset;
+                       fn_r->wr = (Xilinx_wr_fn) addr;
+
+                       fn_r->relocated = TRUE;
+
+               } else {
+                       /* this table has already been moved */
+                       /* XXX - should check to see if the descriptor is correct */
+                       desc->iface_fns = fn_r;
+               }
+
+               ret_val = FPGA_SUCCESS;
        } else {
                printf ("%s: NULL Interface function table!\n", __FUNCTION__);
        }
index ef3c7037edf4c4bc053e7938fa6be8f7ec606c43..f0f8aa86b69791abe2c854d52b9f59ed83c15a30 100644 (file)
--- a/config.mk
+++ b/config.mk
@@ -116,7 +116,7 @@ endif
 AFLAGS_DEBUG := -Wa,-gstabs
 AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
 
-LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
+LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
 
 # Location of a usable BFD library, where we define "usable" as
 # "built for ${HOST}, supports ${TARGET}".  Sensible values are
index 1ee0c1a15aeffd2846e2b8046fad1dd1cbb427ca..4942727272dd7f091c5485c3ad3e9175ff014051 100644 (file)
@@ -42,7 +42,7 @@
 /* ------------------------------------------------------------------------- */
 /* NOTE: This describes the proper use of this file.
  *
- * CONFIG_PLL_INPUT_FREQ should be defined as the input frequency of the PLL.
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  *
  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  * the specified bus in HZ.
@@ -64,7 +64,7 @@ static ulong get_PLLCLK(int pllreg)
     p = ((r & 0x003F0) >> 4) + 2;
     s = r & 0x3;
 
-    return((CONFIG_PLL_INPUT_FREQ * m) / (p << s));
+    return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
 }
 
 /* return FCLK frequency */
index d43dcaafdb612ea308e9e6c9016b13ff270847b5..d2e84089976b0dab3eb142a1a10c411ee5c7c78e 100644 (file)
@@ -76,6 +76,7 @@ int fec_initialize(bd_t *bis)
        struct eth_device* dev;
 
        dev = (struct eth_device*) malloc(sizeof *dev);
+       memset(dev, 0, sizeof *dev);
 
        sprintf(dev->name, "FEC ETHERNET");
        dev->iobase = 0;
index fed03f77e1b48fd3422ef8f0e4d5ab58c5e2550d..4ff23c3b68427026ba7a4a7a00986006f65971fa 100644 (file)
@@ -75,6 +75,7 @@ int scc_initialize(bd_t *bis)
        struct eth_device* dev;
 
        dev = (struct eth_device*) malloc(sizeof *dev);
+       memset(dev, 0, sizeof *dev);
 
        sprintf(dev->name, "SCC ETHERNET");
        dev->iobase = 0;
index cc24c30bfa40d69f770bbbebe6705064f61393d7..e63fece8b219150166131655133eda0b98876bb1 100644 (file)
@@ -175,10 +175,11 @@ OSTIMER_BASE:     .word   0x40a00000
 #define OIER   0x1C
 
        /* Clock Manager Registers                                          */
+#ifdef CFG_CPUSPEED
 CC_BASE:       .word   0x41300000
 #define CCCR   0x00
 cpuspeed:      .word   CFG_CPUSPEED
-
+#endif
        /* RS: ???                                                          */
        .macro CPWAIT
        mrc  p15,0,r0,c2,c0,0
@@ -194,10 +195,14 @@ cpu_init_crit:
        mov     r1, #0x00
        str     r1, [r0, #ICMR]
 
+#ifdef CFG_CPUSPEED
        /* set clock speed */
        ldr     r0, CC_BASE
        ldr     r1, cpuspeed
        str     r1, [r0, #CCCR]
+       mov     r0, #3
+       mcr     p14, 0, r0, c6, c0, 0
+#endif
 
        /*
         * before relocating, we have to setup RAM timing
index 49ab97ce94aee7f9932f569205a97f19837d3bd5..21101f105a638617031d6d425b0ddeb6c8f25884 100644 (file)
@@ -156,6 +156,7 @@ int misc_init_r   (void);
 
 /* $(BOARD)/$(BOARD).c */
 void   reset_phy     (void);
+void    fdc_hw_init   (void);
 
 /* $(BOARD)/eeprom.c */
 void eeprom_init  (void);
index 543dfb071972c0eadfd7c880a26dba078973e07e..c60e74607cfeb74a9dc1c4be63e31de1377fc5a2 100644 (file)
@@ -43,7 +43,7 @@
 #define CONFIG_SMDK2400                1       /* on an SAMSUNG SMDK2400 Board */
 
 /* input clock of PLL */
-#define CONFIG_PLL_INPUT_FREQ  12000000 /* SMDK2400 has 12 MHz input clock */
+#define CONFIG_SYS_CLK_FREQ    12000000 /* SMDK2400 has 12 MHz input clock */
 #undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff  */
 
 #define CONFIG_CMDLINE_TAG      1      /* enable passing of ATAGs      */
index 766b8feece0eee33e6a128f7fc886b87aa825a11..65dd3fec25e124692477fbadbcdbb8a931e5ceab 100644 (file)
@@ -44,7 +44,7 @@
 #define CONFIG_SMDK2410                1       /* on a SAMSUNG SMDK2410 Board  */
 
 /* input clock of PLL */
-#define CONFIG_PLL_INPUT_FREQ  12000000/* the SMDK2410 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ    12000000/* the SMDK2410 has 12MHz input clock */
 
 
 #define USE_920T_MMU           1
index b7a27c692313ee0006771afd80fc483ac1b48811..c6144119e615ba1c984d634916c7a111db4d360f 100644 (file)
@@ -42,7 +42,7 @@
 #undef CONFIG_TRAB_50MHZ               /* run the CPU at 50 MHz */
 
 /* input clock of PLL */
-#define CONFIG_PLL_INPUT_FREQ  12000000 /* TRAB has 12 MHz input clock */
+#define CONFIG_SYS_CLK_FREQ    12000000 /* TRAB has 12 MHz input clock */
 
 #undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff */
 
index 42806e3ae2c06696e3e25b3fb2d06899f458360e..a04aacae4148c6e7a6f904b307a2303d29d63722 100644 (file)
@@ -52,10 +52,12 @@ typedef struct {
 
 /* Slave Serial Implementation function table */
 typedef struct {
+       Xilinx_pre_fn   pre;
        Xilinx_pgm_fn   pgm;
        Xilinx_clk_fn   clk;
-       Xilinx_rdata_fn rdata;
-       Xilinx_wdata_fn wdata;
+       Xilinx_init_fn  init;
+       Xilinx_done_fn  done;
+       Xilinx_wr_fn    wr;
        int             relocated;
 } Xilinx_Spartan2_Slave_Serial_fns;
 
index 3b06440ca977ffd3d8135ab59c3072c2d8424522..c2dbb934279403c9d50b172f0812b0b7d622963e 100644 (file)
--- a/net/eth.c
+++ b/net/eth.c
@@ -229,7 +229,6 @@ int eth_init(bd_t *bis)
                if (eth_current->init(eth_current, bis)) {
                        eth_current->state = ETH_STATE_ACTIVE;
 
-                       printf("%s configured\n", eth_current->name);
                        return 1;
                }
 
index a5a5bdd284cc0c98ac99289e1084ee08cdb18edd..31993bd9170d6498871779fcc76fe1c6cbc895a1 100644 (file)
@@ -22,3 +22,4 @@
 #
 
 PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__
+PLATFORM_LDFLAGS  += -n