dm: arm: imx: migrate cx9020 to CONFIG_DM_MMC
authorPatrick Bruenn <p.bruenn@beckhoff.com>
Thu, 3 Jan 2019 06:54:34 +0000 (07:54 +0100)
committerStefano Babic <sbabic@denx.de>
Mon, 28 Jan 2019 19:55:46 +0000 (20:55 +0100)
Enable esdhc1/2 device nodes for cx9020 and build with CONFIG_DM_MMC=y

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
arch/arm/dts/imx53-cx9020.dts
configs/mx53cx9020_defconfig

index c2e7d86c1b88f4ef41854f5205188791cf1b1f90..36ceae36aa9091558a33ab27c81884ad92eb3868 100644 (file)
                                MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS     0x80000000
                                MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD      0x80000000
 
-                               MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
-                               MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
-                               MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
-                               MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
-                               MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
-                               MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
-
-                               MX53_PAD_SD2_DATA0__ESDHC2_DAT0         0x1d5
-                               MX53_PAD_SD2_DATA1__ESDHC2_DAT1         0x1d5
-                               MX53_PAD_SD2_DATA2__ESDHC2_DAT2         0x1d5
-                               MX53_PAD_SD2_DATA3__ESDHC2_DAT3         0x1d5
-                               MX53_PAD_SD2_CMD__ESDHC2_CMD            0x1d5
-                               MX53_PAD_SD2_CLK__ESDHC2_CLK            0x1d5
-
                                MX53_PAD_FEC_MDC__FEC_MDC               0x4
                                MX53_PAD_FEC_MDIO__FEC_MDIO             0x1fc
                                MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x180
                        >;
                };
 
+               pinctrl_esdhc1: esdhc1grp {
+                       fsl,pins = <
+                               MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
+                               MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
+                               MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
+                               MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
+                               MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
+                               MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
+                       >;
+               };
+
+               pinctrl_esdhc2: esdhc2grp {
+                       fsl,pins = <
+                               MX53_PAD_SD2_DATA0__ESDHC2_DAT0         0x1d5
+                               MX53_PAD_SD2_DATA1__ESDHC2_DAT1         0x1d5
+                               MX53_PAD_SD2_DATA2__ESDHC2_DAT2         0x1d5
+                               MX53_PAD_SD2_DATA3__ESDHC2_DAT3         0x1d5
+                               MX53_PAD_SD2_CMD__ESDHC2_CMD            0x1d5
+                               MX53_PAD_SD2_CLK__ESDHC2_CLK            0x1d5
+                       >;
+               };
+
                pinctrl_uart2: uart2grp {
                        fsl,pins = <
                                MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
        status = "okay";
 };
 
+&esdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esdhc1>;
+       cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+       bus-width = <4>;
+       status = "okay";
+};
+
+&esdhc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esdhc2>;
+       cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+       bus-width = <4>;
+       status = "okay";
+};
+
 &fec {
        pinctrl-names = "default";
        phy-mode = "rmii";
index 3cff52031a0e06afb9d5cfedbd04560af1f2a9c5..ddd65e8ee153d392adc94a670bea93d9981c59ec 100644 (file)
@@ -19,6 +19,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM_MMC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020"
 CONFIG_ENV_IS_IN_MMC=y