config SYS_ARCH
default "sh"
+config CPU_SH2
+ bool
+
+config CPU_SH2A
+ bool
+ select CPU_SH2
+
+config CPU_SH3
+ bool
+
+config CPU_SH4
+ bool
+
+config CPU_SH4A
+ bool
+ select CPU_SH4
+
choice
prompt "Target select"
config TARGET_RSK7203
bool "RSK+ 7203"
+ select CPU_SH2A
config TARGET_RSK7264
bool "RSK2+SH7264"
+ select CPU_SH2A
config TARGET_RSK7269
bool "RSK2+SH7269"
+ select CPU_SH2A
config TARGET_MPR2
bool "Magic Panel Release 2 board"
+ select CPU_SH3
config TARGET_MS7720SE
bool "Support ms7720se"
+ select CPU_SH3
config TARGET_SHMIN
bool "SHMIN"
+ select CPU_SH3
config TARGET_ESPT
bool "Data Technology ESPT-GIGA board"
+ select CPU_SH4
config TARGET_MS7722SE
bool "SolutionEngine 7722"
+ select CPU_SH4
config TARGET_MS7750SE
bool "SolutionEngine 7750"
+ select CPU_SH4
config TARGET_AP_SH4A_4A
bool "ALPHAPROJECT AP-SH4A-4A"
+ select CPU_SH4
config TARGET_AP325RXA
bool "Renesas AP-325RXA"
+ select CPU_SH4
config TARGET_ECOVEC
bool "EcoVec"
+ select CPU_SH4
config TARGET_MIGOR
bool "Migo-R"
+ select CPU_SH4
config TARGET_R0P7734
bool "Support r0p7734"
+ select CPU_SH4
config TARGET_R2DPLUS
bool "Renesas R2D-PLUS"
+ select CPU_SH4
config TARGET_R7780MP
bool "R7780MP board"
+ select CPU_SH4
config TARGET_SH7752EVB
bool "SH7752EVB"
+ select CPU_SH4
config TARGET_SH7753EVB
bool "SH7753EVB"
+ select CPU_SH4
config TARGET_SH7757LCR
bool "SH7757LCR"
+ select CPU_SH4
config TARGET_SH7763RDP
bool "SH7763RDP"
+ select CPU_SH4
config TARGET_SH7785LCR
bool "SH7785LCR"
+ select CPU_SH4
endchoice
#
ENDIANNESS += -EB
-ifdef CONFIG_SH2A
+ifdef CONFIG_CPU_SH2A
PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb
else # SH2
PLATFORM_CPPFLAGS += -m3e -mb
endif
-PLATFORM_CPPFLAGS += -DCONFIG_SH2 $(call cc-option,-mno-fdpic)
+PLATFORM_CPPFLAGS += $(call cc-option,-mno-fdpic)
PLATFORM_LDFLAGS += $(ENDIANNESS)
# SPDX-License-Identifier: GPL-2.0+
#
#
-PLATFORM_CPPFLAGS += -DCONFIG_SH3 -m3
+PLATFORM_CPPFLAGS += -m3
# SPDX-License-Identifier: GPL-2.0+
#
#
-PLATFORM_CPPFLAGS += -DCONFIG_SH4 -m4-nofpu
+PLATFORM_CPPFLAGS += -m4-nofpu
#ifndef __ASM_SH_CACHE_H
#define __ASM_SH_CACHE_H
-#if defined(CONFIG_SH4)
+#if defined(CONFIG_CPU_SH4)
int cache_control(unsigned int cmd);
*/
#define ARCH_DMA_MINALIGN 32
-#endif /* CONFIG_SH4 */
+#endif /* CONFIG_CPU_SH4 */
/*
* Use the L1 data cache line size value for the minimum DMA buffer alignment
#ifndef _ASM_SH_PROCESSOR_H_
#define _ASM_SH_PROCESSOR_H_
-#if defined(CONFIG_SH2)
+#if defined(CONFIG_CPU_SH2)
# include <asm/cpu_sh2.h>
-#elif defined(CONFIG_SH3)
+#elif defined(CONFIG_CPU_SH3)
# include <asm/cpu_sh3.h>
-#elif defined(CONFIG_SH4)
+#elif defined(CONFIG_CPU_SH4)
# include <asm/cpu_sh4.h>
#endif
#endif
obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
-ifeq ($(CONFIG_SH2),y)
+ifeq ($(CONFIG_CPU_SH2),y)
obj-y += time_sh2.o
else
obj-y += time.o
SCI_OUT(sci_size, sci_offset, value);\
}
-#if defined(CONFIG_SH3) || \
+#if defined(CONFIG_CPU_SH3) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372) || \
#define __RSK7203_H
#undef DEBUG
-#define CONFIG_SH2A 1
#define CONFIG_CPU_SH7203 1
#define CONFIG_RSK7203 1
#define __RSK7264_H
#undef DEBUG
-#define CONFIG_SH2A 1
#define CONFIG_CPU_SH7264 1
#define CONFIG_RSK7264 1
#define __RSK7269_H
#undef DEBUG
-#define CONFIG_SH2A 1
#define CONFIG_CPU_SH7269 1
#define CONFIG_RSK7269 1
#include <asm/types.h>
-#if defined(CONFIG_SH3)
+#if defined(CONFIG_CPU_SH3)
struct tmu_regs {
u8 tocr;
u8 reserved0;
u16 reserved4;
u32 tcpr2;
};
-#endif /* CONFIG_SH3 */
+#endif /* CONFIG_CPU_SH3 */
-#if defined(CONFIG_SH4) || defined(CONFIG_RMOBILE)
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_RMOBILE)
struct tmu_regs {
u32 reserved;
u8 tstr;
u16 tcr2;
u16 reserved5;
};
-#endif /* CONFIG_SH4 */
+#endif /* CONFIG_CPU_SH4 */
static inline unsigned long get_tmu0_clk_rate(void)
{