powerpc: p1022ds: Enable P1022DS to boot from SD Card with SPL
authorYing Zhang <b40530@freescale.com>
Fri, 16 Aug 2013 07:16:12 +0000 (15:16 +0800)
committerYork Sun <yorksun@freescale.com>
Tue, 20 Aug 2013 16:47:38 +0000 (09:47 -0700)
Enable p1022ds to start from eSDHC with SPL.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
README
board/freescale/common/Makefile
board/freescale/p1022ds/Makefile
board/freescale/p1022ds/spl.c [new file with mode: 0644]
board/freescale/p1022ds/tlb.c
include/configs/P1022DS.h

diff --git a/README b/README
index 301d1a95cdd9575b520c4aad7a410ca6fdf38084..18f5233acecf535d6792b4e37ffab9f924b2a2d8 100644 (file)
--- a/README
+++ b/README
@@ -3094,6 +3094,10 @@ FIT uImage format:
                Set for the SPL on PPC mpc8xxx targets, support for
                arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
 
+               CONFIG_SPL_COMMON_INIT_DDR
+               Set for common ddr init with serial presence detect in
+               SPL binary.
+
                CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
                CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
                CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
index 457d1adbdc1c902e98d1aa8b90ff5babec654a4d..f9550c48ceba642e6db2707615d962ffad80158c 100644 (file)
@@ -45,9 +45,7 @@ COBJS-$(CONFIG_MPC8555CDS)    += cds_pci_ft.o
 
 COBJS-$(CONFIG_MPC8536DS)      += ics307_clk.o
 COBJS-$(CONFIG_MPC8572DS)      += ics307_clk.o
-ifndef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_P1022DS)                += ics307_clk.o
-endif
 COBJS-$(CONFIG_P2020DS)                += ics307_clk.o
 COBJS-$(CONFIG_P3041DS)                += ics307_clk.o
 COBJS-$(CONFIG_P4080DS)                += ics307_clk.o
index cfc05f71243c1979d986f7355d4f4d46542e1409..3bc4f4325f0593eeb07f3fa6a017f91794f55629 100644 (file)
@@ -21,6 +21,9 @@ ifdef MINIMAL
 COBJS-y        += spl_minimal.o tlb.o law.o
 
 else
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl.o
+endif
 COBJS-y        += $(BOARD).o
 COBJS-y        += ddr.o
 COBJS-y        += law.o
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
new file mode 100644 (file)
index 0000000..71a0f85
--- /dev/null
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include "../common/ngpixis.h"
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+       66666000, 7499900, 83332500, 8999900,
+       99999000, 11111000, 12499800, 13333200
+};
+
+ulong get_effective_memsize(void)
+{
+       return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+       int px_spd;
+       u32 plat_ratio, sys_clk, bus_clk;
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+       console_init_f();
+
+       /* Set pmuxcr to allow both i2c1 and i2c2 */
+       setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+       setbits_be32(&gur->pmuxcr,
+                    in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+       /* Read back the register to synchronize the write. */
+       in_be32(&gur->pmuxcr);
+
+       /* initialize selected port with appropriate baud rate */
+       px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
+       sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
+       plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+       bus_clk = sys_clk * plat_ratio / 2;
+
+       NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+                    bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+       puts("\nSD boot...\n");
+#endif
+
+       /* copy code to RAM and jump to it - this should not return */
+       /* NOTE - code has to be copied out of NAND buffer before
+        * other blocks can be read.
+        */
+       relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+       /* Pointer is writable since we allocated a register for it */
+       gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+       bd_t *bd;
+
+       memset(gd, 0, sizeof(gd_t));
+       bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+       memset(bd, 0, sizeof(bd_t));
+       gd->bd = bd;
+       bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+       bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+       probecpu();
+       get_clocks();
+       mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+                       CONFIG_SPL_RELOC_MALLOC_SIZE);
+       env_init();
+#ifdef CONFIG_SPL_MMC_BOOT
+       mmc_initialize(bd);
+#endif
+       /* relocate environment function pointers etc. */
+       env_relocate();
+
+       i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+       gd->ram_size = initdram(0);
+       puts("Second program loader running in sram...\n");
+
+#ifdef CONFIG_SPL_MMC_BOOT
+       mmc_boot();
+#endif
+}
index 2eef6adbfa86717107571d319ab1a58705f1cb82..e7ae2e25b224acf62009cc39760c2b4e36ea5f30 100644 (file)
@@ -71,25 +71,32 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 7, BOOKE_PAGESZ_4K, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#if defined(CONFIG_SYS_RAMBOOT) || \
+       (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
        /* **** - eSDHC/eSPI/NAND boot */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
-                       0, 8, BOOKE_PAGESZ_1G, 1),
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 8, BOOKE_PAGESZ_1G, 1),
        /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-                       CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
-                       0, 9, BOOKE_PAGESZ_1G, 1),
+                     CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 
 #ifdef CONFIG_SYS_NAND_BASE
        /* *I*G - NAND */
        SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 10, BOOKE_PAGESZ_16K, 1),
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 10, BOOKE_PAGESZ_16K, 1),
 #endif
 
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+       /* *I*G - L2SRAM */
+       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+                     0, 11, BOOKE_PAGESZ_256K, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
index 5ca7f0779749e3feea703b574e9b94bfca5f70c2..6db0c2700b68920c27850a1fce39c43d3a52fbd3 100644 (file)
 #endif
 
 #ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE           0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS    0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE           0x11001000
+#define CONFIG_SPL_TEXT_BASE           0xf8f81000
+#define CONFIG_SPL_PAD_TO              0x18000
+#define CONFIG_SPL_MAX_SIZE            (96 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE     (512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST      (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START    (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS     (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT            "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
 #endif
 
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN          (10 * 1024 * 1024)
 
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD)
+#define CONFIG_SYS_INIT_L2_ADDR        0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS   CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE             (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE     0xf8f81000
+#define CONFIG_SPL_RELOC_STACK         (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE    (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE   (96 << 10)
+#define CONFIG_SPL_GD_ADDR             (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#endif
+#endif
+
 /*
  * Serial Port
  */
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK         get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 
 #define CONFIG_ENV_SIZE                0x2000  /* 8KB */
 #define CONFIG_ENV_OFFSET      0x100000        /* 1MB */
 #define CONFIG_ENV_SECT_SIZE   0x10000
-#elif defined(CONFIG_RAMBOOT_SDCARD)
+#elif defined(CONFIG_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_ENV_SIZE                0x2000
 #define CONFIG_SYS_MMC_ENV_DEV 0
 #elif defined(CONFIG_NAND)