ti: armv7: Move SPL SDRAM init to the right place, drop unused CONFIG_SPL_STACK
authorSimon Glass <sjg@chromium.org>
Tue, 3 Mar 2015 15:03:02 +0000 (08:03 -0700)
committerTom Rini <trini@konsulko.com>
Wed, 4 Mar 2015 19:55:04 +0000 (14:55 -0500)
Currently in some cases SDRAM init requires global_data to be available
and soon this will not be available prior to board_init_f().  Adjust the
code paths in these cases to be correct.  In some cases we had the SPL
stack be in DDR as we might have large stacks (due to Falcon Mode +
Environment).  In these cases switch to CONFIG_SPL_STACK_R.  In other
cases we had simply been setting CONFIG_SPL_STACK into SRAM.  In these
cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also
in SRAM) so drop those lines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested on Beagleboard, Beagleboard xM
Tested-by: Matt Porter <mporter@konsulko.com>
Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
23 files changed:
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/omap-common/hwinit-common.c
arch/arm/cpu/armv7/omap3/board.c
configs/am335x_boneblack_defconfig
configs/am335x_boneblack_vboot_defconfig
configs/am335x_evm_defconfig
configs/am335x_evm_nor_defconfig
configs/am335x_evm_spiboot_defconfig
configs/am335x_evm_usbspl_defconfig
configs/am335x_igep0033_defconfig
include/configs/am3517_crane.h
include/configs/am3517_evm.h
include/configs/bur_am335x_common.h
include/configs/cm_t35.h
include/configs/devkit8000.h
include/configs/omap3_evm_common.h
include/configs/siemens-am33x-common.h
include/configs/tam3517-common.h
include/configs/tao3530.h
include/configs/ti814x_evm.h
include/configs/ti816x_evm.h
include/configs/ti_armv7_common.h
include/configs/tricorder.h

index 81477aa7b0c3fc9e432a248ca632fc0672a693db..67bef23ea90592f93cf176c6cadb3963c04ab8e1 100644 (file)
@@ -275,6 +275,14 @@ static void watchdog_disable(void)
                ;
 }
 
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+       board_early_init_f();
+       sdram_init();
+}
+#endif
+
 void s_init(void)
 {
        /*
@@ -290,6 +298,7 @@ void s_init(void)
        setup_clocks_for_console();
        uart_soft_reset();
 #if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
+       /* TODO: This does not work, gd is not available yet */
        gd->baudrate = CONFIG_BAUDRATE;
        serial_init();
        gd->have_console = 1;
@@ -298,9 +307,5 @@ void s_init(void)
        /* Enable RTC32K clock */
        rtc32k_enable();
 #endif
-#ifdef CONFIG_SPL_BUILD
-       board_early_init_f();
-       sdram_init();
-#endif
 }
 #endif
index cb35c198f1802edc71215f0bb170dc0407ae1e17..6c8f3bcea4f3f83e0ea7a3fa6468db741d234ddd 100644 (file)
@@ -128,14 +128,18 @@ void s_init(void)
        do_io_settings();
 #endif
        prcm_init();
+}
+
 #ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
 #ifdef CONFIG_BOARD_EARLY_INIT_F
        board_early_init_f();
 #endif
        /* For regular u-boot sdram_init() is called from dram_init() */
        sdram_init();
-#endif
 }
+#endif
 
 /*
  * Routine: wait_for_command_complete
index 90d6ae7bb5f5e8c43ef31b6477195875fdb1d1ab..347947c4b3545bcfe1a583d0115a3f0faea17812 100644 (file)
@@ -240,8 +240,6 @@ void try_unlock_memory(void)
  *****************************************************************************/
 void s_init(void)
 {
-       int in_sdram = is_running_in_sdram();
-
        watchdog_init();
 
        try_unlock_memory();
@@ -264,10 +262,14 @@ void s_init(void)
 #ifdef CONFIG_USB_EHCI_OMAP
        ehci_clocks_enable();
 #endif
+}
 
-       if (!in_sdram)
-               mem_init();
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+       mem_init();
 }
+#endif
 
 /*
  * Routine: misc_init_r
index b631c410dc73414eb83f99349236a2cd5ac6d89b..f5b807b05969916ae1140649bdc6dc310b33cdb4 100644 (file)
@@ -1,4 +1,6 @@
 CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_AM335X_EVM=y
index 51bf370364a3e10981c7a874ba89417daca604d2..db27c3e70b5e6d67f56924daf8d6a51b018474b3 100644 (file)
@@ -1,4 +1,6 @@
 CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_AM335X_EVM=y
index 2e5aeaa4dd4840732886b1a6e1ae5b0a38b816e0..b2f332ea76430d0a17a3e12cd8458f7d65974cce 100644 (file)
@@ -1,4 +1,6 @@
 CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_CONS_INDEX=1
 +S:CONFIG_ARM=y
index be901633acd3ea868fa98804920347cde559336f..ed72af6d33073600eeb0e7e7686d688b2e06f043 100644 (file)
@@ -1,4 +1,6 @@
 CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_CONS_INDEX=1
 +S:CONFIG_ARM=y
index a6188ea72666171f7012f9c737f982dc2d34cbc9..097dd47320ec26604c8d91f2f62bf17a0dbd89a8 100644 (file)
@@ -1,4 +1,6 @@
 CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
 CONFIG_CONS_INDEX=1
 +S:CONFIG_ARM=y
index 352c1fb5963a67caa805bc478c275f3b8c00fc35..773042a39340638bf9a1aa319407531eb95223aa 100644 (file)
@@ -1,4 +1,6 @@
 CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
 CONFIG_CONS_INDEX=1
 +S:CONFIG_ARM=y
index f3544b5238fa00d50a08e7ce6fcfb5960a813465..7634d03d3b5c47081eca1213f08ce45eff504e7c 100644 (file)
@@ -1,4 +1,6 @@
 CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_AM335X_IGEP0033=y
 CONFIG_SYS_MALLOC_F=y
index 09ee10c0590b48c1260ff9846486dea9ca9504c6..290a6a3e0640399cce117d6b404ab2b29d66f0bb 100644 (file)
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_TEXT_BASE           0x40200800
 #define CONFIG_SPL_MAX_SIZE            (54 * 1024)     /* 8 KB for stack */
-#define CONFIG_SPL_STACK               LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR      0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE                0x80000         /* 512 KB */
index 190ef0e71bfbeaf9441e701cd65146ddc6e5b4f0..3de50799621ebf82ab2da404a55fb2385cf1a3ee 100644 (file)
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_TEXT_BASE           0x40200800
 #define CONFIG_SPL_MAX_SIZE            (54 * 1024)     /* 8 KB for stack */
-#define CONFIG_SPL_STACK               LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR      0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE                0x80000         /* 512 KB */
index e9d5d0162013b63a22a20a710a86ff855fbd1e09..49afe46e2ae82963ec3acad9fbec5cf95d569c4b 100644 (file)
  *
  * ----------------------------------------------------------------------------
  */
-#define CONFIG_SPL_STACK               CONFIG_SYS_INIT_SP_ADDR
 #undef  CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE           0x80800000
 #define CONFIG_SPL_BSS_START_ADDR      0x80A00000
index b2a9f35797093a7698b6e4db9464849962d51dbe..9feca1b47b381f6a40ba295c80a4102f2fc6127e 100644 (file)
 
 #define CONFIG_SPL_TEXT_BASE           0x40200800
 #define CONFIG_SPL_MAX_SIZE            (54 * 1024)     /* 8 KB for stack */
-#define CONFIG_SPL_STACK               LOW_LEVEL_SRAM_STACK
 
 /*
  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
index 1c69551d16ae31cb3dda2924edf88d261f972c78..84b047e53fb40506ec6dd6b3ef3c6deafbfd1b2b 100644 (file)
 
 #undef CONFIG_SPL_TEXT_BASE
 #define CONFIG_SPL_TEXT_BASE           0x40200000 /*CONFIG_SYS_SRAM_START*/
-#undef CONFIG_SPL_STACK
-#define CONFIG_SPL_STACK               LOW_LEVEL_SRAM_STACK
 
 /* NAND boot config */
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
index 8885e175810620538e1da86eec724f6a21ecb5b9..e7df15400d373d17871362a2f3275a14f48426c6 100644 (file)
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE           0x40200800
 #define CONFIG_SPL_MAX_SIZE            (54 * 1024)     /* 8 KB for stack */
-#define CONFIG_SPL_STACK               LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR      0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE                0x80000         /* 512 KB */
index 21e13e54730e35294b88043c26fd31ac25983d16..c7affd6f3a139e9a8106401fd8921c969b4d2109 100644 (file)
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE           0x402F0400
 #define CONFIG_SPL_MAX_SIZE            (101 * 1024)
-#define CONFIG_SPL_STACK               CONFIG_SYS_INIT_SP_ADDR
 
 #define CONFIG_SPL_BSS_START_ADDR      0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE                0x80000         /* 512 KB */
index 9fbe68a8a2f22b1506c3ef327d442f0ccf75f679..38288f69aaa5584dd97949522247138ae1cfdfc8 100644 (file)
 
 #define CONFIG_SPL_TEXT_BASE           0x40200000 /*CONFIG_SYS_SRAM_START*/
 #define CONFIG_SPL_MAX_SIZE            (54 * 1024)     /* 8 KB for stack */
-#define CONFIG_SPL_STACK               LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SYS_SPL_MALLOC_START    0x8f000000
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000
index 7d2c0d2fa75c2e87b49a2d2bb4d6bd6f15e4a95f..dd69d4ebabfe11ed83174fcf551dddc8c4650d05 100644 (file)
 
 #define CONFIG_SPL_TEXT_BASE           0x40200800
 #define CONFIG_SPL_MAX_SIZE            (54 * 1024)     /* 8 KB for stack */
-#define CONFIG_SPL_STACK               LOW_LEVEL_SRAM_STACK
 
 /*
  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
index deb6bb2b8f643f4e92cc3bf8ce8ff151cb99c822..dcc2bdc7f658f295d0d1a1bc0dce9117c588f3eb 100644 (file)
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE           0x40300000
 #define CONFIG_SPL_MAX_SIZE            ((128 - 18) * 1024)
-#define CONFIG_SPL_STACK               CONFIG_SYS_INIT_SP_ADDR
 
 #define CONFIG_SPL_BSS_START_ADDR      0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE                0x80000         /* 512 KB */
index f69a5599262d40fe3aa30da2e777b5e7fd070520..27a3dd13666210cc0793d36160644f1a7416dfb9 100644 (file)
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE    0x40400000
 #define CONFIG_SPL_MAX_SIZE     ((128 - 18) * 1024)
-#define CONFIG_SPL_STACK        CONFIG_SYS_INIT_SP_ADDR
 
 #define CONFIG_SPL_BSS_START_ADDR   0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE     0x80000     /* 512 KB */
index 2bd116477c07e01a9c81827189c3fa0fb643eeac..c0c106021671ad7de21fa8a6242591ad8e7e9fef 100644 (file)
  * SPLs).  We have our BSS be placed 2MiB after this, to allow for the
  * default Linux kernel address of 0x80008000 to work with most sized
  * kernels, in the Falcon Mode case.  We have the SPL malloc pool at the
- * end of the BSS area.  We place our stack at 32MiB after the start of
- * DRAM to allow room for all of the above.
+ * end of the BSS area.  We suggest that the stack be placed at 32MiB after
+ * the start of DRAM to allow room for all of the above (handled in Kconfig).
  */
-#define CONFIG_SPL_STACK               (CONFIG_SYS_SDRAM_BASE + (32 << 20))
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE           0x80800000
 #endif
index 36621a553cdf961ccd677c7b1194d86029567ada..10ac4a46bc4a38a7d13577ddbdba34f06aa81e7f 100644 (file)
 
 #define CONFIG_SPL_TEXT_BASE           0x40200000 /*CONFIG_SYS_SRAM_START*/
 #define CONFIG_SPL_MAX_SIZE            (57 * 1024)     /* 7 KB for stack */
-#define CONFIG_SPL_STACK               LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR      0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
 #define CONFIG_SPL_BSS_MAX_SIZE                0x80000