pm9263: lowlevel init update

move PSRAM init to pm9263.c
this will allow us after to make the nor lowlevel_init generic

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

diff --git a/board/ronetix/pm9263/lowlevel_init.S b/board/ronetix/pm9263/lowlevel_init.S
index c048c9109606f60df57015d62c46f7870816a264..561722c7099996fbfdb77a1aa11b81571dfef9a2 100644 (file)
--- a/board/ronetix/pm9263/lowlevel_init.S
+++ b/board/ronetix/pm9263/lowlevel_init.S
@@ -194,12 +194,10 @@ SMRDATA:
 
        .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
        .word CONFIG_SYS_MATRIX_EBI0CSA_VAL
-       .word (AT91_BASE_SYS + AT91_MATRIX_EBI1CSA)
-       .word CONFIG_SYS_MATRIX_EBI1CSA_VAL
 
        /* flash */
        .word (AT91_BASE_SYS + AT91_SMC_MODE(0))
-       .word CONFIG_SYS_SMC0_CTRL0_VAL
+       .word CONFIG_SYS_SMC0_MODE0_VAL
 
        .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
        .word CONFIG_SYS_SMC0_CYCLE0_VAL
@@ -210,19 +208,6 @@ SMRDATA:
        .word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
        .word CONFIG_SYS_SMC0_SETUP0_VAL
 
-       /* PSRAM */
-       .word (AT91_BASE_SYS + AT91_SMC1_MODE(0))
-       .word CONFIG_SYS_SMC1_CTRL0_VAL
-
-       .word (AT91_BASE_SYS + AT91_SMC1_CYCLE(0))
-       .word CONFIG_SYS_SMC1_CYCLE0_VAL
-
-       .word (AT91_BASE_SYS + AT91_SMC1_PULSE(0))
-       .word CONFIG_SYS_SMC1_PULSE0_VAL
-
-       .word (AT91_BASE_SYS + AT91_SMC1_SETUP(0))
-       .word CONFIG_SYS_SMC1_SETUP0_VAL
-
 SMRDATA1:
        .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
        .word CONFIG_SYS_SDRC_MR_VAL1

diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index d2598a06807f75548b958604ce25a3b41f9d5ba6..8ca71da9ce58f7a9afde8224f375275cafa508c6 100644 (file)
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -165,6 +165,27 @@ void lcd_disable(void)
 static int pm9263_lcd_hw_psram_init(void)
 {
        volatile uint16_t x;
+       unsigned long csa;
+
+       /* Enable CS3  3.3v, no pull-ups */
+       csa = at91_sys_read(AT91_MATRIX_EBI1CSA);
+       at91_sys_write(AT91_MATRIX_EBI1CSA,
+                      csa | AT91_MATRIX_EBI1_DBPUC |
+                      AT91_MATRIX_EBI1_VDDIOMSEL_3_3V);
+
+       /* Configure SMC1 CS0 for PSRAM - 16-bit */
+       at91_sys_write(AT91_SMC1_SETUP(0),
+                      AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+                      AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+       at91_sys_write(AT91_SMC1_PULSE(0),
+                      AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) |
+                      AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7));
+       at91_sys_write(AT91_SMC1_CYCLE(0),
+                      AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
+       at91_sys_write(AT91_SMC1_MODE(0),
+                      AT91_SMC_DBW_16 |
+                      AT91_SMC_PMEN |
+                      AT91_SMC_PS_32);
 
        /* setup PB29 as output */
        at91_set_gpio_output(PSRAM_CRE_PIN, 1);

diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index f0dbe81d140298e780a7b448662d7bd3d6213148..5ebf2863669e49d95d6b3a57ccfe1b1e60a5e62f 100644 (file)
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -67,8 +67,6 @@
 #define CONFIG_SYS_PIOD_PPUDR_VAL      0xFFFF0000
 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL  0x0001010A
-/* EBI1_CSA, 3.3v, no pull-ups */
-#define CONFIG_SYS_MATRIX_EBI1CSA_VAL  0x00010100
 
 /* SDRAM */
 /* SDRAMC_MR Mode register */
@@ -100,13 +98,7 @@
 #define CONFIG_SYS_SMC0_SETUP0_VAL     0x0A0A0A0A      /* SMC_SETUP */
 #define CONFIG_SYS_SMC0_PULSE0_VAL     0x0B0B0B0B      /* SMC_PULSE */
 #define CONFIG_SYS_SMC0_CYCLE0_VAL     0x00160016      /* SMC_CYCLE */
-#define CONFIG_SYS_SMC0_CTRL0_VAL      0x00161003      /* SMC_MODE */
-
-/* setup SMC1, CS0 (PSRAM) - 16-bit */
-#define CONFIG_SYS_SMC1_SETUP0_VAL     0x00000000      /* SMC_SETUP */
-#define CONFIG_SYS_SMC1_PULSE0_VAL     0x07020707      /* SMC_PULSE */
-#define CONFIG_SYS_SMC1_CYCLE0_VAL     0x00080008      /* SMC_CYCLE */
-#define CONFIG_SYS_SMC1_CTRL0_VAL      0x31001000      /* SMC_MODE */
+#define CONFIG_SYS_SMC0_MODE0_VAL      0x00161003      /* SMC_MODE */
 
 #define CONFIG_SYS_RSTC_RMR_VAL                0xA5000301      /* user reset enable */