#define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 3
#define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1
#define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 0
+
+ #define QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT 2
+ #define QCA_RST_BOOTSTRAP_BOOT_SEL_MASK (1 << QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT)
+ #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT 3
+ #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_MASK (1 << QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT)
+ #define QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT 5
+ #define QCA_RST_BOOTSTRAP_JTAG_MODE_MASK (1 << QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT)
#endif
/* RST_RESET */