#define STM32_GPIOS_PER_BANK 16
#define MODE_BITS(gpio_pin) (gpio_pin * 2)
#define MODE_BITS_MASK 3
-#define IN_OUT_BIT_INDEX(gpio_pin) (1UL << (gpio_pin))
+#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
{
int mask = MODE_BITS_MASK << bits_index;
clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
- mask = IN_OUT_BIT_INDEX(offset);
- clrsetbits_le32(®s->odr, mask, value ? mask : 0);
+
+ writel(BSRR_BIT(offset, value), ®s->bsrr);
return 0;
}
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
- return readl(®s->idr) & IN_OUT_BIT_INDEX(offset) ? 1 : 0;
+ return readl(®s->idr) & BIT(offset) ? 1 : 0;
}
static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
- int mask = IN_OUT_BIT_INDEX(offset);
- clrsetbits_le32(®s->odr, mask, value ? mask : 0);
+ writel(BSRR_BIT(offset, value), ®s->bsrr);
return 0;
}