armv8: fsl-layerscape: Add A72 core detection
authorAlison Wang <b18965@freescale.com>
Tue, 5 Jul 2016 08:01:52 +0000 (16:01 +0800)
committerYork Sun <york.sun@nxp.com>
Tue, 26 Jul 2016 16:02:00 +0000 (09:02 -0700)
Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

index 7a2ec6bf591d720acac8b825a74ae9029ca92ad2..eaff16651a8366e71e42f8bf4279de04735fdffe 100644 (file)
@@ -309,7 +309,8 @@ int print_cpuinfo(void)
                printf("CPU%d(%s):%-4s MHz  ", core,
                       type == TY_ITYP_VER_A7 ? "A7 " :
                       (type == TY_ITYP_VER_A53 ? "A53" :
-                       (type == TY_ITYP_VER_A57 ? "A57" : "   ")),
+                      (type == TY_ITYP_VER_A57 ? "A57" :
+                      (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
                       strmhz(buf, sysinfo.freq_processor[core]));
        }
        printf("\n       Bus:      %-4s MHz  ",
index 87507c79c890c1150b545b4ee4da27d3ac499add..97136a011ecb265e5017394a114f0ca6c7a3aa5a 100644 (file)
@@ -94,6 +94,7 @@
 #define TY_ITYP_VER_A7          0x1
 #define TY_ITYP_VER_A53         0x2
 #define TY_ITYP_VER_A57         0x3
+#define TY_ITYP_VER_A72                0x4
 
 #define TP_CLUSTER_EOC         0xc0000000      /* end of clusters */
 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
index 7e39e927e981e1cde1ccf9a7154c4fd4a1883588..93e26c1d7f489c684a2f2978204bdb642945c016 100644 (file)
 #define TY_ITYP_VER_A7         0x1
 #define TY_ITYP_VER_A53                0x2
 #define TY_ITYP_VER_A57                0x3
+#define TY_ITYP_VER_A72                0x4
 
 #define TP_CLUSTER_EOC         0x80000000      /* end of clusters */
 #define TP_CLUSTER_INIT_MASK   0x0000003f      /* initiator mask */