VERSION = 2014
PATCHLEVEL = 10
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
ret = ahci_init(DWC_AHSATA_BASE);
- scsi_scan(1);
return ret;
}
+
+/* On OMAP platforms SATA provides the SCSI subsystem */
+void scsi_init(void)
+{
+ init_sata(0);
+ scsi_scan(1);
+}
#
obj-y := lowlevel_init.o
-obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
+obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
+ fpga_manager.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
#include <asm/io.h>
#include <asm/arch/clock_manager.h>
+DECLARE_GLOBAL_DATA_PTR;
+
static const struct socfpga_clock_manager *clock_manager_base =
- (void *)SOCFPGA_CLKMGR_ADDRESS;
-
-#define CLKMGR_BYPASS_ENABLE 1
-#define CLKMGR_BYPASS_DISABLE 0
-#define CLKMGR_STAT_IDLE 0
-#define CLKMGR_STAT_BUSY 1
-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
-
-#define CLEAR_BGP_EN_PWRDN \
- (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
- CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
- CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-
-#define VCO_EN_BASE \
- (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
- CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
- CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-
-static inline void cm_wait_for_lock(uint32_t mask)
+ (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
+static void cm_wait_for_lock(uint32_t mask)
{
register uint32_t inter_val;
+ uint32_t retry = 0;
do {
inter_val = readl(&clock_manager_base->inter) & mask;
- } while (inter_val != mask);
+ if (inter_val == mask)
+ retry++;
+ else
+ retry = 0;
+ if (retry >= 10)
+ break;
+ } while (1);
}
/* function to poll in the fsm busy bit */
-static inline void cm_wait_for_fsm(void)
+static void cm_wait_for_fsm(void)
{
while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
;
* function to write the bypass register which requires a poll of the
* busy bit
*/
-static inline void cm_write_bypass(uint32_t val)
+static void cm_write_bypass(uint32_t val)
{
writel(val, &clock_manager_base->bypass);
cm_wait_for_fsm();
}
/* function to write the ctrl register which requires a poll of the busy bit */
-static inline void cm_write_ctrl(uint32_t val)
+static void cm_write_ctrl(uint32_t val)
{
writel(val, &clock_manager_base->ctrl);
cm_wait_for_fsm();
}
/* function to write a clock register that has phase information */
-static inline void cm_write_with_phase(uint32_t value,
- uint32_t reg_address, uint32_t mask)
+static void cm_write_with_phase(uint32_t value,
+ uint32_t reg_address, uint32_t mask)
{
/* poll until phase is zero */
while (readl(reg_address) & mask)
writel(0, &clock_manager_base->per_pll.en);
/* Put all plls in bypass */
- cm_write_bypass(
- CLKMGR_BYPASS_PERPLLSRC_SET(
- CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
- CLKMGR_BYPASS_SDRPLLSRC_SET(
- CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
- CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
- CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
- CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
+ cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
+ CLKMGR_BYPASS_MAINPLL);
- /*
- * Put all plls VCO registers back to reset value.
- * Some code might have messed with them.
- */
- writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
+ /* Put all plls VCO registers back to reset value. */
+ writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
+ ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->main_pll.vco);
- writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
+ writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
+ ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->per_pll.vco);
- writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
+ writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
+ ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->sdr_pll.vco);
/*
* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
* with numerator and denominator.
*/
- writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
- CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->main_pll.vco);
-
- writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
- CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->per_pll.vco);
-
- writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
- cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
- CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->sdr_pll.vco);
+ writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
+ writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
+ writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
/*
* Time starts here
writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
/* Peri pernandsdmmcclk */
+ writel(cfg->mainnandsdmmcclk,
+ &clock_manager_base->main_pll.mainnandsdmmcclk);
+
writel(cfg->pernandsdmmcclk,
&clock_manager_base->per_pll.pernandsdmmcclk);
/* Enable vco */
/* main pll vco */
- writel(cfg->main_vco_base | VCO_EN_BASE,
+ writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->main_pll.vco);
/* periferal pll */
- writel(cfg->peri_vco_base | VCO_EN_BASE,
+ writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->per_pll.vco);
/* sdram pll vco */
- writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
- cfg->sdram_vco_base | VCO_EN_BASE,
- &clock_manager_base->sdr_pll.vco);
+ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+ &clock_manager_base->sdr_pll.vco);
/* L3 MP and L3 SP */
writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
&clock_manager_base->per_pll.vco);
/* assert sdram outresetall */
- writel(cfg->sdram_vco_base | VCO_EN_BASE|
- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
+ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
+ CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
&clock_manager_base->sdr_pll.vco);
/* deassert main outresetall */
&clock_manager_base->per_pll.vco);
/* deassert sdram outresetall */
- writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
- cfg->sdram_vco_base | VCO_EN_BASE,
- &clock_manager_base->sdr_pll.vco);
+ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+ &clock_manager_base->sdr_pll.vco);
/*
* now that we've toggled outreset all, all the clocks
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
/* Take all three PLLs out of bypass when safe mode is cleared. */
- cm_write_bypass(
- CLKMGR_BYPASS_PERPLLSRC_SET(
- CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
- CLKMGR_BYPASS_SDRPLLSRC_SET(
- CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
- CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
- CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
- CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
+ cm_write_bypass(0);
/* clear safe mode */
- cm_write_ctrl(readl(&clock_manager_base->ctrl) |
- CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
+ cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
/*
* now that safe mode is clear with clocks gated
writel(~0, &clock_manager_base->main_pll.en);
writel(~0, &clock_manager_base->per_pll.en);
writel(~0, &clock_manager_base->sdr_pll.en);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
+ CLKMGR_INTER_MAINPLLLOST_MASK,
+ &clock_manager_base->inter);
+}
+
+static unsigned int cm_get_main_vco_clk_hz(void)
+{
+ uint32_t reg, clock;
+
+ /* get the main VCO clock */
+ reg = readl(&clock_manager_base->main_pll.vco);
+ clock = CONFIG_HPS_CLK_OSC1_HZ;
+ clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
+ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
+ clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
+ CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+ return clock;
+}
+
+static unsigned int cm_get_per_vco_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ /* identify PER PLL clock source */
+ reg = readl(&clock_manager_base->per_pll.vco);
+ reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
+ CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
+ clock = CONFIG_HPS_CLK_OSC1_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+ clock = CONFIG_HPS_CLK_OSC2_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_F2S)
+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+
+ /* get the PER VCO clock */
+ reg = readl(&clock_manager_base->per_pll.vco);
+ clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
+ CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
+ clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
+ CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+ return clock;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ uint32_t reg, clock;
+
+ clock = cm_get_main_vco_clk_hz();
+
+ /* get the MPU clock */
+ reg = readl(&clock_manager_base->altera.mpuclk);
+ clock /= (reg + 1);
+ reg = readl(&clock_manager_base->main_pll.mpuclk);
+ clock /= (reg + 1);
+ return clock;
}
+
+unsigned long cm_get_sdram_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ /* identify SDRAM PLL clock source */
+ reg = readl(&clock_manager_base->sdr_pll.vco);
+ reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
+ CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
+ clock = CONFIG_HPS_CLK_OSC1_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+ clock = CONFIG_HPS_CLK_OSC2_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_F2S)
+ clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+
+ /* get the SDRAM VCO clock */
+ reg = readl(&clock_manager_base->sdr_pll.vco);
+ clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
+ CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
+ clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
+ CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+ /* get the SDRAM (DDR_DQS) clock */
+ reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
+ reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
+ CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
+ clock /= (reg + 1);
+
+ return clock;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ /* identify the source of L4 SP clock */
+ reg = readl(&clock_manager_base->main_pll.l4src);
+ reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
+ CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
+
+ if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
+ clock = cm_get_main_vco_clk_hz();
+
+ /* get the clock prior L4 SP divider (main clk) */
+ reg = readl(&clock_manager_base->altera.mainclk);
+ clock /= (reg + 1);
+ reg = readl(&clock_manager_base->main_pll.mainclk);
+ clock /= (reg + 1);
+ } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
+ clock = cm_get_per_vco_clk_hz();
+
+ /* get the clock prior L4 SP divider (periph_base_clk) */
+ reg = readl(&clock_manager_base->per_pll.perbaseclk);
+ clock /= (reg + 1);
+ }
+
+ /* get the L4 SP clock which supplied to UART */
+ reg = readl(&clock_manager_base->main_pll.maindiv);
+ reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
+ CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
+ clock = clock / (1 << reg);
+
+ return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ /* identify the source of MMC clock */
+ reg = readl(&clock_manager_base->per_pll.src);
+ reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
+ CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
+
+ if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+ } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
+ clock = cm_get_main_vco_clk_hz();
+
+ /* get the SDMMC clock */
+ reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
+ clock /= (reg + 1);
+ } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
+ clock = cm_get_per_vco_clk_hz();
+
+ /* get the SDMMC clock */
+ reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
+ clock /= (reg + 1);
+ }
+
+ /* further divide by 4 as we have fixed divider at wrapper */
+ clock /= 4;
+ return clock;
+}
+
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ /* identify the source of QSPI clock */
+ reg = readl(&clock_manager_base->per_pll.src);
+ reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
+ CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
+
+ if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+ } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
+ clock = cm_get_main_vco_clk_hz();
+
+ /* get the qspi clock */
+ reg = readl(&clock_manager_base->main_pll.mainqspiclk);
+ clock /= (reg + 1);
+ } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
+ clock = cm_get_per_vco_clk_hz();
+
+ /* get the qspi clock */
+ reg = readl(&clock_manager_base->per_pll.perqspiclk);
+ clock /= (reg + 1);
+ }
+
+ return clock;
+}
+
+static void cm_print_clock_quick_summary(void)
+{
+ printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
+ printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
+ printf("EOSC1 %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
+ printf("EOSC2 %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
+ printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
+ printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
+ printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+ printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
+ printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+}
+
+int set_cpu_clk_info(void)
+{
+ /* Calculate the clock frequencies required for drivers */
+ cm_get_l4_sp_clk_hz();
+ cm_get_mmc_controller_clk_hz();
+
+ gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
+ gd->bd->bi_dsp_freq = 0;
+ gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
+
+ return 0;
+}
+
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ cm_print_clock_quick_summary();
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
+ "display clocks",
+ ""
+);
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * This file contains only support functions used also by the SoCFPGA
+ * platform code, the real meat is located in drivers/fpga/socfpga.c .
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timeout count */
+#define FPGA_TIMEOUT_CNT 0x1000000
+
+static struct socfpga_fpga_manager *fpgamgr_regs =
+ (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+/* Check whether FPGA Init_Done signal is high */
+static int is_fpgamgr_initdone_high(void)
+{
+ unsigned long val;
+
+ val = readl(&fpgamgr_regs->gpio_ext_porta);
+ return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
+}
+
+/* Get the FPGA mode */
+int fpgamgr_get_mode(void)
+{
+ unsigned long val;
+
+ val = readl(&fpgamgr_regs->stat);
+ return val & FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int fpgamgr_test_fpga_ready(void)
+{
+ /* Check for init done signal */
+ if (!is_fpgamgr_initdone_high())
+ return 0;
+
+ /* Check again to avoid false glitches */
+ if (!is_fpgamgr_initdone_high())
+ return 0;
+
+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
+ return 0;
+
+ return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int fpgamgr_poll_fpga_ready(void)
+{
+ unsigned long i;
+
+ /* If FPGA is blank, wait till WD invoke warm reset */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ /* check for init done signal */
+ if (!is_fpgamgr_initdone_high())
+ continue;
+ /* check again to avoid false glitches */
+ if (!is_fpgamgr_initdone_high())
+ continue;
+ return 1;
+ }
+
+ return 0;
+}
#include <common.h>
#include <asm/io.h>
+#include <altera.h>
#include <miiphy.h>
#include <netdev.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/nic301.h>
+#include <asm/arch/scu.h>
+#include <asm/pl310.h>
DECLARE_GLOBAL_DATA_PTR;
+static struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+static struct socfpga_reset_manager *reset_manager_base =
+ (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+static struct nic301_registers *nic301_regs =
+ (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+static struct scu_registers *scu_regs =
+ (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_DESIGNWARE_ETH
+int cpu_eth_init(bd_t *bis)
+{
+#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
+ const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
+#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
+ const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
+#else
+#error "Incorrect CONFIG_EMAC_BASE value!"
+#endif
+
+ /* Initialize EMAC. This needs to be done at least once per boot. */
+
+ /*
+ * Putting the EMAC controller to reset when configuring the PHY
+ * interface select at System Manager
+ */
+ socfpga_emac_reset(1);
+
+ /* Clearing emac0 PHY interface select to 0 */
+ clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
+ SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
+
+ /* configure to PHY interface select choosed */
+ setbits_le32(&sysmgr_regs->emacgrp_ctrl,
+ SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+
+ /* Release the EMAC controller from reset */
+ socfpga_emac_reset(0);
+
+ /* initialize and register the emac */
+ return designware_initialize(CONFIG_EMAC_BASE,
+ CONFIG_PHY_INTERFACE_MODE);
+}
+#endif
+
+#ifdef CONFIG_DWMMC
+/*
+ * Initializes MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+ return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
+ CONFIG_HPS_SDMMC_BUSWIDTH, 0);
+}
+#endif
+
#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Print CPU information
*/
int print_cpuinfo(void)
{
- puts("CPU : Altera SOCFPGA Platform\n");
+ puts("CPU: Altera SoCFPGA Platform\n");
return 0;
}
#endif
}
#endif
-int misc_init_r(void)
+#ifdef CONFIG_FPGA
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+ {
+ /* Family */
+ Altera_SoCFPGA,
+ /* Interface type */
+ fast_passive_parallel,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* No device function table */
+ NULL,
+ /* Base interface address specified in driver */
+ NULL,
+ /* No cookie implementation */
+ 0
+ },
+};
+
+/* add device descriptor to FPGA device table */
+static void socfpga_fpga_add(void)
{
- return 0;
+ int i;
+ fpga_init();
+ for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
+ fpga_add(fpga_altera, &altera_fpga[i]);
}
+#else
+static inline void socfpga_fpga_add(void) {}
+#endif
+int arch_cpu_init(void)
+{
+ /*
+ * If the HW watchdog is NOT enabled, make sure it is not running,
+ * for example because it was enabled in the preloader. This might
+ * trigger a watchdog-triggered reboot of Linux kernel later.
+ */
+#ifndef CONFIG_HW_WATCHDOG
+ socfpga_watchdog_reset();
+#endif
+ return 0;
+}
/*
- * DesignWare Ethernet initialization
+ * Convert all NIC-301 AMBA slaves from secure to non-secure
*/
-int cpu_eth_init(bd_t *bis)
+static void socfpga_nic301_slave_ns(void)
{
-#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
- /* initialize and register the emac */
- return designware_initialize(CONFIG_EMAC_BASE,
- CONFIG_PHY_INTERFACE_MODE);
+ writel(0x1, &nic301_regs->lwhps2fpgaregs);
+ writel(0x1, &nic301_regs->hps2fpgaregs);
+ writel(0x1, &nic301_regs->acp);
+ writel(0x1, &nic301_regs->rom);
+ writel(0x1, &nic301_regs->ocram);
+ writel(0x1, &nic301_regs->sdrdata);
+}
+
+static uint32_t iswgrp_handoff[8];
+
+int misc_init_r(void)
+{
+ int i;
+ for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
+ iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
+
+ socfpga_bridges_reset(1);
+ socfpga_nic301_slave_ns();
+
+ /*
+ * Private components security:
+ * U-Boot : configure private timer, global timer and cpu component
+ * access as non secure for kernel stage (as required by Linux)
+ */
+ setbits_le32(&scu_regs->sacr, 0xfff);
+
+ /* Configure the L2 controller to make SDRAM start at 0 */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+ writel(0x2, &nic301_regs->remap);
#else
- return 0;
+ writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
+ writel(0x1, &pl310->pl310_addr_filter_start);
#endif
+
+ /* Add device descriptor to FPGA device table */
+ socfpga_fpga_add();
+ return 0;
+}
+
+static void socfpga_sdram_apply_static_cfg(void)
+{
+ const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
+ const uint32_t applymask = 0x8;
+ uint32_t val = readl(staticcfg) | applymask;
+
+ /*
+ * SDRAM staticcfg register specific:
+ * When applying the register setting, the CPU must not access
+ * SDRAM. Luckily for us, we can abuse i-cache here to help us
+ * circumvent the SDRAM access issue. The idea is to make sure
+ * that the code is in one full i-cache line by branching past
+ * it and back. Once it is in the i-cache, we execute the core
+ * of the code and apply the register settings.
+ *
+ * The code below uses 7 instructions, while the Cortex-A9 has
+ * 32-byte cachelines, thus the limit is 8 instructions total.
+ */
+ asm volatile(
+ ".align 5 \n"
+ " b 2f \n"
+ "1: str %0, [%1] \n"
+ " dsb \n"
+ " isb \n"
+ " b 3f \n"
+ "2: b 1b \n"
+ "3: nop \n"
+ : : "r"(val), "r"(staticcfg) : "memory", "cc");
}
+
+int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ argv++;
+
+ switch (*argv[0]) {
+ case 'e': /* Enable */
+ writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
+ socfpga_sdram_apply_static_cfg();
+ writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
+ writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
+ writel(iswgrp_handoff[1], &nic301_regs->remap);
+ break;
+ case 'd': /* Disable */
+ writel(0, &sysmgr_regs->fpgaintfgrp_module);
+ writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
+ socfpga_sdram_apply_static_cfg();
+ writel(0, &reset_manager_base->brg_mod_reset);
+ writel(1, &nic301_regs->remap);
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ bridge, 2, 1, do_bridge,
+ "SoCFPGA HPS FPGA bridge control",
+ "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+ "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+ ""
+);
#include <common.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
+#include <asm/arch/fpga_manager.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
+void socfpga_watchdog_reset(void)
+{
+ /* assert reset for watchdog */
+ setbits_le32(&reset_manager_base->per_mod_reset,
+ 1 << RSTMGR_PERMODRST_L4WD0_LSB);
+
+ /* deassert watchdog from reset (watchdog in not running state) */
+ clrbits_le32(&reset_manager_base->per_mod_reset,
+ 1 << RSTMGR_PERMODRST_L4WD0_LSB);
+}
+
/*
* Write the reset manager register to cause reset
*/
{
writel(0, &reset_manager_base->per_mod_reset);
}
+
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+void socfpga_bridges_reset(int enable)
+{
+ /* For SoCFPGA-VT, this is NOP. */
+}
+#else
+
+#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
+#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
+#define L3REGS_REMAP_OCRAM_MASK 0x01
+
+void socfpga_bridges_reset(int enable)
+{
+ const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
+ L3REGS_REMAP_HPS2FPGA_MASK |
+ L3REGS_REMAP_OCRAM_MASK;
+
+ if (enable) {
+ /* brdmodrst */
+ writel(0xffffffff, &reset_manager_base->brg_mod_reset);
+ } else {
+ /* Check signal from FPGA. */
+ if (fpgamgr_poll_fpga_ready()) {
+ /* FPGA not ready. Wait for watchdog timeout. */
+ printf("%s: fpga not ready, hanging.\n", __func__);
+ hang();
+ }
+
+ /* brdmodrst */
+ writel(0, &reset_manager_base->brg_mod_reset);
+
+ /* Remap the bridges into memory map */
+ writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
+ }
+}
+#endif
+
+/* Change the reset state for EMAC 0 and EMAC 1 */
+void socfpga_emac_reset(int enable)
+{
+ const void *reset = &reset_manager_base->per_mod_reset;
+
+ if (enable) {
+ setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
+ setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+ } else {
+#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
+ clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
+#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
+ clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+#endif
+ }
+}
DECLARE_GLOBAL_DATA_PTR;
+#define MAIN_VCO_BASE ( \
+ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
+ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
+ (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
+ CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
+ )
+
+#define PERI_VCO_BASE ( \
+ (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
+ CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
+ (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
+ CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
+ (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
+ CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
+ )
+
+#define SDR_VCO_BASE ( \
+ (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
+ CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
+ (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
+ CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
+ (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
+ CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
+ )
+
u32 spl_boot_device(void)
{
return BOOT_DEVICE_RAM;
cm_config_t cm_default_cfg = {
/* main group */
MAIN_VCO_BASE,
- CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
- CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
- CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
- CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
- CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
- CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
- CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
- CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
- CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
- CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
- CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
- CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
- CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
- CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
- CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
- CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
- CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
- CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
- CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
- CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
- CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
- CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
- CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
- CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
- CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
- CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
- CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
- CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
- CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
+ (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+ CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+ CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+ CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+ CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+ CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+ CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+ CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+ CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+ CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+ CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
/* peripheral group */
PERI_VCO_BASE,
- CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
- CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
- CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
- CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
- CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
- CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
- CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
- CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
- CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
- CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
- CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
- CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
- CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
- CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
- CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
- CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
- CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
- CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
- CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
- CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
- CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
- CLKMGR_PERPLLGRP_SRC_QSPI_SET(
- CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
- CLKMGR_PERPLLGRP_SRC_NAND_SET(
- CONFIG_HPS_PERPLLGRP_SRC_NAND) |
- CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
- CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
+ (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+ CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+ CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+ CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+ CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+ CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+ CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+ CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+ CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+ CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+ CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+ CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+ CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+ CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
/* sdram pll group */
SDR_VCO_BASE,
- CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
- CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
- CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
- CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
- CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
- CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
- CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
- CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
- CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
- CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
- CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
- CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
- CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
- CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
+ (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+ CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+ CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
+ (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
+ (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+ CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+ CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
+ (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
+
};
debug("Freezing all I/O banks\n");
/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/system_manager.h>
+#include <asm/arch/fpga_manager.h>
DECLARE_GLOBAL_DATA_PTR;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
+ */
+static void populate_sysmgr_fpgaintf_module(void)
+{
+ uint32_t handoff_val = 0;
+
+ /* ISWGRP_HANDOFF_FPGAINTF */
+ writel(0, &sysmgr_regs->iswgrp_handoff[2]);
+
+ /* Enable the signal for those HPS peripherals that use FPGA. */
+ if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_NAND;
+ if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_EMAC1;
+ if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SDMMC;
+ if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_EMAC0;
+ if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SPIM0;
+ if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SPIM1;
+
+ /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
+ based on pinmux setting */
+ setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
+
+ handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
+ if (fpgamgr_test_fpga_ready()) {
+ /* Enable the required signals only */
+ writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
+ }
+}
+
/*
* Configure all the pin muxes
*/
void sysmgr_pinmux_init(void)
{
- unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
-
- const unsigned long *pval = sys_mgr_init_table;
- unsigned long i;
+ uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
+ int i;
- for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table);
- i++, offset += sizeof(unsigned long)) {
- writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+ for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); i++) {
+ writel(sys_mgr_init_table[i], regs);
+ regs += sizeof(regs);
}
+
+ populate_sysmgr_fpgaintf_module();
}
#include <asm/io.h>
#include <asm/arch/timer.h>
+#define TIMER_LOAD_VAL 0xFFFFFFFF
+
static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
/*
#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
#define PLL_BWADJ_HI_MASK 0xf
-#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0)
-#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0)
-#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1)
-#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4)
-#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17)
+#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0)
+#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0)
+#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1)
+#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4)
+#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17)
#endif /* _CLOCK_DEFS_H_ */
#ifndef _CLOCK_MANAGER_H_
#define _CLOCK_MANAGER_H_
+#ifndef __ASSEMBLER__
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#endif
+
typedef struct {
/* main group */
uint32_t main_vco_base;
u32 stat;
};
+struct socfpga_clock_manager_altera {
+ u32 mpuclk;
+ u32 mainclk;
+};
+
struct socfpga_clock_manager {
u32 ctrl;
u32 bypass;
struct socfpga_clock_manager_main_pll main_pll;
struct socfpga_clock_manager_per_pll per_pll;
struct socfpga_clock_manager_sdr_pll sdr_pll;
- u32 _pad_0xe0_0x200[72];
+ struct socfpga_clock_manager_altera altera;
+ u32 _pad_0xe8_0x200[70];
};
-#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
-#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
-#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
-#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
-#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
-#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
-#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
-#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
-#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
-#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
-#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
-#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
-#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
-#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
-#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
-#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
-#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
-#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
-#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
-#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
-#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
-#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
- (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
- (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
-#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
-#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
-#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
-#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
-#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
-#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
-#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
-#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
-#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
-#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
-#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
-#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
-#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
-#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
-#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
-#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
-#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
-#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
-#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
-#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
-#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
-
-#define MAIN_VCO_BASE \
- (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
- CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
-
-#define PERI_VCO_BASE \
- (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
- CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
- CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
-
-#define SDR_VCO_BASE \
- (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
- CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
- CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
+#define CLKMGR_CTRL_SAFEMODE (1 << 0)
+#define CLKMGR_CTRL_SAFEMODE_OFFSET 0
+
+#define CLKMGR_BYPASS_PERPLLSRC (1 << 4)
+#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4
+#define CLKMGR_BYPASS_PERPLL (1 << 3)
+#define CLKMGR_BYPASS_PERPLL_OFFSET 3
+#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2)
+#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2
+#define CLKMGR_BYPASS_SDRPLL (1 << 1)
+#define CLKMGR_BYPASS_SDRPLL_OFFSET 1
+#define CLKMGR_BYPASS_MAINPLL (1 << 0)
+#define CLKMGR_BYPASS_MAINPLL_OFFSET 0
+
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
+#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010
+#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020
+#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008
+
+#define CLKMGR_STAT_BUSY (1 << 0)
+
+/* Main PLL */
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0)
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
+#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1)
+#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2)
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
+
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
+
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380
+
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c
+
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007
+
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
+#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
+#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
+
+/* Per PLL */
+#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16
+#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000
+#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3
+#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8
+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22
+#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000
+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22
+#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000
+
+#define CLKMGR_VCO_SSRC_EOSC1 0x0
+#define CLKMGR_VCO_SSRC_EOSC2 0x1
+#define CLKMGR_VCO_SSRC_F2S 0x2
+
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff
+
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
+
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007
+
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff
+
+#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2
+#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c
+#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4
+#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030
+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003
+#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
+#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
+#define CLKMGR_SDMMC_CLK_SRC_PER 0x2
+#define CLKMGR_QSPI_CLK_SRC_F2S 0x0
+#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
+#define CLKMGR_QSPI_CLK_SRC_PER 0x2
+
+/* SDR PLL */
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000
+
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00
+
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00
#endif /* _CLOCK_MANAGER_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FPGA_MANAGER_H_
+#define _FPGA_MANAGER_H_
+
+#include <altera.h>
+
+struct socfpga_fpga_manager {
+ /* FPGA Manager Module */
+ u32 stat; /* 0x00 */
+ u32 ctrl;
+ u32 dclkcnt;
+ u32 dclkstat;
+ u32 gpo; /* 0x10 */
+ u32 gpi;
+ u32 misci; /* 0x18 */
+ u32 _pad_0x1c_0x82c[517];
+
+ /* Configuration Monitor (MON) Registers */
+ u32 gpio_inten; /* 0x830 */
+ u32 gpio_intmask;
+ u32 gpio_inttype_level;
+ u32 gpio_int_polarity;
+ u32 gpio_intstatus; /* 0x840 */
+ u32 gpio_raw_intstatus;
+ u32 _pad_0x848;
+ u32 gpio_porta_eoi;
+ u32 gpio_ext_porta; /* 0x850 */
+ u32 _pad_0x854_0x85c[3];
+ u32 gpio_1s_sync; /* 0x860 */
+ u32 _pad_0x864_0x868[2];
+ u32 gpio_ver_id_code;
+ u32 gpio_config_reg2; /* 0x870 */
+ u32 gpio_config_reg1;
+};
+
+#define FPGAMGRREGS_STAT_MODE_MASK 0x7
+#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
+#define FPGAMGRREGS_STAT_MSEL_LSB 3
+
+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
+#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
+#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
+#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
+#define FPGAMGRREGS_CTRL_EN_MASK 0x1
+#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
+
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
+
+/* FPGA Mode */
+#define FPGAMGRREGS_MODE_FPGAOFF 0x0
+#define FPGAMGRREGS_MODE_RESETPHASE 0x1
+#define FPGAMGRREGS_MODE_CFGPHASE 0x2
+#define FPGAMGRREGS_MODE_INITPHASE 0x3
+#define FPGAMGRREGS_MODE_USERMODE 0x4
+#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+
+/* FPGA CD Ratio Value */
+#define CDRATIO_x1 0x0
+#define CDRATIO_x2 0x1
+#define CDRATIO_x4 0x2
+#define CDRATIO_x8 0x3
+
+/* SoCFPGA support functions */
+int fpgamgr_test_fpga_ready(void);
+int fpgamgr_poll_fpga_ready(void);
+int fpgamgr_get_mode(void);
+
+#endif /* _FPGA_MANAGER_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _NIC301_REGISTERS_H_
+#define _NIC301_REGISTERS_H_
+
+struct nic301_registers {
+ u32 remap; /* 0x0 */
+ /* Security Register Group */
+ u32 _pad_0x4_0x8[1];
+ u32 l4main;
+ u32 l4sp;
+ u32 l4mp; /* 0x10 */
+ u32 l4osc1;
+ u32 l4spim;
+ u32 stm;
+ u32 lwhps2fpgaregs; /* 0x20 */
+ u32 _pad_0x24_0x28[1];
+ u32 usb1;
+ u32 nanddata;
+ u32 _pad_0x30_0x80[20];
+ u32 usb0; /* 0x80 */
+ u32 nandregs;
+ u32 qspidata;
+ u32 fpgamgrdata;
+ u32 hps2fpgaregs; /* 0x90 */
+ u32 acp;
+ u32 rom;
+ u32 ocram;
+ u32 sdrdata; /* 0xA0 */
+ u32 _pad_0xa4_0x1fd0[1995];
+ /* ID Register Group */
+ u32 periph_id_4; /* 0x1FD0 */
+ u32 _pad_0x1fd4_0x1fe0[3];
+ u32 periph_id_0; /* 0x1FE0 */
+ u32 periph_id_1;
+ u32 periph_id_2;
+ u32 periph_id_3;
+ u32 comp_id_0; /* 0x1FF0 */
+ u32 comp_id_1;
+ u32 comp_id_2;
+ u32 comp_id_3;
+ u32 _pad_0x2000_0x2008[2];
+ /* L4 MAIN */
+ u32 l4main_fn_mod_bm_iss;
+ u32 _pad_0x200c_0x3008[1023];
+ /* L4 SP */
+ u32 l4sp_fn_mod_bm_iss;
+ u32 _pad_0x300c_0x4008[1023];
+ /* L4 MP */
+ u32 l4mp_fn_mod_bm_iss;
+ u32 _pad_0x400c_0x5008[1023];
+ /* L4 OSC1 */
+ u32 l4osc_fn_mod_bm_iss;
+ u32 _pad_0x500c_0x6008[1023];
+ /* L4 SPIM */
+ u32 l4spim_fn_mod_bm_iss;
+ u32 _pad_0x600c_0x7008[1023];
+ /* STM */
+ u32 stm_fn_mod_bm_iss;
+ u32 _pad_0x700c_0x7108[63];
+ u32 stm_fn_mod;
+ u32 _pad_0x710c_0x8008[959];
+ /* LWHPS2FPGA */
+ u32 lwhps2fpga_fn_mod_bm_iss;
+ u32 _pad_0x800c_0x8108[63];
+ u32 lwhps2fpga_fn_mod;
+ u32 _pad_0x810c_0xa008[1983];
+ /* USB1 */
+ u32 usb1_fn_mod_bm_iss;
+ u32 _pad_0xa00c_0xa044[14];
+ u32 usb1_ahb_cntl;
+ u32 _pad_0xa048_0xb008[1008];
+ /* NANDDATA */
+ u32 nanddata_fn_mod_bm_iss;
+ u32 _pad_0xb00c_0xb108[63];
+ u32 nanddata_fn_mod;
+ u32 _pad_0xb10c_0x20008[21439];
+ /* USB0 */
+ u32 usb0_fn_mod_bm_iss;
+ u32 _pad_0x2000c_0x20044[14];
+ u32 usb0_ahb_cntl;
+ u32 _pad_0x20048_0x21008[1008];
+ /* NANDREGS */
+ u32 nandregs_fn_mod_bm_iss;
+ u32 _pad_0x2100c_0x21108[63];
+ u32 nandregs_fn_mod;
+ u32 _pad_0x2110c_0x22008[959];
+ /* QSPIDATA */
+ u32 qspidata_fn_mod_bm_iss;
+ u32 _pad_0x2200c_0x22044[14];
+ u32 qspidata_ahb_cntl;
+ u32 _pad_0x22048_0x23008[1008];
+ /* FPGAMGRDATA */
+ u32 fpgamgrdata_fn_mod_bm_iss;
+ u32 _pad_0x2300c_0x23040[13];
+ u32 fpgamgrdata_wr_tidemark; /* 0x23040 */
+ u32 _pad_0x23044_0x23108[49];
+ u32 fn_mod;
+ u32 _pad_0x2310c_0x24008[959];
+ /* HPS2FPGA */
+ u32 hps2fpga_fn_mod_bm_iss;
+ u32 _pad_0x2400c_0x24040[13];
+ u32 hps2fpga_wr_tidemark; /* 0x24040 */
+ u32 _pad_0x24044_0x24108[49];
+ u32 hps2fpga_fn_mod;
+ u32 _pad_0x2410c_0x25008[959];
+ /* ACP */
+ u32 acp_fn_mod_bm_iss;
+ u32 _pad_0x2500c_0x25108[63];
+ u32 acp_fn_mod;
+ u32 _pad_0x2510c_0x26008[959];
+ /* Boot ROM */
+ u32 bootrom_fn_mod_bm_iss;
+ u32 _pad_0x2600c_0x26108[63];
+ u32 bootrom_fn_mod;
+ u32 _pad_0x2610c_0x27008[959];
+ /* On-chip RAM */
+ u32 ocram_fn_mod_bm_iss;
+ u32 _pad_0x2700c_0x27040[13];
+ u32 ocram_wr_tidemark; /* 0x27040 */
+ u32 _pad_0x27044_0x27108[49];
+ u32 ocram_fn_mod;
+ u32 _pad_0x2710c_0x42024[27590];
+ /* DAP */
+ u32 dap_fn_mod2;
+ u32 dap_fn_mod_ahb;
+ u32 _pad_0x4202c_0x42100[53];
+ u32 dap_read_qos; /* 0x42100 */
+ u32 dap_write_qos;
+ u32 dap_fn_mod;
+ u32 _pad_0x4210c_0x43100[1021];
+ /* MPU */
+ u32 mpu_read_qos; /* 0x43100 */
+ u32 mpu_write_qos;
+ u32 mpu_fn_mod;
+ u32 _pad_0x4310c_0x44028[967];
+ /* SDMMC */
+ u32 sdmmc_fn_mod_ahb;
+ u32 _pad_0x4402c_0x44100[53];
+ u32 sdmmc_read_qos; /* 0x44100 */
+ u32 sdmmc_write_qos;
+ u32 sdmmc_fn_mod;
+ u32 _pad_0x4410c_0x45100[1021];
+ /* DMA */
+ u32 dma_read_qos; /* 0x45100 */
+ u32 dma_write_qos;
+ u32 dma_fn_mod;
+ u32 _pad_0x4510c_0x46040[973];
+ /* FPGA2HPS */
+ u32 fpga2hps_wr_tidemark; /* 0x46040 */
+ u32 _pad_0x46044_0x46100[47];
+ u32 fpga2hps_read_qos; /* 0x46100 */
+ u32 fpga2hps_write_qos;
+ u32 fpga2hps_fn_mod;
+ u32 _pad_0x4610c_0x47100[1021];
+ /* ETR */
+ u32 etr_read_qos; /* 0x47100 */
+ u32 etr_write_qos;
+ u32 etr_fn_mod;
+ u32 _pad_0x4710c_0x48100[1021];
+ /* EMAC0 */
+ u32 emac0_read_qos; /* 0x48100 */
+ u32 emac0_write_qos;
+ u32 emac0_fn_mod;
+ u32 _pad_0x4810c_0x49100[1021];
+ /* EMAC1 */
+ u32 emac1_read_qos; /* 0x49100 */
+ u32 emac1_write_qos;
+ u32 emac1_fn_mod;
+ u32 _pad_0x4910c_0x4a028[967];
+ /* USB0 */
+ u32 usb0_fn_mod_ahb;
+ u32 _pad_0x4a02c_0x4a100[53];
+ u32 usb0_read_qos; /* 0x4A100 */
+ u32 usb0_write_qos;
+ u32 usb0_fn_mod;
+ u32 _pad_0x4a10c_0x4b100[1021];
+ /* NAND */
+ u32 nand_read_qos; /* 0x4B100 */
+ u32 nand_write_qos;
+ u32 nand_fn_mod;
+ u32 _pad_0x4b10c_0x4c028[967];
+ /* USB1 */
+ u32 usb1_fn_mod_ahb;
+ u32 _pad_0x4c02c_0x4c100[53];
+ u32 usb1_read_qos; /* 0x4C100 */
+ u32 usb1_write_qos;
+ u32 usb1_fn_mod;
+};
+
+#endif /* _NIC301_REGISTERS_H_ */
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+void socfpga_bridges_reset(int enable);
+
+void socfpga_emac_reset(int enable);
+void socfpga_watchdog_reset(void);
+
struct socfpga_reset_manager {
u32 status;
u32 ctrl;
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
#endif
+#define RSTMGR_PERMODRST_EMAC0_LSB 0
+#define RSTMGR_PERMODRST_EMAC1_LSB 1
+#define RSTMGR_PERMODRST_L4WD0_LSB 6
+
#endif /* _RESET_MANAGER_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SOCFPGA_SCU_H__
+#define __SOCFPGA_SCU_H__
+
+struct scu_registers {
+ u32 ctrl; /* 0x00 */
+ u32 cfg;
+ u32 cpsr;
+ u32 iassr;
+ u32 _pad_0x10_0x3c[12]; /* 0x10 */
+ u32 fsar; /* 0x40 */
+ u32 fear;
+ u32 _pad_0x48_0x50[2];
+ u32 acr; /* 0x54 */
+ u32 sacr;
+};
+
+#endif /* __SOCFPGA_SCU_H__ */
#ifndef _SOCFPGA_BASE_ADDRS_H_
#define _SOCFPGA_BASE_ADDRS_H_
-#define SOCFPGA_L3REGS_ADDRESS 0xff800000
-#define SOCFPGA_UART0_ADDRESS 0xffc02000
-#define SOCFPGA_UART1_ADDRESS 0xffc03000
-#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
-#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
-#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
-#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
-#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
-#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
-#define SOCFPGA_EMAC0_ADDRESS 0xff700000
-#define SOCFPGA_EMAC1_ADDRESS 0xff702000
+#define SOCFPGA_STM_ADDRESS 0xfc000000
+#define SOCFPGA_DAP_ADDRESS 0xff000000
+#define SOCFPGA_EMAC0_ADDRESS 0xff700000
+#define SOCFPGA_EMAC1_ADDRESS 0xff702000
+#define SOCFPGA_SDMMC_ADDRESS 0xff704000
+#define SOCFPGA_QSPI_ADDRESS 0xff705000
+#define SOCFPGA_GPIO0_ADDRESS 0xff708000
+#define SOCFPGA_GPIO1_ADDRESS 0xff709000
+#define SOCFPGA_GPIO2_ADDRESS 0xff70a000
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_USB0_ADDRESS 0xffb00000
+#define SOCFPGA_USB1_ADDRESS 0xffb40000
+#define SOCFPGA_CAN0_ADDRESS 0xffc00000
+#define SOCFPGA_CAN1_ADDRESS 0xffc01000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_I2C0_ADDRESS 0xffc04000
+#define SOCFPGA_I2C1_ADDRESS 0xffc05000
+#define SOCFPGA_I2C2_ADDRESS 0xffc06000
+#define SOCFPGA_I2C3_ADDRESS 0xffc07000
+#define SOCFPGA_SDR_ADDRESS 0xffc20000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
+#define SOCFPGA_L4WD1_ADDRESS 0xffd03000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
+#define SOCFPGA_SPIS0_ADDRESS 0xffe02000
+#define SOCFPGA_SPIS1_ADDRESS 0xffe03000
+#define SOCFPGA_SPIM0_ADDRESS 0xfff00000
+#define SOCFPGA_SPIM1_ADDRESS 0xfff01000
+#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
+#define SOCFPGA_ROM_ADDRESS 0xfffd0000
+#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000
+#define SOCFPGA_MPUL2_ADDRESS 0xfffef000
+#define SOCFPGA_OCRAM_ADDRESS 0xffff0000
+#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000
+#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000
+#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000
+#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000
+#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000
+#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000
+#define SOCFPGA_NANDDATA_ADDRESS 0xff900000
+#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000
+#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000
+#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000
+#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000
+#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000
+#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */
/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#endif
-
-#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
-
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
- ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
-
struct socfpga_system_manager {
- u32 siliconid1;
+ /* System Manager Module */
+ u32 siliconid1; /* 0x00 */
u32 siliconid2;
u32 _pad_0x8_0xf[2];
- u32 wddbg;
+ u32 wddbg; /* 0x10 */
u32 bootinfo;
u32 hpsinfo;
u32 parityinj;
- u32 fpgaintfgrp_gbl;
+ /* FPGA Interface Group */
+ u32 fpgaintfgrp_gbl; /* 0x20 */
u32 fpgaintfgrp_indiv;
u32 fpgaintfgrp_module;
u32 _pad_0x2c_0x2f;
- u32 scanmgrgrp_ctrl;
+ /* Scan Manager Group */
+ u32 scanmgrgrp_ctrl; /* 0x30 */
u32 _pad_0x34_0x3f[3];
- u32 frzctrl_vioctrl;
+ /* Freeze Control Group */
+ u32 frzctrl_vioctrl; /* 0x40 */
u32 _pad_0x44_0x4f[3];
- u32 frzctrl_hioctrl;
+ u32 frzctrl_hioctrl; /* 0x50 */
u32 frzctrl_src;
u32 frzctrl_hwctrl;
u32 _pad_0x5c_0x5f;
- u32 emacgrp_ctrl;
+ /* EMAC Group */
+ u32 emacgrp_ctrl; /* 0x60 */
u32 emacgrp_l3master;
u32 _pad_0x68_0x6f[2];
- u32 dmagrp_ctrl;
+ /* DMA Controller Group */
+ u32 dmagrp_ctrl; /* 0x70 */
u32 dmagrp_persecurity;
u32 _pad_0x78_0x7f[2];
- u32 iswgrp_handoff[8];
- u32 _pad_0xa0_0xbf[8];
- u32 romcodegrp_ctrl;
+ /* Preloader (initial software) Group */
+ u32 iswgrp_handoff[8]; /* 0x80 */
+ u32 _pad_0xa0_0xbf[8]; /* 0xa0 */
+ /* Boot ROM Code Register Group */
+ u32 romcodegrp_ctrl; /* 0xc0 */
u32 romcodegrp_cpu1startaddr;
u32 romcodegrp_initswstate;
u32 romcodegrp_initswlastld;
- u32 romcodegrp_bootromswstate;
+ u32 romcodegrp_bootromswstate; /* 0xd0 */
u32 __pad_0xd4_0xdf[3];
- u32 romcodegrp_warmramgrp_enable;
+ /* Warm Boot from On-Chip RAM Group */
+ u32 romcodegrp_warmramgrp_enable; /* 0xe0 */
u32 romcodegrp_warmramgrp_datastart;
u32 romcodegrp_warmramgrp_length;
u32 romcodegrp_warmramgrp_execution;
- u32 romcodegrp_warmramgrp_crc;
+ u32 romcodegrp_warmramgrp_crc; /* 0xf0 */
u32 __pad_0xf4_0xff[3];
- u32 romhwgrp_ctrl;
+ /* Boot ROM Hardware Register Group */
+ u32 romhwgrp_ctrl; /* 0x100 */
u32 _pad_0x104_0x107;
+ /* SDMMC Controller Group */
u32 sdmmcgrp_ctrl;
u32 sdmmcgrp_l3master;
- u32 nandgrp_bootstrap;
+ /* NAND Flash Controller Register Group */
+ u32 nandgrp_bootstrap; /* 0x110 */
u32 nandgrp_l3master;
+ /* USB Controller Group */
u32 usbgrp_l3master;
u32 _pad_0x11c_0x13f[9];
- u32 eccgrp_l2;
+ /* ECC Management Register Group */
+ u32 eccgrp_l2; /* 0x140 */
u32 eccgrp_ocram;
u32 eccgrp_usb0;
u32 eccgrp_usb1;
- u32 eccgrp_emac0;
+ u32 eccgrp_emac0; /* 0x150 */
u32 eccgrp_emac1;
u32 eccgrp_dma;
u32 eccgrp_can0;
- u32 eccgrp_can1;
+ u32 eccgrp_can1; /* 0x160 */
u32 eccgrp_nand;
u32 eccgrp_qspi;
u32 eccgrp_sdmmc;
+ u32 _pad_0x170_0x3ff[164];
+ /* Pin Mux Control Group */
+ u32 emacio[20]; /* 0x400 */
+ u32 flashio[12]; /* 0x450 */
+ u32 generalio[28]; /* 0x480 */
+ u32 _pad_0x4f0_0x4ff[4];
+ u32 mixed1io[22]; /* 0x500 */
+ u32 mixed2io[8]; /* 0x558 */
+ u32 gplinmux[23]; /* 0x578 */
+ u32 gplmux[71]; /* 0x5d4 */
+ u32 nandusefpga; /* 0x6f0 */
+ u32 _pad_0x6f4;
+ u32 rgmii1usefpga; /* 0x6f8 */
+ u32 _pad_0x6fc_0x700[2];
+ u32 i2c0usefpga; /* 0x704 */
+ u32 sdmmcusefpga; /* 0x708 */
+ u32 _pad_0x70c_0x710[2];
+ u32 rgmii0usefpga; /* 0x714 */
+ u32 _pad_0x718_0x720[3];
+ u32 i2c3usefpga; /* 0x724 */
+ u32 i2c2usefpga; /* 0x728 */
+ u32 i2c1usefpga; /* 0x72c */
+ u32 spim1usefpga; /* 0x730 */
+ u32 _pad_0x734;
+ u32 spim0usefpga; /* 0x738 */
};
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1)
+#define SYSMGR_ECC_OCRAM_EN (1 << 0)
+#define SYSMGR_ECC_OCRAM_SERR (1 << 3)
+#define SYSMGR_ECC_OCRAM_DERR (1 << 4)
+#define SYSMGR_FPGAINTF_USEFPGA 0x1
+#define SYSMGR_FPGAINTF_SPIM0 (1 << 0)
+#define SYSMGR_FPGAINTF_SPIM1 (1 << 1)
+#define SYSMGR_FPGAINTF_EMAC0 (1 << 2)
+#define SYSMGR_FPGAINTF_EMAC1 (1 << 3)
+#define SYSMGR_FPGAINTF_NAND (1 << 4)
+#define SYSMGR_FPGAINTF_SDMMC (1 << 5)
+
+/* FIXME: This is questionable macro. */
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+ ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
+
#endif /* _SYSTEM_MANAGER_H_ */
DCACHE_OFF = 0x12,
DCACHE_WRITETHROUGH = 0x1a,
DCACHE_WRITEBACK = 0x1e,
+ DCACHE_WRITEALLOC = 0x16,
};
/* Size of an MMU section */
i++) {
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+ set_section_dcache(i, DCACHE_WRITEALLOC);
#else
set_section_dcache(i, DCACHE_WRITEBACK);
#endif
config TARGET_UC101
bool "Support uc101"
-config TARGET_MVBC_P
- bool "Support MVBC_P"
-
-config TARGET_MVSMR
- bool "Support MVSMR"
-
config TARGET_PCM030
bool "Support pcm030"
source "board/manroland/hmi1001/Kconfig"
source "board/manroland/mucmc52/Kconfig"
source "board/manroland/uc101/Kconfig"
-source "board/matrix_vision/mvbc_p/Kconfig"
-source "board/matrix_vision/mvsmr/Kconfig"
source "board/mcc200/Kconfig"
source "board/motionpro/Kconfig"
source "board/munices/Kconfig"
config TARGET_TUXX1
bool "Support tuxx1"
-config TARGET_MERGERBOX
- bool "Support MERGERBOX"
-
-config TARGET_MVBLM7
- bool "Support MVBLM7"
-
config TARGET_TQM834X
bool "Support TQM834x"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
source "board/keymile/km83xx/Kconfig"
-source "board/matrix_vision/mergerbox/Kconfig"
-source "board/matrix_vision/mvblm7/Kconfig"
source "board/mpc8308_p1m/Kconfig"
source "board/sbc8349/Kconfig"
source "board/tqc/tqm834x/Kconfig"
config TARGET_BAMBOO
bool "Support bamboo"
-config TARGET_BLUESTONE
- bool "Support bluestone"
-
config TARGET_BUBINGA
bool "Support bubinga"
config TARGET_V5FX30TEVAL
bool "Support v5fx30teval"
-config TARGET_CRAYL1
- bool "Support CRAYL1"
-
config TARGET_CATCENTER
bool "Support CATcenter"
config TARGET_P3P440
bool "Support p3p440"
-config TARGET_KAREF
- bool "Support KAREF"
-
-config TARGET_METROBOX
- bool "Support METROBOX"
-
config TARGET_XPEDITE1000
bool "Support xpedite1000"
source "board/amcc/acadia/Kconfig"
source "board/amcc/bamboo/Kconfig"
-source "board/amcc/bluestone/Kconfig"
source "board/amcc/bubinga/Kconfig"
source "board/amcc/canyonlands/Kconfig"
source "board/amcc/ebony/Kconfig"
source "board/amcc/yucca/Kconfig"
source "board/avnet/fx12mm/Kconfig"
source "board/avnet/v5fx30teval/Kconfig"
-source "board/cray/L1/Kconfig"
source "board/csb272/Kconfig"
source "board/csb472/Kconfig"
source "board/dave/PPChameleonEVB/Kconfig"
source "board/pcs440ep/Kconfig"
source "board/prodrive/alpr/Kconfig"
source "board/prodrive/p3p440/Kconfig"
-source "board/sandburst/karef/Kconfig"
-source "board/sandburst/metrobox/Kconfig"
source "board/sbc405/Kconfig"
source "board/sc3/Kconfig"
source "board/t3corp/Kconfig"
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif
-#if defined(CONFIG_APM821XX)
-#define SDR0_PINSTP_SHIFT 29
-static char *bootstrap_str[] = {
- "RESERVED",
- "RESERVED",
- "RESERVED",
- "NAND (8 bits)",
- "NOR (8 bits)",
- "NOR (8 bits) w/PLL Bypassed",
- "I2C (Addr 0x54)",
- "I2C (Addr 0x52)",
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
-#endif
#if defined(SDR0_PINSTP_SHIFT)
static int bootstrap_option(void)
reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
- !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE)
+ !defined(CONFIG_SYS_4xx_GPIO_TABLE)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
#if defined(CONFIG_405EX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+ defined(CONFIG_460SX)
/*
* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
*/
#elif defined(CONFIG_440)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+ defined(CONFIG_460SX)
static u8 pll_fwdv_multi_bits[] = {
/* values for: 1 - 16 */
0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
return 0;
}
-#if defined(CONFIG_APM821XX)
-
-void get_sys_info(sys_info_t *sysInfo)
-{
- unsigned long plld;
- unsigned long temp;
- unsigned long mul;
- unsigned long cpudv;
- unsigned long plb2dv;
- unsigned long ddr2dv;
-
- /* Calculate Forward divisor A and Feeback divisor */
- mfcpr(CPR0_PLLD, plld);
-
- temp = CPR0_PLLD_FWDVA(plld);
- sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
-
- temp = CPR0_PLLD_FDV(plld);
- sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
-
- /* Calculate OPB clock divisor */
- mfcpr(CPR0_OPBD, temp);
- temp = CPR0_OPBD_OPBDV(temp);
- sysInfo->pllOpbDiv = temp ? temp : 4;
-
- /* Calculate Peripheral clock divisor */
- mfcpr(CPR0_PERD, temp);
- temp = CPR0_PERD_PERDV(temp);
- sysInfo->pllExtBusDiv = temp ? temp : 4;
-
- /* Calculate CPU clock divisor */
- mfcpr(CPR0_CPUD, temp);
- temp = CPR0_CPUD_CPUDV(temp);
- cpudv = temp ? temp : 8;
-
- /* Calculate PLB2 clock divisor */
- mfcpr(CPR0_PLB2D, temp);
- temp = CPR0_PLB2D_PLB2DV(temp);
- plb2dv = temp ? temp : 4;
-
- /* Calculate DDR2 clock divisor */
- mfcpr(CPR0_DDR2D, temp);
- temp = CPR0_DDR2D_DDR2DV(temp);
- ddr2dv = temp ? temp : 4;
-
- /* Calculate 'M' based on feedback source */
- mfcpr(CPR0_PLLC, temp);
- temp = CPR0_PLLC_SEL(temp);
- if (temp == 0) {
- /* PLL internal feedback */
- mul = sysInfo->pllFbkDiv;
- } else {
- /* PLL PerClk feedback */
- mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv
- * plb2dv * 2 * sysInfo->pllOpbDiv *
- sysInfo->pllExtBusDiv;
- }
-
- /* Now calculate the individual clocks */
- sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1);
- sysInfo->freqProcessor = sysInfo->freqVCOMhz /
- sysInfo->pllFwdDivA / cpudv;
- sysInfo->freqPLB = sysInfo->freqVCOMhz /
- sysInfo->pllFwdDivA / cpudv / plb2dv / 2;
- sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
- sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
- sysInfo->freqDDR = sysInfo->freqVCOMhz /
- sysInfo->pllFwdDivA / cpudv / ddr2dv / 2;
- sysInfo->freqUART = sysInfo->freqPLB;
-}
-
-#else
/*
* AMCC_TODO: verify this routine against latest EAS, cause stuff changed
* with latest EAS
return;
}
-#endif
#elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460SX)
mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_APM821XX)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
lis r1, 0x0000
ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
mtdcr L2_CACHE_CFG,r1
ori r1,r1, 0x0980 /* fourth 64k */
mtdcr ISRAM0_SB3CR,r1
#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
- defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
+ defined(CONFIG_460GT)
lis r1,0x0000 /* BAS = X_0000_0000 */
ori r1,r1,0x0984 /* first 64k */
mtdcr ISRAM0_SB0CR,r1
lis r1, 0x0003
ori r1,r1, 0x0984 /* fourth 64k */
mtdcr ISRAM0_SB3CR,r1
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_APM821XX)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
lis r2,0x7fff
ori r2,r2,0xffff
mfdcr r1,ISRAM1_DPC
+++ /dev/null
-/*
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _APM821XX_H_
-#define _APM821XX_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
-
-/* Memory mapped registers */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-#define SDR0_SRST0_DMC 0x00200000
-#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
-
-/* AHB config. */
-#define AHB_TOP 0xA4
-#define AHB_BOT 0xA5
-
-/* clk divisors */
-#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
-#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
-#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
-#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
-#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
-#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/
-#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
-#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
-
-/*
- + * Clocking Controller
- + */
-#define CPR0_CLKUPD 0x0020
-#define CPR0_PLLC 0x0040
-#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24)
-#define CPR0_PLLD 0x0060
-#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24)
-#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16)
-#define CPR0_CPUD 0x0080
-#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24)
-#define CPR0_PLB2D 0x00a0
-#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25)
-#define CPR0_OPBD 0x00c0
-#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24)
-#define CPR0_PERD 0x00e0
-#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24)
-#define CPR0_DDR2D 0x0100
-#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25)
-#define CLK_ICFG 0x0140
-
-#endif /* _APM821XX_H_ */
#define EBC_NUM_BANKS 6
#endif
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_APM821XX)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define EBC_NUM_BANKS 3
#endif
/*
* Internal SRAM
*/
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_APM821XX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define ISRAM0_DCR_BASE 0x380
#else
#define ISRAM0_DCR_BASE 0x020
#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_APM821XX)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define ISRAM1_DCR_BASE 0x0B0
#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define ISRAM1_SIZE 0x0984 /* OCM size 64k */
-#elif defined(CONFIG_APM821XX)
-#define ISRAM1_SIZE 0x0784 /* OCM size 32k */
#endif
/*
#if defined (CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+ defined(CONFIG_460SX)
#define L2_CACHE_BASE 0x030
#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
*/
#if defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+ defined(CONFIG_460SX)
#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
/*
* Memory controller registers
*/
-#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
+#if defined(CONFIG_405EX)
#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
#define SDRAM_BEARL 0x02 /* PLB bus error address low */
#define SDRAM_PLBOPT 0x08 /* PLB slave options */
#define SDRAM_PUABA 0x09 /* PLB upper address base */
#define SDRAM_MCSTAT 0x1F /* memory controller status */
-#else /* CONFIG_405EX || CONFIG_APM821XX */
+#else /* CONFIG_405EX */
#define SDRAM_MCSTAT 0x14 /* memory controller status */
-#endif /* CONFIG_405EX || CONFIG_APM821XX */
+#endif /* CONFIG_405EX */
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
#define SDRAM_MEMODE 0x89 /* memory extended mode */
#define SDRAM_ECCES 0x98 /* ECC error status */
#define SDRAM_CID 0xA4 /* core ID */
-#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX)
+#if !defined(CONFIG_405EX)
#define SDRAM_RID 0xA8 /* revision ID */
#endif
#define SDRAM_FCSR 0xB0 /* feedback calibration status */
#define SDRAM_RTSR 0xB1 /* run time status tracking */
-#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
+#if defined(CONFIG_405EX)
#define SDRAM_RID 0xF8 /* revision ID */
#endif
*/
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+ defined(CONFIG_460SX)
#define UIC_MAX 4
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define VECNUM_ETH0 (32 + 28)
#endif /* CONFIG_440SPE */
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_APM821XX)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
/* UIC 0 */
#define VECNUM_UIC2NCI 10
#define VECNUM_UIC2CI 11
#include <asm/ppc460sx.h>
#endif
-#if defined(CONFIG_APM821XX)
-#include <asm/apm821xx.h>
-#endif
-
/*
* Common registers for all SoC's
*/
};
static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
+ {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
};
static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
+ {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
{OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
{OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
+ {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
/*
* MII2_CRS is shared with
* NAND_WAIT0
/* Info for driver */
#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
+#define CONFIG_HPS_CLK_OSC2_HZ 0
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
#ifdef CONFIG_SOCFPGA_ARRIA5
*/
int checkboard(void)
{
- puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
+ puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
return 0;
}
*/
int board_init(void)
{
- icache_enable();
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
return 0;
}
+++ /dev/null
-if TARGET_BLUESTONE
-
-config SYS_BOARD
- default "bluestone"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "bluestone"
-
-endif
+++ /dev/null
-BLUESTONE BOARD
-#M: Tirumala Marri <tmarri@apm.com>
-S: Orphan (since 2014-03)
-F: board/amcc/bluestone/
-F: include/configs/bluestone.h
-F: configs/bluestone_defconfig
+++ /dev/null
-#
-# Copyright (c) 2010, Applied Micro Circuits Corporation
-# Author: Tirumala R Marri <tmarri@apm.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bluestone.o
-extra-y += init.o
+++ /dev/null
-/*
- * Bluestone board support
- *
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/apm821xx.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx-gpio.h>
-
-int board_early_init_f(void)
-{
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC3SR, 0xffffffff); /* clear all */
- mtdcr(UIC3ER, 0x00000000); /* disable all */
- mtdcr(UIC3CR, 0x00000000); /* all non-critical */
- mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC3SR, 0xffffffff); /* clear all */
-
- /*
- * Configure PFC (Pin Function Control) registers
- * UART0: 2 pins
- */
- mtsdr(SDR0_PFC1, 0x0000000);
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: Bluestone Evaluation Board");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- u32 sdr0_srst1 = 0;
-
- /* Setup PLB4-AHB bridge based on the system address map */
- mtdcr(AHB_TOP, 0x8000004B);
- mtdcr(AHB_BOT, 0x8000004B);
-
- /*
- * The AHB Bridge core is held in reset after power-on or reset
- * so enable it now
- */
- mfsdr(SDR0_SRST1, sdr0_srst1);
- sdr0_srst1 &= ~SDR0_SRST1_AHB;
- mtsdr(SDR0_SRST1, sdr0_srst1);
-
- return 0;
-}
+++ /dev/null
-#
-# Copyright (c) 2010, Applied Micro Circuits Corporation
-# Author: Tirumala R Marri <tmarri@apm.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Applied Micro APM821XX Evaluation board.
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /* TLB 0 */
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
- 4, AC_RWX | SA_G)
-
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
- 0, AC_RWX | SA_G)
-
- /* TLB-entry for OCM */
- tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4,
- AC_RWX | SA_I)
-
- /* TLB-entry for Local Configuration registers => peripherals */
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K,
- CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG)
- tlbtab_end
+++ /dev/null
-bootscript.c
-bootscript.image
+++ /dev/null
-if TARGET_CRAYL1
-
-config SYS_BOARD
- default "L1"
-
-config SYS_VENDOR
- default "cray"
-
-config SYS_CONFIG_NAME
- default "CRAYL1"
-
-endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-i2c.h>
-#include <command.h>
-#include <rtc.h>
-#include <post.h>
-#include <net.h>
-#include <malloc.h>
-
-#define L1_MEMSIZE (32*1024*1024)
-
-/* the std. DHCP stufff */
-#define DHCP_ROUTER 3
-#define DHCP_NETMASK 1
-#define DHCP_BOOTFILE 67
-#define DHCP_ROOTPATH 17
-#define DHCP_HOSTNAME 12
-
-/* some extras used by CRAY
- *
- * on the server this looks like:
- *
- * option L1-initrd-image code 224 = string;
- * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image"
- */
-#define DHCP_L1_INITRD 224
-
-/* new, [better?] way via official vendor-extensions, defining an option
- * space.
- * on the server this looks like:
- *
- * option space CRAYL1;
- * option CRAYL1.initrd code 3 = string;
- * ..etc...
- */
-#define DHCP_VENDOR_SPECX 43
-#define DHCP_VX_INITRD 3
-#define DHCP_VX_BOOTCMD 4
-#define DHCP_VX_BOOTARGS 5
-#define DHCP_VX_ROOTDEV 6
-#define DHCP_VX_FROMFLASH 7
-#define DHCP_VX_BOOTSCRIPT 8
-#define DHCP_VX_RCFILE 9
-#define DHCP_VX_MAGIC 10
-
-/* Things DHCP server can tellme about. If there's no flash address, then
- * they dont participate in 'update' to flash, and we force their values
- * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I
- * know this is a pain...
- *
- * If I get no bootfile, boot from flash. If rootpath, use that. If no
- * rootpath use initrd in flash.
- */
-typedef struct dhcp_item_s {
- u8 dhcp_option;
- u8 dhcp_vendor_option;
- char *dhcpvalue;
- char *envname;
-} dhcp_item_t;
-static dhcp_item_t Things[] = {
- {DHCP_ROUTER, 0, NULL, "gateway"},
- {DHCP_NETMASK, 0, NULL, "netmask"},
- {DHCP_BOOTFILE, 0, NULL, "bootfile"},
- {DHCP_ROOTPATH, 0, NULL, "rootpath"},
- {DHCP_HOSTNAME, 0, NULL, "hostname"},
- {DHCP_L1_INITRD, 0, NULL, "initrd"},
-/* and the other way.. */
- {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"},
- {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"},
- {DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"},
- {DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"},
- {DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"},
- {DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"},
- {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL},
- {DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL}
-};
-
-#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t)))
-
-extern char bootscript[];
-
-/* Here is the boot logic as HUSH script. Overridden by any TFP provided
- * bootscript file.
- */
-
-static void init_sdram (void);
-
-/* ------------------------------------------------------------------------- */
-int board_early_init_f (void)
-{
- /* Running from ROM: global data is still READONLY */
- init_sdram ();
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-int checkboard (void)
-{
- return (0);
-}
-/* ------------------------------------------------------------------------- */
-
-/* ------------------------------------------------------------------------- */
-int misc_init_r (void)
-{
- char *s, *e;
- image_header_t *hdr;
- time_t timestamp;
- struct rtc_time tm;
- char bootcmd[32];
-
- hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ());
-#if defined(CONFIG_FIT)
- if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
- puts ("Non legacy image format not supported\n");
- return -1;
- }
-#endif
-
- timestamp = (time_t)image_get_time (hdr);
- to_tm (timestamp, &tm);
- printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
-
-#define FACTORY_SETTINGS 0xFFFC0000
- if ((s = getenv ("ethaddr")) == NULL) {
- e = (char *) (FACTORY_SETTINGS);
- if (*(e + 0) != '0'
- || *(e + 1) != '0'
- || *(e + 2) != ':'
- || *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') {
- printf ("No valid MAC address in flash location 0x3C0000!\n");
- } else {
- printf ("Factory MAC: %s\n", e);
- setenv ("ethaddr", e);
- }
- }
- sprintf (bootcmd,"source %X",(unsigned)bootscript);
- setenv ("bootcmd", bootcmd);
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-/* stubs so we can print dates w/o any nvram RTC.*/
-int rtc_get (struct rtc_time *tmp)
-{
- return 0;
-}
-int rtc_set (struct rtc_time *tmp)
-{
- return 0;
-}
-void rtc_reset (void)
-{
- return;
-}
-
-/* ------------------------------------------------------------------------- */
-/* Do sdram bank init in C so I can read it..no console to print to yet!
- */
-static void init_sdram (void)
-{
- unsigned long tmp;
-
- /* write SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- mtdcr (SDRAM0_CFGDATA, 0x00062001);
-
-/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
-/* To set the appropriate timings, we need to know the SDRAM speed. */
-/* We can use the PLB speed since the SDRAM speed is the same as */
-/* the PLB speed. The PLB speed is the FBK divider times the */
-/* 405GP reference clock, which on the L1 is 25MHz. */
-/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */
-/* 150MHz; if FBK is 3, SDRAM is 150MHz. */
-
- /* divisor = ((mfdcr(strap)>> 28) & 0x3); */
-
-/* write SDRAM timing for 100MHz. */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- mtdcr (SDRAM0_CFGDATA, 0x0086400D);
-
-/* write SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- mtdcr (SDRAM0_CFGDATA, 0x05F00000);
- udelay (200);
-
-/* sdram controller.*/
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, 0x90800000);
- udelay (200);
-
-/* initially, disable ECC on all banks */
- udelay (200);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- tmp = mfdcr (SDRAM0_CFGDATA);
- tmp &= 0xff0fffff;
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- mtdcr (SDRAM0_CFGDATA, tmp);
-
- return;
-}
-
-extern int memory_post_test (int flags);
-
-int testdram (void)
-{
- unsigned long tmp;
- uint *pstart = (uint *) 0x00000000;
- uint *pend = (uint *) L1_MEMSIZE;
- uint *p;
-
- if (getenv_f("booted",NULL,0) <= 0)
- {
- printf ("testdram..");
- /*AA*/
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
- (uint) p, *p, 0xaaaaaaaa);
- return 1;
- }
- }
- /*55*/
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
- (uint) p, *p, 0x55555555);
- return 1;
- }
- }
- /*addr*/
- for (p = pstart; p < pend; p++)
- *p = (unsigned)p;
- for (p = pstart; p < pend; p++) {
- if (*p != (unsigned)p) {
- printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
- (uint) p, *p, (uint)p);
- return 1;
- }
- }
- printf ("Success. ");
- }
- printf ("Enable ECC..");
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, tmp);
- udelay (600);
- for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
- ;
- udelay (400);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- tmp = mfdcr (SDRAM0_CFGDATA);
- tmp |= 0x00800000;
- mtdcr (SDRAM0_CFGDATA, tmp);
- udelay (400);
- printf ("enabled.\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-static u8 *dhcp_env_update (u8 thing, u8 * pop)
-{
- u8 i, oplen;
-
- oplen = *(pop + 1);
-
- if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) {
- printf ("Whoops! failed to malloc space for DHCP thing %s\n",
- Things[thing].envname);
- return NULL;
- }
- for (i = 0; (i < oplen); i++)
- if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ')
- break;
- *(Things[thing].dhcpvalue + i) = '\0';
-
-/* set env. */
- if (Things[thing].envname)
- {
- setenv (Things[thing].envname, Things[thing].dhcpvalue);
- }
- return ((u8 *)(Things[thing].dhcpvalue));
-}
-
-/* ------------------------------------------------------------------------- */
-u8 *dhcp_vendorex_prep (u8 * e)
-{
- u8 thing;
-
-/* ask for the things I want. */
- *e++ = 55; /* Parameter Request List */
- *e++ = N_THINGS;
- for (thing = 0; thing < N_THINGS; thing++)
- *e++ = Things[thing].dhcp_option;
- *e++ = 255;
-
- return e;
-}
-
-/* ------------------------------------------------------------------------- */
-/* .. return NULL means it wasnt mine, non-null means I got it..*/
-u8 *dhcp_vendorex_proc (u8 * pop)
-{
- u8 oplen, *sub_op, sub_oplen, *retval;
- u8 thing = 0;
-
- retval = NULL;
- oplen = *(pop + 1);
-/* if pop is vender spec indicator, there are sub-options. */
- if (*pop == DHCP_VENDOR_SPECX) {
- for (sub_op = pop + 2;
- oplen && (sub_oplen = *(sub_op + 1));
- oplen -= sub_oplen, sub_op += (sub_oplen + 2)) {
- for (thing = 0; thing < N_THINGS; thing++) {
- if (*sub_op == Things[thing].dhcp_vendor_option) {
- if (!(retval = dhcp_env_update (thing, sub_op))) {
- return NULL;
- }
- }
- }
- }
- } else {
- for (thing = 0; thing < N_THINGS; thing++) {
- if (*pop == Things[thing].dhcp_option)
- if (!(retval = dhcp_env_update (thing, pop)))
- return NULL;
- }
- }
- return (pop);
-}
+++ /dev/null
-L1 BOARD
-#M: David Updegraff <dave@cray.com>
-S: Orphan (since 2014-03)
-F: board/cray/L1/
-F: include/configs/CRAYL1.h
-F: configs/CRAYL1_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = L1.o flash.o
-obj-y += init.o
-obj-y += bootscript.o
-
-quiet_cmd_awk = AWK $@
- cmd_awk = od -t x1 -v -A x $< | $(AWK) -f $(filter-out $<,$^) > $@
-
-$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk
- $(call cmd,awk)
-
-MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \
- -a 0 -e 0 -n bootscript
-$(obj)/bootscript.image: $(src)/bootscript.hush
- $(call cmd,mkimage)
-
-clean-files := bootscript.c bootscript.image
+++ /dev/null
-# $Header$
-# hush bootscript for PPCBOOT on L1
-# note: all #s are in hex, do _NOT_ prefix it with 0x
-
-flash_rfs=ffc00000
-flash_krl=fff00000
-tftp_addr=100000
-tftp2_addr=1000000
-
-if printenv booted
-then
- echo already booted before
-else
- echo first boot in environment, create and save settings
- setenv booted OK
- saveenv
-fi
-
-setenv autoload no
-# clear out stale env stuff, so we get fresh from dhcp.
-for setting in initrd fromflash kernel rootfs rootpath
-do
-setenv $setting
-done
-
-dhcp
-
-# if host provides us with a different bootscript, us it.
-if printenv bootscript
- then
- tftp $tftp_addr $bootcript
- if imi $tftp_addr
- then
- source $tftp_addr
- fi
-fi
-
-# default base kernel arguments.
-setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120
-
-# Have a kernel in flash?
-if imi $flash_krl
-then
- echo ok kernel to boot from $flash_krl
- setenv kernel $flash_krl
-else
- echo no kernel to boot from $flash_krl, need tftp
-fi
-
-# Have a rootfs in flash?
-echo test for SQUASHfs at $flash_rfs
-
-if imi $flash_rfs
-then
- echo appears to be a good initrd image at base of flash OK
- setenv rootfs $flash_rfs
-else
- echo no image at base of flash, need nfsroot or initrd
-fi
-
-# I boot from flash if told to and I can.
-if printenv fromflash && printenv kernel && printenv rootfs
-then
- echo booting entirely from flash
- setenv bootargs root=/dev/ram0 rw $bootargs
- bootm $kernel $rootfs
- echo oh no failed so I try some other stuff
-fi
-
-# TFTP down a kernel
-if printenv bootfile
-then
- tftp $tftp_addr $bootfile
- setenv kernel $tftp_addr
- echo I will boot the TFTP kernel
-else
- if printenv kernel
- then
- echo no bootfile specified, will use one from flash
- else
- setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image
- echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile
- tftp $tftp_addr $bootfile
- setenv kernel $tftp_addr
- fi
-fi
-
-# the rootfs.
-if printenv rootpath
-then
- echo rootpath is $rootpath
- if printenv initrd
- then
- echo initrd is also specified, so use $initrd
- tftp $tftp2_addr $initrd
- setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs
- bootm $kernel $tftp2_addr
- else
- echo initrd is not specified, so use NFSROOT $rootpat
- setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs
- bootm $kernel
- fi
-else
- echo we have no rootpath check for one in flash
- if printenv rootfs
- then
- echo I will use the one in flash
- setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
- bootm $kernel
- else
- setenv rootpath /export/crayl1
- echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath
- setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
- bootm $kernel
- fi
-fi
-reset
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-/*
- * Modified July 20, 2001
- * Strip down to support ONLY the AMD29F032B.
- * Dave Updegraff - Cray, Inc. dave@cray.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/* The flash chip we use... */
-#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */
-#define FLASH_AM320B 0x0009
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Only one bank */
- if (CONFIG_SYS_MAX_FLASH_BANKS == 1)
- {
- /* Setup offsets */
- flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
-
-#if 0
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE0_PRELIM,
- FLASH_BASE0_PRELIM+monitor_flash_len-1,
- &flash_info[0]);
-#endif
- size_b1 = 0 ;
- flash_info[0].size = size_b0;
- }
-
- return (size_b0 + size_b1);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
-
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
-
- value = addr2[0];
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr2[1]; /* device ID */
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_ID_F032B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 64;
- info->size = 0x0400000; /* => 4 MB */
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = addr2[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-int wait_for_DQ7(flash_info_t *info, int sect)
-{
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
-
- start = get_timer (0);
- last = start;
- while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
- printf("Erasing sector %p\n", addr2);
-
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
- ulong start;
- int flag;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *)dest) &
- (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
- {
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-
-/*----------------------------------------------------------------------------- */
-/* Function: ext_bus_cntlr_init */
-/* Description: Initializes the External Bus Controller for the external */
-/* peripherals. IMPORTANT: For pass1 this code must run from */
-/* cache since you can not reliably change a peripheral banks */
-/* timing register (pbxap) while running code from that bank. */
-/* For ex., since we are running from ROM on bank 0, we can NOT */
-/* execute the code that modifies bank 0 timings from ROM, so */
-/* we run it from cache. */
-/* Bank 0 - Flash and SRAM */
-/* Bank 1 - NVRAM/RTC */
-/* Bank 2 - Keyboard/Mouse controller */
-/* Bank 3 - IR controller */
-/* Bank 4 - not used */
-/* Bank 5 - not used */
-/* Bank 6 - not used */
-/* Bank 7 - FPGA registers */
-/*-----------------------------------------------------------------------------#include <config.h> */
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
-/* except for #1 which we use for DMA'ing to IOCA-like things, so the */
-/* control registers to set that up are determined by what we've */
-/* empirically discovered work there. */
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 /* save link register */
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 10; used to prefetch */
- mtctr r4 /* 10 cache lines to fit this function */
- /* in cache (gives us 8x10=80 instrctns) */
-..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 10 cache lines */
-
- /*------------------------------------------------------------------- */
- /* Delay to ensure all accesses to ROM are complete before changing */
- /* bank 0 timings. 200usec should be enough. */
- /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
- /*------------------------------------------------------------------- */
- addis r3,0,0x0
- ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
-
- /*---------------------------------------------------------------------- */
- /* Peripheral Bank 0 (Flash) initialization */
- /*---------------------------------------------------------------------- */
- /* 0x7F8FFE80 slowest boot */
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x9B01
- ori r4,r4,0x5480
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
- ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
- mtdcr EBC0_CFGDATA,r4
-
- blr
-
- /*---------------------------------------------------------------------- */
- /* Peripheral Bank 1 (NVRAM/RTC) initialization */
- /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
- /* and we do DMA on it. The ConfigurationRegister part is threfore */
- /* almost arbitrary, except that our linux driver needs to know the */
- /* address, but it can query, it.. */
- /* */
- /* The AccessParameter is CRITICAL, */
- /* thouch, since it needs to agree with the electrical timings on the */
- /* IOCA parallel interface. That value is: 0x0185,4380 */
- /* BurstModeEnable BME=0 */
- /* TransferWait TWT=3 */
- /* ChipSelectOnTiming CSN=1 */
- /* OutputEnableOnTimimg OEN=1 */
- /* WriteByteEnableOnTiming WBN=1 */
- /* WriteByteEnableOffTiming WBF=0 */
- /* TransferHold TH=1 */
- /* ReadyEnable RE=1 */
- /* SampleOnReady SOR=1 */
- /* ByteEnableMode BEM=0 */
- /* ParityEnable PEN=0 */
- /* all reserved bits=0 */
- /*---------------------------------------------------------------------- */
- /*---------------------------------------------------------------------- */
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0185 /* hiword */
- ori r4,r4,0x4380 /* loword */
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB1CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
- ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
- mtdcr EBC0_CFGDATA,r4
-
- blr
+++ /dev/null
-# master confi.mk
-echo "CROSS_COMPILE = powerpc-linux-" >>include/config.mk
-
-# patch the examples/Makefile to ignore return value from OBJCOPY
-sed -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile
-
-# add a built target for mkimage on the target architecture
-sed -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile
-
-cat <<EOF >>tools/makefile
-mkimage.ppc : mkimage.o.ppc crc32.o.ppc
- powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^
- powerpc-linux-strip $@
-
-XFLAGS="-D__KERNEL__ -I../include -DCONFIG_4xx -Wall -Wstict-prototypes"
-mkimage.o.ppc: mkimage.c
- powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
-
-crc32.o.ppc: crc32.c
- powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
-
-EOF
-
-# make an image by default out of the u-boot image
-sed -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile
-cat <<EOF >>makefile
-u-boot.image: u-boot.bin
- tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@
-
-EOF
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#!/bin/awk
-BEGIN { print "unsigned char bootscript[] = { \n"}
-{ for (i = 2; i <= NF ; i++ ) printf "0x"$i","
- print ""
-}
-END { print "\n};\n" }
+++ /dev/null
-if TARGET_MERGERBOX
-
-config SYS_BOARD
- default "mergerbox"
-
-config SYS_VENDOR
- default "matrix_vision"
-
-config SYS_CONFIG_NAME
- default "MERGERBOX"
-
-endif
+++ /dev/null
-MERGERBOX BOARD
-#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
-S: Orphan (since 2014-03)
-F: board/matrix_vision/mergerbox/
-F: include/configs/MERGERBOX.h
-F: configs/MERGERBOX_defconfig
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mergerbox.o pci.o fpga.o sm107.o
+++ /dev/null
-Matrix Vision MergerBox
------------------------
-
-1. Board Description
-
- The MergerBox is a 120x160mm single board computing platform
- for 3D Full-HD digital video processing.
-
- Power Supply is 10-32VDC.
-
-2 System Components
-
-2.1 CPU
- Freescale MPC8377 CPU running at 800MHz core and 333MHz csb.
- 256 MByte DDR-II memory @ 333MHz data rate.
- 64 MByte Nor Flash on local bus.
- 1 GByte Nand Flash on FCM.
- 1 Vitesse VSC8601 RGMII ethernet Phys.
- 1 USB host controller over ULPI I/F with 4-Port hub.
- 2 serial ports. Console running on ttyS0 @ 115200 8N1.
- 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt.
- 2 PCIe x1 busses on local mPCIe and cutom expansion connector.
- 2 SATA host ports.
- System configuration (HRCW) is taken from I2C EEPROM.
-
-2.2 Graphics
- SM107 emebedded video controller driving a 5" 800x480 TFT panel.
- Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory.
-
-2.3 FPGA
- Altera Cyclone-IV EP4C115 with several PCI DMA engines.
- Connects to 7x Gennum 3G-SDI transceivers as video interconnect
- as well as a HDMI v1.4 compliant output for 3D monitoring.
- Utilizes two more DDR-II controllers providing 256MB memory.
-
-2.4 I2C
- Bus1:
- AD7418 @ 0x50 for voltage/temp. monitoring.
- SX8650 @ 0x90 touch controller for HMI.
- EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
- Bus2:
- mPCIe SMBus
- SiI9022A @ 0x72/0xC0 HDMI transmitter.
- TCA6416A @ 0x40 + 0x42 16-Bit I/O expander.
- LMH1983 @ 0xCA video PLL.
- DS1338C @ 0xD0 real-time clock with embedded crystal.
- 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock.
-
-3 Flash layout.
-
- reset vector is 0x00000100, i.e. low boot.
-
- 00000000 u-boot binary.
- 00100000 FPGA raw bit file.
- 00300000 FIT image holding kernel, dtb and rescue squashfs.
- 03d00000 u-boot environment.
- 03e00000 splash image
-
- mtd partitions are propagated to linux kernel via device tree blob.
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2011
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include "mergerbox.h"
-#include "fpga.h"
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
- fpga_null_fn,
- fpga_config_fn,
- fpga_status_fn,
- fpga_done_fn,
- fpga_wr_fn,
- fpga_null_fn,
- fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
- Altera_CYC2,
- passive_serial,
- Altera_EP2C20_SIZE,
- (void *) &altera_fns,
- NULL,
- 0
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mergerbox_init_fpga(void)
-{
- debug("Initialize FPGA interface\n");
- fpga_init();
- fpga_add(fpga_altera, &cyclone2);
-
- return 1;
-}
-
-int fpga_null_fn(int cookie)
-{
- return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
- u32 dvo = gpio->dat;
-
- dvo &= ~FPGA_CONFIG;
- gpio->dat = dvo;
- udelay(5);
- dvo |= FPGA_CONFIG;
- gpio->dat = dvo;
-
- return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
- int result = 0;
-
- udelay(10);
- debug("CONF_DONE check ... ");
- if (gpio->dat & FPGA_CONF_DONE) {
- debug("high\n");
- result = 1;
- } else
- debug("low\n");
-
- return result;
-}
-
-int fpga_status_fn(int cookie)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
- int result = 0;
-
- debug("STATUS check ... ");
- if (gpio->dat & FPGA_STATUS) {
- debug("high\n");
- result = 1;
- } else
- debug("low\n");
-
- return result;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
- u32 dvo = gpio->dat;
-
- debug("CLOCK %s\n", assert_clk ? "high" : "low");
- if (assert_clk)
- dvo |= FPGA_CCLK;
- else
- dvo &= ~FPGA_CCLK;
-
- if (flush)
- gpio->dat = dvo;
-
- return assert_clk;
-}
-
-static inline int _write_fpga(u8 val, int dump)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
- int i;
- u32 dvo = gpio->dat;
-
- if (dump)
- debug(" %02x -> ", val);
- for (i = 0; i < 8; i++) {
- dvo &= ~FPGA_CCLK;
- gpio->dat = dvo;
- dvo &= ~FPGA_DIN;
- if (dump)
- debug("%d ", val&1);
- if (val & 1)
- dvo |= FPGA_DIN;
- gpio->dat = dvo;
- dvo |= FPGA_CCLK;
- gpio->dat = dvo;
- val >>= 1;
- }
- if (dump)
- debug("\n");
-
- return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
- unsigned char *data = (unsigned char *) buf;
- int i;
-
- debug("fpga_wr: buf %p / size %d\n", buf, len);
- for (i = 0; i < len; i++)
- _write_fpga(data[i], 0);
- debug("\n");
-
- return FPGA_SUCCESS;
-}
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-extern int mergerbox_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
+++ /dev/null
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <spi.h>
-#include <asm/io.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-#include <fdt_support.h>
-#include <spd_sdram.h>
-#include "mergerbox.h"
-#include "fpga.h"
-#include "../common/mv_common.h"
-
-static void setup_serdes(void)
-{
- fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram(void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- printf("Testing DRAM from 0x%08x to 0x%08x\n",
- CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
-
- printf("DRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test passed.\n");
- return 0;
-}
-#endif
-
-phys_size_t initdram(int board_type)
-{
- u32 msize;
-
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;
-
- /* Enable PCI_CLK[0:1] */
- clk->occr |= 0xc0000000;
- udelay(2000);
-
-#if defined(CONFIG_SPD_EEPROM)
- msize = spd_sdram();
-#else
- immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- msize_log2 = __ilog2(msize);
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
- udelay(50000);
-
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
- udelay(1000);
-
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- udelay(1000);
-
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- __asm__ __volatile__("sync");
- udelay(1000);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- udelay(2000);
-#endif
- setup_serdes();
-
- return msize << 20;
-}
-
-int checkboard(void)
-{
- puts("Board: Matrix Vision MergerBox\n");
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- u16 dim;
- int result;
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (gpio83xx_t *)&immr->gpio[1];
- unsigned char mac[6], mac_verify[6];
- char *s = getenv("reset_env");
-
- for (dim = 10; dim < 180; dim += 5) {
- mergerbox_tft_dim(dim);
- udelay(100000);
- }
-
- if (s)
- mv_reset_environment();
-
- i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac));
-
- /* check if Matrix Vision prefix present and export to env */
- if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) {
- printf("valid MAC found in eeprom: %pM\n", mac);
- eth_setenv_enetaddr("ethaddr", mac);
- } else {
- printf("no valid MAC found in eeprom.\n");
-
- /* no: check the env */
- if (!eth_getenv_enetaddr("ethaddr", mac)) {
- printf("no valid MAC found in env either.\n");
- /* TODO: ask for valid MAC */
- } else {
- printf("valid MAC found in env: %pM\n", mac);
- printf("updating MAC in eeprom.\n");
-
- do {
- result = test_and_clear_bit(20, &gpio->dat);
- if (result)
- printf("unprotect EEPROM failed !\n");
- udelay(20000);
- } while(result);
-
- i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6);
- udelay(20000);
-
- do {
- result = test_and_set_bit(20, &gpio->dat);
- if (result)
- printf("protect EEPROM failed !\n");
- udelay(20000);
- } while(result);
-
- printf("verify MAC %pM ... ", mac);
- i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6);
-
- if (!strncmp((char *)mac, (char *)mac_verify, 6))
- printf("ok.\n");
- else
- /* TODO: retry or do something useful */
- printf("FAILED (got %pM) !\n", mac_verify);
- }
- }
-
- return 0;
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
- iopd->dat &= ~TFT_SPI_CPLD_CS;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
- iopd->dat |= TFT_SPI_CPLD_CS;
-}
-
-/* control backlight pwm (display brightness).
- * allow values 0-250 with 0 = turn off and 250 = max brightness
- */
-void mergerbox_tft_dim(u16 value)
-{
- struct spi_slave *slave;
- u16 din;
- u16 dout = 0;
-
- if (value > 0 && value < 250)
- dout = 0x4000 | value;
-
- slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH);
- spi_claim_bus(slave);
- spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END);
- spi_release_bus(slave);
- spi_free_slave(slave);
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
- fdt_fixup_dr_usb(blob, bd);
- ft_pci_setup(blob, bd);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MERGERBOX_H__
-#define __MERGERBOX_H__
-
-#define MV_GPIO
-
-/*
- * GPIO Bank 1
- */
-#define TFT_SPI_EN (0x80000000>>0)
-#define FPGA_CONFIG (0x80000000>>1)
-#define FPGA_STATUS (0x80000000>>2)
-#define FPGA_CONF_DONE (0x80000000>>3)
-#define FPGA_DIN (0x80000000>>4)
-#define FPGA_CCLK (0x80000000>>5)
-#define MAN_RST (0x80000000>>6)
-#define FPGA_SYS_RST (0x80000000>>7)
-#define WD_WDI (0x80000000>>8)
-#define TFT_RST (0x80000000>>9)
-#define HISCON_GPIO1 (0x80000000>>10)
-#define HISCON_GPIO2 (0x80000000>>11)
-#define B2B_GPIO2 (0x80000000>>12)
-#define CCU_GPIN (0x80000000>>13)
-#define CCU_GPOUT (0x80000000>>14)
-#define TFT_GPIO0 (0x80000000>>15)
-#define TFT_GPIO1 (0x80000000>>16)
-#define TFT_GPIO2 (0x80000000>>17)
-#define TFT_GPIO3 (0x80000000>>18)
-#define B2B_GPIO0 (0x80000000>>19)
-#define B2B_GPIO1 (0x80000000>>20)
-#define TFT_SPI_CPLD_CS (0x80000000>>21)
-#define TFT_SPI_CS (0x80000000>>22)
-#define CCU_PWR_EN (0x80000000>>23)
-#define B2B_GPIO3 (0x80000000>>24)
-#define CCU_PWR_STAT (0x80000000>>25)
-
-#define MV_GPIO1_DAT (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS)
-#define MV_GPIO1_OUT (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \
- TFT_SPI_CPLD_CS)
-#define MV_GPIO1_ODE (FPGA_CONFIG|MAN_RST)
-
-/*
- * GPIO Bank 2
- */
-#define SPI_FLASH_WP (0x80000000>>10)
-#define SYS_EEPROM_WP (0x80000000>>11)
-#define SPI_FLASH_CS (0x80000000>>22)
-
-#define MV_GPIO2_DAT (SYS_EEPROM_WP|SPI_FLASH_CS)
-#define MV_GPIO2_OUT (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS)
-#define MV_GPIO2_ODE 0
-
-void mergerbox_tft_dim(u16 value);
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-#include "mergerbox.h"
-#include "fpga.h"
-#include "../common/mv_common.h"
-
-static struct pci_region pci_regions[] = {
- {
- .bus_start = CONFIG_SYS_PCI_MEM_BASE,
- .phys_start = CONFIG_SYS_PCI_MEM_PHYS,
- .size = CONFIG_SYS_PCI_MEM_SIZE,
- .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- .bus_start = CONFIG_SYS_PCI_MMIO_BASE,
- .phys_start = CONFIG_SYS_PCI_MMIO_PHYS,
- .size = CONFIG_SYS_PCI_MMIO_SIZE,
- .flags = PCI_REGION_MEM
- },
- {
- .bus_start = CONFIG_SYS_PCI_IO_BASE,
- .phys_start = CONFIG_SYS_PCI_IO_PHYS,
- .size = CONFIG_SYS_PCI_IO_SIZE,
- .flags = PCI_REGION_IO
- }
-};
-
-static struct pci_region pcie_regions_0[] = {
- {
- .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
- .size = CONFIG_SYS_PCIE1_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
- .size = CONFIG_SYS_PCIE1_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-static struct pci_region pcie_regions_1[] = {
- {
- .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
- .size = CONFIG_SYS_PCIE2_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
- .size = CONFIG_SYS_PCIE2_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile sysconf83xx_t *sysconf = &immr->sysconf;
- volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile law83xx_t *pcie_law = sysconf->pcielaw;
- struct pci_region *reg[] = { pci_regions };
- struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-
- volatile gpio83xx_t *gpio;
- gpio = (gpio83xx_t *)&immr->gpio[0];
-
- gpio->dat = MV_GPIO1_DAT;
- gpio->odr = MV_GPIO1_ODE;
- gpio->dir = MV_GPIO1_OUT;
-
- gpio = (gpio83xx_t *)&immr->gpio[1];
-
- gpio->dat = MV_GPIO2_DAT;
- gpio->odr = MV_GPIO2_ODE;
- gpio->dir = MV_GPIO2_OUT;
-
- printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
- immr->sysconf.sicrl);
-
- /* Enable PCI_CLK[0:1] */
- clk->occr |= 0xc0000000;
- udelay(2000);
-
- mergerbox_init_fpga();
- mv_load_fpga();
-
- mergerbox_tft_dim(0);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- udelay(2000);
-
- mpc83xx_pci_init(1, reg);
-
- /* Deassert the resets in the control register */
- out_be32(&sysconf->pecr1, 0xE0008000);
- out_be32(&sysconf->pecr2, 0xE0008000);
- udelay(2000);
-
- out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- mpc83xx_pcie_init(2, pcie_reg);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <netdev.h>
-#include <sm501.h>
-#include <pci.h>
-#include "../common/mv_common.h"
-
-#ifdef CONFIG_VIDEO
-static const SMI_REGS init_regs_800x480[] = {
- /* set endianess to little endian */
- {0x0005c, 0x00000000},
- /* PCI drive 12mA */
- {0x00004, 0x42401001},
- /* current clock */
- {0x0003c, 0x310a1818},
- /* clocks for pm0... */
- {0x00040, 0x0002184f},
- {0x00044, 0x2a1a0a01},
- /* GPIO */
- {0x10008, 0x00000000},
- {0x1000C, 0x00000000},
- /* panel control regs */
- {0x80000, 0x0f017106},
- {0x80004, 0x0},
- {0x80008, 0x0},
- {0x8000C, 0x00000000},
- {0x80010, 0x0c800c80},
- /* width 0x320 */
- {0x80014, 0x03200000},
- /* height 0x1e0 */
- {0x80018, 0x01E00000},
- {0x8001C, 0x0},
- {0x80020, 0x01df031f},
- {0x80024, 0x041f031f},
- {0x80028, 0x00800347},
- {0x8002C, 0x020c01df},
- {0x80030, 0x000201e9},
- {0x80200, 0x00000000},
- /* ZV[0:7] */
- {0x00008, 0x00ff0000},
- /* 24-Bit TFT */
- {0x0000c, 0x3f000000},
- {0, 0}
-};
-
-/*
- * Returns SM107 register base address. First thing called in the driver.
- */
-unsigned int board_video_init(void)
-{
- pci_dev_t devbusfn;
- u32 addr;
-
- devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
- if (devbusfn != -1) {
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1,
- (u32 *)&addr);
- return addr & 0xfffffffe;
- }
-
- return 0;
-}
-
-/*
- * Called after initializing the SM501 and before clearing the screen.
- */
-void board_validate_screen(unsigned int base)
-{
-}
-
-/*
- * Returns SM107 framebuffer address
- */
-unsigned int board_video_get_fb(void)
-{
- pci_dev_t devbusfn;
- u32 addr;
-
- devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
- if (devbusfn != -1) {
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
- (u32 *)&addr);
- addr &= 0xfffffffe;
-#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
- addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
-#endif
- return addr;
- }
-
- printf("board_video_get_fb(): FAILED\n");
-
- return 0;
-}
-
-/*
- * Return a pointer to the initialization sequence.
- */
-const SMI_REGS *board_get_regs(void)
-{
- return init_regs_800x480;
-}
-
-int board_get_width(void)
-{
- return 800;
-}
-
-int board_get_height(void)
-{
- return 480;
-}
-#endif
+++ /dev/null
-if TARGET_MVBC_P
-
-config SYS_BOARD
- default "mvbc_p"
-
-config SYS_VENDOR
- default "matrix_vision"
-
-config SYS_CONFIG_NAME
- default "MVBC_P"
-
-endif
+++ /dev/null
-MVBC_P BOARD
-#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
-S: Orphan (since 2014-03)
-F: board/matrix_vision/mvbc_p/
-F: include/configs/MVBC_P.h
-F: configs/MVBC_P_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004-2008
-# Matrix-Vision GmbH, info@matrix-vision.de
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mvbc_p.o fpga.o
+++ /dev/null
-Matrix Vision mvBlueCOUGAR-P (mvBC-P)
--------------------------------------
-
-1. Board Description
-
- The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera
- with main focus on GigEVision protocol in combination with local image
- preprocessing.
-
- Power Supply is either VDC 48V or Pover over Ethernet (PoE).
-
-2 System Components
-
-2.1 CPU
- Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
- 64MB SDRAM @ 133MHz.
- 8 MByte Nor Flash on local bus.
- 1 serial ports. Console running on ttyS0 @ 115200 8N1.
-
-2.2 PCI
- PCI clock fixed at 66MHz. Arbitration inside FPGA.
- Intel GD82541ER network MAC/PHY and FPGA connected.
-
-2.3 FPGA
- Altera Cyclone-II EP2C8 with PCI DMA engine.
- Connects to Matrix Vision specific CCD/CMOS sensor interface.
- Utilizes 64MB Nand Flash.
-
-2.3.1 I/O @ FPGA
- 2 Outputs : photo coupler
- 2 Inputs : photo coupler
-
-2.4 I2C
- LM75 @ 0x90 for temperature monitoring.
- EEPROM @ 0xA0 for vendor specifics.
- image sensor interface (slave addresses depend on sensor)
-
-3 Flash layout.
-
- reset vector is 0x00000100, i.e. "LOWBOOT".
-
- FF800000 u-boot
- FF840000 u-boot script image
- FF850000 redundant u-boot script image
- FF860000 FPGA raw bit file
- FF8A0000 tbd.
- FF900000 root FS
- FFC00000 kernel
- FFFC0000 device tree blob
- FFFD0000 redundant device tree blob
- FFFE0000 environment
- FFFF0000 redundant environment
-
- mtd partitions are propagated to linux kernel via device tree blob.
-
-4 Booting
-
- On startup the bootscript @ FF840000 is executed. This script can be
- exchanged easily. Default boot mode is "boot from flash", i.e. system
- works stand-alone.
-
- This behaviour depends on some environment variables :
-
- "netboot" : yes ->try dhcp/bootp and boot from network.
- A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
- DHCP server configuration, e.g. to provide different images to
- different devices.
-
- During netboot the system tries to get 3 image files:
- 1. Kernel - name + data is given during BOOTP.
- 2. Initrd - name is stored in "initrd_name"
- 3. device tree blob - name is stored in "dtb_name"
- Fallback files are the flash versions.
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include "fpga.h"
-#include "mvbc_p.h"
-
-#ifdef FPGA_DEBUG
-#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
-#else
-#define fpga_debug(fmt, args...)
-#endif
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
- fpga_null_fn,
- fpga_config_fn,
- fpga_status_fn,
- fpga_done_fn,
- fpga_wr_fn,
- fpga_null_fn,
- fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
- Altera_CYC2,
- passive_serial,
- Altera_EP2C8_SIZE,
- (void *) &altera_fns,
- NULL,
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mvbc_p_init_fpga(void)
-{
- fpga_debug("Initialize FPGA interface\n");
- fpga_init();
- fpga_add(fpga_altera, &cyclone2);
- fpga_config_fn(0, 1, 0);
- udelay(60);
-
- return 1;
-}
-
-int fpga_null_fn(int cookie)
-{
- return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
- u32 dvo = gpio->simple_dvo;
-
- fpga_debug("SET config : %s\n", assert ? "low" : "high");
- if (assert)
- dvo |= FPGA_CONFIG;
- else
- dvo &= ~FPGA_CONFIG;
-
- if (flush)
- gpio->simple_dvo = dvo;
-
- return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
- int result = 0;
-
- udelay(10);
- fpga_debug("CONF_DONE check ... ");
- if (gpio->simple_ival & FPGA_CONF_DONE) {
- fpga_debug("high\n");
- result = 1;
- } else
- fpga_debug("low\n");
-
- return result;
-}
-
-int fpga_status_fn(int cookie)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
- int result = 0;
-
- fpga_debug("STATUS check ... ");
- if (gpio->sint_ival & FPGA_STATUS) {
- fpga_debug("high\n");
- result = 1;
- } else
- fpga_debug("low\n");
-
- return result;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
- u32 dvo = gpio->simple_dvo;
-
- fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
- if (assert_clk)
- dvo |= FPGA_CCLK;
- else
- dvo &= ~FPGA_CCLK;
-
- if (flush)
- gpio->simple_dvo = dvo;
-
- return assert_clk;
-}
-
-static inline int _write_fpga(u8 val)
-{
- int i;
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
- u32 dvo = gpio->simple_dvo;
-
- for (i=0; i<8; i++) {
- dvo &= ~FPGA_CCLK;
- gpio->simple_dvo = dvo;
- dvo &= ~FPGA_DIN;
- if (val & 1)
- dvo |= FPGA_DIN;
- gpio->simple_dvo = dvo;
- dvo |= FPGA_CCLK;
- gpio->simple_dvo = dvo;
- val >>= 1;
- }
-
- return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
- unsigned char *data = (unsigned char *) buf;
- int i;
-
- fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
- for (i = 0; i < len; i++)
- _write_fpga(data[i]);
- fpga_debug("\n");
-
- return FPGA_SUCCESS;
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-extern int mvbc_p_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2005-2007
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <malloc.h>
-#include <pci.h>
-#include <i2c.h>
-#include <fpga.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include "fpga.h"
-#include "mvbc_p.h"
-#include "../common/mv_common.h"
-
-#define SDRAM_MODE 0x00CD0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xD2322800
-#define SDRAM_CONFIG2 0x8AD70000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_start (int hi_addr)
-{
- long hi_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
-
- /* precharge all banks */
- out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
-
- /* precharge all banks */
- out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
-
- /* auto refresh */
- out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
-
- /* set mode register */
- out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
- /* normal operation */
- out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
-}
-
-phys_addr_t initdram (int board_type)
-{
- ulong dramsize = 0;
- ulong test1,
- test2;
-
- /* setup SDRAM chip selects */
- out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
-
- /* setup config registers */
- out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
- out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else
- dramsize = test2;
-
- if (dramsize < (1 << 20))
- dramsize = 0;
-
- if (dramsize > 0)
- out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
- __builtin_ffs(dramsize >> 20) - 1);
- else
- out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
-
- return dramsize;
-}
-
-void mvbc_init_gpio(void)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
- printf("Ports : 0x%08x\n", gpio->port_config);
- printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
-
- out_be32(&gpio->simple_ddr, SIMPLE_DDR);
- out_be32(&gpio->simple_dvo, SIMPLE_DVO);
- out_be32(&gpio->simple_ode, SIMPLE_ODE);
- out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
-
- out_8(&gpio->sint_ode, SINT_ODE);
- out_8(&gpio->sint_ddr, SINT_DDR);
- out_8(&gpio->sint_dvo, SINT_DVO);
- out_8(&gpio->sint_inten, SINT_INTEN);
- out_be16(&gpio->sint_itype, SINT_ITYPE);
- out_8(&gpio->sint_gpioe, SINT_GPIOEN);
-
- out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
- out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
- out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
- out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
-
- printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
- printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
-}
-
-int misc_init_r(void)
-{
- char *s = getenv("reset_env");
-
- if (!s) {
- if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
- return 0;
- udelay(50000);
- if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
- return 0;
- udelay(50000);
- if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
- return 0;
- }
- printf(" === FACTORY RESET ===\n");
- mv_reset_environment();
- saveenv();
-
- return -1;
-}
-
-int checkboard(void)
-{
- mvbc_init_gpio();
- printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
-
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
-}
-
-void flash_afterinit(ulong size)
-{
- out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
- size));
- out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
- size));
- out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
- size));
- out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
- size));
-}
-
-void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char line = 0xff;
- char *s = getenv("pci_latency");
- u32 base;
- u8 val = 0;
-
- if (s)
- val = simple_strtoul(s, NULL, 16);
-
- if (PCI_BUS(dev) == 0) {
- switch (PCI_DEV (dev)) {
- case 0xa: /* FPGA */
- line = 3;
- pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
- printf("found FPGA - enable arbitration\n");
- writel(0x03, (u32*)(base + 0x80c0));
- writel(0xf0, (u32*)(base + 0x8080));
- if (val)
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
- break;
- case 0xb: /* LAN */
- line = 2;
- if (val)
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
- break;
- case 0x1a:
- break;
- default:
- printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
- break;
- }
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
- }
-}
-
-struct pci_controller hose = {
- fixup_irq:pci_mvbc_fixup_irq
-};
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- mvbc_p_init_fpga();
- mv_load_fpga();
- pci_mpc5xxx_init(&hose);
-}
-
-void show_boot_progress(int val)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
- switch(val) {
- case BOOTSTAGE_ID_START: /* FPGA ok */
- setbits_be32(&gpio->simple_dvo, LED_G0);
- break;
- case BOOTSTAGE_ID_NET_ETH_INIT:
- setbits_be32(&gpio->simple_dvo, LED_G1);
- break;
- case BOOTSTAGE_ID_COPY_RAMDISK:
- setbits_be32(&gpio->simple_dvo, LED_Y);
- break;
- case BOOTSTAGE_ID_RUN_OS:
- setbits_be32(&gpio->simple_dvo, LED_R);
- break;
- default:
- break;
- }
-
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-}
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in FEC comes first */
- return pci_eth_init(bis);
-}
+++ /dev/null
-#ifndef __MVBC_H__
-#define __MVBC_H__
-
-#define LED_G0 MPC5XXX_GPIO_SIMPLE_PSC2_0
-#define LED_G1 MPC5XXX_GPIO_SIMPLE_PSC2_1
-#define LED_Y MPC5XXX_GPIO_SIMPLE_PSC2_2
-#define LED_R MPC5XXX_GPIO_SIMPLE_PSC2_3
-#define ARB_X_EN MPC5XXX_GPIO_WKUP_PSC2_4
-
-#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
-#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
-#define FPGA_CONF_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
-#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
-#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
-
-#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
-#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
-#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
-#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
-#define FACT_RST MPC5XXX_GPIO_WKUP_6
-#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
-
-#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \
- FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
-#define SIMPLE_DVO (FPGA_CONFIG)
-#define SIMPLE_ODE (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R)
-#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \
- FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
- WD_WDI | COP_PRESENT)
-
-#define SINT_ODE 0
-#define SINT_DDR 0
-#define SINT_DVO 0
-#define SINT_INTEN 0
-#define SINT_ITYPE 0
-#define SINT_GPIOEN (FPGA_STATUS)
-
-#define WKUP_ODE (MAN_RST)
-#define WKUP_DIR (ARB_X_EN|MAN_RST|WD_TS)
-#define WKUP_DO (ARB_X_EN|MAN_RST|WD_TS)
-#define WKUP_EN (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY)
-
-#endif
+++ /dev/null
-echo
-echo "==== running autoscript ===="
-echo
-setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
-setenv ramkernel setenv kernel_boot \${loadaddr}
-setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
-setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
-setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb
-setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
-setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
-setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
-setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
-if test ${console} = yes;
-then
-setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8
-else
-setenv addcons setenv bootargs \${bootargs} console=tty0
-fi
-setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1
-setenv set_static_ip setenv ipaddr \${static_ipaddr}
-setenv set_static_nm setenv netmask \${static_netmask}
-setenv set_static_gw setenv gatewayip \${static_gateway}
-setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
-setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
-if test ${oprofile} = yes;
-then
-setenv addprofile setenv bootargs \${bootargs} profile=\${profile}
-fi
-if test ${autoscript_boot} != no;
-then
- if test ${netboot} = yes;
- then
- bootp
- if test $? = 0;
- then
- echo "=== bootp succeeded -> netboot ==="
- run set_ip
- run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb
- else
- echo "=== netboot failed ==="
- fi
- fi
- run set_static_ip set_static_nm set_static_gw set_ip
- echo "=== bootfromflash ==="
- run cpdtb rundtb bootfromflash
-else
- echo "=== boot stopped with autoscript_boot no ==="
-fi
+++ /dev/null
-bootscript.img
+++ /dev/null
-if TARGET_MVBLM7
-
-config SYS_BOARD
- default "mvblm7"
-
-config SYS_VENDOR
- default "matrix_vision"
-
-config SYS_CONFIG_NAME
- default "MVBLM7"
-
-endif
+++ /dev/null
-MVBLM7 BOARD
-#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
-S: Orphan (since 2014-03)
-F: board/matrix_vision/mvblm7/
-F: include/configs/MVBLM7.h
-F: configs/MVBLM7_defconfig
+++ /dev/null
-#
-# Copyright (C) Freescale Semiconductor, Inc. 2006.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mvblm7.o pci.o fpga.o
-
-extra-y := bootscript.img
-
-MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script
-
-$(obj)/bootscript.img: $(src)/bootscript
- $(call cmd,mkimage)
+++ /dev/null
-Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
--------------------------------------
-
-1. Board Description
-
- The mvBL-M7 is a 120x120mm single board computing platform
- with strong focus on stereo image processing applications.
-
- Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
- on any port (requires add-on board).
-
-2 System Components
-
-2.1 CPU
- Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
- 512MByte DDR-II memory @ 133MHz.
- 8 MByte Nor Flash on local bus.
- 2 Vitesse VSC8601 RGMII ethernet Phys.
- 1 USB host controller over ULPI I/F.
- 2 serial ports. Console running on ttyS0 @ 115200 8N1.
- 1 SD-Card slot connected to SPI.
- System configuration (HRCW) is taken from I2C EEPROM.
-
-2.2 PCI
- A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
-
-2.3 FPGA
- Altera Cyclone-II EP2C20/35 with PCI DMA engines.
- Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
- Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.
-
-2.3.1 I/O @ FPGA
- 2x8 Outputs : Infineon High-Side Switches to Main Supply.
- 2x8 Inputs : Programmable input threshold + trigger capabilities
- 2 dedicated flash interfaces for illuminator boards.
- Cross trigger for chaining several boards.
-
-2.4 I2C
- Bus1:
- MAX5381 DAC @ 0x60 for 1st digital input threshold.
- LM75 @ 0x90 for temperature monitoring.
- EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
- 1st image sensor interface (slave addresses depend on sensor)
- Bus2:
- MAX5381 DAC @ 0x60 for 2nd digital input threshold.
- 2nd image sensor interface (slave addresses depend on sensor)
-
-3 Flash layout.
-
- reset vector is 0xFFF00100, i.e. "HIGHBOOT".
-
- FF800000 environment
- FF802000 redundant environment
- FF804000 u-boot script image
- FF806000 redundant u-boot script image
- FF808000 device tree blob
- FF80A000 redundant device tree blob
- FF80C000 tbd.
- FF80E000 tbd.
- FF810000 kernel
- FFC00000 root FS
- FFF00000 u-boot
- FFF80000 FPGA raw bit file
-
- mtd partitions are propagated to linux kernel via device tree blob.
-
-4 Booting
-
- On startup the bootscript @ FF804000 is executed. This script can be
- exchanged easily. Default boot mode is "boot from flash", i.e. system
- works stand-alone.
-
- This behaviour depends on some environment variables :
-
- "netboot" : yes ->try dhcp/bootp and boot from network.
- A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
- DHCP server configuration, e.g. to provide different images to
- different devices.
-
- During netboot the system tries to get 3 image files:
- 1. Kernel - name + data is given during BOOTP.
- 2. Initrd - name is stored in "initrd_name"
- 3. device tree blob - name is stored in "dtb_name"
- Fallback files are the flash versions.
+++ /dev/null
-echo
-echo "==== running autoscript ===="
-echo
-setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
-setenv ramkernel setenv kernel_boot \${loadaddr}
-setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
-setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
-setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb
-setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
-setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
-setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
-setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
-if test ${console} = yes;
-then
-setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8
-else
-setenv addcons setenv bootargs \${bootargs} console=tty0
-fi
-setenv set_static_ip setenv ipaddr \${static_ipaddr}
-setenv set_static_nm setenv netmask \${static_netmask}
-setenv set_static_gw setenv gatewayip \${static_gateway}
-setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
-setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
-if test ${autoscript_boot} != no;
-then
- if test ${netboot} = yes;
- then
- bootp
- if test $? = 0;
- then
- echo "=== bootp succeeded -> netboot ==="
- run set_ip
- run getdtb rundtb bootfromnet ramparam addcons bootdtb
- else
- echo "=== netboot failed ==="
- fi
- fi
- run set_static_ip set_static_nm set_static_gw set_ip
- echo "=== bootfromflash ==="
- run cpdtb rundtb bootfromflash
-else
- echo "=== boot stopped with autoscript_boot no ==="
-fi
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include "fpga.h"
-#include "mvblm7.h"
-
-#ifdef FPGA_DEBUG
-#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
-#else
-#define fpga_debug(fmt, args...)
-#endif
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
- fpga_null_fn,
- fpga_config_fn,
- fpga_status_fn,
- fpga_done_fn,
- fpga_wr_fn,
- fpga_null_fn,
- fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
- Altera_CYC2,
- passive_serial,
- Altera_EP2C20_SIZE,
- (void *) &altera_fns,
- NULL,
- 0
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mvblm7_init_fpga(void)
-{
- fpga_debug("Initialize FPGA interface\n");
- fpga_init();
- fpga_add(fpga_altera, &cyclone2);
- fpga_config_fn(0, 1, 0);
- udelay(60);
-
- return 1;
-}
-
-int fpga_null_fn(int cookie)
-{
- return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
- u32 dvo = gpio->dat;
-
- fpga_debug("SET config : %s\n", assert ? "low" : "high");
- if (assert)
- dvo |= FPGA_CONFIG;
- else
- dvo &= ~FPGA_CONFIG;
-
- if (flush)
- gpio->dat = dvo;
-
- return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
- int result = 0;
-
- udelay(10);
- fpga_debug("CONF_DONE check ... ");
- if (gpio->dat & FPGA_CONF_DONE) {
- fpga_debug("high\n");
- result = 1;
- } else
- fpga_debug("low\n");
-
- return result;
-}
-
-int fpga_status_fn(int cookie)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
- int result = 0;
-
- fpga_debug("STATUS check ... ");
- if (gpio->dat & FPGA_STATUS) {
- fpga_debug("high\n");
- result = 1;
- } else
- fpga_debug("low\n");
-
- return result;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
- u32 dvo = gpio->dat;
-
- fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
- if (assert_clk)
- dvo |= FPGA_CCLK;
- else
- dvo &= ~FPGA_CCLK;
-
- if (flush)
- gpio->dat = dvo;
-
- return assert_clk;
-}
-
-static inline int _write_fpga(u8 val, int dump)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
- int i;
- u32 dvo = gpio->dat;
-
- if (dump)
- fpga_debug(" %02x -> ", val);
- for (i = 0; i < 8; i++) {
- dvo &= ~FPGA_CCLK;
- gpio->dat = dvo;
- dvo &= ~FPGA_DIN;
- if (dump)
- fpga_debug("%d ", val&1);
- if (val & 1)
- dvo |= FPGA_DIN;
- gpio->dat = dvo;
- dvo |= FPGA_CCLK;
- gpio->dat = dvo;
- val >>= 1;
- }
- if (dump)
- fpga_debug("\n");
-
- return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
- unsigned char *data = (unsigned char *) buf;
- int i;
-
- fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
- for (i = 0; i < len; i++)
- _write_fpga(data[i], 0);
- fpga_debug("\n");
-
- return FPGA_SUCCESS;
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-extern int mvblm7_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
+++ /dev/null
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/mpc8349_pci.h>
-#include <pci.h>
-#include <spi.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-#include "../common/mv_common.h"
-#include "mvblm7.h"
-
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
- char *s = getenv("ddr_size");
-
- msize = CONFIG_SYS_DDR_SIZE;
- if (s) {
- u32 env_ddr_size = simple_strtoul(s, NULL, 10);
- if (env_ddr_size == 512)
- msize = 512;
- }
-
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1);
- ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1)
- return -1;
- }
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
- LAWAR_SIZE);
-
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-
- asm("sync;isync");
- udelay(600);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
- asm("sync;isync");
- udelay(500);
-
- return msize;
-}
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
- msize = fixed_sdram();
-
- /* return total bus RAM size(bytes) */
- return msize * 1024 * 1024;
-}
-
-int misc_init_r(void)
-{
- char *s = getenv("reset_env");
-
- if (s) {
- mv_reset_environment();
- }
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: Matrix Vision mvBlueLYNX-M7\n");
-
- return 0;
-}
-
-#ifdef CONFIG_HARD_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
- iopd->dat &= ~MVBLM7_MMC_CS;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
- iopd->dat |= ~MVBLM7_MMC_CS;
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-}
-
-#endif
+++ /dev/null
-#ifndef __MVBC_H__
-#define __MVBC_H__
-
-#define MV_GPIO
-
-#define FPGA_CONFIG 0x80000000
-#define FPGA_CCLK 0x40000000
-#define FPGA_DIN 0x20000000
-#define FPGA_STATUS 0x10000000
-#define FPGA_CONF_DONE 0x08000000
-
-#define WD_WDI 0x00400000
-#define WD_TS 0x00200000
-#define MAN_RST 0x00100000
-
-#define MV_GPIO_DAT (WD_TS)
-#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS)
-#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST)
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#include <pci.h>
-#include <mpc83xx.h>
-#include <fpga.h>
-#include "mvblm7.h"
-#include "fpga.h"
-#include "../common/mv_common.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- }
-};
-
-void pci_init_board(void)
-{
- int i;
- volatile immap_t *immr;
- volatile pcictrl83xx_t *pci_ctrl;
- volatile gpio83xx_t *gpio;
- volatile clk83xx_t *clk;
- volatile law83xx_t *pci_law;
- struct pci_region *reg[] = { pci_regions };
-
- immr = (immap_t *) CONFIG_SYS_IMMR;
- clk = (clk83xx_t *) &immr->clk;
- pci_ctrl = immr->pci_ctrl;
- pci_law = immr->sysconf.pcilaw;
- gpio = (volatile gpio83xx_t *)&immr->gpio[0];
-
- gpio->dat = MV_GPIO_DAT;
- gpio->odr = MV_GPIO_ODE;
- gpio->dir = MV_GPIO_OUT;
-
- printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
- immr->sysconf.sicrl);
-
- mvblm7_init_fpga();
- mv_load_fpga();
-
- gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
-
- /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
- clk->occr = 0xc0000000;
-
- pci_ctrl[0].gcr = 0;
- udelay(2000);
- pci_ctrl[0].gcr = 1;
-
- for (i = 0; i < 1000; ++i)
- udelay(1000);
-
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-}
+++ /dev/null
-bootscript.img
+++ /dev/null
-if TARGET_MVSMR
-
-config SYS_BOARD
- default "mvsmr"
-
-config SYS_VENDOR
- default "matrix_vision"
-
-config SYS_CONFIG_NAME
- default "MVSMR"
-
-endif
+++ /dev/null
-MVSMR BOARD
-#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
-S: Orphan (since 2014-03)
-F: board/matrix_vision/mvsmr/
-F: include/configs/MVSMR.h
-F: configs/MVSMR_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004-2008
-# Matrix-Vision GmbH, info@matrix-vision.de
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mvsmr.o fpga.o
-
-extra-y := bootscript.img
-
-MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script
-
-$(obj)/bootscript.img: $(src)/bootscript
- $(call cmd,mkimage)
+++ /dev/null
-Matrix Vision mvSMR
--------------------
-
-1. Board Description
-
- The mvSMR is a 75x130mm single image processing board used
- in automation. Power Supply is 24VDC.
-
-2 System Components
-
-2.1 CPU
- Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
- 64MB DDR-I @ 133MHz.
- 8 MByte Nor Flash on local bus.
- 2 serial ports. Console running on ttyS0 @ 115200 8N1.
-
-2.2 PCI
- PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core.
-
-2.3 FPGA
- Xilinx Spartan-3 XC3S200 with PCI DMA engine.
- Connects to Matrix Vision specific CCD/CMOS sensor interface.
-
-2.4 I2C
- EEPROM @ 0xA0 for vendor specifics.
- image sensor interface (slave addresses depend on sensor)
-
-3 Flash layout.
-
- reset vector is 0x00000100, i.e. "LOWBOOT".
-
- FF800000 u-boot
- FF806000 u-boot script image
- FF808000 u-boot environment
- FF840000 FPGA raw bit file
- FF880000 root FS
- FFF00000 kernel
-
-4 Booting
-
- On startup the bootscript @ FF806000 is executed. This script can be
- exchanged easily. Default boot mode is "boot from flash", i.e. system
- works stand-alone.
-
- This behaviour depends on some environment variables :
-
- "netboot" : yes ->try dhcp/bootp and boot from network.
- A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
- DHCP server configuration, e.g. to provide different images to
- different devices.
-
- During netboot the system tries to get 3 image files:
- 1. Kernel - name + data is given during BOOTP.
- 2. Initrd - name is stored in "initrd_name"
- Fallback files are the flash versions.
+++ /dev/null
-echo
-echo "==== running autoscript ===="
-echo
-setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
-setenv ramkernel 'setenv kernel_boot ${loadaddr}'
-setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
-setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
-setenv bootfromflash run flashkernel cpird addcons boot24
-setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
-if test ${console} = yes;
-then
-setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
-else
-setenv addcons 'setenv bootargs ${bootargs} console=tty0'
-fi
-setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
-setenv set_static_nm 'setenv netmask ${static_netmask}'
-setenv set_static_gw 'setenv gatewayip ${static_gateway}'
-setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
-if test ${servicemode} != yes;
-then
- echo "=== forced flash mode ==="
- run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
-fi
-if test ${autoscript_boot} != no;
-then
- if test ${netboot} = yes;
- then
- bootp
- if test $? = 0;
- then
- echo "=== bootp succeeded -> netboot ==="
- run set_ip bootfromnet addcons boot24
- else
- echo "=== netboot failed ==="
- fi
- fi
- echo "=== bootfromflash ==="
- run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
-else
- echo "=== boot stopped with autoscript_boot no ==="
-fi
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2010
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spartan3.h>
-#include <command.h>
-#include <asm/io.h>
-#include "fpga.h"
-#include "mvsmr.h"
-
-xilinx_spartan3_slave_serial_fns fpga_fns = {
- fpga_pre_config_fn,
- fpga_pgm_fn,
- fpga_clk_fn,
- fpga_init_fn,
- fpga_done_fn,
- fpga_wr_fn,
- 0
-};
-
-xilinx_desc spartan3 = {
- xilinx_spartan2,
- slave_serial,
- XILINX_XC3S200_SIZE,
- (void *) &fpga_fns,
- 0,
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mvsmr_init_fpga(void)
-{
- fpga_init();
- fpga_add(fpga_xilinx, &spartan3);
-
- return 1;
-}
-
-int fpga_init_fn(int cookie)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
- if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
- return 0;
-
- return 1;
-}
-
-int fpga_done_fn(int cookie)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
- int result = 0;
-
- udelay(10);
- if (in_be32(&gpio->simple_ival) & FPGA_DONE)
- result = 1;
-
- return result;
-}
-
-int fpga_pgm_fn(int assert, int flush, int cookie)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
- if (!assert)
- setbits_8(&gpio->sint_dvo, FPGA_STATUS);
- else
- clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
-
- return assert;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
- if (assert_clk)
- setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
- else
- clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
-
- return assert_clk;
-}
-
-int fpga_wr_fn(int assert_write, int flush, int cookie)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
- if (assert_write)
- setbits_be32(&gpio->simple_dvo, FPGA_DIN);
- else
- clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
-
- return assert_write;
-}
-
-int fpga_pre_config_fn(int cookie)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
- setbits_8(&gpio->sint_dvo, FPGA_STATUS);
-
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-extern int mvsmr_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_init_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(int assert_write, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_pre_config_fn(int cookie);
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2005-2010
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <malloc.h>
-#include <pci.h>
-#include <i2c.h>
-#include <fpga.h>
-#include <environment.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include "fpga.h"
-#include "mvsmr.h"
-#include "../common/mv_common.h"
-
-#define SDRAM_DDR 1
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x715f0f00
-#define SDRAM_CONFIG1 0xd3722930
-#define SDRAM_CONFIG2 0x46770000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_start(int hi_addr)
-{
- long hi_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
- hi_bit);
-
- /* precharge all banks */
- out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
- hi_bit);
-
- /* set mode register: extended mode */
- out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
-
- /* set mode register: reset DLL */
- out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
-
- /* precharge all banks */
- out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
- hi_bit);
-
- /* auto refresh */
- out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
- hi_bit);
-
- /* set mode register */
- out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
- /* normal operation */
- out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
-}
-
-phys_addr_t initdram(int board_type)
-{
- ulong dramsize = 0;
- ulong test1,
- test2;
-
- /* setup SDRAM chip selects */
- out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
-
- /* setup config registers */
- out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
- out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else
- dramsize = test2;
-
- if (dramsize < (1 << 20))
- dramsize = 0;
-
- if (dramsize > 0)
- out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
- __builtin_ffs(dramsize >> 20) - 1);
- else
- out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
-
- return dramsize;
-}
-
-void mvsmr_init_gpio(void)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
- struct mpc5xxx_wu_gpio *wu_gpio =
- (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
- struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
- printf("Ports : 0x%08x\n", gpio->port_config);
- printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
-
- out_be32(&gpio->simple_ddr, SIMPLE_DDR);
- out_be32(&gpio->simple_dvo, SIMPLE_DVO);
- out_be32(&gpio->simple_ode, SIMPLE_ODE);
- out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
-
- out_8(&gpio->sint_ode, SINT_ODE);
- out_8(&gpio->sint_ddr, SINT_DDR);
- out_8(&gpio->sint_dvo, SINT_DVO);
- out_8(&gpio->sint_inten, SINT_INTEN);
- out_be16(&gpio->sint_itype, SINT_ITYPE);
- out_8(&gpio->sint_gpioe, SINT_GPIOEN);
-
- out_8(&wu_gpio->ode, WKUP_ODE);
- out_8(&wu_gpio->ddr, WKUP_DIR);
- out_8(&wu_gpio->dvo, WKUP_DO);
- out_8(&wu_gpio->enable, WKUP_EN);
-
- out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
- out_be32(&timers->gpt1.emsr, 0x00000234);
- out_be32(&timers->gpt2.emsr, 0x00000234);
- out_be32(&timers->gpt3.emsr, 0x00000234);
- out_be32(&timers->gpt4.emsr, 0x00000234);
- out_be32(&timers->gpt5.emsr, 0x00000234);
- out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
- out_be32(&timers->gpt7.emsr, 0x00000024);
-}
-
-int misc_init_r(void)
-{
- char *s = getenv("reset_env");
-
- if (s) {
- printf(" === FACTORY RESET ===\n");
- mv_reset_environment();
- saveenv();
- }
-
- return -1;
-}
-
-void mvsmr_get_dbg_present(void)
-{
- struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
- struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
-
- if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
- setenv("dbg_present", "no\0");
- setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
- } else {
- setenv("dbg_present", "yes\0");
- setenv("bootstopkey", "s\0");
- setbits_8(&psc->command, PSC_RX_ENABLE);
- }
-}
-
-void mvsmr_get_service_mode(void)
-{
- struct mpc5xxx_wu_gpio *wu_gpio =
- (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-
- if (in_8(&wu_gpio->ival) & SERVICE_MODE)
- setenv("servicemode", "no\0");
- else
- setenv("servicemode", "yes\0");
-}
-
-int mvsmr_get_mac(void)
-{
- unsigned char mac[6];
- struct mpc5xxx_wu_gpio *wu_gpio =
- (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-
- if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
- setenv("lan_present", "no\0");
- return -1;
- } else
- setenv("lan_present", "yes\0");
-
- i2c_read(0x50, 0, 1, mac, 6);
-
- eth_setenv_enetaddr("ethaddr", mac);
-
- return 0;
-}
-
-int checkboard(void)
-{
- mvsmr_init_gpio();
- printf("Board: Matrix Vision mvSMR\n");
-
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
-}
-
-void flash_afterinit(ulong size)
-{
- out_be32((u32 *)MPC5XXX_BOOTCS_START,
- START_REG(CONFIG_SYS_BOOTCS_START | size));
- out_be32((u32 *)MPC5XXX_CS0_START,
- START_REG(CONFIG_SYS_BOOTCS_START | size));
- out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
- STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
- out_be32((u32 *)MPC5XXX_CS0_STOP,
- STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
-}
-
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
- mvsmr_get_dbg_present();
- mvsmr_get_service_mode();
- mvsmr_init_fpga();
- mv_load_fpga();
- pci_mpc5xxx_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
- if (!mvsmr_get_mac())
- return cpu_eth_init(bis);
-
- return pci_eth_init(bis);
-}
+++ /dev/null
-#include <pci.h>
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
-#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
-#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
-#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
-#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
-#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5
-#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6
-#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7
-#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8
-#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9
-
-#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
-#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
-#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
-#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
-#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6
-#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
-#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4
-#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4
-
-#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
- S_FPGA_CCLK)
-#define SIMPLE_DVO (FPGA_CONFIG)
-#define SIMPLE_ODE (FPGA_CONFIG)
-#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
- S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
-
-#define SINT_ODE 0x1
-#define SINT_DDR 0x3
-#define SINT_DVO 0x1
-#define SINT_INTEN 0
-#define SINT_ITYPE 0
-#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
-
-#define WKUP_ODE (MAN_RST | S_FPGA_STATUS)
-#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS)
-#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS)
-#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
- FLASH_RBY | UART_EN1 | LAN_PRSNT)
+++ /dev/null
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2010
- * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the first two sectors (=8KB) of our S29GL flash chip */
- arch/powerpc/cpu/mpc5xxx/start.o (.text*)
- arch/powerpc/cpu/mpc5xxx/traps.o (.text*)
- board/matrix_vision/common/built-in.o (.text*)
-
- /* This is only needed to force failure if size of above code will ever */
- /* increase and grow into reserved space. */
- . = ALIGN(0x2000); /* location counter has to be 0x4000 now */
- . += 0x4000; /* ->0x8000, i.e. move to env_offset */
-
- . = env_offset; /* ld error as soon as above ALIGN misplaces lc */
- common/env_embedded.o (.ppcenv)
-
- *(.text*)
- . = ALIGN(16);
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
sysconf->sc_sgpiodt2=reg; /* Data register */
}
+int board_early_init_f(void)
+{
+ spi_init_f();
+ return 0;
+}
/****************************************************************
* Last Stage Init
+++ /dev/null
-/*
- * (C) Copyright 2002-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * Ported from Ebony flash support
- * Travis B. Sawyer
- * Sandburst Corporation
- */
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
- {0xfff80000} /* Boot Flash */
-};
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long total_b = 0;
- unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
- unsigned short index = 0;
- int i;
-
-
- DEBUGF("\n");
- DEBUGF("FLASH: Index: %d\n", index);
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
-
- /* check whether the address is 0 */
- if (flash_addr_table[index][i] == 0) {
- continue;
- }
-
- /* call flash_get_size() to initialize sector address */
- size_b[i] = flash_get_size(
- (vu_long *)flash_addr_table[index][i], &flash_info[i]);
- flash_info[i].size = size_b[i];
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, size_b[i], size_b[i]<<20);
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
- }
-
- total_b += flash_info[i].size;
- }
-
- return total_b;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " "
- );
- }
- printf ("\n");
- return;
- }
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
-
- DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
-
- /* Write auto select command: read Manufacturer ID */
- udelay(10000);
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- udelay(1000);
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- udelay(1000);
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
- udelay(1000);
-
- value = addr2[0];
-
- DEBUGF("FLASH MANUFACT: %x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr2[1]; /* device ID */
-
- DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000; /* => 512 kb */
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (info->flash_id == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
- }
-
- /* reset to return to reading data */
- addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-int wait_for_DQ7(flash_info_t *info, int sect)
-{
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
-
- start = get_timer (0);
- last = start;
- while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
- DEBUGF("Erasing sector %p\n", addr2);
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
- for (i=0; i<50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
- }
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
+++ /dev/null
-/*
- * Copyright (C) 2005 Sandburst Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include "sb_common.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-long int fixed_sdram (void);
-
-/*************************************************************************
- * metrobox_get_master
- *
- * PRI_N - active low signal. If the GPIO pin is low we are the master
- *
- ************************************************************************/
-int sbcommon_get_master(void)
-{
- ppc440_gpio_regs_t *gpio_regs;
-
- gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
-
- if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) {
- return 0;
- }
- else {
- return 1;
- }
-}
-
-/*************************************************************************
- * metrobox_secondary_present
- *
- * Figure out if secondary/slave board is present
- *
- ************************************************************************/
-int sbcommon_secondary_present(void)
-{
- ppc440_gpio_regs_t *gpio_regs;
-
- gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
-
- if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES)
- return 0;
- else
- return 1;
-}
-
-/*************************************************************************
- * sbcommon_get_serial_number
- *
- * Retrieve the board serial number via the mac address in eeprom
- *
- ************************************************************************/
-unsigned short sbcommon_get_serial_number(void)
-{
- unsigned char buff[0x100];
- unsigned short sernum;
-
- /* Get the board serial number from eeprom */
- /* Initialize I2C */
- i2c_set_bus_num(0);
-
- /* Read 256 bytes in EEPROM */
- i2c_read (0x50, 0, 1, buff, 0x100);
-
- memcpy(&sernum, &buff[0xF4], 2);
- sernum /= 32;
-
- return (sernum);
-}
-
-/*************************************************************************
- * sbcommon_fans
- *
- * Spin up fans 2 & 3 to get some air moving. OS will take care
- * of the rest. This is mostly a precaution...
- *
- * Assumes i2c bus 1 is ready.
- *
- ************************************************************************/
-void sbcommon_fans(void)
-{
- /*
- * Attempt to turn on 2 of the fans...
- * Need to go through the bridge
- */
- i2c_set_bus_num(1);
- puts ("FANS: ");
-
- /* select fan4 through the bridge */
- i2c_reg_write(0x73, /* addr */
- 0x00, /* reg */
- 0x08); /* val = bus 4 */
-
- /* Turn on FAN 4 */
- i2c_reg_write(0x2e,
- 1,
- 0x80);
-
- i2c_reg_write(0x2e,
- 0,
- 0x19);
-
- /* Deselect bus 4 on the bridge */
- i2c_reg_write(0x73,
- 0x00,
- 0x00);
-
- /* select fan3 through the bridge */
- i2c_reg_write(0x73, /* addr */
- 0x00, /* reg */
- 0x04); /* val = bus 3 */
-
- /* Turn on FAN 3 */
- i2c_reg_write(0x2e,
- 1,
- 0x80);
-
- i2c_reg_write(0x2e,
- 0,
- 0x19);
-
- /* Deselect bus 3 on the bridge */
- i2c_reg_write(0x73,
- 0x00,
- 0x00);
-
- /* select fan2 through the bridge */
- i2c_reg_write(0x73, /* addr */
- 0x00, /* reg */
- 0x02); /* val = bus 4 */
-
- /* Turn on FAN 2 */
- i2c_reg_write(0x2e,
- 1,
- 0x80);
-
- i2c_reg_write(0x2e,
- 0,
- 0x19);
-
- /* Deselect bus 2 on the bridge */
- i2c_reg_write(0x73,
- 0x00,
- 0x00);
-
- /* select fan1 through the bridge */
- i2c_reg_write(0x73, /* addr */
- 0x00, /* reg */
- 0x01); /* val = bus 0 */
-
- /* Turn on FAN 1 */
- i2c_reg_write(0x2e,
- 1,
- 0x80);
-
- i2c_reg_write(0x2e,
- 0,
- 0x19);
-
- /* Deselect bus 1 on the bridge */
- i2c_reg_write(0x73,
- 0x00,
- 0x00);
-
- puts ("on\n");
- i2c_set_bus_num(0);
-
- return;
-
-}
-
-/*************************************************************************
- * initdram
- *
- * Initialize sdram
- *
- ************************************************************************/
-phys_size_t initdram (int board_type)
-{
- long dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram ();
-#else
- dram_size = fixed_sdram ();
-#endif
- return dram_size;
-}
-
-
-/*************************************************************************
- * testdram
- *
- *
- ************************************************************************/
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- printf("Testing SDRAM: ");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("OK\n");
- return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- *
- * Assumes: 128 MB, non-ECC, non-registered
- * PLB @ 133 MHz
- *
- ************************************************************************/
-long int fixed_sdram (void)
-{
- uint reg;
-
- /*--------------------------------------------------------------------
- * Setup some default
- *------------------------------------------------------------------*/
- mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
- mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
-
- /*--------------------------------------------------------------------
- * Setup for board-specific specific mem
- *------------------------------------------------------------------*/
- /*
- * Following for CAS Latency = 2.5 @ 133 MHz PLB
- */
- mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
- /* RA=10 RD=3 */
- mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
- mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
- mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
- udelay (400); /* Delay 200 usecs (min) */
-
- /*--------------------------------------------------------------------
- * Enable the controller, then wait for DCEN to complete
- *------------------------------------------------------------------*/
- mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
- for (;;) {
- mfsdram (SDRAM0_MCSTS, reg);
- if (reg & 0x80000000)
- break;
- }
-
- return (128 * 1024 * 1024); /* 128 MB */
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-/*************************************************************************
- * board_get_enetaddr
- *
- * Get the ethernet MAC address for the management ethernet from the
- * strap EEPROM. Note that is the BASE address for the range of
- * external ethernet MACs on the board. The base + 31 is the actual
- * mgmt mac address.
- *
- ************************************************************************/
-
-void board_get_enetaddr(int macaddr_idx, uchar *enet)
-{
- int i;
- unsigned short tmp;
- unsigned char buff[0x100], *cp;
-
- if (0 == macaddr_idx) {
-
- /* Initialize I2C */
- i2c_set_bus_num(0);
-
- /* Read 256 bytes in EEPROM */
- i2c_read (0x50, 0, 1, buff, 0x100);
-
- cp = &buff[0xF0];
-
- for (i = 0; i < 6; i++,cp++)
- enet[i] = *cp;
-
- memcpy(&tmp, &enet[4], 2);
- tmp += 31;
- memcpy(&enet[4], &tmp, 2);
-
- } else {
- enet[0] = 0x02;
- enet[1] = 0x00;
- enet[2] = 0x00;
- enet[3] = 0x00;
- enet[4] = 0x00;
- if (1 == sbcommon_get_master() ) {
- /* Master/Primary card */
- enet[5] = 0x01;
- } else {
- /* Slave/Secondary card */
- enet [5] = 0x02;
- }
- }
-
- return;
-}
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-
- return (ctrlc());
-}
-#endif
+++ /dev/null
-#ifndef __SBCOMMON_H__
-#define __SBCOMMON_H__
-/*
- * Copyright (C) 2005 Sandburst Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-
-/*
- * GPIO Settings
- */
-/* Chassis settings */
-#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */
-#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */
-
-/* Debug LEDs */
-#define SBCOMMON_GPIO_DBGLED_0 0x00000400
-#define SBCOMMON_GPIO_DBGLED_1 0x00000200
-#define SBCOMMON_GPIO_DBGLED_2 0x00100000
-#define SBCOMMON_GPIO_DBGLED_3 0x00000100
-
-#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \
- SBCOMMON_GPIO_DBGLED_1 | \
- SBCOMMON_GPIO_DBGLED_2 | \
- SBCOMMON_GPIO_DBGLED_3)
-
-#define SBCOMMON_GPIO_SYS_FAULT 0x00000080
-#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040
-#define SBCOMMON_GPIO_SYS_STATUS 0x00000020
-
-#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS)
-
-#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \
- SBCOMMON_GPIO_DBGLED_1 | \
- SBCOMMON_GPIO_DBGLED_2 | \
- SBCOMMON_GPIO_DBGLED_3 | \
- SBCOMMON_GPIO_SYS_STATUS)
-
-typedef struct ppc440_gpio_regs {
- volatile unsigned long out;
- volatile unsigned long tri_state;
- volatile unsigned long dummy[4];
- volatile unsigned long open_drain;
- volatile unsigned long in;
-} __attribute__((packed)) ppc440_gpio_regs_t;
-
-int sbcommon_get_master(void);
-int sbcommon_secondary_present(void);
-unsigned short sbcommon_get_serial_number(void);
-void sbcommon_fans(void);
-void board_get_enetaddr(int macaddr_idx, uchar *enet);
-
-#endif /* __SBCOMMON_H__ */
+++ /dev/null
-if TARGET_KAREF
-
-config SYS_BOARD
- default "karef"
-
-config SYS_VENDOR
- default "sandburst"
-
-config SYS_CONFIG_NAME
- default "KAREF"
-
-endif
+++ /dev/null
-KAREF BOARD
-#M: Travis Sawyer <travis.sawyer@sandburst.com>
-S: Orphan (since 2014-03)
-F: board/sandburst/karef/
-F: include/configs/KAREF.h
-F: configs/KAREF_defconfig
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2005
-# Sandburst Corporation
-# Travis B. Sawyer
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# TBS: add for debugging purposes
-ccflags-y += -DBUILDUSER='"$(shell whoami)"'
-
-obj-y = karef.o ../common/flash.o ../common/sb_common.o
-extra-y += init.o
+++ /dev/null
-#
-# (C) Copyright 2005
-# Sandburst Corporation
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# Sandburst Corporation Metrobox Reference Design
-# Travis B. Sawyer
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/* ****************************************************************
- * Common defs for reg spec for chip ka_of
- * Auto-generated by trex2: DO NOT HAND-EDIT!!
- * ****************************************************************
- */
-
-#ifndef HAL_KA_OF_AUTO_H
-#define HAL_KA_OF_AUTO_H
-
-
-/* ----------------------------------------------------------------
- * For block: 'ofem'
- */
-
-/* ---- Block instance addressing (for block-select) */
-#define OFEM_BLOCK_ADDR_BIT_L 6
-#define OFEM_BLOCK_ADDR_BIT_H 9
-#define OFEM_BLOCK_ADDR_WIDTH 4
-
-#define OFEM_ADDR 0x0
-
-/* ---- Reg addressing (within block) */
-#define OFEM_REG_ADDR_BIT_L 2
-#define OFEM_REG_ADDR_BIT_H 5
-#define OFEM_REG_ADDR_WIDTH 4
-
-
-/* ================================================================
- * ---- Register KA_OF_OFEM_REVISION */
-#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000
-#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK
-#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff
-#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31
-#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0
-
-/* ================================================================
- * ---- Register KA_OF_OFEM_RESET */
-#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004
-#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK
-#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff
-#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31
-#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0
-
-/* ================================================================
- * ---- Register KA_OF_OFEM_CNTL */
-#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018
-#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK
-#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff
-#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31
-#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0
-
-/* ================================================================
- * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c
-#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0
-
-/* ================================================================
- * ---- Register KA_OF_OFEM_INTERRUPT */
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008
-#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0
-
-/* ================================================================
- * ---- Register KA_OF_OFEM_INTERRUPT_MASK */
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c
-#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0
-
-/* ================================================================
- * ---- Register KA_OF_OFEM_SCRATCH */
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010
-#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0
-
-/* ================================================================
- * ---- Register KA_OF_OFEM_SCRATCH_MASK */
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014
-#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0
-
-/* ================================================================
- * Field info for register KA_OF_OFEM_REVISION */
-#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00
-#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8
-#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15
-#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8
-#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024
-#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff
-#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0
-#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7
-#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0
-#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_OF_OFEM_RESET */
-#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004
-#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2
-#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2
-#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2
-#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002
-#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1
-#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1
-#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1
-#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001
-#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0
-#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0
-#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0
-#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_OF_OFEM_CNTL */
-#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0
-#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6
-#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7
-#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6
-#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030
-#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4
-#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5
-#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4
-#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_OF_OFEM_INTERRUPT */
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_OF_OFEM_INTERRUPT_MASK */
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001
-
-/* ================================================================
- * Field info for register KA_OF_OFEM_SCRATCH */
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_OF_OFEM_SCRATCH_MASK */
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
-
-#endif /* matches #ifndef HAL_KA_OF_AUTO_H */
+++ /dev/null
-/* ****************************************************************
- * Common defs for reg spec for chip ka_sc
- * Auto-generated by trex2: DO NOT HAND-EDIT!!
- * ****************************************************************
- */
-
-#ifndef HAL_KA_SC_AUTO_H
-#define HAL_KA_SC_AUTO_H
-
-
-/* ----------------------------------------------------------------
- * For block: 'scan'
- */
-
-/* ---- Block instance addressing (for block-select) */
-#define SCAN_BLOCK_ADDR_BIT_L 7
-#define SCAN_BLOCK_ADDR_BIT_H 9
-#define SCAN_BLOCK_ADDR_WIDTH 3
-
-#define SCAN_ADDR 0x0
-
-/* ---- Reg addressing (within block) */
-#define SCAN_REG_ADDR_BIT_L 2
-#define SCAN_REG_ADDR_BIT_H 6
-#define SCAN_REG_ADDR_WIDTH 5
-
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_REVISION */
-#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000
-#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31
-#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_RESET */
-#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004
-#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31
-#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_STATUS */
-#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008
-#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31
-#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_CNTL */
-#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c
-#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31
-#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_BRD_INFO */
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020
-#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_SCAN_FROM_0 */
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024
-#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_SCAN_FROM_1 */
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028
-#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_SCAN_TO_0 */
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c
-#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_SCAN_TO_1 */
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030
-#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_SCAN_CTRL */
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034
-#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_PLL_CTRL */
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038
-#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c
-#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_DR_CLK_COUNT */
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040
-#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044
-#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048
-#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c
-#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_BRD_BRD_IN */
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050
-#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_MISC */
-#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054
-#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31
-#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_INTERRUPT */
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c
-#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_INTERRUPT_MASK */
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010
-#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_SCRATCH */
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014
-#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0
-
-/* ================================================================
- * ---- Register KA_SC_SCAN_SCRATCH_MASK */
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018
-#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_REVISION */
-#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00
-#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8
-#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15
-#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8
-#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023
-#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff
-#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7
-#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0
-#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_RESET */
-#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200
-#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9
-#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9
-#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9
-#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100
-#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8
-#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8
-#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8
-#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080
-#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7
-#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7
-#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7
-#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040
-#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6
-#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6
-#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6
-#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020
-#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5
-#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5
-#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5
-#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010
-#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4
-#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4
-#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4
-#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008
-#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3
-#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3
-#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3
-#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_STATUS */
-#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040
-#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6
-#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6
-#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6
-#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020
-#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5
-#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5
-#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5
-#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010
-#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4
-#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4
-#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4
-#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008
-#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3
-#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3
-#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3
-#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001
-#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0
-#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0
-#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_CNTL */
-#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400
-#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10
-#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10
-#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10
-#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200
-#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9
-#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9
-#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9
-#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001
-#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100
-#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8
-#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8
-#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8
-#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001
-#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0
-#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6
-#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7
-#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6
-#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030
-#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4
-#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5
-#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4
-#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_BRD_INFO */
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_SCAN_FROM_0 */
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_SCAN_FROM_1 */
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_SCAN_TO_0 */
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_SCAN_TO_1 */
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_SCAN_CTRL */
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_PLL_CTRL */
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_DR_CLK_COUNT */
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_BRD_BRD_IN */
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_MISC */
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_INTERRUPT */
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_INTERRUPT_MASK */
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_SCRATCH */
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register KA_SC_SCAN_SCRATCH_MASK */
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
-
-#endif /* matches #ifndef HAL_KA_SC_AUTO_H */
+++ /dev/null
-/*
-* Copyright (C) 2005 Sandburst Corporation
- * SPDX-License-Identifier: GPL-2.0+
-*/
-/*
- * Ported from Ebony init.S by Travis B. Sawyer
- */
-
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
- tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
- tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
- tlbtab_end
+++ /dev/null
-/*
- * Copyright (C) 2005 Sandburst Corporation
- * Travis B. Sawyer
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include "karef.h"
-#include "karef_version.h"
-#include <timestamp.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include "../common/sb_common.h"
-#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
- defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
-#include <net.h>
-#endif
-
-void fpga_init (void);
-
-KAREF_BOARD_ID_ST board_id_as[] =
-{
- {"Undefined"}, /* Not specified */
- {"Kamino Reference Design"},
- {"Reserved"}, /* Reserved for future use */
- {"Reserved"}, /* Reserved for future use */
-};
-
-KAREF_BOARD_ID_ST ofem_board_id_as[] =
-{
- {"Undefined"},
- {"1x10 + 10x2"},
- {"Reserved"},
- {"Reserved"},
-};
-
-/*************************************************************************
- * board_early_init_f
- *
- * Setup chip selects, initialize the Opto-FPGA, initialize
- * interrupt polarity and triggers.
- ************************************************************************/
-int board_early_init_f (void)
-{
- ppc440_gpio_regs_t *gpio_regs;
-
- /* Enable GPIO interrupts */
- mtsdr(SDR0_PFC0, 0x00103E00);
-
- /* Setup access for LEDs, and system topology info */
- gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
- gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
- gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
-
- /* Turn on all the leds for now */
- gpio_regs->out = SBCOMMON_GPIO_LEDS;
-
- /*--------------------------------------------------------------------+
- | Initialize EBC CONFIG
- +-------------------------------------------------------------------*/
- mtebc(EBC0_CFG,
- EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
- EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
- EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
- EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
- EBC_CFG_PR_32);
-
- /*--------------------------------------------------------------------+
- | 1/2 MB FLASH. Initialize bank 0 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB0AP,
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
- EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
- EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
- EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
- EBC_BXAP_PEN_DISABLED);
-
- mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
- /*--------------------------------------------------------------------+
- | 8KB NVRAM/RTC. Initialize bank 1 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB1AP,
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
- EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
- EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
- EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
- EBC_BXAP_PEN_DISABLED);
-
- mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
-
- /*--------------------------------------------------------------------+
- | Compact Flash, uses 2 Chip Selects (2 & 6)
- +-------------------------------------------------------------------*/
- mtebc(PB2AP,
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
- EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
- EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
- EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
- EBC_BXAP_PEN_DISABLED);
-
- mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
-
- /*--------------------------------------------------------------------+
- | KaRef Scan FPGA. Initialize bank 3 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB5AP,
- EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
- EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
- EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
- EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
- mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
- /*--------------------------------------------------------------------+
- | MAC A & B for Kamino. OFEM FPGA decodes the addresses
- | Initialize bank 4 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB4AP,
- EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
- EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
- EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
- EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
- mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
- EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
- /*--------------------------------------------------------------------+
- | OFEM FPGA Initialize bank 5 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB3AP,
- EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
- EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
- EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
- EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
-
- mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
-
- /*--------------------------------------------------------------------+
- | Compact Flash, uses 2 Chip Selects (2 & 6)
- +-------------------------------------------------------------------*/
- mtebc(PB6AP,
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
- EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
- EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
- EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
- EBC_BXAP_PEN_DISABLED);
-
- mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
-
- /*--------------------------------------------------------------------+
- | BME-32. Initialize bank 7 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB7AP,
- EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
- EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
- EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
- EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
- mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
- /*--------------------------------------------------------------------+
- * Setup the interrupt controller polarities, triggers, etc.
- +-------------------------------------------------------------------*/
- /*
- * Because of the interrupt handling rework to handle 440GX interrupts
- * with the common code, we needed to change names of the UIC registers.
- * Here the new relationship:
- *
- * U-Boot name 440GX name
- * -----------------------
- * UIC0 UICB0
- * UIC1 UIC0
- * UIC2 UIC1
- * UIC3 UIC2
- */
- mtdcr (UIC1SR, 0xffffffff); /* clear all */
- mtdcr (UIC1ER, 0x00000000); /* disable all */
- mtdcr (UIC1CR, 0x00000000); /* all non- critical */
- mtdcr (UIC1PR, 0xfffffe03); /* polarity */
- mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
- mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr (UIC2SR, 0xffffffff); /* clear all */
- mtdcr (UIC2ER, 0x00000000); /* disable all */
- mtdcr (UIC2CR, 0x00000000); /* all non-critical */
- mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
- mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
- mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (UIC2SR, 0xffffffff); /* clear all */
-
- mtdcr (UIC3SR, 0xffffffff); /* clear all */
- mtdcr (UIC3ER, 0x00000000); /* disable all */
- mtdcr (UIC3CR, 0x00000000); /* all non-critical */
- mtdcr (UIC3PR, 0xffff83ff); /* polarity */
- mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
- mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (UIC3SR, 0xffffffff); /* clear all */
-
- mtdcr (UIC0SR, 0xfc000000); /* clear all */
- mtdcr (UIC0ER, 0x00000000); /* disable all */
- mtdcr (UIC0CR, 0x00000000); /* all non-critical */
- mtdcr (UIC0PR, 0xfc000000);
- mtdcr (UIC0TR, 0x00000000);
- mtdcr (UIC0VR, 0x00000001);
-
- fpga_init();
-
- return 0;
-}
-
-
-/*************************************************************************
- * checkboard
- *
- * Dump pertinent info to the console
- ************************************************************************/
-int checkboard (void)
-{
- sys_info_t sysinfo;
- unsigned char brd_rev, brd_id;
- unsigned short sernum;
- unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
- unsigned char ofem_brd_rev, ofem_brd_id;
- KAREF_FPGA_REGS_ST *karef_ps;
- OFEM_FPGA_REGS_ST *ofem_ps;
-
- karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
- ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
-
- scan_id = (unsigned char)((karef_ps->revision_ul &
- SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
- >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
-
- scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
- >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
-
- brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
- >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
-
- brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
- >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
-
- ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
- >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
-
- ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
- >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
-
- if (0xF != ofem_brd_id) {
- ofem_id = (unsigned char)((ofem_ps->revision_ul &
- SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
- >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
-
- ofem_rev = (unsigned char)((ofem_ps->revision_ul &
- SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
- >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
- }
-
- get_sys_info (&sysinfo);
-
- sernum = sbcommon_get_serial_number();
-
- printf ("Board: Sandburst Corporation Kamino Reference Design "
- "Serial Number: %d\n", sernum);
- printf ("%s\n", KAREF_U_BOOT_REL_STR);
-
- printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
- if (sbcommon_get_master()) {
- printf("Slot 0 - Master\nSlave board");
- if (sbcommon_secondary_present())
- printf(" present\n");
- else
- printf(" not detected\n");
- } else {
- printf("Slot 1 - Slave\n\n");
- }
-
- printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev);
- printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id);
- if(0xF != ofem_brd_id) {
- printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev);
- printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev);
- }
-
- /* Fix the ack in the bme 32 */
- udelay(5000);
- out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
- asm("eieio");
-
-
- return (0);
-}
-
-/*************************************************************************
- * misc_init_f
- *
- * Initialize I2C bus one to gain access to the fans
- ************************************************************************/
-int misc_init_f (void)
-{
- /* Turn on fans 3 & 4 */
- sbcommon_fans();
-
- return (0);
-}
-
-/*************************************************************************
- * misc_init_r
- *
- * Do nothing.
- ************************************************************************/
-int misc_init_r (void)
-{
- unsigned short sernum;
- char envstr[255];
- uchar enetaddr[6];
- KAREF_FPGA_REGS_ST *karef_ps;
- OFEM_FPGA_REGS_ST *ofem_ps;
-
- if(NULL != getenv("secondserial")) {
- puts("secondserial is set, switching to second serial port\n");
- setenv("stderr", "serial1");
- setenv("stdout", "serial1");
- setenv("stdin", "serial1");
- }
-
- setenv("ubrelver", KAREF_U_BOOT_REL_STR);
-
- memset(envstr, 0, 255);
- sprintf (envstr, "Built %s %s by %s",
- U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
- setenv("bldstr", envstr);
- saveenv();
-
- if( getenv("autorecover")) {
- setenv("autorecover", NULL);
- saveenv();
- sernum = sbcommon_get_serial_number();
-
- printf("\nSetting up environment for automatic filesystem recovery\n");
- /*
- * Setup default bootargs
- */
- memset(envstr, 0, 255);
-
- sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
- "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
- sernum, sernum);
- setenv("bootargs", envstr);
-
- /*
- * Setup Default boot command
- */
- setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
- "fatload ide 0 8100000 pramdisk;"
- "bootm 8000000 8100000");
-
- printf("Done. Please type allow the system to continue to boot\n");
- }
-
- if( getenv("fakeled")) {
- karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
- ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
- ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
- karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
- setenv("bootdelay", "-1");
- saveenv();
- printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
- }
-
-#ifdef CONFIG_HAS_ETH0
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
- board_get_enetaddr(0, enetaddr);
- eth_setenv_enetaddr("ethaddr", enetaddr);
- }
-#endif
-
-#ifdef CONFIG_HAS_ETH1
- if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
- board_get_enetaddr(1, enetaddr);
- eth_setenv_enetaddr("eth1addr", enetaddr);
- }
-#endif
-
-#ifdef CONFIG_HAS_ETH2
- if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
- board_get_enetaddr(2, enetaddr);
- eth_setenv_enetaddr("eth2addr", enetaddr);
- }
-#endif
-
-#ifdef CONFIG_HAS_ETH3
- if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
- board_get_enetaddr(3, enetaddr);
- eth_setenv_enetaddr("eth3addr", enetaddr);
- }
-#endif
-
- return (0);
-}
-
-/*************************************************************************
- * ide_set_reset
- ************************************************************************/
-#ifdef CONFIG_IDE_RESET
-void ide_set_reset(int on)
-{
- KAREF_FPGA_REGS_ST *karef_ps;
- /* TODO: ide reset */
- karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
-
- if (on) {
- karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
- } else {
- karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
- }
-}
-#endif /* CONFIG_IDE_RESET */
-
-/*************************************************************************
- * fpga_init
- ************************************************************************/
-void fpga_init(void)
-{
- KAREF_FPGA_REGS_ST *karef_ps;
- OFEM_FPGA_REGS_ST *ofem_ps;
- unsigned char ofem_id;
- unsigned long tmp;
-
- /* Ensure we have power all around */
- udelay(500);
-
- karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
- tmp =
- SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
- SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
- SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
- SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
- SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
- SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
- SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
- SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
- SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
-
- karef_ps->reset_ul = tmp;
-
- /*
- * Wait a bit to allow the ofem fpga to get its brains
- */
- udelay(5000);
-
- /*
- * Check to see if the ofem is there
- */
- ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
- >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
- if(0xF != ofem_id) {
- tmp =
- SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
- SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
- SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
-
- ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
- ofem_ps->reset_ul = tmp;
-
- ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
- }
-
- karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
-
- asm("eieio");
-
- return;
-}
-
-int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned short sernum;
- char envstr[255];
-
- sernum = sbcommon_get_serial_number();
-
- memset(envstr, 0, 255);
- /*
- * Setup our ip address
- */
- sprintf(envstr, "10.100.70.%d", sernum);
-
- setenv("ipaddr", envstr);
- /*
- * Setup the host ip address
- */
- setenv("serverip", "10.100.17.10");
-
- /*
- * Setup default bootargs
- */
- memset(envstr, 0, 255);
-
- sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
- "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
- "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
- "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
- sernum, sernum, sernum);
-
- setenv("bootargs_nfs", envstr);
- setenv("bootargs", envstr);
-
- /*
- * Setup CF bootargs
- */
- memset(envstr, 0, 255);
-
- sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
- "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
- sernum, sernum);
-
- setenv("bootargs_cf", envstr);
-
- /*
- * Setup Default boot command
- */
- setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
- setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
-
- /*
- * Setup compact flash boot command
- */
- setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
-
- saveenv();
-
- return(1);
-}
-
-int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned short sernum;
- char envstr[255];
-
- sernum = sbcommon_get_serial_number();
-
- printf("\nSetting up environment for filesystem recovery\n");
- /*
- * Setup default bootargs
- */
- memset(envstr, 0, 255);
-
- sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
- "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
- sernum, sernum);
- setenv("bootargs", envstr);
-
- /*
- * Setup Default boot command
- */
-
- setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
- "fatload ide 0 8100000 pramdisk;"
- "bootm 8000000 8100000");
-
- printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
- " please type fsrecover.sh<cr>\n");
-
- return(1);
-}
-
-U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
- "Set environment to factory defaults", "");
-
-U_BOOT_CMD(karecover, 1, 1, karefRecover,
- "Set environment to allow for fs recovery", "");
+++ /dev/null
-#ifndef __KAREF_H__
-#define __KAREF_H__
-/*
- * (C) Copyright 2005
- * Sandburst Corporation
- * Travis B. Sawyer
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Ka Reference Design OFEM FPGA Registers & definitions */
-#include "hal_ka_sc_auto.h"
-#include "hal_ka_of_auto.h"
-
-typedef struct karef_board_id_s {
- const char name[40];
-} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST;
-
-/* SCAN FPGA */
-typedef struct karef_fpga_regs_s
-{
- volatile unsigned long revision_ul; /* Read Only */
- volatile unsigned long reset_ul; /* Read/Write */
- volatile unsigned long interrupt_ul; /* Read Only */
- volatile unsigned long mask_ul; /* Read/Write */
- volatile unsigned long scratch_ul; /* Read/Write */
- volatile unsigned long scrmask_ul; /* Read/Write */
- volatile unsigned long status_ul; /* Read Only */
- volatile unsigned long control_ul; /* Read/Write */
- volatile unsigned long boardinfo_ul; /* Read Only */
- volatile unsigned long scan_from0_ul; /* Read Only */
- volatile unsigned long scan_from1_ul; /* Read Only */
- volatile unsigned long scan_to0_ul; /* Read/Write */
- volatile unsigned long scan_to1_ul; /* Read/Write */
- volatile unsigned long scan_control_ul; /* Read/Write */
- volatile unsigned long pll_control_ul; /* Read/Write */
- volatile unsigned long core_clock_cnt_ul; /* Read/Write */
- volatile unsigned long dr_clock_cnt_ul; /* Read/Write */
- volatile unsigned long spi_clock_cnt_ul; /* Read/Write */
- volatile unsigned long brdout_data_ul; /* Read/Write */
- volatile unsigned long brdout_enable_ul; /* Read/Write */
- volatile unsigned long brdin_data_ul; /* Read Only */
- volatile unsigned long misc_ul; /* Read/Write */
-} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST;
-
-/* OFEM FPGA */
-typedef struct ofem_fpga_regs_s
-{
- volatile unsigned long revision_ul; /* Read Only */
- volatile unsigned long reset_ul; /* Read/Write */
- volatile unsigned long interrupt_ul; /* Read Only */
- volatile unsigned long mask_ul; /* Read/Write */
- volatile unsigned long scratch_ul; /* Read/Write */
- volatile unsigned long scrmask_ul; /* Read/Write */
- volatile unsigned long control_ul; /* Read/Write */
- volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */
-} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST;
-
-
-#endif /* __KAREF_H__ */
+++ /dev/null
-#ifndef _KAREF_VERSION_H_
-#define _KAREF_VERSION_H_
-/*
- * Copyright (C) 2005 Sandburst Corporation
- * Travis B. Sawyer
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#define KAREF_U_BOOT_REL_STR "Release 0.0.7"
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
- board/sandburst/karef/init.o (.text)
- arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
- arch/powerpc/cpu/ppc4xx/traps.o (.text)
- arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
- arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
- arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
- arch/powerpc/cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
-
-/* common/env_embedded.o(.text) */
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-if TARGET_METROBOX
-
-config SYS_BOARD
- default "metrobox"
-
-config SYS_VENDOR
- default "sandburst"
-
-config SYS_CONFIG_NAME
- default "METROBOX"
-
-endif
+++ /dev/null
-METROBOX BOARD
-#M: Travis Sawyer <travis.sawyer@sandburst.com>
-S: Orphan (since 2014-03)
-F: board/sandburst/metrobox/
-F: include/configs/METROBOX.h
-F: configs/METROBOX_defconfig
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2005
-# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# TBS: add for debugging purposes
-ccflags-y += -DBUILDUSER='"$(shell whoami)"'
-
-obj-y = metrobox.o ../common/flash.o ../common/sb_common.o
-extra-y += init.o
+++ /dev/null
-#
-# (C) Copyright 2005
-# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/* ****************************************************************
- * Common defs for reg spec for chip xc
- * Auto-generated by trex2: DO NOT HAND-EDIT!!
- * ****************************************************************
- */
-
-#ifndef HAL_XC_AUTO_H
-#define HAL_XC_AUTO_H
-
-/* ----------------------------------------------------------------
- * For block: 'xcvr_cntl'
- */
-
-/* ---- Block instance addressing (for block-select) */
-#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6
-#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9
-#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4
-
-#define XCVR_CNTL_ADDR 0x0
-
-/* ---- Reg addressing (within block) */
-#define XCVR_CNTL_REG_ADDR_BIT_L 2
-#define XCVR_CNTL_REG_ADDR_BIT_H 5
-#define XCVR_CNTL_REG_ADDR_WIDTH 4
-
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_REVISION */
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000
-#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_RESET */
-#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004
-#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_STATUS */
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008
-#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_CNTL */
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c
-#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_BRD_INFO */
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020
-#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024
-#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_INTERRUPT */
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c
-#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010
-#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_SCRATCH */
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014
-#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018
-#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_REVISION */
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_RESET */
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_STATUS */
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_CNTL */
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_BRD_INFO */
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_INTERRUPT */
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_SCRATCH */
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
-
-#endif /* matches #ifndef HAL_XC_AUTO_H */
+++ /dev/null
-/*
-* Copyright (C) 2005
-* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
- tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
- tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
- tlbtab_end
+++ /dev/null
-/*
- * Copyright (c) 2005
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include "metrobox.h"
-#include "metrobox_version.h"
-#include <timestamp.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include "../common/sb_common.h"
-#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
- defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
-#include <net.h>
-#endif
-
-void fpga_init (void);
-
-METROBOX_BOARD_ID_ST board_id_as[] =
-{ {"Undefined"}, /* Not specified */
- {"2x10Gb"}, /* 2 ports, 10 GbE */
- {"20x1Gb"}, /* 20 ports, 1 GbE */
- {"Reserved"}, /* Reserved for future use */
-};
-
-/*************************************************************************
- * board_early_init_f
- *
- * Setup chip selects, initialize the Opto-FPGA, initialize
- * interrupt polarity and triggers.
- ************************************************************************/
-int board_early_init_f (void)
-{
- ppc440_gpio_regs_t *gpio_regs;
-
- /* Enable GPIO interrupts */
- mtsdr(SDR0_PFC0, 0x00103E00);
-
- /* Setup access for LEDs, and system topology info */
- gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
- gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
- gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
-
- /* Turn on all the leds for now */
- gpio_regs->out = SBCOMMON_GPIO_LEDS;
-
- /*--------------------------------------------------------------------+
- | Initialize EBC CONFIG
- +-------------------------------------------------------------------*/
- mtebc(EBC0_CFG,
- EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
- EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
- EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
- EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
- EBC_CFG_PR_32);
-
- /*--------------------------------------------------------------------+
- | 1/2 MB FLASH. Initialize bank 0 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB0AP,
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
- EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
- EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
- EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
- EBC_BXAP_PEN_DISABLED);
-
- mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
- /*--------------------------------------------------------------------+
- | 8KB NVRAM/RTC. Initialize bank 1 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB1AP,
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
- EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
- EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
- EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
- EBC_BXAP_PEN_DISABLED);
-
- mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
-
- /*--------------------------------------------------------------------+
- | Compact Flash, uses 2 Chip Selects (2 & 6)
- +-------------------------------------------------------------------*/
- mtebc(PB2AP,
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
- EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
- EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
- EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
- EBC_BXAP_PEN_DISABLED);
-
- mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
-
- /*--------------------------------------------------------------------+
- | OPTO & OFEM FPGA. Initialize bank 3 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB3AP,
- EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
- EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
- EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
- EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
- mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
- /*--------------------------------------------------------------------+
- | MAC A for metrobox
- | MAC A & B for Kamino. OFEM FPGA decodes the addresses
- | Initialize bank 4 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB4AP,
- EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
- EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
- EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
- EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
- mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
- /*--------------------------------------------------------------------+
- | Metrobox MAC B Initialize bank 5 with default values.
- | KA REF FPGA Initialize bank 5 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB5AP,
- EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
- EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
- EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
- EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
- mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
- /*--------------------------------------------------------------------+
- | Compact Flash, uses 2 Chip Selects (2 & 6)
- +-------------------------------------------------------------------*/
- mtebc(PB6AP,
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
- EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
- EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
- EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
- EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
- EBC_BXAP_PEN_DISABLED);
-
- mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
-
- /*--------------------------------------------------------------------+
- | BME-32. Initialize bank 7 with default values.
- +-------------------------------------------------------------------*/
- mtebc(PB7AP,
- EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
- EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
- EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
- EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
- EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
- mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
- EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
- /*--------------------------------------------------------------------+
- * Setup the interrupt controller polarities, triggers, etc.
- +-------------------------------------------------------------------*/
- /*
- * Because of the interrupt handling rework to handle 440GX interrupts
- * with the common code, we needed to change names of the UIC registers.
- * Here the new relationship:
- *
- * U-Boot name 440GX name
- * -----------------------
- * UIC0 UICB0
- * UIC1 UIC0
- * UIC2 UIC1
- * UIC3 UIC2
- */
- mtdcr (UIC1SR, 0xffffffff); /* clear all */
- mtdcr (UIC1ER, 0x00000000); /* disable all */
- mtdcr (UIC1CR, 0x00000000); /* all non- critical */
- mtdcr (UIC1PR, 0xfffffe03); /* polarity */
- mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
- mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr (UIC2SR, 0xffffffff); /* clear all */
- mtdcr (UIC2ER, 0x00000000); /* disable all */
- mtdcr (UIC2CR, 0x00000000); /* all non-critical */
- mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
- mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
- mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (UIC2SR, 0xffffffff); /* clear all */
-
- mtdcr (UIC3SR, 0xffffffff); /* clear all */
- mtdcr (UIC3ER, 0x00000000); /* disable all */
- mtdcr (UIC3CR, 0x00000000); /* all non-critical */
- mtdcr (UIC3PR, 0xffff83ff); /* polarity */
- mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
- mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (UIC3SR, 0xffffffff); /* clear all */
-
- mtdcr (UIC0SR, 0xfc000000); /* clear all */
- mtdcr (UIC0ER, 0x00000000); /* disable all */
- mtdcr (UIC0CR, 0x00000000); /* all non-critical */
- mtdcr (UIC0PR, 0xfc000000);
- mtdcr (UIC0TR, 0x00000000);
- mtdcr (UIC0VR, 0x00000001);
-
- fpga_init();
-
- return 0;
-}
-
-/*************************************************************************
- * checkboard
- *
- * Dump pertinent info to the console
- ************************************************************************/
-int checkboard (void)
-{
- sys_info_t sysinfo;
- unsigned char brd_rev, brd_id;
- unsigned short sernum;
- unsigned char opto_rev, opto_id;
- OPTO_FPGA_REGS_ST *opto_ps;
-
- opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
-
- opto_rev = (unsigned char)((opto_ps->revision_ul &
- SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
- >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
-
- opto_id = (unsigned char)((opto_ps->revision_ul &
- SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
- >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
-
- brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
- SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
- >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
-
- brd_id = (unsigned char)((opto_ps->boardinfo_ul &
- SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
- >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
-
- get_sys_info (&sysinfo);
-
- sernum = sbcommon_get_serial_number();
- printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
- printf ("%s\n", METROBOX_U_BOOT_REL_STR);
-
- printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
- if (sbcommon_get_master()) {
- printf("Slot 0 - Master\nSlave board");
- if (sbcommon_secondary_present())
- printf(" present\n");
- else
- printf(" not detected\n");
- } else {
- printf("Slot 1 - Slave\n\n");
- }
-
- printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
- printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name);
-
- /* Fix the ack in the bme 32 */
- udelay(5000);
- out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
- asm("eieio");
-
-
- return (0);
-}
-
-/*************************************************************************
- * misc_init_f
- *
- * Initialize I2C bus one to gain access to the fans
- ************************************************************************/
-int misc_init_f (void)
-{
- /* Turn on fans */
- sbcommon_fans();
-
- return (0);
-}
-
-/*************************************************************************
- * misc_init_r
- *
- * Do nothing.
- ************************************************************************/
-int misc_init_r (void)
-{
- unsigned short sernum;
- char envstr[255];
- uchar enetaddr[6];
- unsigned char opto_rev;
- OPTO_FPGA_REGS_ST *opto_ps;
-
- opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
-
- if(NULL != getenv("secondserial")) {
- puts("secondserial is set, switching to second serial port\n");
- setenv("stderr", "serial1");
- setenv("stdout", "serial1");
- setenv("stdin", "serial1");
- }
-
- setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
-
- memset(envstr, 0, 255);
- sprintf (envstr, "Built %s %s by %s",
- U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
- setenv("bldstr", envstr);
- saveenv();
-
- if( getenv("autorecover")) {
- setenv("autorecover", NULL);
- saveenv();
- sernum = sbcommon_get_serial_number();
-
- printf("\nSetting up environment for automatic filesystem recovery\n");
- /*
- * Setup default bootargs
- */
- memset(envstr, 0, 255);
- sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
- "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
- sernum, sernum);
- setenv("bootargs", envstr);
-
- /*
- * Setup Default boot command
- */
- setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
- "fatload ide 0 8100000 pramdisk;"
- "bootm 8000000 8100000");
-
- printf("Done. Please type allow the system to continue to boot\n");
- }
-
- if( getenv("fakeled")) {
- setenv("bootdelay", "-1");
- saveenv();
- printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
- opto_rev = (unsigned char)((opto_ps->revision_ul &
- SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
- >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
-
- if(0x12 <= opto_rev) {
- opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
- }
- }
-
-#ifdef CONFIG_HAS_ETH0
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
- board_get_enetaddr(0, enetaddr);
- eth_setenv_enetaddr("ethaddr", enetaddr);
- }
-#endif
-
-#ifdef CONFIG_HAS_ETH1
- if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
- board_get_enetaddr(1, enetaddr);
- eth_setenv_enetaddr("eth1addr", enetaddr);
- }
-#endif
-
-#ifdef CONFIG_HAS_ETH2
- if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
- board_get_enetaddr(2, enetaddr);
- eth_setenv_enetaddr("eth2addr", enetaddr);
- }
-#endif
-
-#ifdef CONFIG_HAS_ETH3
- if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
- board_get_enetaddr(3, enetaddr);
- eth_setenv_enetaddr("eth3addr", enetaddr);
- }
-#endif
-
- return (0);
-}
-
-/*************************************************************************
- * ide_set_reset
- ************************************************************************/
-#ifdef CONFIG_IDE_RESET
-void ide_set_reset(int on)
-{
- OPTO_FPGA_REGS_ST *opto_ps;
- opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
-
- if (on) { /* assert RESET */
- opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
- } else { /* release RESET */
- opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
- }
-}
-#endif /* CONFIG_IDE_RESET */
-
-/*************************************************************************
- * fpga_init
- ************************************************************************/
-void fpga_init(void)
-{
- OPTO_FPGA_REGS_ST *opto_ps;
- unsigned char opto_rev;
- unsigned long tmp;
-
- /* Ensure we have power all around */
- udelay(500);
-
- /*
- * Take appropriate hw bits out of reset
- */
- opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
-
- tmp =
- SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
- SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
- opto_ps->reset_ul = tmp;
- /*
- * Turn on the 'Slow Blink' for the System Error Led.
- * Ensure FPGA rev is up to at least rev 0x12
- */
- opto_rev = (unsigned char)((opto_ps->revision_ul &
- SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
- >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
- if(0x12 <= opto_rev) {
- opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
- }
-
- asm("eieio");
-
- return;
-}
-
-int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned short sernum;
- char envstr[255];
-
- sernum = sbcommon_get_serial_number();
-
- memset(envstr, 0, 255);
- /*
- * Setup our ip address
- */
- sprintf(envstr, "10.100.60.%d", sernum);
-
- setenv("ipaddr", envstr);
- /*
- * Setup the host ip address
- */
- setenv("serverip", "10.100.17.10");
-
- /*
- * Setup default bootargs
- */
- memset(envstr, 0, 255);
-
- sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
- "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
- "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
- ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
- sernum, sernum, sernum);
-
- setenv("bootargs_nfs", envstr);
- setenv("bootargs", envstr);
-
- /*
- * Setup CF bootargs
- */
- memset(envstr, 0, 255);
- sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
- "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
- sernum, sernum);
-
- setenv("bootargs_cf", envstr);
-
- /*
- * Setup Default boot command
- */
- setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
- setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
-
- /*
- * Setup compact flash boot command
- */
- setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
-
- saveenv();
-
-
- return(1);
-}
-
-int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned short sernum;
- char envstr[255];
-
- sernum = sbcommon_get_serial_number();
-
- printf("\nSetting up environment for filesystem recovery\n");
- /*
- * Setup default bootargs
- */
- memset(envstr, 0, 255);
- sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
- "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
- sernum, sernum);
-
- setenv("bootargs", envstr);
-
- /*
- * Setup Default boot command
- */
- setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
- "fatload ide 0 8100000 pramdisk;"
- "bootm 8000000 8100000");
-
- printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
- " please type fsrecover.sh<cr>\n");
-
- return(1);
-}
-
-U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
- "Set environment to factory defaults", "");
-
-U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
- "Set environment to allow for fs recovery", "");
+++ /dev/null
-#ifndef __METROBOX_H__
-#define __METROBOX_H__
-/*
- * (C) Copyright 2005
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-typedef struct metrobox_board_id_s {
- const char name[40];
-} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST;
-
-
-/* Metrobox Opto-FPGA registers and definitions */
-#include "hal_xc_auto.h"
-typedef struct opto_fpga_regs_s {
- volatile unsigned long revision_ul; /* Read Only */
- volatile unsigned long reset_ul; /* Read/Write */
- volatile unsigned long status_ul; /* Read Only */
- volatile unsigned long interrupt_ul; /* Read Only */
- volatile unsigned long mask_ul; /* Read/Write */
- volatile unsigned long scratch_ul; /* Read/Write */
- volatile unsigned long scrmask_ul; /* Read/Write */
- volatile unsigned long control_ul; /* Read/Write */
- volatile unsigned long boardinfo_ul; /* Read Only */
-} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST;
-
-#endif /* __METROBOX_H__ */
+++ /dev/null
-#ifndef _METROBOX_VERSION_H_
-#define _METROBOX_VERSION_H_
-/*
- * (C) Copyright 2005
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#define METROBOX_U_BOOT_REL_STR "Release 2.0.3"
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
- board/sandburst/metrobox/init.o (.text)
- arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
- arch/powerpc/cpu/ppc4xx/traps.o (.text)
- arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
- arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
- arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
- arch/powerpc/cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
-
-/* common/env_embedded.o(.text) */
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
CCM_GMAC_CTRL_GPIT_MII);
#endif
+ /*
+ * In order for the gmac nic to work reliable on the Bananapi, we
+ * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain"
+ * of the GMAC clk register to 3.
+ */
+#ifdef CONFIG_BANANAPI
+ setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
+#endif
+
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
#ifdef CONFIG_RGMII
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
bool generate_fake_mac = false;
+ u32 value;
/* Enable i2c2 pullup resisters */
- writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1);
+ value = readl(&prog_io_base->io1);
+ value &= ~(PRG_I2C2_PULLUPRESX);
+ writel(value, &prog_io_base->io1);
switch (get_board_revision()) {
case REVISION_AXBX:
else
setenv("board_name", "dra7xx");
#endif
- init_sata(0);
return 0;
}
return 0;
}
-int board_late_init(void)
-{
- init_sata(0);
- return 0;
-}
-
int board_eth_init(bd_t *bis)
{
return 0;
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
# endif
- sprintf(memsz, "%ldk", (gd->ram_size / 1024) - pram);
+ sprintf(memsz, "%ldk", (long int) ((gd->ram_size / 1024) - pram));
setenv("mem", memsz);
return 0;
initr_caches,
#endif
initr_reloc_global_data,
+#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
+ initr_unlock_ram_in_cache,
+#endif
initr_barrier,
initr_malloc,
bootstage_relocate,
#ifdef CONFIG_SYS_DELAYED_ICACHE
initr_icache_enable,
#endif
-#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
- initr_unlock_ram_in_cache,
-#endif
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
* Do early PCI configuration _before_ the flash gets initialised,
U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""),
#ifdef CONFIG_SUPPORT_EMMC_BOOT
U_BOOT_CMD_MKENT(bootbus, 5, 0, do_mmc_bootbus, "", ""),
- U_BOOT_CMD_MKENT(bootpart-resize, 3, 0, do_mmc_boot_resize, "", ""),
+ U_BOOT_CMD_MKENT(bootpart-resize, 4, 0, do_mmc_boot_resize, "", ""),
U_BOOT_CMD_MKENT(partconf, 5, 0, do_mmc_partconf, "", ""),
U_BOOT_CMD_MKENT(rst-function, 3, 0, do_mmc_rst_func, "", ""),
#endif
char bootargs[CONFIG_SYS_CBSIZE] = "";
char finalbootargs[CONFIG_SYS_CBSIZE];
+ if (strlen(label->append ?: "") +
+ strlen(ip_str) + strlen(mac_str) + 1 > sizeof(bootargs)) {
+ printf("bootarg overflow %zd+%zd+%zd+1 > %zd\n",
+ strlen(label->append ?: ""),
+ strlen(ip_str), strlen(mac_str),
+ sizeof(bootargs));
+ return 1;
+ }
+
if (label->append)
strcpy(bootargs, label->append);
strcat(bootargs, ip_str);
}
#endif /* CONFIG_USB_STORAGE */
+static int do_usb_stop_keyboard(int force)
+{
+#ifdef CONFIG_USB_KEYBOARD
+ if (usb_kbd_deregister(force) != 0) {
+ printf("USB not stopped: usbkbd still using USB\n");
+ return 1;
+ }
+#endif
+ return 0;
+}
/******************************************************************************
* usb command intepreter
if ((strncmp(argv[1], "reset", 5) == 0) ||
(strncmp(argv[1], "start", 5) == 0)) {
bootstage_mark_name(BOOTSTAGE_ID_USB_START, "usb_start");
+ if (do_usb_stop_keyboard(1) != 0)
+ return 1;
usb_stop();
printf("(Re)start USB...\n");
if (usb_init() >= 0) {
return 0;
}
if (strncmp(argv[1], "stop", 4) == 0) {
-#ifdef CONFIG_USB_KEYBOARD
- if (argc == 2) {
- if (usb_kbd_deregister() != 0) {
- printf("USB not stopped: usbkbd still"
- " using USB\n");
- return 1;
- }
- } else {
- /* forced stop, switch console in to serial */
+ if (argc != 2)
console_assign(stdin, "serial");
- usb_kbd_deregister();
- }
-#endif
+ if (do_usb_stop_keyboard(0) != 0)
+ return 1;
printf("stopping USB..\n");
usb_stop();
return 0;
#ifdef CONFIG_SPL_BUILD
dev = 0;
#endif
- if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num)
+ if (mmc_get_env_part(mmc) != mmc->part_num)
mmc_switch_part(dev, mmc->part_num);
#endif
}
{ IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",},
{ IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", },
{ IH_TYPE_SCRIPT, "script", "Script", },
+ { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SOCFPGA preloader",},
{ IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
{ IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",},
{ IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",},
hang();
} else {
/* try to recognize storage devices immediately */
+ scsi_scan(0);
stor_dev = scsi_get_dev(0);
}
#define CONFIG_SYS_DEVICE_NULLDEV 1
#endif
+#ifdef CONFIG_SYS_STDIO_DEREGISTER
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+#endif
#ifdef CONFIG_SYS_DEVICE_NULLDEV
void nulldev_putc(struct stdio_dev *dev, const char c)
* returns 0 if success, -1 if device is assigned and 1 if devname not found
*/
#ifdef CONFIG_SYS_STDIO_DEREGISTER
-int stdio_deregister_dev(struct stdio_dev *dev)
+int stdio_deregister_dev(struct stdio_dev *dev, int force)
{
int l;
struct list_head *pos;
/* get stdio devices (ListRemoveItem changes the dev list) */
for (l=0 ; l< MAX_FILES; l++) {
if (stdio_devices[l] == dev) {
+ if (force) {
+ strcpy(temp_names[l], "nulldev");
+ continue;
+ }
/* Device is assigned -> report error */
return -1;
}
return 0;
}
-int stdio_deregister(const char *devname)
+int stdio_deregister(const char *devname, int force)
{
struct stdio_dev *dev;
if (!dev) /* device not found */
return -ENODEV;
- return stdio_deregister_dev(dev);
+ return stdio_deregister_dev(dev, force);
}
#endif /* CONFIG_SYS_STDIO_DEREGISTER */
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <errno.h>
#include <malloc.h>
#include <stdio_dev.h>
#include <asm/byteorder.h>
{
struct usb_interface *iface = &dev->config.if_desc[0];
struct usb_kbd_pdata *data = dev->privptr;
- uint32_t leds = data->flags & USB_KBD_LEDMASK;
+ ALLOC_ALIGN_BUFFER(uint32_t, leds, 1, USB_DMA_MINALIGN);
+ *leds = data->flags & USB_KBD_LEDMASK;
usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
USB_REQ_SET_REPORT, USB_TYPE_CLASS | USB_RECIP_INTERFACE,
- 0x200, iface->desc.bInterfaceNumber, (void *)&leds, 1, 0);
+ 0x200, iface->desc.bInterfaceNumber, leds, 1, 0);
}
#define CAPITAL_MASK 0x20
/* Search for keyboard and register it if found. */
int drv_usb_kbd_init(void)
{
- struct stdio_dev usb_kbd_dev, *old_dev;
+ struct stdio_dev usb_kbd_dev;
struct usb_device *dev;
char *stdinname = getenv("stdin");
int error, i;
if (usb_kbd_probe(dev, 0) != 1)
continue;
- /* We found a keyboard, check if it is already registered. */
- debug("USB KBD: found set up device.\n");
- old_dev = stdio_get_by_name(DEVNAME);
- if (old_dev) {
- /* Already registered, just return ok. */
- debug("USB KBD: is already registered.\n");
- usb_kbd_deregister();
- return 1;
- }
-
/* Register the keyboard */
debug("USB KBD: register.\n");
memset(&usb_kbd_dev, 0, sizeof(struct stdio_dev));
}
/* Deregister the keyboard. */
-int usb_kbd_deregister(void)
+int usb_kbd_deregister(int force)
{
#ifdef CONFIG_SYS_STDIO_DEREGISTER
- return stdio_deregister(DEVNAME);
+ int ret = stdio_deregister(DEVNAME, force);
+ if (ret && ret != -ENODEV)
+ return ret;
+
+ return 0;
#else
return 1;
#endif
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CRAYL1=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_KAREF=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MERGERBOX=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_METROBOX=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MVBC_P"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MVBC_P=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MVBLM7=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MVSMR=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_BLUESTONE=y
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+MVBC_P powerpc mpc5xxx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
+MVSMR powerpc mpc5xxx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
+MERGERBOX powerpc mpc83xx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
+MVBLM7 powerpc mpc83xx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
+bluestone powerpc ppc4xx - - Tirumala Marri <tmarri@apm.com>
+CRAYL1 powerpc ppc4xx - - David Updegraff <dave@cray.com>
+KAREF powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com>
+METROBOX powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com>
PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt <smcnutt@psyent.com>
PCI5441 nios2 - 70fbc461 2014-08-24 Scott McNutt <smcnutt@psyent.com>
flagadm powerpc mpc8xx aec6f8c5 2014-08-22 Kári DavÃðsson <kd@flaga.is>
* already be on in the command register.
*/
cmd = readl(port_mmio + PORT_CMD);
- cmd |= PORT_CMD_FIS_RX;
cmd |= PORT_CMD_SPIN_UP;
writel_with_flush(cmd, port_mmio + PORT_CMD);
obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
+obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
endif
* Altera FPGA support
*/
#include <common.h>
+#include <errno.h>
#include <ACEX1K.h>
#include <stratixII.h>
-/* Define FPGA_DEBUG to get debug printf's */
-/* #define FPGA_DEBUG */
+/* Define FPGA_DEBUG to 1 to get debug printf's */
+#define FPGA_DEBUG 0
-#ifdef FPGA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-/* Local Static Functions */
-static int altera_validate (Altera_desc * desc, const char *fn);
-
-/* ------------------------------------------------------------------------- */
-int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
-{
- int ret_val = FPGA_FAIL; /* assume a failure */
-
- if (!altera_validate (desc, (char *)__FUNCTION__)) {
- printf ("%s: Invalid device descriptor\n", __FUNCTION__);
- } else {
- switch (desc->family) {
- case Altera_ACEX1K:
- case Altera_CYC2:
+static const struct altera_fpga {
+ enum altera_family family;
+ const char *name;
+ int (*load)(Altera_desc *, const void *, size_t);
+ int (*dump)(Altera_desc *, const void *, size_t);
+ int (*info)(Altera_desc *);
+} altera_fpga[] = {
#if defined(CONFIG_FPGA_ACEX1K)
- PRINTF ("%s: Launching the ACEX1K Loader...\n",
- __FUNCTION__);
- ret_val = ACEX1K_load (desc, buf, bsize);
+ { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
+ { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
#elif defined(CONFIG_FPGA_CYCLON2)
- PRINTF ("%s: Launching the CYCLONE II Loader...\n",
- __FUNCTION__);
- ret_val = CYC2_load (desc, buf, bsize);
-#else
- printf ("%s: No support for ACEX1K devices.\n",
- __FUNCTION__);
+ { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
+ { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
#endif
- break;
-
#if defined(CONFIG_FPGA_STRATIX_II)
- case Altera_StratixII:
- PRINTF ("%s: Launching the Stratix II Loader...\n",
- __FUNCTION__);
- ret_val = StratixII_load (desc, buf, bsize);
- break;
+ { Altera_StratixII, "StratixII", StratixII_load,
+ StratixII_dump, StratixII_info },
+#endif
+#if defined(CONFIG_FPGA_SOCFPGA)
+ { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
#endif
- default:
- printf ("%s: Unsupported family type, %d\n",
- __FUNCTION__, desc->family);
- }
+};
+
+static int altera_validate(Altera_desc *desc, const char *fn)
+{
+ if (!desc) {
+ printf("%s: NULL descriptor!\n", fn);
+ return -EINVAL;
+ }
+
+ if ((desc->family < min_altera_type) ||
+ (desc->family > max_altera_type)) {
+ printf("%s: Invalid family type, %d\n", fn, desc->family);
+ return -EINVAL;
+ }
+
+ if ((desc->iface < min_altera_iface_type) ||
+ (desc->iface > max_altera_iface_type)) {
+ printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
+ return -EINVAL;
}
- return ret_val;
+ if (!desc->size) {
+ printf("%s: NULL part size\n", fn);
+ return -EINVAL;
+ }
+
+ return 0;
}
-int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
+static const struct altera_fpga *
+altera_desc_to_fpga(Altera_desc *desc, const char *fn)
{
- int ret_val = FPGA_FAIL; /* assume a failure */
+ int i;
- if (!altera_validate (desc, (char *)__FUNCTION__)) {
- printf ("%s: Invalid device descriptor\n", __FUNCTION__);
- } else {
- switch (desc->family) {
- case Altera_ACEX1K:
-#if defined(CONFIG_FPGA_ACEX)
- PRINTF ("%s: Launching the ACEX1K Reader...\n",
- __FUNCTION__);
- ret_val = ACEX1K_dump (desc, buf, bsize);
-#else
- printf ("%s: No support for ACEX1K devices.\n",
- __FUNCTION__);
-#endif
- break;
+ if (altera_validate(desc, fn)) {
+ printf("%s: Invalid device descriptor\n", fn);
+ return NULL;
+ }
-#if defined(CONFIG_FPGA_STRATIX_II)
- case Altera_StratixII:
- PRINTF ("%s: Launching the Stratix II Reader...\n",
- __FUNCTION__);
- ret_val = StratixII_dump (desc, buf, bsize);
+ for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) {
+ if (desc->family == altera_fpga[i].family)
break;
-#endif
- default:
- printf ("%s: Unsupported family type, %d\n",
- __FUNCTION__, desc->family);
- }
}
- return ret_val;
+ if (i == ARRAY_SIZE(altera_fpga)) {
+ printf("%s: Unsupported family type, %d\n", fn, desc->family);
+ return NULL;
+ }
+
+ return &altera_fpga[i];
}
-int altera_info( Altera_desc *desc )
+int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
{
- int ret_val = FPGA_FAIL;
+ const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
- if (altera_validate (desc, (char *)__FUNCTION__)) {
- printf ("Family: \t");
- switch (desc->family) {
- case Altera_ACEX1K:
- printf ("ACEX1K\n");
- break;
- case Altera_CYC2:
- printf ("CYCLON II\n");
- break;
- case Altera_StratixII:
- printf ("Stratix II\n");
- break;
- /* Add new family types here */
- default:
- printf ("Unknown family type, %d\n", desc->family);
- }
-
- printf ("Interface type:\t");
- switch (desc->iface) {
- case passive_serial:
- printf ("Passive Serial (PS)\n");
- break;
- case passive_parallel_synchronous:
- printf ("Passive Parallel Synchronous (PPS)\n");
- break;
- case passive_parallel_asynchronous:
- printf ("Passive Parallel Asynchronous (PPA)\n");
- break;
- case passive_serial_asynchronous:
- printf ("Passive Serial Asynchronous (PSA)\n");
- break;
- case altera_jtag_mode: /* Not used */
- printf ("JTAG Mode\n");
- break;
- case fast_passive_parallel:
- printf ("Fast Passive Parallel (FPP)\n");
- break;
- case fast_passive_parallel_security:
- printf
- ("Fast Passive Parallel with Security (FPPS) \n");
- break;
- /* Add new interface types here */
- default:
- printf ("Unsupported interface type, %d\n", desc->iface);
- }
-
- printf("Device Size: \t%zd bytes\n"
- "Cookie: \t0x%x (%d)\n",
- desc->size, desc->cookie, desc->cookie);
-
- if (desc->iface_fns) {
- printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
- switch (desc->family) {
- case Altera_ACEX1K:
- case Altera_CYC2:
-#if defined(CONFIG_FPGA_ACEX1K)
- ACEX1K_info (desc);
-#elif defined(CONFIG_FPGA_CYCLON2)
- CYC2_info (desc);
-#else
- /* just in case */
- printf ("%s: No support for ACEX1K devices.\n",
- __FUNCTION__);
-#endif
- break;
-#if defined(CONFIG_FPGA_STRATIX_II)
- case Altera_StratixII:
- StratixII_info (desc);
- break;
-#endif
- /* Add new family types here */
- default:
- /* we don't need a message here - we give one up above */
- break;
- }
- } else {
- printf ("No Device Function Table.\n");
- }
-
- ret_val = FPGA_SUCCESS;
- } else {
- printf ("%s: Invalid device descriptor\n", __FUNCTION__);
- }
+ if (!fpga)
+ return FPGA_FAIL;
- return ret_val;
+ debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n",
+ __func__, fpga->name);
+ if (fpga->load)
+ return fpga->load(desc, buf, bsize);
+ return 0;
}
-/* ------------------------------------------------------------------------- */
+int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
+{
+ const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
+
+ if (!fpga)
+ return FPGA_FAIL;
-static int altera_validate (Altera_desc * desc, const char *fn)
+ debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n",
+ __func__, fpga->name);
+ if (fpga->dump)
+ return fpga->dump(desc, buf, bsize);
+ return 0;
+}
+
+int altera_info(Altera_desc *desc)
{
- int ret_val = false;
-
- if (desc) {
- if ((desc->family > min_altera_type) &&
- (desc->family < max_altera_type)) {
- if ((desc->iface > min_altera_iface_type) &&
- (desc->iface < max_altera_iface_type)) {
- if (desc->size) {
- ret_val = true;
- } else {
- printf ("%s: NULL part size\n", fn);
- }
- } else {
- printf ("%s: Invalid Interface type, %d\n",
- fn, desc->iface);
- }
- } else {
- printf ("%s: Invalid family type, %d\n", fn, desc->family);
- }
+ const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
+
+ if (!fpga)
+ return FPGA_FAIL;
+
+ printf("Family: \t%s\n", fpga->name);
+
+ printf("Interface type:\t");
+ switch (desc->iface) {
+ case passive_serial:
+ printf("Passive Serial (PS)\n");
+ break;
+ case passive_parallel_synchronous:
+ printf("Passive Parallel Synchronous (PPS)\n");
+ break;
+ case passive_parallel_asynchronous:
+ printf("Passive Parallel Asynchronous (PPA)\n");
+ break;
+ case passive_serial_asynchronous:
+ printf("Passive Serial Asynchronous (PSA)\n");
+ break;
+ case altera_jtag_mode: /* Not used */
+ printf("JTAG Mode\n");
+ break;
+ case fast_passive_parallel:
+ printf("Fast Passive Parallel (FPP)\n");
+ break;
+ case fast_passive_parallel_security:
+ printf("Fast Passive Parallel with Security (FPPS)\n");
+ break;
+ /* Add new interface types here */
+ default:
+ printf("Unsupported interface type, %d\n", desc->iface);
+ }
+
+ printf("Device Size: \t%zd bytes\n"
+ "Cookie: \t0x%x (%d)\n",
+ desc->size, desc->cookie, desc->cookie);
+
+ if (desc->iface_fns) {
+ printf("Device Function Table @ 0x%p\n", desc->iface_fns);
+ if (fpga->info)
+ fpga->info(desc);
} else {
- printf ("%s: NULL descriptor!\n", fn);
+ printf("No Device Function Table.\n");
}
- return ret_val;
+ return FPGA_SUCCESS;
}
-
-/* ------------------------------------------------------------------------- */
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timeout count */
+#define FPGA_TIMEOUT_CNT 0x1000000
+
+static struct socfpga_fpga_manager *fpgamgr_regs =
+ (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/* Set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+ clrsetbits_le32(&fpgamgr_regs->ctrl,
+ 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
+ (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
+}
+
+static int fpgamgr_dclkcnt_set(unsigned long cnt)
+{
+ unsigned long i;
+
+ /* Clear any existing done status */
+ if (readl(&fpgamgr_regs->dclkstat))
+ writel(0x1, &fpgamgr_regs->dclkstat);
+
+ /* Write the dclkcnt */
+ writel(cnt, &fpgamgr_regs->dclkcnt);
+
+ /* Wait till the dclkcnt done */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (!readl(&fpgamgr_regs->dclkstat))
+ continue;
+
+ writel(0x1, &fpgamgr_regs->dclkstat);
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+/* Start the FPGA programming by initialize the FPGA Manager */
+static int fpgamgr_program_init(void)
+{
+ unsigned long msel, i;
+
+ /* Get the MSEL value */
+ msel = readl(&fpgamgr_regs->stat);
+ msel &= FPGAMGRREGS_STAT_MSEL_MASK;
+ msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
+
+ /*
+ * Set the cfg width
+ * If MSEL[3] = 1, cfg width = 32 bit
+ */
+ if (msel & 0x8) {
+ setbits_le32(&fpgamgr_regs->ctrl,
+ FPGAMGRREGS_CTRL_CFGWDTH_MASK);
+
+ /* To determine the CD ratio */
+ /* MSEL[1:0] = 0, CD Ratio = 1 */
+ if ((msel & 0x3) == 0x0)
+ fpgamgr_set_cd_ratio(CDRATIO_x1);
+ /* MSEL[1:0] = 1, CD Ratio = 4 */
+ else if ((msel & 0x3) == 0x1)
+ fpgamgr_set_cd_ratio(CDRATIO_x4);
+ /* MSEL[1:0] = 2, CD Ratio = 8 */
+ else if ((msel & 0x3) == 0x2)
+ fpgamgr_set_cd_ratio(CDRATIO_x8);
+
+ } else { /* MSEL[3] = 0 */
+ clrbits_le32(&fpgamgr_regs->ctrl,
+ FPGAMGRREGS_CTRL_CFGWDTH_MASK);
+
+ /* To determine the CD ratio */
+ /* MSEL[1:0] = 0, CD Ratio = 1 */
+ if ((msel & 0x3) == 0x0)
+ fpgamgr_set_cd_ratio(CDRATIO_x1);
+ /* MSEL[1:0] = 1, CD Ratio = 2 */
+ else if ((msel & 0x3) == 0x1)
+ fpgamgr_set_cd_ratio(CDRATIO_x2);
+ /* MSEL[1:0] = 2, CD Ratio = 4 */
+ else if ((msel & 0x3) == 0x2)
+ fpgamgr_set_cd_ratio(CDRATIO_x4);
+ }
+
+ /* To enable FPGA Manager configuration */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
+
+ /* To enable FPGA Manager drive over configuration line */
+ setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
+
+ /* Put FPGA into reset phase */
+ setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
+
+ /* (1) wait until FPGA enter reset phase */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
+ break;
+ }
+
+ /* If not in reset state, return error */
+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
+ puts("FPGA: Could not reset\n");
+ return -1;
+ }
+
+ /* Release FPGA from reset phase */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
+
+ /* (2) wait until FPGA enter configuration phase */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
+ break;
+ }
+
+ /* If not in configuration state, return error */
+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
+ puts("FPGA: Could not configure\n");
+ return -2;
+ }
+
+ /* Clear all interrupts in CB Monitor */
+ writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
+
+ /* Enable AXI configuration */
+ setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
+
+ return 0;
+}
+
+/* Write the RBF data to FPGA Manager */
+static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
+{
+ uint32_t src = (uint32_t)rbf_data;
+ uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
+
+ /* Number of loops for 32-byte long copying. */
+ uint32_t loops32 = rbf_size / 32;
+ /* Number of loops for 4-byte long copying + trailing bytes */
+ uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
+
+ asm volatile(
+ "1: ldmia %0!, {r0-r7}\n"
+ " stmia %1!, {r0-r7}\n"
+ " sub %1, #32\n"
+ " subs %2, #1\n"
+ " bne 1b\n"
+ "2: ldr %2, [%0], #4\n"
+ " str %2, [%1]\n"
+ " subs %3, #1\n"
+ " bne 2b\n"
+ : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
+ : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
+}
+
+/* Ensure the FPGA entering config done */
+static int fpgamgr_program_poll_cd(void)
+{
+ const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
+ FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
+ unsigned long reg, i;
+
+ /* (3) wait until full config done */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ reg = readl(&fpgamgr_regs->gpio_ext_porta);
+
+ /* Config error */
+ if (!(reg & mask)) {
+ printf("FPGA: Configuration error.\n");
+ return -3;
+ }
+
+ /* Config done without error */
+ if (reg & mask)
+ break;
+ }
+
+ /* Timeout happened, return error */
+ if (i == FPGA_TIMEOUT_CNT) {
+ printf("FPGA: Timeout waiting for program.\n");
+ return -4;
+ }
+
+ /* Disable AXI configuration */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
+
+ return 0;
+}
+
+/* Ensure the FPGA entering init phase */
+static int fpgamgr_program_poll_initphase(void)
+{
+ unsigned long i;
+
+ /* Additional clocks for the CB to enter initialization phase */
+ if (fpgamgr_dclkcnt_set(0x4))
+ return -5;
+
+ /* (4) wait until FPGA enter init phase or user mode */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
+ break;
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
+ break;
+ }
+
+ /* If not in configuration state, return error */
+ if (i == FPGA_TIMEOUT_CNT)
+ return -6;
+
+ return 0;
+}
+
+/* Ensure the FPGA entering user mode */
+static int fpgamgr_program_poll_usermode(void)
+{
+ unsigned long i;
+
+ /* Additional clocks for the CB to exit initialization phase */
+ if (fpgamgr_dclkcnt_set(0x5000))
+ return -7;
+
+ /* (5) wait until FPGA enter user mode */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
+ break;
+ }
+ /* If not in configuration state, return error */
+ if (i == FPGA_TIMEOUT_CNT)
+ return -8;
+
+ /* To release FPGA Manager drive over configuration line */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
+
+ return 0;
+}
+
+/*
+ * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
+ * Return 0 for sucess, non-zero for error.
+ */
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ unsigned long status;
+
+ if ((uint32_t)rbf_data & 0x3) {
+ puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
+ return -EINVAL;
+ }
+
+ /* Prior programming the FPGA, all bridges need to be shut off */
+
+ /* Disable all signals from hps peripheral controller to fpga */
+ writel(0, &sysmgr_regs->fpgaintfgrp_module);
+
+ /* Disable all signals from FPGA to HPS SDRAM */
+#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
+ writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
+
+ /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+ socfpga_bridges_reset(1);
+
+ /* Unmap the bridges from NIC-301 */
+ writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init();
+ if (status)
+ return status;
+
+ /* Write the RBF data to FPGA Manager */
+ fpgamgr_program_write(rbf_data, rbf_size);
+
+ /* Ensure the FPGA entering config done */
+ status = fpgamgr_program_poll_cd();
+ if (status)
+ return status;
+
+ /* Ensure the FPGA entering init phase */
+ status = fpgamgr_program_poll_initphase();
+ if (status)
+ return status;
+
+ /* Ensure the FPGA entering user mode */
+ return fpgamgr_program_poll_usermode();
+}
if (data->flags & MMC_DATA_WRITE)
return UNUSABLE_ERR;
#ifndef RSI_BLKSZ
- data_ctl |= ((ffs(data_size) - 1) << 4);
+ data_ctl |= ((ffs(data->blocksize) - 1) << 4);
#else
- bfin_write_SDH_BLK_SIZE(data_size);
+ bfin_write_SDH_BLK_SIZE(data->blocksize);
#endif
data_ctl |= DTX_DIR;
bfin_write_SDH_DATA_CTL(data_ctl);
do {
udelay(1);
status = bfin_read_SDH_STATUS();
- } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));
+ } while (!(status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
+ RX_OVERRUN)));
if (status & DAT_TIME_OUT) {
bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
if (get_timer(start) > timeout) {
- printf("Timeout on data busy\n");
+ printf("%s: Timeout on data busy\n", __func__);
return TIMEOUT;
}
}
}
}
- if (i == retry)
+ if (i == retry) {
+ printf("%s: Timeout.\n", __func__);
return TIMEOUT;
+ }
if (mask & DWMCI_INTMSK_RTO) {
- debug("Response Timeout..\n");
+ /*
+ * Timeout here is not necessarily fatal. (e)MMC cards
+ * will splat here when they receive CMD55 as they do
+ * not support this command and that is exactly the way
+ * to tell them apart from SD cards. Thus, this output
+ * below shall be debug(). eMMC cards also do not favor
+ * CMD8, please keep that in mind.
+ */
+ debug("%s: Response Timeout.\n", __func__);
return TIMEOUT;
} else if (mask & DWMCI_INTMSK_RE) {
- debug("Response Error..\n");
+ printf("%s: Response Error.\n", __func__);
return -1;
}
do {
mask = dwmci_readl(host, DWMCI_RINTSTS);
if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
- debug("DATA ERROR!\n");
+ printf("%s: DATA ERROR!\n", __func__);
return -1;
}
} while (!(mask & DWMCI_INTMSK_DTO));
if ((freq == host->clock) || (freq == 0))
return 0;
/*
- * If host->get_mmc_clk didn't define,
+ * If host->get_mmc_clk isn't defined,
* then assume that host->bus_hz is source clock value.
- * host->bus_hz should be set from user.
+ * host->bus_hz should be set by user.
*/
if (host->get_mmc_clk)
sclk = host->get_mmc_clk(host);
else if (host->bus_hz)
sclk = host->bus_hz;
else {
- printf("Didn't get source clock value..\n");
+ printf("%s: Didn't get source clock value.\n", __func__);
return -EINVAL;
}
do {
status = dwmci_readl(host, DWMCI_CMD);
if (timeout-- < 0) {
- printf("TIMEOUT error!!\n");
+ printf("%s: Timeout!\n", __func__);
return -ETIMEDOUT;
}
} while (status & DWMCI_CMD_START);
do {
status = dwmci_readl(host, DWMCI_CMD);
if (timeout-- < 0) {
- printf("TIMEOUT error!!\n");
+ printf("%s: Timeout!\n", __func__);
return -ETIMEDOUT;
}
} while (status & DWMCI_CMD_START);
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
u32 ctype, regs;
- debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
+ debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
dwmci_setup_bus(host, mmc->clock);
switch (mmc->bus_width) {
dwmci_writel(host, DWMCI_PWREN, 1);
if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
- debug("%s[%d] Fail-reset!!\n",__func__,__LINE__);
+ printf("%s[%d] Fail-reset!!\n", __func__, __LINE__);
return -1;
}
ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
(mmc->part_config & ~PART_ACCESS_MASK)
| (part_num & PART_ACCESS_MASK));
- if (ret)
- return ret;
- return mmc_set_capacity(mmc, part_num);
+ /*
+ * Set the capacity if the switch succeeded or was intended
+ * to return to representing the raw device.
+ */
+ if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
+ ret = mmc_set_capacity(mmc, part_num);
+
+ return ret;
}
int mmc_getcd(struct mmc *mmc)
if (err)
return err;
+ else
+ ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
/* Read out group size from ext_csd */
mmc->erase_grp_size =
mmc_set_bus_width(mmc, widths[idx]);
err = mmc_send_ext_csd(mmc, test_csd);
+ /* Only compare read only fields */
if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
== test_csd[EXT_CSD_PARTITIONING_SUPPORT]
- && ext_csd[EXT_CSD_ERASE_GROUP_DEF] \
- == test_csd[EXT_CSD_ERASE_GROUP_DEF] \
+ && ext_csd[EXT_CSD_HC_WP_GRP_SIZE] \
+ == test_csd[EXT_CSD_HC_WP_GRP_SIZE] \
&& ext_csd[EXT_CSD_REV] \
== test_csd[EXT_CSD_REV]
&& ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
#include <asm/arch/kirkwood.h>
#include <mvebu_mmc.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define DRIVER_NAME "MVEBU_MMC"
+#define MVEBU_TARGET_DRAM 0
+
static void mvebu_mmc_write(u32 offs, u32 val)
{
writel(val, CONFIG_SYS_MMC_BASE + (offs));
return TIMEOUT;
}
}
+ if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
+ (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
+ return TIMEOUT;
/* Handling response */
if (cmd->resp_type & MMC_RSP_136) {
/* default to maximum timeout */
ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
+ ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN;
ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
mvebu_mmc_set_clk(mmc->clock);
}
+/*
+ * Set window register.
+ */
+static void mvebu_window_setup(void)
+{
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ mvebu_mmc_write(WINDOW_CTRL(i), 0);
+ mvebu_mmc_write(WINDOW_BASE(i), 0);
+ }
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ u32 size, base, attrib;
+
+ /* Enable DRAM bank */
+ switch (i) {
+ case 0:
+ attrib = KWCPU_ATTR_DRAM_CS0;
+ break;
+ case 1:
+ attrib = KWCPU_ATTR_DRAM_CS1;
+ break;
+ case 2:
+ attrib = KWCPU_ATTR_DRAM_CS2;
+ break;
+ case 3:
+ attrib = KWCPU_ATTR_DRAM_CS3;
+ break;
+ default:
+ /* invalide bank, disable access */
+ attrib = 0;
+ break;
+ }
+
+ size = gd->bd->bi_dram[i].size;
+ base = gd->bd->bi_dram[i].start;
+ if (size && attrib) {
+ mvebu_mmc_write(WINDOW_CTRL(i),
+ MVCPU_WIN_CTRL_DATA(size,
+ MVEBU_TARGET_DRAM,
+ attrib,
+ MVCPU_WIN_ENABLE));
+ } else {
+ mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
+ }
+ mvebu_mmc_write(WINDOW_BASE(i), base);
+ }
+}
+
static int mvebu_mmc_initialize(struct mmc *mmc)
{
debug("%s: mvebu_mmc_initialize", DRIVER_NAME);
mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
+ mvebu_window_setup();
+
/* SW reset */
mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
.f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
.f_max = MVEBU_MMC_CLOCKRATE_MAX,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .host_caps = MMC_MODE_4BIT | MMC_MODE_HS,
+ .host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HC |
+ MMC_MODE_HS_52MHz,
.part_type = PART_TYPE_DOS,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
#include <common.h>
#include <malloc.h>
#include <dwmmc.h>
+#include <errno.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/system_manager.h>
int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
{
struct dwmci_host *host;
+ unsigned long clk = cm_get_mmc_controller_clk_hz();
+
+ if (clk == 0) {
+ printf("%s: MMC clock is zero!", __func__);
+ return -EINVAL;
+ }
/* calloc for zero init */
- host = calloc(sizeof(struct dwmci_host), 1);
+ host = calloc(1, sizeof(struct dwmci_host));
if (!host) {
- printf("dwmci_host calloc fail!\n");
- return -1;
+ printf("%s: calloc() failed!\n", __func__);
+ return -ENOMEM;
}
host->name = "SOCFPGA DWMMC";
host->clksel = socfpga_dwmci_clksel;
host->dev_index = index;
/* fixed clock divide by 4 which due to the SDMMC wrapper */
- host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ;
+ host->bus_hz = clk;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_EXTENDED:
case CFI_CMDSET_INTEL_STANDARD:
- if ((retcode != ERR_OK)
+ if ((retcode == ERR_OK)
&& !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
retcode = ERR_INVAL;
printf ("Flash %s error at address %lx\n", prompt,
addr = MODE_11 | BANK(denali->flash_bank);
index_addr(denali, addr | 0, cmd);
break;
- case NAND_CMD_PARAM:
- clear_interrupts(denali);
case NAND_CMD_READID:
+ case NAND_CMD_PARAM:
reset_buf(denali);
/* sometimes ManufactureId read from register is not right
* e.g. some of Micron MT29F32G08QAA MLC NAND chips
addr = MODE_11 | BANK(denali->flash_bank);
index_addr(denali, addr | 0, cmd);
index_addr(denali, addr | 1, col & 0xFF);
+ if (cmd == NAND_CMD_PARAM)
+ udelay(50);
+ break;
+ case NAND_CMD_RNDOUT:
+ addr = MODE_11 | BANK(denali->flash_bank);
+ index_addr(denali, addr | 0, cmd);
+ index_addr(denali, addr | 1, col & 0xFF);
+ index_addr(denali, addr | 1, col >> 8);
+ index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART);
break;
case NAND_CMD_READ0:
case NAND_CMD_SEQIN:
struct eth_dma_regs *dma_p = priv->dma_regs_p;
u32 desc_num = priv->tx_currdescnum;
struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
-
+ uint32_t desc_start = (uint32_t)desc_p;
+ uint32_t desc_end = desc_start +
+ roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+ uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
+ uint32_t data_end = data_start +
+ roundup(length, ARCH_DMA_MINALIGN);
/*
* Strictly we only need to invalidate the "txrx_status" field
* for the following check, but on some platforms we cannot
- * invalidate only 4 bytes, so roundup to
- * ARCH_DMA_MINALIGN. This is safe because the individual
- * descriptors in the array are each aligned to
- * ARCH_DMA_MINALIGN.
+ * invalidate only 4 bytes, so we flush the entire descriptor,
+ * which is 16 bytes in total. This is safe because the
+ * individual descriptors in the array are each aligned to
+ * ARCH_DMA_MINALIGN and padded appropriately.
*/
- invalidate_dcache_range(
- (unsigned long)desc_p,
- (unsigned long)desc_p +
- roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN));
+ invalidate_dcache_range(desc_start, desc_end);
/* Check if the descriptor is owned by CPU */
if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
return -1;
}
- memcpy((void *)desc_p->dmamac_addr, packet, length);
+ memcpy(desc_p->dmamac_addr, packet, length);
/* Flush data to be sent */
- flush_dcache_range((unsigned long)desc_p->dmamac_addr,
- (unsigned long)desc_p->dmamac_addr + length);
+ flush_dcache_range(data_start, data_end);
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
#endif
/* Flush modified buffer descriptor */
- flush_dcache_range((unsigned long)desc_p,
- (unsigned long)desc_p + sizeof(struct dmamacdescr));
+ flush_dcache_range(desc_start, desc_end);
/* Test the wrap-around condition. */
if (++desc_num >= CONFIG_TX_DESCR_NUM)
u32 status, desc_num = priv->rx_currdescnum;
struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
int length = 0;
+ uint32_t desc_start = (uint32_t)desc_p;
+ uint32_t desc_end = desc_start +
+ roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+ uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
+ uint32_t data_end;
/* Invalidate entire buffer descriptor */
- invalidate_dcache_range((unsigned long)desc_p,
- (unsigned long)desc_p +
- sizeof(struct dmamacdescr));
+ invalidate_dcache_range(desc_start, desc_end);
status = desc_p->txrx_status;
DESC_RXSTS_FRMLENSHFT;
/* Invalidate received data */
- invalidate_dcache_range((unsigned long)desc_p->dmamac_addr,
- (unsigned long)desc_p->dmamac_addr +
- roundup(length, ARCH_DMA_MINALIGN));
+ data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(data_start, data_end);
NetReceive(desc_p->dmamac_addr, length);
desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
/* Flush only status field - others weren't changed */
- flush_dcache_range((unsigned long)&desc_p->txrx_status,
- (unsigned long)&desc_p->txrx_status +
- sizeof(desc_p->txrx_status));
+ flush_dcache_range(desc_start, desc_end);
/* Test the wrap-around condition. */
if (++desc_num >= CONFIG_RX_DESCR_NUM)
#ifndef CONFIG_PHY_MICREL_KSZ9021
/*
* I can't believe Micrel used the exact same part number
- * for the KSZ9021
- * Shame Micrel, Shame!!!!!
+ * for the KSZ9021. Shame Micrel, Shame!
*/
static struct phy_driver KS8721_driver = {
.name = "Micrel KS8721BL",
#endif
-/**
+/*
* KSZ9021 - KSZ9031 common
*/
phydev->speed = SPEED_10;
return 0;
}
-#ifdef CONFIG_PHY_MICREL_KSZ9021
+#ifdef CONFIG_PHY_MICREL_KSZ9021
/*
* KSZ9021
*/
#ifdef CONFIG_SYS_STDIO_DEREGISTER
struct serial_dev_priv *upriv = dev->uclass_priv;
- if (stdio_deregister_dev(upriv->sdev))
+ if (stdio_deregister_dev(upriv->sdev), 0)
return -EPERM;
#endif
/* select DEVICE mode */
writel(USBMODE_DEVICE, &udc->usbmode);
+#if !defined(CONFIG_USB_GADGET_DUALSPEED)
+ /* Port force Full-Speed Connect */
+ setbits_le32(&udc->portsc, PFSC);
+#endif
+
writel(0xffffffff, &udc->epflush);
/* Turn on the USB connection by enabling the pullup resistor */
NULL,
};
-static const struct usb_qualifier_descriptor dev_qualifier = {
- .bLength = sizeof dev_qualifier,
- .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
- .bcdUSB = __constant_cpu_to_le16(0x0200),
- .bDeviceClass = USB_CLASS_VENDOR_SPEC,
- .bNumConfigurations = 1,
-};
-
static const char dfu_name[] = "Device Firmware Upgrade";
/*
{
f_dfu->usb_function.strings = dfu_strings;
f_dfu->usb_function.hs_descriptors = f_dfu->function;
+ f_dfu->usb_function.descriptors = f_dfu->function;
f_dfu->dfu_state = DFU_STATE_dfuIDLE;
}
{
f_dfu->usb_function.strings = NULL;
f_dfu->usb_function.hs_descriptors = dfu_runtime_descs;
+ f_dfu->usb_function.descriptors = dfu_runtime_descs;
}
static int handle_upload(struct usb_request *req, u16 len)
return -ENOMEM;
f_dfu->usb_function.name = "dfu";
f_dfu->usb_function.hs_descriptors = dfu_runtime_descs;
+ f_dfu->usb_function.descriptors = dfu_runtime_descs;
f_dfu->usb_function.bind = dfu_bind;
f_dfu->usb_function.unbind = dfu_unbind;
f_dfu->usb_function.set_alt = dfu_set_alt;
strncat(response, FASTBOOT_VERSION, chars_left);
} else if (!strcmp_l1("bootloader-version", cmd)) {
strncat(response, U_BOOT_VERSION, chars_left);
- } else if (!strcmp_l1("downloadsize", cmd)) {
+ } else if (!strcmp_l1("downloadsize", cmd) ||
+ !strcmp_l1("max-download-size", cmd)) {
char str_num[12];
- sprintf(str_num, "%08x", CONFIG_USB_FASTBOOT_BUF_SIZE);
+ sprintf(str_num, "0x%08x", CONFIG_USB_FASTBOOT_BUF_SIZE);
strncat(response, str_num, chars_left);
} else if (!strcmp_l1("serialno", cmd)) {
s = getenv("serial#");
unsigned int transfer_size = download_size - download_bytes;
const unsigned char *buffer = req->buf;
unsigned int buffer_size = req->actual;
+ unsigned int pre_dot_num, now_dot_num;
if (req->status != 0) {
printf("Bad status: %d\n", req->status);
memcpy((void *)CONFIG_USB_FASTBOOT_BUF_ADDR + download_bytes,
buffer, transfer_size);
+ pre_dot_num = download_bytes / BYTES_PER_DOT;
download_bytes += transfer_size;
+ now_dot_num = download_bytes / BYTES_PER_DOT;
+
+ if (pre_dot_num != now_dot_num) {
+ putc('.');
+ if (!(now_dot_num % 74))
+ putc('\n');
+ }
/* Check if transfer is done */
if (download_bytes >= download_size) {
req->length = ep->maxpacket;
}
- if (download_bytes && !(download_bytes % BYTES_PER_DOT)) {
- putc('.');
- if (!(download_bytes % (74 * BYTES_PER_DOT)))
- putc('\n');
- }
req->actual = 0;
usb_ep_queue(ep, req, 0);
}
error("unknown command: %s\n", cmdbuf);
fastboot_tx_write_str("FAILunknown command");
} else {
- func_cb(ep, req);
+ if (req->actual < req->length) {
+ u8 *buf = (u8 *)req->buf;
+ buf[req->actual] = 0;
+ func_cb(ep, req);
+ } else {
+ error("buffer overflow\n");
+ fastboot_tx_write_str("FAILbuffer overflow");
+ }
}
if (req->status == 0) {
memset(buf, 0, 8);
buf[0] = TYPE_DISK;
+ buf[1] = curlun->removable ? 0x80 : 0;
buf[2] = 2; /* ANSI SCSI level 2 */
buf[3] = 2; /* SCSI-2 INQUIRY data format */
buf[4] = 31; /* Additional length */
.bInterval = 0x9,
};
-static struct usb_qualifier_descriptor dev_qualifier = {
- .bLength = sizeof(dev_qualifier),
- .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
-
- .bcdUSB = __constant_cpu_to_le16(0x0200),
- .bDeviceClass = USB_CLASS_VENDOR_SPEC,
-
- .bNumConfigurations = 2,
-};
-
/*
* This attribute vendor descriptor is necessary for correct operation with
* Windows version of THOR download program
return QH_FULL_SPEED;
}
+static void ehci_update_endpt2_dev_n_port(struct usb_device *dev,
+ struct QH *qh)
+{
+ struct usb_device *ttdev;
+
+ if (dev->speed != USB_SPEED_LOW && dev->speed != USB_SPEED_FULL)
+ return;
+
+ /*
+ * For full / low speed devices we need to get the devnum and portnr of
+ * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs
+ * in the tree before that one!
+ */
+ ttdev = dev;
+ while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH)
+ ttdev = ttdev->parent;
+ if (!ttdev->parent)
+ return;
+
+ qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) |
+ QH_ENDPT2_HUBADDR(ttdev->parent->devnum));
+}
+
static int
ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
int length, struct devrequest *req)
QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
qh->qh_endpt1 = cpu_to_hc32(endpt);
- endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
- QH_ENDPT2_HUBADDR(dev->parent->devnum) |
- QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
+ endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
qh->qh_endpt2 = cpu_to_hc32(endpt);
+ ehci_update_endpt2_dev_n_port(dev, qh);
qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
* Set up periodic list
* Step 1: Parent QH for all periodic transfers.
*/
+ ehcic[index].periodic_schedules = 0;
periodic = &ehcic[index].periodic_queue;
memset(periodic, 0, sizeof(*periodic));
periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
return 0;
}
-static int periodic_schedules;
-
struct int_queue *
create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
int elementsize, void *buffer)
(1 << 0)); /* S-mask: microframe 0 */
if (dev->speed == USB_SPEED_LOW ||
dev->speed == USB_SPEED_FULL) {
- debug("TT: port: %d, hub address: %d\n",
- dev->portnr, dev->parent->devnum);
- qh->qh_endpt2 |= cpu_to_hc32((dev->portnr << 23) |
- (dev->parent->devnum << 16) |
- (0x1c << 8)); /* C-mask: microframes 2-4 */
+ /* C-mask: microframes 2-4 */
+ qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
}
+ ehci_update_endpt2_dev_n_port(dev, qh);
td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
debug("FATAL: periodic should never fail, but did");
goto fail3;
}
- periodic_schedules++;
+ ctrl->periodic_schedules++;
debug("Exit create_int_queue\n");
return result;
void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
{
struct QH *cur = queue->current;
+ struct qTD *cur_td;
/* depleted queue */
if (cur == NULL) {
return NULL;
}
/* still active */
- invalidate_dcache_range((uint32_t)cur,
- ALIGN_END_ADDR(struct QH, cur, 1));
- if (cur->qh_overlay.qt_token & cpu_to_hc32(0x80)) {
- debug("Exit poll_int_queue with no completed intr transfer. "
- "token is %x\n", cur->qh_overlay.qt_token);
+ cur_td = &queue->tds[queue->current - queue->first];
+ invalidate_dcache_range((uint32_t)cur_td,
+ ALIGN_END_ADDR(struct qTD, cur_td, 1));
+ if (QT_TOKEN_GET_STATUS(hc32_to_cpu(cur_td->qt_token)) &
+ QT_TOKEN_STATUS_ACTIVE) {
+ debug("Exit poll_int_queue with no completed intr transfer. token is %x\n",
+ hc32_to_cpu(cur_td->qt_token));
return NULL;
}
if (!(cur->qh_link & QH_LINK_TERMINATE))
queue->current++;
else
queue->current = NULL;
- debug("Exit poll_int_queue with completed intr transfer. "
- "token is %x at %p (first at %p)\n", cur->qh_overlay.qt_token,
- &cur->qh_overlay.qt_token, queue->first);
+ debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
+ hc32_to_cpu(cur_td->qt_token), cur, queue->first);
return cur->buffer;
}
debug("FATAL: periodic should never fail, but did");
goto out;
}
- periodic_schedules--;
+ ctrl->periodic_schedules--;
struct QH *cur = &ctrl->periodic_queue;
timeout = get_timer(0) + 500; /* abort after 500ms */
if (NEXT_QH(cur) == queue->first) {
debug("found candidate. removing from chain\n");
cur->qh_link = queue->last->qh_link;
+ flush_dcache_range((uint32_t)cur,
+ ALIGN_END_ADDR(struct QH, cur, 1));
result = 0;
break;
}
}
}
- if (periodic_schedules > 0) {
+ if (ctrl->periodic_schedules > 0) {
result = enable_periodic(ctrl);
if (result < 0)
debug("FATAL: periodic should never fail, but did");
#if defined(CONFIG_TEGRA20)
if (config->periph_id == PERIPH_ID_USBD) {
clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
- PTS_UTMI << PTS1_SHIFT);
+ pts << PTS1_SHIFT);
clrbits_le32(&usbctlr->port_sc1, STS1);
} else {
clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
- PTS_UTMI << PTS_SHIFT);
+ pts << PTS_SHIFT);
clrbits_le32(&usbctlr->port_sc1, STS);
}
#else
struct QH qh_list __aligned(USB_DMA_MINALIGN);
struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
uint32_t *periodic_list;
+ int periodic_schedules;
int ntds;
};
/* put into basic highspeed mode and start session */
musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
-#ifdef CONFIG_USB_GADGET_DUALSPEED
| MUSB_POWER_HSENAB
-#endif
/* ENSUSPEND wedges tusb */
/* | MUSB_POWER_ENSUSPEND */
);
#ifndef _ALTERA_H_
#define _ALTERA_H_
-typedef enum { /* typedef Altera_iface */
- min_altera_iface_type, /* insert all new types after this */
- passive_serial, /* serial data and external clock */
- passive_parallel_synchronous, /* parallel data */
- passive_parallel_asynchronous, /* parallel data */
- passive_serial_asynchronous, /* serial data w/ internal clock (not used) */
- altera_jtag_mode, /* jtag/tap serial (not used ) */
- fast_passive_parallel, /* fast passive parallel (FPP) */
- fast_passive_parallel_security, /* fast passive parallel with security (FPPS) */
- max_altera_iface_type /* insert all new types before this */
-} Altera_iface; /* end, typedef Altera_iface */
+enum altera_iface {
+ /* insert all new types after this */
+ min_altera_iface_type,
+ /* serial data and external clock */
+ passive_serial,
+ /* parallel data */
+ passive_parallel_synchronous,
+ /* parallel data */
+ passive_parallel_asynchronous,
+ /* serial data w/ internal clock (not used) */
+ passive_serial_asynchronous,
+ /* jtag/tap serial (not used ) */
+ altera_jtag_mode,
+ /* fast passive parallel (FPP) */
+ fast_passive_parallel,
+ /* fast passive parallel with security (FPPS) */
+ fast_passive_parallel_security,
+ /* insert all new types before this */
+ max_altera_iface_type,
+};
-typedef enum { /* typedef Altera_Family */
- min_altera_type, /* insert all new types after this */
- Altera_ACEX1K, /* ACEX1K Family */
- Altera_CYC2, /* CYCLONII Family */
- Altera_StratixII, /* StratixII Family */
-/* Add new models here */
- max_altera_type /* insert all new types before this */
-} Altera_Family; /* end, typedef Altera_Family */
+enum altera_family {
+ /* insert all new types after this */
+ min_altera_type,
+ /* ACEX1K Family */
+ Altera_ACEX1K,
+ /* CYCLONII Family */
+ Altera_CYC2,
+ /* StratixII Family */
+ Altera_StratixII,
+ /* SoCFPGA Family */
+ Altera_SoCFPGA,
-typedef struct { /* typedef Altera_desc */
- Altera_Family family; /* part type */
- Altera_iface iface; /* interface type */
- size_t size; /* bytes of data part can accept */
- void * iface_fns;/* interface function table */
- void * base; /* base interface address */
- int cookie; /* implementation specific cookie */
-} Altera_desc; /* end, typedef Altera_desc */
+ /* Add new models here */
+
+ /* insert all new types before this */
+ max_altera_type,
+};
+
+typedef struct {
+ /* part type */
+ enum altera_family family;
+ /* interface type */
+ enum altera_iface iface;
+ /* bytes of data part can accept */
+ size_t size;
+ /* interface function table */
+ void *iface_fns;
+ /* base interface address */
+ void *base;
+ /* implementation specific cookie */
+ int cookie;
+} Altera_desc;
/* Generic Altera Functions
*********************************************************************/
Altera_post_fn post;
} altera_board_specific_func;
+#ifdef CONFIG_FPGA_SOCFPGA
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+#endif
+
#endif /* _ALTERA_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite..
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_CRAYL1
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-
-/*
- * Note: I make an "image" from U-Boot itself, which prefixes 0x40
- * bytes of header info, hence start address is thus shifted.
- */
-#define CONFIG_SYS_TEXT_BASE 0xFFFD0040
-
-#define CONFIG_SYS_CLK_FREQ 25000000
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */
-#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
- * keep possible initrd ramdisk decompression out. This is in k (1024 bytes)
- #define CONFIG_PRAM 16
- */
-#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */
-#undef CONFIG_BOOTARGS
-
-/* Bootcmd is overridden by the bootscript in board/cray/L1
- */
-#define CONFIG_SYS_AUTOLOAD "no"
-#define CONFIG_BOOTCOMMAND "dhcp"
-
-/*
- * ..during experiments..
- #define CONFIG_SERVERIP 10.0.0.1
- #define CONFIG_ETHADDR 00:40:a6:80:14:5
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SDRAM_BANK0 1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_IDENT_STRING "Cray L1"
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_SOURCE 1
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_SOURCE
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * how many time to fail & restart a net-TFTP before giving up & resetting
- * the board hoping that a reset of net interface might help..
- */
-#define CONFIG_NET_RESET 5
-
-/*
- * bauds. Just to make it compile; in our case, I read the base_baud
- * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
- * drives the system clock.
- */
-#define CONFIG_SYS_BASE_BAUD 403225
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_SYS_DRAM_TEST 1
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFC00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */
-#define CONFIG_ENV_OFFSET 0x3c8000
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment area */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-
-/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
- * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
- */
-#define CONFIG_SYS_SDRAM_SIZE 32 /* megs of ram */
-#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
- /* the exception vector table */
- /* to the end of the DRAM */
- /* less monitor and malloc area */
-#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128k for malloc space */
-#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
- + CONFIG_SYS_MALLOC_LEN \
- + CONFIG_ENV_SECT_SIZE \
- + CONFIG_SYS_STACK_USAGE )
-
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE)
-/* END ENVIRONNEMENT FLASH */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in OnChipMem )
- */
-#if 1
-/* On Chip Memory location */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#endif
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- */
-#define EEPROM_WRITE_ADDRESS 0xA0
-#define EEPROM_READ_ADDRESS 0xA1
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2004 Sandburst Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
- * design.
- ***********************************************************************/
-
-/*
- * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
-#define CONFIG_440GX 1 /* Specifc GX support */
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
-#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
-
-#define CONFIG_VERY_BIG_RAM 1
-#define CONFIG_VERSION_VARIABLE
-
-#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-#define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
-#define CONFIG_SYS_OFEM_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
-#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
-#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
-
-/* Here for completeness */
-#define CONFIG_SYS_OFEMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
-#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
-#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_PPC4XX_CH1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
-#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */
-#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
-#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
-
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
-
-#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*-----------------------------------------------------------------------
- * Networking
- *----------------------------------------------------------------------*/
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
-#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
-#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
-#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
-#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
-#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
-#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_NETMASK 255.255.0.0
-#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
-#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-
-
-/* Include NetConsole support */
-#define CONFIG_NETCONSOLE
-
-/* Include auto complete with tabs */
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */
-
-
-/*-----------------------------------------------------------------------
- * Console Buffer
- *----------------------------------------------------------------------*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
-
-/*-----------------------------------------------------------------------
- * Memory Test
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*-----------------------------------------------------------------------
- * Compact Flash (in true IDE mode)
- *----------------------------------------------------------------------*/
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
-
-#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride
- to get to the correct offset */
-#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
-
-/*-----------------------------------------------------------------------
- * PCI
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
-#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
-#endif
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1
-#define CONFIG_MPC837x 1
-#define CONFIG_MPC8377 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFC000000
-
-#define CONFIG_PCI 1
-#define CONFIG_PCI_INDIRECT_BRIDGE 1
-
-#define CONFIG_MASK_AER_AO
-#define CONFIG_DISPLAY_AER_FULL
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * On-board devices
- */
-#define CONFIG_TSEC_ENET
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#define CONFIG_PCIE
-#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word stored in EEPROM.
- */
-#define CONFIG_SYS_HRCW_LOW 0
-#define CONFIG_SYS_HRCW_HIGH 0
-
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP 3
-#define CONFIG_SYS_ACR_RPTCNT 3
-
-/* System Priority Control Regsiter */
-#define CONFIG_SYS_SPCR_TSECEP 3
-
-/* System Clock Configuration Register */
-#define CONFIG_SYS_SCCR_TSEC1CM 3
-#define CONFIG_SYS_SCCR_TSEC2CM 0
-#define CONFIG_SYS_SCCR_SDHCCM 3
-#define CONFIG_SYS_SCCR_ENCCM 3 /* also clock for I2C-1 */
-#define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM /* must match */
-#define CONFIG_SYS_SCCR_PCIEXP1CM 3
-#define CONFIG_SYS_SCCR_PCIEXP2CM 3
-#define CONFIG_SYS_SCCR_PCICM 1
-#define CONFIG_SYS_SCCR_SATACM 0xFF
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH 0x087c0000
-#define CONFIG_SYS_SICRL 0x40000000
-
-/*
- * Output Buffer Impedance
- */
-#define CONFIG_SYS_OBIR 0x30000000
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN | DDRCDR_PZ_HIZ |\
- DDRCDR_NZ_HIZ | DDRCDR_ODT |\
- DDRCDR_Q_DRN)
-
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-
-#define CONFIG_SYS_DDR_MODE_WEAK
-#define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2
-#define CONFIG_SYS_DDR_CPO 0x1f
-
-/* SPD table located at offset 0x20 in extended adressing ROM
- * used for HRCW fetch after power-on reset
- */
-#define CONFIG_SPD_EEPROM
-#define SPD_EEPROM_ADDRESS 0x50
-#define SPD_EEPROM_OFFSET 0x20
-#define SPD_EEPROM_ADDR_LEN 2
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (512*1024)
-#define CONFIG_SYS_MALLOC_LEN (512*1024)
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
- GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-#define CONFIG_FSL_ELBC 1
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE 64
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
- BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
- OR_GPCM_XACS | OR_GPCM_SCY_15 |\
- OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
- OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-/*
- * NAND Flash on the Local Bus
- */
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
-
-#define CONFIG_SYS_NAND_BASE 0xE0600000
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
- BR_PS_8 | BR_MS_FCM | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
- OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
- OR_FCM_TRLX | OR_FCM_EHTR)
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CONSOLE ttyS0
-#define CONFIG_BAUDRATE 115200
-
-/* SERDES */
-#define CONFIG_FSL_SERDES
-#define CONFIG_FSL_SERDES1 0xe3000
-#define CONFIG_FSL_SERDES2 0xe3100
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE (256 << 20)
-#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20)
-#define CONFIG_SYS_PCI_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE (1 << 20)
-
-#ifdef CONFIG_PCIE
-#define CONFIG_SYS_PCIE1_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20)
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20)
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
-#define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20)
-
-#define CONFIG_SYS_PCIE2_BASE 0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20)
-#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20)
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
-#define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20)
-#endif
-
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-/*
- * TSEC
- */
-#define CONFIG_GMII /* MII PHY management */
-#define CONFIG_SYS_VSC8601_SKEWFIX
-#define CONFIG_SYS_VSC8601_SKEW_TX 3
-#define CONFIG_SYS_VSC8601_SKEW_RX 3
-
-#define CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 0x10
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHYIDX 0
-
-#define CONFIG_ETHPRIME "TSEC0"
-#define CONFIG_HAS_ETH0
-
-/*
- * SATA
- */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1_OFFSET 0x18000
-#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2_OFFSET 0x19000
-#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_SATA
-
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
-#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
-
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE 1
-
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_LOAD_ADDR 0x2000000
-#define CONFIG_LOADADDR 0x4000000
-#define CONFIG_SYS_CBSIZE 256
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_LOADS_ECHO 1
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
-
-#define CONFIG_SYS_MEMTEST_START (60<<20)
-#define CONFIG_SYS_MEMTEST_END (70<<20)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS 1
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* unused */
-#define CONFIG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* unused */
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-/*
- * I2C EEPROM settings
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_SIZE 0x4000
-
-/*
- * Environment Configuration
- */
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0xFFD00000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-
-/*
- * Video
- */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501_PCI
-#define VIDEO_FB_LITTLE_ENDIAN
-#define CONFIG_CMD_BMP
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-
-/*
- * SPI
- */
-#define CONFIG_MPC8XXX_SPI
-
-/*
- * USB
- */
-#define CONFIG_SYS_USB_HOST
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_KEYBOARD
-/*
- *
- */
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR "s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY 1000
-
-#define MV_CI "MergerBox"
-#define MV_VCI "MergerBox"
-#define MV_FPGA_DATA 0xfc100000
-#define MV_FPGA_SIZE 0x00200000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM 0x02800000
-#define MV_DTB_ADDR_RAM 0x00600000
-#define MV_INITRD_ADDR_RAM 0x01000000
-#define MV_FITADDR 0xfc300000
-#define MV_SPLAH_ADDR 0xffe00000
-
-#define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\
- "then; run fitboot;else;run ubiboot;fi;"
-#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console_nr=0\0"\
- "stdin=serial\0"\
- "stdout=serial\0"\
- "stderr=serial\0"\
- "boot_sqfs=1\0"\
- "usb_dr_mode=host\0"\
- "bootfile=MergerBox.fit\0"\
- "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
- "fpga=0\0"\
- "fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
- "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
- "mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
- "mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
- "mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
- "uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
- "fitaddr=" __stringify(MV_FITADDR) "\0"\
- "mv_version=" U_BOOT_VERSION "\0"\
- "mtdids=" MTDIDS_DEFAULT "\0"\
- "mtdparts=" MTDPARTS_DEFAULT "\0"\
- "dhcp_client_id=" MV_CI "\0"\
- "dhcp_vendor-class-identifier=" MV_VCI "\0"\
- "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
- "protect off all;erase $uboota +0xC0000;"\
- "cp.b $loadaddr $uboota $filesize\0"\
- "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
- "cp.b $loadaddr $fpgadata $filesize\0"\
- "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
- "cp.b $loadaddr $fitaddr $filesize\0"\
- "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
- "rootfstype=squashfs\0"\
- "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
- "rootfstype=ubifs\0"\
- "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
- "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
- "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
- "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
- "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
- "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
- "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
- "imxtract $fitaddr ramdisk $mv_initrd_ram;"\
- "imxtract $fitaddr fdt $mv_dtb_ram\0"\
- "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
- "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
- "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
- "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
- "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
- "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
- "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
- "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
- "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
- "splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
- ""
-
-/*
- * FPGA
- */
-#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004 Sandburst Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * METROBOX.h - configuration Sandburst MetroBox
- ***********************************************************************/
-
-/*
- * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
- *
- *
- * $Log: METROBOX.h,v $
- * Revision 1.21 2005/06/03 15:05:25 tsawyer
- * MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
- *
- * Revision 1.20 2005/04/11 20:51:11 tsawyer
- * fix ethernet
- *
- * Revision 1.19 2005/04/06 15:13:36 tsawyer
- * Update appropriate files to coincide with u-boot 1.1.3
- *
- * Revision 1.18 2005/03/10 14:16:02 tsawyer
- * add def'n for cis8201 short etch option.
- *
- * Revision 1.17 2005/03/09 19:49:51 tsawyer
- * Remove KGDB to allow use of 2nd serial port
- *
- * Revision 1.16 2004/12/02 19:00:23 tsawyer
- * Add misc_init_f to turn on i2c-1 and all four fans before sdram init
- *
- * Revision 1.15 2004/09/15 18:04:12 tsawyer
- * add multiple serial port support
- *
- * Revision 1.14 2004/09/03 15:27:51 tsawyer
- * All metrobox boards are at 66.66 sys clock
- *
- * Revision 1.13 2004/08/05 20:27:46 tsawyer
- * Remove system ace definitions, add net console support
- *
- * Revision 1.12 2004/07/29 20:00:13 tsawyer
- * Add i2c bus 1
- *
- * Revision 1.11 2004/07/21 13:44:18 tsawyer
- * SystemACE is out, CF direct to local bus is in
- *
- * Revision 1.10 2004/06/29 19:08:55 tsawyer
- * Add CONFIG_MISC_INIT_R
- *
- * Revision 1.9 2004/06/28 21:30:53 tsawyer
- * Fix default BOOTARGS
- *
- * Revision 1.8 2004/06/17 15:51:08 tsawyer
- * auto complete
- *
- * Revision 1.7 2004/06/17 15:08:49 tsawyer
- * Add autocomplete
- *
- * Revision 1.6 2004/06/15 12:33:57 tsawyer
- * debugging checkpoint
- *
- * Revision 1.5 2004/06/12 19:48:28 tsawyer
- * Debugging checkpoint
- *
- * Revision 1.4 2004/06/02 13:03:06 tsawyer
- * Fix eth addrs
- *
- * Revision 1.3 2004/05/18 19:56:10 tsawyer
- * Change default bootcommand to pImage.metrobox
- *
- * Revision 1.2 2004/05/18 14:13:44 tsawyer
- * Add bringup values for bootargs and bootcommand.
- * Remove definition of ipaddress and serverip addresses.
- *
- * Revision 1.1 2004/04/16 15:08:54 tsawyer
- * Initial Revision
- *
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_METROBOX 1 /* Board is Metrobox */
-#define CONFIG_440GX 1 /* Specifc GX support */
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
-#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
-
-#define CONFIG_VERY_BIG_RAM 1
-#define CONFIG_VERSION_VARIABLE
-
-#define CONFIG_IDENT_STRING " Sandburst Metrobox"
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
-#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
-#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
-#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
-#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_PPC4XX_CH1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
-#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */
-#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
-#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
-
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
-
-#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
-#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000"
-#define CONFIG_BOOTDELAY 5 /* disable autoboot */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*-----------------------------------------------------------------------
- * Networking
- *----------------------------------------------------------------------*/
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
-#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
-#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
-#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
-#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
-#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
-#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_NETMASK 255.255.0.0
-#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
-#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-
-
-/* Include NetConsole support */
-#define CONFIG_NETCONSOLE
-
-/* Include auto complete with tabs */
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "MetroBox=> " /* Monitor Command Prompt */
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */
-
-
-/*-----------------------------------------------------------------------
- * Console Buffer
- *----------------------------------------------------------------------*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
-
-/*-----------------------------------------------------------------------
- * Memory Test
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*-----------------------------------------------------------------------
- * Compact Flash (in true IDE mode)
- *----------------------------------------------------------------------*/
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
-
-#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride
- to get to the correct offset */
-#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
-
-/*-----------------------------------------------------------------------
- * PCI
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
-#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
-#endif
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+#define CONFIG_SYS_GENERIC_BOARD
+
/***********************************************************
* Note that it may also be a MIP405T board which is a subset of the
* MIP405
+++ /dev/null
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2008
- * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-#define CONFIG_MPC5200 1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFF800000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
-
-#define CONFIG_MISC_INIT_R 1
-
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT 5
-#endif
-
-#define CONFIG_PSC_CONSOLE 1
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#undef CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING 1
-#define CONFIG_HIGH_BATS 1
-
-#define MV_CI mvBlueCOUGAR-P
-#define MV_VCI mvBlueCOUGAR-P
-#define MV_FPGA_DATA 0xff860000
-#define MV_FPGA_SIZE 0
-#define MV_KERNEL_ADDR 0xffd00000
-#define MV_INITRD_ADDR 0xff900000
-#define MV_INITRD_LENGTH 0x00400000
-#define MV_SCRATCH_ADDR 0x00000000
-#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
-#define MV_SCRIPT_ADDR 0xff840000
-#define MV_SCRIPT_ADDR2 0xff850000
-#define MV_DTB_ADDR 0xfffc0000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM 0x00100000
-#define MV_DTB_ADDR_RAM 0x00600000
-#define MV_INITRD_ADDR_RAM 0x01000000
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,5200@0"
-#define OF_SOC "soc5200@f0000000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define MV_DTB_NAME mvbc-p.dtb
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/*
- * Supported commands
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_I2C
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/*
- * Autoboot
- */
-#define CONFIG_BOOTDELAY 2
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR "s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY 1000
-
-#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
- then source ${script_addr}; \
- else source ${script_addr2}; \
- fi;"
-
-#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console_nr=0\0" \
- "console=yes\0" \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0" \
- "fpga=0\0" \
- "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
- "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
- "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
- "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
- "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
- "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
- "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
- "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
- "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
- "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
- "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
- "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
- "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
- "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
- "mv_version=" U_BOOT_VERSION "\0" \
- "dhcp_client_id=" __stringify(MV_CI) "\0" \
- "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
- "netretry=no\0" \
- "use_static_ipaddr=no\0" \
- "static_ipaddr=192.168.90.10\0" \
- "static_netmask=255.255.255.0\0" \
- "static_gateway=0.0.0.0\0" \
- "initrd_name=uInitrd.mvbc-p-rfs\0" \
- "zcip=no\0" \
- "netboot=yes\0" \
- "mvtest=Ff\0" \
- "tried_bootfromflash=no\0" \
- "tried_bootfromnet=no\0" \
- "use_dhcp=yes\0" \
- "gev_start=yes\0" \
- "mvbcdma_debug=0\0" \
- "mvbcia_debug=0\0" \
- "propdev_debug=0\0" \
- "gevss_debug=0\0" \
- "watchdog=1\0" \
- "sensor_cnt=1\0" \
- ""
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-
-/*
- * Flash configuration
- */
-#undef CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE 0x00800000
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_SYS_FLASH_PROTECTION
-
-#define CONFIG_ENV_ADDR 0xFFFE0000
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT 1
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-#define CONFIG_SYS_MALLOC_LEN (512 << 10)
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_MODULE 1
-#define CONFIG_SYS_I2C_SPEED 86000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_E1000
-#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
-#undef CONFIG_MPC5xxx_FEC
-#undef CONFIG_PHY_ADDR
-#define CONFIG_NETDEV eth0
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#undef CONFIG_SYS_LONGHELP
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE 1024
-#else
-#define CONFIG_SYS_CBSIZE 256
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00800000
-#define CONFIG_SYS_MEMTEST_END 0x02f00000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x02000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 0x00200000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
-
-#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x00047800
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST 0x000000f0
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
-
-#define CONFIG_SYS_RESET_ADDRESS 0x00000100
-
-#undef FPGA_DEBUG
-#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA 1
-#define CONFIG_FPGA_CYCLON2 1
-#define CONFIG_FPGA_COUNT 1
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) Matrix Vision GmbH 2008
- *
- * Matrix Vision mvBlueLYNX-M7 configuration file
- * based on Freescale's MPC8349ITX.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1
-#define CONFIG_MPC834x 1
-#define CONFIG_MPC8343 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_SKIP_HOST_BRIDGE
-#define CONFIG_TSEC_ENET
-#define CONFIG_MPC8XXX_SPI
-#define CONFIG_HARD_SPI
-#define MVBLM7_MMC_CS 0x04000000
-#define CONFIG_MISC_INIT_R
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 100000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-/*
- * DDR Setup
- */
-#undef CONFIG_SPD_EEPROM
-
-#define CONFIG_SYS_DDR_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_83XX_DDR_USES_CS0 1
-#define CONFIG_SYS_MEMTEST_START (60<<20)
-#define CONFIG_SYS_MEMTEST_END (70<<20)
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \
- | DDRCDR_NZ_HIZ \
- | DDRCDR_Q_DRN)
- /* 0x22000001 */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-
-#define CONFIG_SYS_DDR_SIZE 512
-
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3837c322
-#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_INTERVAL 0x02000100
-
-#define CONFIG_SYS_DDR_MODE 0x04040242
-#define CONFIG_SYS_DDR_MODE2 0x00800000
-
-/* Flash */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE 0xFF800000
-#define CONFIG_SYS_FLASH_SIZE 8
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-
-/*
- * U-Boot memory configuration
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#undef CONFIG_SYS_RAMBOOT
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-
-/*
- * Local Bus LCRR and LBCR regs
- * LCRR: DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
-/* LB refresh timer prescal, 266MHz/32*/
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_CONSOLE ttyS0
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define MV_DTB_NAME "mvblm7.dtb"
-
-/*
- * PCI
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCI1_MMIO_BASE \
- (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
-
-#define CONFIG_NET_RETRY_COUNT 3
-
-#define CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66666667
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-
-/* TSEC */
-#define CONFIG_GMII
-#define CONFIG_SYS_VSC8601_SKEWFIX
-#define CONFIG_SYS_VSC8601_SKEW_TX 3
-#define CONFIG_SYS_VSC8601_SKEW_RX 3
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC2
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_FEC1_PHY_NORXERR
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define TSEC1_PHY_ADDR 0x10
-#define TSEC1_PHYIDX 0
-#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
-
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_FEC2_PHY_NORXERR
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-#define TSEC2_PHY_ADDR 0x11
-#define TSEC2_PHYIDX 0
-#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
-
-#define CONFIG_ETHPRIME "TSEC0"
-
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/* USB */
-#define CONFIG_SYS_USB_HOST
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-/*
- * Environment
- */
-#undef CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0xFF800000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#define CONFIG_LOADS_ECHO
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_USB
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 0x200000
-
-#define CONFIG_SYS_PROMPT "mvBL-M7> "
-#define CONFIG_SYS_CBSIZE 256
-
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-#define CONFIG_SYS_HRCW_LOW 0x0
-#define CONFIG_SYS_HRCW_HIGH 0x0
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
-
-/* clocking */
-#define CONFIG_SYS_SCCR_ENCCM 0
-#define CONFIG_SYS_SCCR_USBMPHCM 0
-#define CONFIG_SYS_SCCR_USBDRCM 2
-#define CONFIG_SYS_SCCR_TSEC1CM 1
-#define CONFIG_SYS_SCCR_TSEC2CM 1
-
-#define CONFIG_SYS_SICRH 0x1fef0003
-#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
-
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1
-
-/* DDR */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* no PCI2 */
-#define CONFIG_SYS_IBAT3L 0
-#define CONFIG_SYS_IBAT3U 0
-#define CONFIG_SYS_IBAT4L 0
-#define CONFIG_SYS_IBAT4U 0
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT7L 0
-#define CONFIG_SYS_IBAT7U 0
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV eth0
-
-/* Default path and filenames */
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR "s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY 1000
-
-#define MV_CI "mvBL-M7"
-#define MV_VCI "mvBL-M7"
-#define MV_FPGA_DATA 0xfff40000
-#define MV_FPGA_SIZE 0
-#define MV_KERNEL_ADDR 0xff810000
-#define MV_INITRD_ADDR 0xffb00000
-#define MV_SCRIPT_ADDR 0xff804000
-#define MV_SCRIPT_ADDR2 0xff806000
-#define MV_DTB_ADDR 0xff808000
-#define MV_INITRD_LENGTH 0x00400000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM 0x00100000
-#define MV_DTB_ADDR_RAM 0x00600000
-#define MV_INITRD_ADDR_RAM 0x01000000
-
-#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \
- "then source ${script_addr}; " \
- "else source ${script_addr2}; " \
- "fi;"
-#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console_nr=0\0" \
- "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0" \
- "fpga=0\0" \
- "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
- "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
- "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
- "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
- "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
- "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
- "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
- "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
- "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
- "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
- "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
- "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
- "mv_version=" U_BOOT_VERSION "\0" \
- "dhcp_client_id=" MV_CI "\0" \
- "dhcp_vendor-class-identifier=" MV_VCI "\0" \
- "netretry=no\0" \
- "use_static_ipaddr=no\0" \
- "static_ipaddr=192.168.90.10\0" \
- "static_netmask=255.255.255.0\0" \
- "static_gateway=0.0.0.0\0" \
- "initrd_name=uInitrd.mvBL-M7-rfs\0" \
- "zcip=no\0" \
- "netboot=yes\0" \
- "mvtest=Ff\0" \
- "tried_bootfromflash=no\0" \
- "tried_bootfromnet=no\0" \
- "bootfile=mvblm72625.boot\0" \
- "use_dhcp=yes\0" \
- "gev_start=yes\0" \
- "mvbcdma_debug=0\0" \
- "mvbcia_debug=0\0" \
- "propdev_debug=0\0" \
- "gevss_debug=0\0" \
- "watchdog=0\0" \
- "usb_dr_mode=host\0" \
- "sensor_cnt=2\0" \
- ""
-
-#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2010
- * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-#define CONFIG_MPC5200 1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFF800000
-#endif
-#define CONFIG_SYS_LDSCRIPT "board/matrix_vision/mvsmr/u-boot.lds"
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
-
-#define CONFIG_MISC_INIT_R 1
-
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT 5
-#endif
-
-#define CONFIG_PSC_CONSOLE 1
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\
- 230400}
-
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#undef CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING 1
-#define CONFIG_HIGH_BATS 1
-
-#define MV_CI mvSMR
-#define MV_VCI mvSMR
-#define MV_FPGA_DATA 0xff840000
-#define MV_FPGA_SIZE 0x1ff88
-#define MV_KERNEL_ADDR 0xfff00000
-#define MV_SCRIPT_ADDR 0xff806000
-#define MV_INITRD_ADDR 0xff880000
-#define MV_INITRD_LENGTH 0x00240000
-#define MV_SCRATCH_ADDR 0xffcc0000
-#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM 0x00100000
-#define MV_INITRD_ADDR_RAM 0x00400000
-
-/*
- * Supported commands
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_LIB_RAND
-
-/*
- * Autoboot
- */
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR "abcdefg"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_BOOTCOMMAND "source ${script_addr}"
-#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \
- " allocate=6M"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console_nr=0\0" \
- "console=no\0" \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0" \
- "fpga=0\0" \
- "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
- "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
- "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
- "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
- "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
- "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
- "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
- "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
- "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
- "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
- "mv_version=" U_BOOT_VERSION "\0" \
- "dhcp_client_id=" __stringify(MV_CI) "\0" \
- "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
- "netretry=no\0" \
- "use_static_ipaddr=no\0" \
- "static_ipaddr=192.168.0.101\0" \
- "static_netmask=255.255.255.0\0" \
- "static_gateway=0.0.0.0\0" \
- "initrd_name=uInitrd.mvsmr-rfs\0" \
- "zcip=yes\0" \
- "netboot=no\0" \
- ""
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-
-/*
- * Flash configuration
- */
-#undef CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE 0x00800000
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-#define CONFIG_ENV_OFFSET 0x8000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-
-/* used by linker script to wrap code around */
-#define CONFIG_SCRIPT_OFFSET 0x6000
-#define CONFIG_SCRIPT_SECT_SIZE 0x2000
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT 1
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-#define CONFIG_SYS_MALLOC_LEN (512 << 10)
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_MODULE 1
-#define CONFIG_SYS_I2C_SPEED 86000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_MPC5xxx_FEC
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR 0x00
-#define CONFIG_NETDEV eth0
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#undef CONFIG_SYS_LONGHELP
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE 1024
-#else
-#define CONFIG_SYS_CBSIZE 256
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00800000
-#define CONFIG_SYS_MEMTEST_END 0x02f00000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x02000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 0x00200000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044
-
-#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x00047800
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST 0x000000f0
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
-
-#define CONFIG_SYS_RESET_ADDRESS 0x00000100
-
-#undef FPGA_DEBUG
-#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX 1
-#define CONFIG_FPGA_SPARTAN2 1
-#define CONFIG_FPGA_COUNT 1
-
-#endif
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Serial Console Configuration */
#define CONFIG_5xx_CONS_SCI1
#undef CONFIG_5xx_CONS_SCI2
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
+#define CONFIG_BOARD_EARLY_INIT_F
/***********************************************************************
* Last Stage Init
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+#define CONFIG_SYS_GENERIC_BOARD
+
/***********************************************************
* Clock
***********************************************************/
#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_SYS_GENERIC_BOARD
+
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/* input clock of PLL (VCMA9 has 12MHz input clock) */
/* File system */
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_JFFS2
/* Bootcount using the RTC block */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_AM33XX
+#define CONFIG_SYS_BOOTCOUNT_BE
/* USB gadget RNDIS */
#define CONFIG_SPL_MUSB_NEW_SUPPORT
*/
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_AUTONEG
-#define CONFIG_DW_SEARCH_PHY
#define CONFIG_NET_MULTI
/*
+++ /dev/null
-/*
- * bluestone.h - configuration for Bluestone (APM821XX)
- *
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_APM821XX 1 /* APM821XX series */
-#define CONFIG_HOSTNAME bluestone
-
-#define CONFIG_440 1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-#define CONFIG_SYS_CLK_FREQ 50000000
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-/* EBC stuff */
-/* later mapped to this addr */
-#define CONFIG_SYS_FLASH_BASE 0xFFF00000
-#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */
-
-/* EBC Boot Space: 0xFF000000 */
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000
-#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */
-#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
-#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/
-
-#define CONFIG_SYS_SRAM_SIZE (256 << 10)
-/*
- * Initial RAM & stack pointer (placed in OCM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Environment
- */
-/*
- * Define here the location of the environment variables (FLASH).
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 80
-/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-/* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-/* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/* SDRAM */
-#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
-#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
-#define CONFIG_DDR_ECC 1 /* with ECC support */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-
-/*
- * Ethernet
- */
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII
-#define CONFIG_HAS_ETH0
-/* PHY address, See schematics */
-#define CONFIG_PHY_ADDR 0x1f
-/* reset phy upon startup */
-#define CONFIG_PHY_RESET 1
-/* Include GbE speed/duplex detection */
-#define CONFIG_PHY_GIGE 1
-#define CONFIG_PHY_DYNAMIC_ANEG 1
-
-/*
- * External Bus Controller (EBC) Setup
- **/
-#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \
- EBC_CFG_PTD_ENABLE | \
- EBC_CFG_RTC_2048PERCLK | \
- EBC_CFG_ATC_HI | \
- EBC_CFG_DTC_HI | \
- EBC_CFG_CTC_HI | \
- EBC_CFG_OEO_PREVIOUS)
-/* NOR Flash */
-#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
- EBC_BXAP_TWT_ENCODE(64) | \
- EBC_BXAP_BCE_DISABLE | \
- EBC_BXAP_BCT_2TRANS | \
- EBC_BXAP_CSN_ENCODE(1) | \
- EBC_BXAP_OEN_ENCODE(2) | \
- EBC_BXAP_WBN_ENCODE(2) | \
- EBC_BXAP_WBF_ENCODE(2) | \
- EBC_BXAP_TH_ENCODE(7) | \
- EBC_BXAP_SOR_DELAYED | \
- EBC_BXAP_BEM_WRITEONLY | \
- EBC_BXAP_PEN_DISABLED)
-/* Peripheral Bank Configuration Register - EBC_BxCR */
-#define CONFIG_SYS_EBC_PB0CR \
- (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
- EBC_BXCR_BS_1MB | \
- EBC_BXCR_BU_RW | \
- EBC_BXCR_BW_8BIT)
-
-
-#endif /* __CONFIG_H */
"run mmcboot;" \
"fi;" \
"if run loadzimage; then " \
- "if test $fdtfile; then " \
+ "if test -z \"${fdtfile}\"; then " \
"setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \
"fi;" \
"if run loadfdt; then " \
/* Max time to hold reset on this board, see doc/README.omap-reset-time */
#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
-#define CONFIG_BOARD_LATE_INIT
#define CONFIG_CMD_SCSI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_MUSB_GADGET
#define CONFIG_MUSB_PIO_ONLY
#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET_DUALSPEED
+#undef CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_MUSB_HOST
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Virtual target or real hardware */
+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
+
+#define CONFIG_ARMV7
+#define CONFIG_SYS_THUMB_BUILD
+
+#define CONFIG_SOCFPGA
+
+/*
+ * High level configuration
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CLOCKS
+
+#define CONFIG_FIT
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x0
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TEXT_BASE 0x08000040
+#else
+#define CONFIG_SYS_TEXT_BASE 0x01000040
+#endif
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Cache
+ */
+#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
+
+/*
+ * Ethernet on SoC (EMAC)
+ */
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_MII
+#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_GIGE
+#endif
+
+/*
+ * FPGA Driver
+ */
+#ifdef CONFIG_CMD_FPGA
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_SOCFPGA
+#define CONFIG_FPGA_COUNT 1
+#endif
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
+#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TIMER_RATE 2400000
+#else
+#define CONFIG_SYS_TIMER_RATE 25000000
+#endif
+
+/*
+ * L4 Watchdog
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
+#define CONFIG_DW_WDT_CLOCK_KHZ 25000
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000
+#endif
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
+#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
+#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
+/* FIXME */
+/* using smaller max blk cnt to avoid flooding the limited stack we have */
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
+#endif
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_NS16550_CLK 1000000
+#else
+#define CONFIG_SYS_NS16550_CLK 100000000
+#endif
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * U-Boot environment
+ */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 4096
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_STACK_SIZE (4 * 1024)
+#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */
+#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
+#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
+
+#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_H__
#include <asm/arch/socfpga_base_addrs.h>
#include "../../board/altera/socfpga/pinmux_config.h"
#include "../../board/altera/socfpga/iocsr_config.h"
#include "../../board/altera/socfpga/pll_config.h"
-/*
- * High level configuration
- */
-/* Virtual target or real hardware */
-#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
-
-#define CONFIG_ARMV7
-#define CONFIG_SYS_DCACHE_OFF
-#undef CONFIG_USE_IRQ
-
-#define CONFIG_MISC_INIT_R
-#define CONFIG_SINGLE_BOOTLOADER
-#define CONFIG_SOCFPGA
-
-/* base address for .text section */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TEXT_BASE 0x08000040
-#else
-#define CONFIG_SYS_TEXT_BASE 0x01000040
-#endif
-#define CONFIG_SYS_LOAD_ADDR 0x7fc0
-
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 256
-/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/*
- * Display CPU and Board Info
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/*
- * Enable early stage initialization at C environment
- */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* flat device tree */
-#define CONFIG_OF_LIBFDT
-/* skip updating the FDT blob */
-#define CONFIG_FDT_BLOB_SKIP_UPDATE
-/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
-#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
-
-#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
-#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
-
-/*
- * Memory allocation (MALLOC)
- */
-/* Room required on the stack for the environment data */
-#define CONFIG_ENV_SIZE 1024
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/* SP location before relocation, must use scratch RAM */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-/* Reserving 0x100 space at back of scratch RAM for debug info */
-#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
-/* Stack pointer prior relocation, must situated at on-chip RAM */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-
-/*
- * Command line configuration.
- */
+/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#include <config_cmd_default.h>
-/* FAT file system support */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_REGEX /* Enable regular expression support */
-/*
- * Misc
- */
-#define CONFIG_DOS_PARTITION 1
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_PARTITIONS
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "zImage"
+#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_BOOTCOMMAND "run ramboot"
+#else
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
#endif
+#define CONFIG_LOADADDR 0x8000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/*
- * Environment setup
- */
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
+#define CONFIG_EPHY0_PHY_ADDR 0
-/* Delay before automatically booting the default image */
-#define CONFIG_BOOTDELAY 3
-/* Enable auto completion of commands using TAB */
-#define CONFIG_AUTO_COMPLETE
-/* use "hush" command parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_CMD_RUN
+/* PHY */
+#define CONFIG_EPHY1_PHY_ADDR 4
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
-#define CONFIG_BOOTCOMMAND "run ramboot"
+#endif
-/*
- * arguments passed to the bootm command. The value of
- * CONFIG_BOOTARGS goes into the environment value "bootargs".
- * Do note the value will overide also the chosen node in FDT blob.
- */
-#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
+/* Extra Environment */
+#define CONFIG_HOSTNAME socfpga_cyclone5
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
- "bootimage=uImage\0" \
+ "bootimage=zImage\0" \
"fdt_addr=100\0" \
- "fsloadcmd=ext2load\0" \
- "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "fsloadcmd=ext2load\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
"qspiroot=/dev/mtdblock0\0" \
"qspirootfstype=jffs2\0" \
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
"bootm ${loadaddr} - ${fdt_addr}\0"
-/* using environment setting for stdin, stdout, stderr */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-/* Enable the call to overwrite_console() */
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-/* Enable overwrite of previous console environment settings */
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-
-
-/*
- * Hardware drivers
- */
-
-/*
- * SDRAM Memory Map
- */
-/* We have 1 bank of DRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-/* SDRAM Bank #1 */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE 0x40000000
-
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_START 0x00000000
-#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
-
-/*
- * NS16550 Configuration
- */
-#define UART0_BASE SOCFPGA_UART0_ADDRESS
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define V_NS16550_CLK 1000000
-#else
-#define V_NS16550_CLK 100000000
-#endif
-#define CONFIG_BAUDRATE 115200
-
-/*
- * FLASH
- */
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * L4 OSC1 Timer 0
- */
-/* This timer use eosc1 where the clock frequency is fixed
- * throughout any condition */
-#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-/* reload value when timer count to zero */
-#define TIMER_LOAD_VAL 0xFFFFFFFF
-/* Timer info */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TIMER_RATE 2400000
-#else
-#define CONFIG_SYS_TIMER_RATE 25000000
-#endif
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
-
-#define CONFIG_ENV_IS_NOWHERE
-
-/*
- * network support
- */
-#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_DESIGNWARE_ETH 1
-#endif
-
-#ifdef CONFIG_DESIGNWARE_ETH
-#define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS
-#define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS
-/* console support for network */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-/* designware */
-#define CONFIG_NET_MULTI
-#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_DW_SEARCH_PHY
-#define CONFIG_MII
-#define CONFIG_PHY_GIGE
-#define CONFIG_DW_AUTONEG
-#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
-/* EMAC controller and PHY used */
-#define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE
-#define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR
-#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
-#endif /* CONFIG_DESIGNWARE_ETH */
-
-/*
- * L4 Watchdog
- */
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
-#define CONFIG_DESIGNWARE_WATCHDOG
-#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
-/* Clocks source frequency to watchdog timer */
-#define CONFIG_DW_WDT_CLOCK_KHZ 25000
-
-
-/*
- * SPL "Second Program Loader" aka Initial Software
- */
-
-/* Enable building of SPL globally */
-#define CONFIG_SPL_FRAMEWORK
-
-/* TEXT_BASE for linking the SPL binary */
-#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
-
-/* Stack size for SPL */
-#define CONFIG_SPL_STACK_SIZE (4 * 1024)
-
-/* MALLOC size for SPL */
-#define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
-
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_BOARD_INIT
-
-#define CHUNKSZ_CRC32 (1 * 1024)
-
-#define CONFIG_CRC32_VERIFY
-
-/* Linker script for SPL */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
-
-/* Support for common/libcommon.o in SPL binary */
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-/* Support for lib/libgeneric.o in SPL binary */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-
-/* Support for watchdog */
-#define CONFIG_SPL_WATCHDOG_SUPPORT
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */
u32 cnt;
u32 addr;
u32 next_addr;
-};
+} __aligned(ARCH_DMA_MINALIGN);
static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
{
#define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */
#define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */
#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */
+#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */
/*
* Compression Types
*
* Copyright 1994 - 2000 Neil Russell.
* (See License)
- *
+ * SPDX-License-Identifier: GPL-2.0
*
* History
* 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added
void stdio_print_current_devices(void);
#ifdef CONFIG_SYS_STDIO_DEREGISTER
-int stdio_deregister(const char *devname);
-int stdio_deregister_dev(struct stdio_dev *dev);
+int stdio_deregister(const char *devname, int force);
+int stdio_deregister_dev(struct stdio_dev *dev, int force);
#endif
struct list_head* stdio_get_list(void);
struct stdio_dev* stdio_get_by_name(const char* name);
#ifdef CONFIG_USB_KEYBOARD
int drv_usb_kbd_init(void);
-int usb_kbd_deregister(void);
+int usb_kbd_deregister(int force);
#endif
/* routines */
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ARP_H__
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ * SPDX-License-Identifier: GPL-2.0
*/
#if defined(CONFIG_CMD_CDP)
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ * SPDX-License-Identifier: GPL-2.0
*/
#include "ping.h"
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __PING_H__
# CONFIG_SPL=y -> spl
# CONFIG_TPL=y -> tpl
- sed -n -e 's/^CONFIG_\(SPL\|TPL\)=y$/\1/p' $KCONFIG_CONFIG | \
- tr '[A-Z]' '[a-z]'
+ sed -n -e 's/^CONFIG_SPL=y$/spl/p' -e 's/^CONFIG_TPL=y$/tpl/p' \
+ $KCONFIG_CONFIG
}
do_silentoldconfig () {
if [ ! -r $defconfig_path ]; then
echo >&2 "***"
- echo >&2 "*** Can't find default configuration \"confis/$1\"!"
+ echo >&2 "*** Can't find default configuration \"configs/$1\"!"
echo >&2 "***"
exit 1
fi
unmatched="$unmatched%$symbol:$line"
fi
done < defconfig
+
+ output_lines="$output_lines%$unmatched"
done
rm -f defconfig
os_support.o \
pblimage.o \
pbl_crc32.o \
+ socfpgaimage.o \
lib/sha1.o \
lib/sha256.o \
ublimage.o \
init_ubl_image_type();
/* Init Davinci AIS support */
init_ais_image_type();
+ /* Init Altera SOCFPGA support */
+ init_socfpga_image_type();
/* Init TI Keystone boot image generation/list support */
init_gpimage_type();
}
void init_fit_image_type(void);
void init_ubl_image_type(void);
void init_omap_image_type(void);
+void init_socfpga_image_type(void);
void init_gpimage_type(void);
void pbl_load_uboot(int fd, struct image_tool_params *mparams);
--- /dev/null
+/*
+ * Copyright (C) 2014 Charles Manning <cdhmanning@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Reference doc http://www.altera.com.cn/literature/hb/cyclone-v/cv_5400A.pdf
+ * Note this doc is not entirely accurate. Of particular interest to us is the
+ * "header" length field being in U32s and not bytes.
+ *
+ * "Header" is a structure of the following format.
+ * this is positioned at 0x40.
+ *
+ * Endian is LSB.
+ *
+ * Offset Length Usage
+ * -----------------------
+ * 0x40 4 Validation word 0x31305341
+ * 0x44 1 Version (whatever, zero is fine)
+ * 0x45 1 Flags (unused, zero is fine)
+ * 0x46 2 Length (in units of u32, including the end checksum).
+ * 0x48 2 Zero
+ * 0x4A 2 Checksum over the header. NB Not CRC32
+ *
+ * At the end of the code we have a 32-bit CRC checksum over whole binary
+ * excluding the CRC.
+ *
+ * Note that the CRC used here is **not** the zlib/Adler crc32. It is the
+ * CRC-32 used in bzip2, ethernet and elsewhere.
+ *
+ * The image is padded out to 64k, because that is what is
+ * typically used to write the image to the boot medium.
+ */
+
+#include "pbl_crc32.h"
+#include "imagetool.h"
+#include <image.h>
+
+#define HEADER_OFFSET 0x40
+#define VALIDATION_WORD 0x31305341
+#define PADDED_SIZE 0x10000
+
+/* To allow for adding CRC, the max input size is a bit smaller. */
+#define MAX_INPUT_SIZE (PADDED_SIZE - sizeof(uint32_t))
+
+static uint8_t buffer[PADDED_SIZE];
+
+static struct socfpga_header {
+ uint32_t validation;
+ uint8_t version;
+ uint8_t flags;
+ uint16_t length_u32;
+ uint16_t zero;
+ uint16_t checksum;
+} header;
+
+/*
+ * The header checksum is just a very simple checksum over
+ * the header area.
+ * There is still a crc32 over the whole lot.
+ */
+static uint16_t hdr_checksum(struct socfpga_header *header)
+{
+ int len = sizeof(*header) - sizeof(header->checksum);
+ uint8_t *buf = (uint8_t *)header;
+ uint16_t ret = 0;
+
+ while (--len)
+ ret += *buf++;
+
+ return ret;
+}
+
+
+static void build_header(uint8_t *buf, uint8_t version, uint8_t flags,
+ uint16_t length_bytes)
+{
+ header.validation = htole32(VALIDATION_WORD);
+ header.version = version;
+ header.flags = flags;
+ header.length_u32 = htole16(length_bytes/4);
+ header.zero = 0;
+ header.checksum = htole16(hdr_checksum(&header));
+
+ memcpy(buf, &header, sizeof(header));
+}
+
+/*
+ * Perform a rudimentary verification of header and return
+ * size of image.
+ */
+static int verify_header(const uint8_t *buf)
+{
+ memcpy(&header, buf, sizeof(header));
+
+ if (le32toh(header.validation) != VALIDATION_WORD)
+ return -1;
+ if (le16toh(header.checksum) != hdr_checksum(&header))
+ return -1;
+
+ return le16toh(header.length_u32) * 4;
+}
+
+/* Sign the buffer and return the signed buffer size */
+static int sign_buffer(uint8_t *buf,
+ uint8_t version, uint8_t flags,
+ int len, int pad_64k)
+{
+ uint32_t calc_crc;
+
+ /* Align the length up */
+ len = (len + 3) & (~3);
+
+ /* Build header, adding 4 bytes to length to hold the CRC32. */
+ build_header(buf + HEADER_OFFSET, version, flags, len + 4);
+
+ /* Calculate and apply the CRC */
+ calc_crc = ~pbl_crc32(0, (char *)buf, len);
+
+ *((uint32_t *)(buf + len)) = htole32(calc_crc);
+
+ if (!pad_64k)
+ return len + 4;
+
+ return PADDED_SIZE;
+}
+
+/* Verify that the buffer looks sane */
+static int verify_buffer(const uint8_t *buf)
+{
+ int len; /* Including 32bit CRC */
+ uint32_t calc_crc;
+ uint32_t buf_crc;
+
+ len = verify_header(buf + HEADER_OFFSET);
+ if (len < 0) {
+ fprintf(stderr, "Invalid header\n");
+ return -1;
+ }
+
+ if (len < HEADER_OFFSET || len > PADDED_SIZE) {
+ fprintf(stderr, "Invalid header length (%i)\n", len);
+ return -1;
+ }
+
+ /*
+ * Adjust length to the base of the CRC.
+ * Check the CRC.
+ */
+ len -= 4;
+
+ calc_crc = ~pbl_crc32(0, (const char *)buf, len);
+
+ buf_crc = le32toh(*((uint32_t *)(buf + len)));
+
+ if (buf_crc != calc_crc) {
+ fprintf(stderr, "CRC32 does not match (%08x != %08x)\n",
+ buf_crc, calc_crc);
+ return -1;
+ }
+
+ return 0;
+}
+
+/* mkimage glue functions */
+static int socfpgaimage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ if (image_size != PADDED_SIZE)
+ return -1;
+
+ return verify_buffer(ptr);
+}
+
+static void socfpgaimage_print_header(const void *ptr)
+{
+ if (verify_buffer(ptr) == 0)
+ printf("Looks like a sane SOCFPGA preloader\n");
+ else
+ printf("Not a sane SOCFPGA preloader\n");
+}
+
+static int socfpgaimage_check_params(struct image_tool_params *params)
+{
+ /* Not sure if we should be accepting fflags */
+ return (params->dflag && (params->fflag || params->lflag)) ||
+ (params->fflag && (params->dflag || params->lflag)) ||
+ (params->lflag && (params->dflag || params->fflag));
+}
+
+static int socfpgaimage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_SOCFPGAIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+/*
+ * To work in with the mkimage framework, we do some ugly stuff...
+ *
+ * First, socfpgaimage_vrec_header() is called.
+ * We prepend a fake header big enough to make the file PADDED_SIZE.
+ * This gives us enough space to do what we want later.
+ *
+ * Next, socfpgaimage_set_header() is called.
+ * We fix up the buffer by moving the image to the start of the buffer.
+ * We now have some room to do what we need (add CRC and padding).
+ */
+
+static int data_size;
+#define FAKE_HEADER_SIZE (PADDED_SIZE - data_size)
+
+static int socfpgaimage_vrec_header(struct image_tool_params *params,
+ struct image_type_params *tparams)
+{
+ struct stat sbuf;
+
+ if (params->datafile &&
+ stat(params->datafile, &sbuf) == 0 &&
+ sbuf.st_size <= MAX_INPUT_SIZE) {
+ data_size = sbuf.st_size;
+ tparams->header_size = FAKE_HEADER_SIZE;
+ }
+ return 0;
+}
+
+static void socfpgaimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ uint8_t *buf = (uint8_t *)ptr;
+
+ /*
+ * This function is called after vrec_header() has been called.
+ * At this stage we have the FAKE_HEADER_SIZE dummy bytes followed by
+ * data_size image bytes. Total = PADDED_SIZE.
+ * We need to fix the buffer by moving the image bytes back to
+ * the beginning of the buffer, then actually do the signing stuff...
+ */
+ memmove(buf, buf + FAKE_HEADER_SIZE, data_size);
+ memset(buf + data_size, 0, FAKE_HEADER_SIZE);
+
+ sign_buffer(buf, 0, 0, data_size, 0);
+}
+
+static struct image_type_params socfpgaimage_params = {
+ .name = "Altera SOCFPGA preloader support",
+ .vrec_header = socfpgaimage_vrec_header,
+ .header_size = 0, /* This will be modified by vrec_header() */
+ .hdr = (void *)buffer,
+ .check_image_type = socfpgaimage_check_image_types,
+ .verify_header = socfpgaimage_verify_header,
+ .print_header = socfpgaimage_print_header,
+ .set_header = socfpgaimage_set_header,
+ .check_params = socfpgaimage_check_params,
+};
+
+void init_socfpga_image_type(void)
+{
+ register_image_type(&socfpgaimage_params);
+}
projects / oweals / u-boot.git / commitdiff