First tests with O/C recovery mode for AR9331

diff --git a/u-boot/board/ar7240/ap121/hornet_pll_init.S b/u-boot/board/ar7240/ap121/hornet_pll_init.S
index a718490c55c1951a007e918ba7ece8e1cc13ad2b..0158625caa74502b52dea5ab2623144d12988d96 100755 (executable)
--- a/u-boot/board/ar7240/ap121/hornet_pll_init.S
+++ b/u-boot/board/ar7240/ap121/hornet_pll_init.S
@@ -283,10 +283,22 @@ pmu_loop2_end:
     set_reg(AR7240_USB_PLL_CONFIG, CPU_PLL_SETTLE_TIME_VAL)
     nop
 
-pll_unlock_handler:
+/* read GPIO_SET register */
+       li  t0, KSEG1ADDR(AR7240_GPIO_IN)
+       lw  t1, 0(t0)
+       and t1, t1, (1 << GPIO_RST_BUTTON_BIT)
+       beq     t1,     (1 << GPIO_RST_BUTTON_BIT), pll_default_unlock_handler
+       nop
 
+pll_unlock_handler:
 /* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */
     set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL1)
+    j  wait_loop2
+    nop
+
+pll_default_unlock_handler:
+/* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */
+    set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL1_DEFAULT)
     nop
 
 wait_loop2:
@@ -301,9 +313,24 @@ wait_loop2:
     set_reg(AR7240_PCIE_PLL_CONFIG, CPU_PLL_DITHER_FRAC_VAL)
     nop
 
+/* read GPIO_SET register */
+       li  t0, KSEG1ADDR(AR7240_GPIO_IN)
+       lw  t1, 0(t0)
+       and t1, t1, (1 << GPIO_RST_BUTTON_BIT)
+       beq     t1,     (1 << GPIO_RST_BUTTON_BIT), pll_default_lock_handler
+       nop
+
+pll_lock_handler:
 /* clear PLL power down bit in CPU PLLl configuration */
     set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL2)
+    j  wait_loop3
+    nop
+
+pll_default_lock_handler:
+/* clear PLL power down bit in CPU PLLl configuration */
+    set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL2_DEFAULT)
     nop
+
 wait_loop3:
     li  t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG)
     lw  t7, 0(t6)

diff --git a/u-boot/board/ar7240/common/ar7240_flash.c b/u-boot/board/ar7240/common/ar7240_flash.c
index 03f878f3693794a93f85a49b659b4aa720786964..16e7c66e18652e1a99e2df3b685ee5cefbf24035 100755 (executable)
--- a/u-boot/board/ar7240/common/ar7240_flash.c
+++ b/u-boot/board/ar7240/common/ar7240_flash.c
@@ -18,6 +18,7 @@
 
 extern void led_toggle(void);
 extern void all_led_off(void);
+extern int reset_button_status(void);
 
 /*
  * globals
@@ -83,7 +84,14 @@ unsigned long flash_init(void){
 
        // spi flash clock
        ar7240_reg_wr(AR7240_SPI_FS,    0x01);
-       ar7240_reg_wr(AR7240_SPI_CLOCK, AR7240_SPI_CONTROL);
+
+       // if reset button is pressed -> write default CLOCK_DIVIDER for SPI CLOCK
+       if(reset_button_status()){
+               ar7240_reg_wr(AR7240_SPI_CLOCK, AR7240_SPI_CONTROL_DEFAULT);
+       } else {
+               ar7240_reg_wr(AR7240_SPI_CLOCK, AR7240_SPI_CONTROL);
+       }
+
        ar7240_reg_wr(AR7240_SPI_FS,    0x0);
 
        // get flash id

diff --git a/u-boot/include/configs/ap121.h b/u-boot/include/configs/ap121.h
index 7ade40142e40bfdd6fc6a9442ee66a380999db98..be9f3fc15c40245ca2f27a2b000293ab663b8f83 100755 (executable)
--- a/u-boot/include/configs/ap121.h
+++ b/u-boot/include/configs/ap121.h
@@ -92,7 +92,8 @@
 #undef CPU_CLK_CONTROL_VAL2
 
 // CPU-RAM-AHB frequency setting
-#define CFG_PLL_FREQ    CFG_PLL_400_400_200
+//#define CFG_PLL_FREQ    CFG_PLL_400_400_200
+#define CFG_PLL_FREQ   CFG_PLL_525_525_262     // only for test!
 
 /*
  * MIPS32 24K Processor Core Family Software User's Manual
@@ -187,6 +188,33 @@
  *
  */
 
+/*
+ * Default values (400/400/200 MHz) for O/C recovery mode
+ */
+
+// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
+#define CPU_CLK_CONTROL_VAL1_DEFAULT   0x00018004
+#define CPU_CLK_CONTROL_VAL2_DEFAULT   0x00008000
+
+#if CONFIG_40MHZ_XTAL_SUPPORT
+       // DIV_INT      = 20    (40 MHz * 20/2 = 400 MHz)
+       // REFDIV       = 1
+       // RANGE        = 0
+       // OUTDIV       = 1
+       #define CPU_PLL_CONFIG_VAL1_DEFAULT     0x40815000
+       #define CPU_PLL_CONFIG_VAL2_DEFAULT     0x00815000
+#else
+       // DIV_INT      = 32    (25 MHz * 32/2 = 400 MHz)
+       // REFDIV       = 1
+       // RANGE        = 0
+       // OUTDIV       = 1
+       #define CPU_PLL_CONFIG_VAL1_DEFAULT     0x40818000
+       #define CPU_PLL_CONFIG_VAL2_DEFAULT     0x00818000
+#endif
+
+// CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
+#define AR7240_SPI_CONTROL_DEFAULT             0x42
+
 #if (CFG_PLL_FREQ == CFG_PLL_400_400_200)
 
        #define CFG_HZ                                  (400000000LU/2)
@@ -414,6 +442,24 @@
        // CLOCK_DIVIDER = 1 (SPI clock = 131 / 4 ~ 32,8 MHz)
        #define AR7240_SPI_CONTROL              0x41
 
+#elif (CFG_PLL_FREQ == CFG_PLL_525_525_262)
+
+       #define CFG_HZ                                  (525000000LU/2)
+
+       // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
+       #define CPU_CLK_CONTROL_VAL1    0x00008004
+       #define CPU_CLK_CONTROL_VAL2    0x00008000
+
+       // DIV_INT      = 42    (25 MHz * 42/2 = 525 MHz)
+       // REFDIV       = 1
+       // RANGE        = 0
+       // OUTDIV       = 1
+       #define CPU_PLL_CONFIG_VAL1             0x4081A800
+       #define CPU_PLL_CONFIG_VAL2             0x0081A800
+
+       // CLOCK_DIVIDER = 1 (SPI clock = 131 / 4 ~ 32,8 MHz)
+       #define AR7240_SPI_CONTROL              0x41
+
 #endif
 
 /*

diff --git a/u-boot/include/configs/ar7240.h b/u-boot/include/configs/ar7240.h
index b0eb96221ffda3374d11ac0faba23c675c37eeca..3a644f0d3503b39e3eae2dabc8ce1c525e55b78c 100755 (executable)
--- a/u-boot/include/configs/ar7240.h
+++ b/u-boot/include/configs/ar7240.h
@@ -48,6 +48,7 @@
 #define CFG_PLL_500_250_250                    10
 #define CFG_PLL_562_281_140                    11
 #define CFG_PLL_525_262_131                    12
+#define CFG_PLL_525_525_262                    13
 
 // WASP
 #define CFG_PLL_566_400_200                    0x31