ARM: omap: fix GPMC address-map size for NAND and NOR devices
authorpekon gupta <pekon@ti.com>
Fri, 18 Jul 2014 12:29:40 +0000 (17:59 +0530)
committerTom Rini <trini@ti.com>
Fri, 25 Jul 2014 20:26:12 +0000 (16:26 -0400)
Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91
    ARM: omap: merge GPMC initialization code for all platform

1) NAND device are not directly memory-mapped to CPU address-space, they are
 indirectly accessed via following GPMC registers:
 - GPMC_NAND_COMMAND_x
 - GPMC_NAND_ADDRESS_x
 - GPMC_NAND_DATA_x
 Therefore from CPU's point of view, NAND address-map can be limited to just
 above register addresses. But GPMC chip-select address-map can be configured
 in granularity of 16MB only.
 So this patch uses GPMC_SIZE_16M for all NAND devices.

2) NOR device are directly memory-mapped to CPU address-space, so its
 address-map size depends on actual addressable region in NOR FLASH device.
 So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map
 size configuration.

Signed-off-by: Pekon Gupta <pekon@ti.com>
arch/arm/cpu/armv7/omap-common/mem-common.c
include/configs/am335x_evm.h

index ba26cd1fdb78b35a2c81707c2ee6760af7b95dd0..e9da70fe7098f0182f0b550221c09e2820c0d5a7 100644 (file)
@@ -87,8 +87,12 @@ void gpmc_init(void)
                                                STNOR_GPMC_CONFIG6,
                                                STNOR_GPMC_CONFIG7
                                                };
-       u32 size = GPMC_SIZE_16M;
        u32 base = CONFIG_SYS_FLASH_BASE;
+       u32 size =      (CONFIG_SYS_FLASH_SIZE  > 0x08000000) ? GPMC_SIZE_256M :
+       /* > 64MB */    ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
+       /* > 32MB */    ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M  :
+       /* > 16MB */    ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M  :
+       /* min 16MB */  GPMC_SIZE_16M)));
 #elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
 /* configure GPMC for NAND */
        const u32  gpmc_regs[GPMC_MAX_REG] = {  M_NAND_GPMC_CONFIG1,
@@ -99,8 +103,9 @@ void gpmc_init(void)
                                                M_NAND_GPMC_CONFIG6,
                                                0
                                                };
-       u32 size = GPMC_SIZE_256M;
        u32 base = CONFIG_SYS_NAND_BASE;
+       u32 size = GPMC_SIZE_16M;
+
 #elif defined(CONFIG_CMD_ONENAND)
        const u32 gpmc_regs[GPMC_MAX_REG] = {   ONENAND_GPMC_CONFIG1,
                                                ONENAND_GPMC_CONFIG2,
index a48b386477167010c8e0d206423a3bdbe611cf83..c1a6ada0a87404f3bed8e5c818542fdf3c25ffa1 100644 (file)
 #define CONFIG_SYS_MAX_FLASH_BANKS     1
 #define CONFIG_SYS_FLASH_BASE          (0x08000000)
 #define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE          0x01000000
 #define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_FLASH_BASE
 /* Reduce SPL size by removing unlikey targets */
 #ifdef CONFIG_NOR_BOOT