# TODO: broken symbolic link
/u-boot/include/asm-*/arch
+# Do not ignore original u-boot images
+!/original_u-boot_images/*.bin
+
#
# git files that we don't want to ignore even it they are dot-files
#
export BUILD_TOPDIR=$(PWD)
export STAGING_DIR=$(BUILD_TOPDIR)/tmp
-export MAKECMD=make --silent --no-print-directory ARCH=mips CROSS_COMPILE=mips-linux-gnu-
+ifndef CROSS_COMPILE
+CROSS_COMPILE = mips-openwrt-linux-musl-
+endif
+export CROSS_COMPILE
+
+export MAKECMD=make --silent --no-print-directory ARCH=mips
# boot delay (time to autostart boot command)
export CONFIG_BOOTDELAY=1
@cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all
@make --no-print-directory show_size
-tplink_wr720n_v3_CH: export UBOOT_FILE_NAME=uboot_for_tp-link_tl-wr720n_v3_CH
-tplink_wr720n_v3_CH: export CONFIG_MAX_UBOOT_SIZE_KB=123
+tplink_wr720n_v3_CN: export UBOOT_FILE_NAME=uboot_for_tp-link_tl-wr720n_v3_CN
+tplink_wr720n_v3_CN: export CONFIG_MAX_UBOOT_SIZE_KB=123
ifndef CONFIG_SKIP_LOWLEVEL_INIT
-tplink_wr720n_v3_CH: export COMPRESSED_UBOOT=1
+tplink_wr720n_v3_CN: export COMPRESSED_UBOOT=1
endif
-tplink_wr720n_v3_CH:
- @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) wr720n_v3_CH_config
+tplink_wr720n_v3_CN:
+ @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) wr720n_v3_CN_config
@cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all
@make --no-print-directory show_size
@cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all
@make --no-print-directory show_size
+tplink_wr841n_v9: export UBOOT_FILE_NAME=uboot_for_tp-link_tl-wr841n_v9
+tplink_wr841n_v9: export CONFIG_MAX_UBOOT_SIZE_KB=123
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+tplink_wr841n_v9: export COMPRESSED_UBOOT=1
+endif
+tplink_wr841n_v9: export ETH_CONFIG=_s27
+tplink_wr841n_v9:
+ @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) wr841n_v9_config
+ @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all
+ @make --no-print-directory show_size
+
tplink_wa830re_v2_wa801nd_v2: export UBOOT_FILE_NAME=uboot_for_tp-link_tl-wa830re_v2_tl-wa801nd_v2
tplink_wa830re_v2_wa801nd_v2: export CONFIG_MAX_UBOOT_SIZE_KB=123
ifndef CONFIG_SKIP_LOWLEVEL_INIT
@cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all
@make --no-print-directory show_size
+tplink_wr820n_CN: export UBOOT_FILE_NAME=uboot_for_tp-link_tl-wr820n_CN
+tplink_wr820n_CN: export CONFIG_MAX_UBOOT_SIZE_KB=123
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+tplink_wr820n_CN: export COMPRESSED_UBOOT=1
+endif
+tplink_wr820n_CN: export ETH_CONFIG=_s27
+tplink_wr820n_CN:
+ @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) wr820n_CN_config
+ @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all
+ @make --no-print-directory show_size
+
+tplink_wr802n: export UBOOT_FILE_NAME=uboot_for_tp-link_tl-wr802n
+tplink_wr802n: export CONFIG_MAX_UBOOT_SIZE_KB=123
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+tplink_wr802n: export COMPRESSED_UBOOT=1
+endif
+tplink_wr802n: export ETH_CONFIG=_s27
+tplink_wr802n:
+ @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) wr802n_config
+ @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all
+ @make --no-print-directory show_size
+
dlink_dir505: export UBOOT_FILE_NAME=uboot_for_d-link_dir-505
dlink_dir505: export CONFIG_MAX_UBOOT_SIZE_KB=64
ifndef CONFIG_SKIP_LOWLEVEL_INIT
@cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all
@make --no-print-directory show_size
+black_swift_board: export UBOOT_FILE_NAME=uboot_for_black_swift_board
+black_swift_board: export CONFIG_MAX_UBOOT_SIZE_KB=128
+black_swift_board: export COMPRESSED_UBOOT=1
+black_swift_board: export DEVICE_VENDOR=SE
+black_swift_board:
+ @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) black_swift_board_config
+ @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all
+ @make --no-print-directory show_size
+
villagetelco_mp2: export UBOOT_FILE_NAME=uboot_for_villagetelco_mp2
villagetelco_mp2: export CONFIG_MAX_UBOOT_SIZE_KB=192
villagetelco_mp2: export DEVICE_VENDOR=villagetelco
- [Modifications, changes](#modifications-changes)
- [Web server](#web-server)
- [Network Console](#network-console)
+ - [Writable environment variables](#writable-environment-variables)
- [Other](#other)
- [Supported FLASH chips](#supported-flash-chips)
- [How to install it?](#how-to-install-it)
- [Using external programmer](#using-external-programmer)
- [Using UART, U-Boot console and TFTP server](#using-uart-u-boot-console-and-tftp-server)
- [Important notice!](#important-notice)
- - [Step by step instruction](#step-by-step-instruction)
+ - [Step by step instructions](#step-by-step-instructions)
- [Using OpenWrt](#using-openwrt)
- [Using DD-WRT](#using-dd-wrt)
- [How to use it?](#how-to-use-it)
Introduction
------------
-In short, this project is a deep modification of **U-Boot 1.1.4** sources, mostly from **TP-Link**, but some code fragments were taken also from **D-Link**.
+In short, this project is a deep modification of **U-Boot 1.1.4** sources, mostly from **TP-Link**, but some code fragments were taken also from **D-Link**, **Netgear**, **ZyXEL** and **Belkin**. All these companies are using SDK from Qualcomm/Atheros which includes modified version of **U-Boot 1.1.4**.
You can download original sources from the following pages:
- [TP-Link GPL Code Center](http://www.tp-link.com/en/support/gpl/ "TP-Link GPL Code Center")
- [D-Link GPL Source Code Support](http://tsd.dlink.com.tw/GPL.asp "D-Link GPL Source Code Support")
+- [NETGEAR Open Source Code for Programmers (GPL)](http://kb.netgear.com/app/answers/detail/a_id/2649/~/netgear-open-source-code-for-programmers-%28gpl%29 "NETGEAR Open Source Code for Programmers (GPL)")
+- [ZyXEL GPL-OSS](http://www.zyxel.com/us/en/form/gpl_oss_form.shtml "ZyXEL GPL-OSS")
+- [Belkin Open Source Code Center](http://www.belkin.com/us/support-article?articleNum=51238 "Belkin Open Source Code Center")
The concept for this project came from another U-Boot modification, dedicated to a small and very popular TP-Link router - model **TL-WR703N**, which includes web fail safe mode: **[wr703n-uboot-with-web-failsafe](http://code.google.com/p/wr703n-uboot-with-web-failsafe/)**. I was using it and decided to make my own version, which could have some improvements, additional capabilities, support for different models and work with all modern web browsers.
-First version of this modification was introduced on **OpenWrt** forum in [this thread](https://forum.openwrt.org/viewtopic.php?id=43237), at the end of March 2013 and was dedicated only for TP-Link routers with **Atheros AR9331** SoC. Now, it supports also models from different manufacturers, devices with **Atheros AR934x** (like **TP-Link TL-WDR3600**, **TL-WDR43x0**, **TL-WR841N/D v8**, **TL-WA830RE v2**) and other (in the near future **Qualcomm Atheros QCA955x**) are under development.
+First version of this modification was introduced on **OpenWrt** forum in [this thread](https://forum.openwrt.org/viewtopic.php?id=43237), at the end of March 2013 and was dedicated only for TP-Link routers with **Atheros AR9331** SoC. Now, it supports also models from different manufacturers, devices with **Atheros AR934x**, **Qualcomm Atheros QCA953x**, **Qualcomm Atheros QCA955x** and other (in the near future **Qualcomm Atheros QCA956x** and **MediaTek MT762x**) are under development.
You can find some information about previous versions of this project also on my [blog](http://www.tech-blog.pl), in [this article](http://www.tech-blog.pl/2013/03/29/zmodyfikowany-u-boot-dla-routerow-tp-link-z-atheros-ar9331-z-trybem-aktualizacji-oprogramowania-przez-www-i-konsola-sieciowa-netconsole/). It is in Polish, but [Google Translator](http://translate.google.com/translate?hl=pl&sl=pl&tl=en&u=http%3A%2F%2Fwww.tech-blog.pl%2F2013%2F03%2F29%2Fzmodyfikowany-u-boot-dla-routerow-tp-link-z-atheros-ar9331-z-trybem-aktualizacji-oprogramowania-przez-www-i-konsola-sieciowa-netconsole%2F&sandbox=1) will help you to understand it.
- Dragino 2 (MS14)
- Village Telco Mesh Potato 2 (based on Dragino MS14)
- GL.iNet 64xxA ([photos in my gallery](http://galeria.tech-blog.pl/GLiNet/))
+ - Black Swift
- **Atheros AR1311 (similar to AR9331)**
- D-Link DIR-505 H/W ver. A1 ([photos in my gallery](http://galeria.tech-blog.pl/D-Link_DIR-505/))
- TP-Link TL-WDR43x0 v1
- TP-Link TL-WDR3500 v1
+- **Qualcomm Atheros QCA953x**:
+ - TP-Link TL-WR841N/D v9
+ - TP-Link TL-WR820N (version for Chinese market)
+ - TP-Link TL-WR802N
+
I tested this modification on most of these devices, with OpenWrt and OFW firmware. If you are not sure about the version of your device, please contact with me **before** you try to make an upgrade. Changing bootloader to a wrong version will probably damage your router and you will need special hardware to fix it, so please, **be very careful**.
More information about supported devices:
| [Dragino 2 (MS14)](http://wiki.openwrt.org/toh/dragino/ms14) | AR9331 | 16 MiB | 64 MiB DDR1 | 192 KiB | R/W |
| Village Telco Mesh Potato 2 | AR9331 | 16 MiB | 64 MiB DDR1 | 192 KiB | R/W |
| [GL.iNet](http://wiki.openwrt.org/toh/gl-inet/gl-inet) | AR9331 | 8/16 MiB | 64 MiB DDR1 | 64 KiB | RO |
+| [Black Swift](http://www.black-swift.com) | AR9331 | 16 MiB | 64 MiB DDR2 | 128 KiB, LZMA | R/W |
| [TP-Link TL-MR3420 v2](http://wikidevi.com/wiki/TP-LINK_TL-MR3420_v2) | AR9341 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
| [TP-Link TL-WR841N/D v8](http://wiki.openwrt.org/toh/tp-link/tl-wr841nd) | AR9341 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
| [TP-Link TL-WA830RE v2](http://wikidevi.com/wiki/TP-LINK_TL-WA830RE_v2) | AR9341 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
| [TP-Link TL-WDR43x0 v1](http://wiki.openwrt.org/toh/tp-link/tl-wdr4300) | AR9344 | 8 MiB | 128 MiB DDR2 | 64 KiB, LZMA | RO |
| [TP-Link TL-WDR3500 v1](http://wiki.openwrt.org/toh/tp-link/tl-wdr3500) | AR9344 | 8 MiB | 128 MiB DDR2 | 64 KiB, LZMA | RO |
| [D-Link DIR-505 H/W ver. A1](http://wiki.openwrt.org/toh/d-link/dir-505) | AR1311 | 8 MiB | 64 MiB DDR2 | 64 KiB, LZMA | RO |
+| [TP-Link TL-WR841N/D v9](https://wiki.openwrt.org/toh/tp-link/tl-wr841nd) | QCA9533 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
+| [TP-Link TL-WR820N](https://wiki.openwrt.org/toh/tp-link/tl-wr820n) | QCA9531 | 4 MiB | 64 MiB DDR2 | 64 KiB, LZMA | RO |
+| [TP-Link TL-WR802N](https://wikidevi.com/wiki/TP-LINK_TL-WR802N_v1.0) | QCA9533 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
*(LZMA) - U-Boot binary image is compressed with LZMA.*
*(R/W) - environment exists in separate FLASH block which allows you to save it and keep after power down.*
6. fail.html
7. style.css
-
+
+
+
+
+
+
### Network Console
# nc -u -p 6666 192.168.1.1 6666
```
+### Writable environment variables
+
+U-Boot uses special "**environment variables**" which are used for storing values of many different settings, like IP addresses of device and remote server for TFTP transaction, serial console baud rate, boot command, etc. Environment is usually stored in separate FLASH sector or its part, so all changes can be saved permanently.
+
+None of the popular manufacturers provides this feature and use so called "**read-only environment**" (embedded in U-Boot image), which means that all changes made during a runtime will be lost after device restart and there is no way to store them in FLASH.
+
+This modification uses writable environment variables in almost all supported devices, so you can do for example:
+
+```
+uboot> setenv ipaddr 192.168.1.100
+uboot> saveenv
+Saving environment to FLASH...
+
+Erase FLASH from 0x9F010000 to 0x9F01FFFF in bank #1
+Erasing: #
+
+Erased sectors: 1
+
+Writting at address: 0x9F010000
+
+uboot> reset
+```
+
+Which will change device IP address and save updated environment variables in FLASH. From next power up, the device will use new value for its IP address.
+
+Using command **run** and writable environment variables you are able to write custom, small scripts like below example, used for firmware upgrade using TFTP method:
+
+```
+uboot> printenv
+[...]
+firmware_addr=0x9F020000
+firmware_name=firmware.bin
+firmware_upg=if ping $serverip; then tftp $loadaddr $firmware_name && erase $firmware_addr +$filesize && cp.b $loadaddr $firmware_addr $filesize && echo OK!; else echo ERROR! Server not reachable!; fi
+[...]
+
+uboot> run firmware_upg
+Ethernet mode (duplex/speed): 1/100 Mbps
+Using eth0 device
+
+Ping OK, host 192.168.1.2 is alive!
+
+
+TFTP from IP: 192.168.1.2
+ Our IP: 192.168.1.1
+ Filename: 'firmware.bin'
+Load address: 0x80800000
+ Using: eth0
+
+ Loading: ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ #########
+
+TFTP transfer complete!
+
+Bytes transferred: 3932160 (0x3c0000)
+Erase FLASH from 0x9F020000 to 0x9F3DFFFF in bank #1
+Erasing: #######################################
+ #####################
+
+Erased sectors: 60
+
+Copying to FLASH...
+Writting at address: 0x9F020000
+
+Done!
+
+OK!
+uboot>
+```
+
### Other
Moreover:
- FLASH chip is automatically recognized (using JEDEC ID)
- Ethernet MAC is set from FLASH (no more "No valid address in FLASH. Using fixed address")
- Automatic kernel booting can be interrupted using any key
+- Better UART serial console driver with support for different baud rates
- Press and hold reset button to run:
- Web server (min. 3 seconds)
- U-Boot serial console (min. 5 seconds)
- U-Boot network console (min. 7 seconds)
- Additional commands (in comparison to the default version; availability depends on router model):
+ - defenv
- httpd
+ - itest
+ - loadb
+ - loady
- printmac
- setmac
- printmodel
- printpin
- startnc
- startsc
- - eraseenv
- ping
- dhcp
- sntp
FLASH type detection may be very useful for people who has exchanged the FLASH chip in their routers. You will not need to recompile U-Boot sources, to have access to overall FLASH space in U-Boot console.
-If you use FLASH type which is not listed below, this version of U-Boot will use default size for your router and, in most supported models, updating the ART image will not be available.
+If you use FLASH type which is not listed below, this version of U-Boot will try to get information about the chip using **Serial Flash Discoverable Parameter** (**SFDP**, more information: https://www.jedec.org/standards-documents/docs/jesd216b) standard. If your chip does not support SFDP, it will use default size for your router and, in most supported models, updating the ART image will not be available.
Currently supported FLASH types:
- Winbond W25Q128 (16 MB, JEDEC ID: EF 4018)*
- Macronix MX25L128 (16 MB, JEDEC ID: C2 2018, C2 2618)
- Spansion S25FL127S (16 MB, JEDEC ID: 01 2018)*
+- Micron N25Q128 (16 MB, JEDEC ID: 20 BA18)
(*) tested
mtd5: 00fd0000 00010000 "firmware"
```
-As you can see, `u-boot` partition size is **0x20000** (128 KiB) and my image for this model has size of **0x10000** (64 KiB) - it is a very important difference! You should remember about this if you want to use `mtd` utility, to change U-Boot.
+As you can see, `u-boot` partition size is **0x20000** (128 KiB) and my image for this model has smaller size: **0x1EC00** (123 KiB) - it is a very important difference! You should remember about this if you want to use `mtd` utility or serial console and U-Boot command line, to change the bootloader.
To backup `u-boot` partition in RAM, run:
If you have an external FLASH programmer (all supported devices have **SPI NOR FLASH** chips), you probably know how to use it. Download package with prebuilt images or compile the code, choose right file for your device and put it on FLASH at the beginning (offset `0x00000`). Remember to first erase block(s) - with high probability, if you use some kind of automatic mode, the programmer will do it for you.
-All prebuilt images are padded with 0xFF, so their size will always be a **multiple of 64 KiB block** and they will not be bigger than the original versions. For example, **TP-Link** uses only first **64 KiB** block to store compressed U-Boot image (in most of their modern devices). In the second 64 KiB block they store additional information like MAC address, model number and WPS pin number.
+All prebuilt images are padded with 0xFF and since change "****", in most supported devices, **their size is no longer a multiple of 64 KiB block**. For example, **TP-Link** uses only first **64 KiB** block to store compressed U-Boot image (in most of their modern devices). In the second 64 KiB block they store additional information like MAC address, model number and WPS pin number. This modification will use both sectors for U-Boot image and also other data, including small block for writable environment variables.
+
+Below image with beginning part of FLASH memory map for TP-Link TL-MR3020 shows differences between stock version and this modification.
+
+
On the other hand, U-Boot image in **Carambola 2** from **8devices** may have up to **256 KiB** (4x 64 KiB block), they use uncompressed version and environment stored in FLASH. Immediately after the Carambola 2 U-Boot partition is an area which contains U-Boot environment variables (1x 64 KiB block), called `u-boot-env`:
### Using UART, U-Boot console and TFTP server
+**WARNING! This method is highly not recommended!**
+
It is probably the most common method to change firmware in case of any problems. Main disadvantage of this approach is the need to connect with device using a serial port (this does not apply to Carambola 2 with development board, which already has a built-in USB-UART adapter, based on FTDI FT232RQ).
#### Important notice!
For a long time I have been using without any problems a small and very cheap (about 1-2 USD) **CP2102** based adapter. Go to [Serial Console article in OpenWrt Wiki](http://wiki.openwrt.org/doc/hardware/port.serial) for more, detailed information.
-#### Step by step instruction
+#### Step by step instructions
1. Install and configure any **TFTP server** on your PC (on Windows, you can use [TFTP32](http://tftpd32.jounin.net)).
serverip=192.168.1.2
```
-7. Download and store in RAM proper image for your router, using `tftpboot` command in U-Boot console (in this example, for **TP-Link TL-MR3020**):
+7. Due to differences in FLASH memory map and sizes of original and modified version of U-Boot, you must first make a backup of the partition with original version in RAM. **If you skip this step or make a mistake, your device will be probably broken!**
+
+ This step is different between supported models, so you should pay attention to the size of image with modified version of U-Boot, **round it to the nearest multiple of 64 KiB** and use this value in all next steps.
+ For example, if image of the modified version is **123 KiB** (**0x1EC00**) you must first make a backup of **128 KiB** (**0x20000**) in RAM, at the same address where you are going to download the image:
+
+ ```
+ hornet> cp.b 0x9F000000 0x80800000 0x20000
```
- tftpboot 0x80800000 uboot_for_tp-link_tl-mr3020.bin
+ Using the same offset address in RAM for backup and new image will end up with combination of both images and preserve additional data like MAC address, model number and PIN.
+
+8. Download and store in RAM proper image for your router, using `tftpboot` command in U-Boot console (in this example, for **TP-Link TL-MR3020**):
+
+ ```
+ hornet> tftpboot 0x80800000 uboot_for_tp-link_tl-mr3020.bin
eth1 link down
Using eth0 device
TFTP from server 192.168.1.2; our IP address is 192.168.1.1
Filename 'uboot_for_tp-link_tl-mr3020.bin'.
Load address: 0x80800000
- Loading: #############
+ Loading: #########################
done
- Bytes transferred = 65536 (10000 hex)
+ Bytes transferred = 125952 (1ec00 hex)
+
hornet>
```
-8. Next step is very risky! You are going to delete existing U-Boot image from FLASH in your device and copy from RAM the new one. If something goes wrong (for example, a power failure), your router, without bootloader, will not boot again!
+9. Next step is very risky! You are going to delete existing U-Boot image from FLASH in your device and copy from RAM the new one. If something goes wrong (for example, a power failure), your router, without bootloader, will not boot again!
- You should also note the size of downloaded image. For supported **TP-Link** and **D-Link** routers it will be always **0x10000** (64 KiB), but for Carambola 2 image size is different: **0x40000** (256 KiB). In all cases, the start address of FLASH is **0x9F000000** and for RAM: **0x80000000** (as you may noticed, I did not use start address of RAM to store image and you should follow this approach).
+ You should also note the size of image and use value from step 7. In all cases, the start address of FLASH is **0x9F000000** and for RAM: **0x80000000** (as you may noticed, I did not use start address of RAM to store image and you should follow this approach).
Please, do not make any mistake with offsets and sizes during next steps!
-9. Erase appropriate FLASH space for new U-Boot image (this command will remove default U-Boot image!):
+10. Erase appropriate FLASH space for new U-Boot image (this command will remove default U-Boot image!):
```
- hornet> erase 0x9F000000 +0x10000
+ hornet> erase 0x9F000000 +0x20000
- First 0x0 last 0x0 sector size 0x10000
- 0
- Erased 1 sectors
+ First 0x0 last 0x1 sector size 0x10000
+ Erased 2 sectors
+ hornet>
```
-10. Now your router does not have U-Boot, so do not wait and copy to FLASH the new one, stored earlier in RAM:
+11. Now your router does not have U-Boot, so do not wait and copy to FLASH the new one, stored earlier in RAM:
```
- hornet> cp.b 0x80800000 0x9F000000 0x10000
+ hornet> cp.b 0x80800000 0x9F000000 0x20000
Copy to Flash... write addr: 9f000000
done
```
-11. If you want, you can check content of the newly written FLASH and compare it to the image on your PC (or better also do such a "legit memory content" comparison prior to writing!), using `md` command in U-Boot console, which prints indicated memory area (press only ENTER after first execution of this command to move further in memory):
+12. If you want, you can check content of the newly written FLASH and compare it to the image on your PC (or better also do such a "legit memory content" comparison prior to writing!), using `md` command in U-Boot console, which prints indicated memory area (press only ENTER after first execution of this command to move further in memory):
```
hornet> md 0x9F000000
9f0000f0: 100001ea 00000000 100001e8 00000000 ................
```
-12. If you are sure that everything went OK, you may reset the board:
+12. If you are sure that everything went OK, you may reset the board using below command or just reset power:
```
hornet> reset
### Using OpenWrt
-1. Compile and flash OpenWrt with an unlocked U-Boot partition.
- - This is done by removing the `MTD_WRITEABLE` from the `mask_flags` of the `u-boot` partition.
- - To put it simply, for TP-Link products, just remove [this line](https://dev.openwrt.org/browser/trunk/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c?rev=41580#L152), compile and flash the image as usual.
-2. Find out which mtd partition is the `u-boot` partition:
+**This method is recommended!**
+
+Starting from official release "**[2014-11-19](https://github.com/pepe2k/u-boot_mod/releases/tag/2014-11-19)**", you will find ready **OpenWrt** images, with unlocked `u-boot` partition, embedded U-Boot image and dedicated small script for easy update process inside release tarball. All you need to do is download last release, select proper OpenWrt image for your device, install it and invoke one command: `u-boot-upgrade`:
+
+```
+root@OpenWrt:/# u-boot-upgrade
+
+=================================================================
+ DISCLAIMER: you are using this script at your own risk!
+
+ The author of U-Boot modification and this script takes
+ no responsibility for any of the results of using them.
+
+ Updating U-Boot is a very dangerous operation
+ and may damage your device! You have been warned!
+=================================================================
+ Are you sure you want to continue (type 'yes' or 'no')? yes
+=================================================================
+
+[ ok ] Found U-Boot image file: uboot_for_tp-link_tl-mr3020.bin
+ Do you want to use this file (type 'yes' or 'no')? yes
+[ ok ] MD5 checksum of new U-Boot image file is correct
+[ ok ] Backup of /dev/mtd0 successfully created
+ Do you want to store backup in /etc/u-boot_mod/backup/ (recommended, type 'yes' or 'no')? no
+[ ok ] New U-Boot image successfully combined with backup file
+[info] New U-Boot image is ready to be written into FLASH
+ Are you sure you want to continue (type 'yes' or 'no')? yes
+[ ok ] New U-Boot image successfully written info FLASH
+[ ok ] MD5 checksum of mtd0 and new U-Boot image are equal
+[info] Done!
+```
+
+### Using DD-WRT
+
+**WARNING! This method is not recommended!**
+
+1. Login into the router using telnet or SSH and find out which of the mtd partitions is the first one. In DD-WRT it is usally called `RedBoot`:
```
- root@OpenWrt:/tmp/uboot-work# cat /proc/mtd
+ root@DD-WRT:~# cat /proc/mtd
dev: size erasesize name
- mtd0: 00020000 00010000 "u-boot"
- mtd1: 000feba0 00010000 "kernel"
- mtd2: 002d1460 00010000 "rootfs"
- mtd3: 00100000 00010000 "rootfs_data"
- mtd4: 00010000 00010000 "art"
- mtd5: 003d0000 00010000 "firmware"
+ mtd0: 00020000 00010000 "RedBoot"
+ mtd1: 003c0000 00010000 "linux"
+ mtd2: 002c0000 00010000 "rootfs"
+ mtd3: 00010000 00010000 "ddwrt"
+ mtd4: 00010000 00010000 "nvram"
+ mtd5: 00010000 00010000 "board_config"
+ mtd6: 00400000 00010000 "fullflash"
+ mtd7: 00020000 00010000 "fullboot"
```
-3. Transfer the new U-Boot image to the device:
+ In this case, for **TP-Link TL-MR3020**, the `RedBoot` partition is the one, which contains U-Boot and additional data (MAC address, model number, PIN).
+
+ **Warning!** If size of the first partition is smaller than the size of the modified U-Boot image, you should not continue!
+
+2. Using SCP or other method, transfer the new U-Boot image and corresponding MD5 file to the `/tmp` folder in device.
```
- me@laptop:~# scp uboot_for_tp-link_tl-mr3220_v2.bin root@192.168.1.1:/tmp/
- uboot_for_tp-link_tl-mr3220_v2.bin 100% 64KB 64.0KB/s 00:00
+ root@DD-WRT:/tmp# ls -la
+ [...]
+ -rw-r--r-- 1 root root 125952 Nov 5 2015 uboot_for_tp-link_tl-mr3020.bin
+ -rw-r--r-- 1 root root 66 Nov 5 2015 uboot_for_tp-link_tl-mr3020.md5
+ [...]
```
-4. Verify the MD5 sum of the image:
+3. Verify the MD5 sum of the image:
```
- me@laptop:~# md5sum uboot_for_tp-link_tl-mr3220_v2.bin
- cefad12aa9fbd04291652dae3eb7650c uboot_for_tp-link_tl-mr3220_v2.bin
+ root@DD-WRT:/tmp# md5sum uboot_for_tp-link_tl-mr3020.bin
+ aaae0f772ce007f7d1542b9233dd765b uboot_for_tp-link_tl-mr3020.bin
- root@OpenWrt:/tmp# md5sum uboot_for_tp-link_tl-mr3220_v2.bin
- cefad12aa9fbd04291652dae3eb7650c uboot_for_tp-link_tl-mr3220_v2.bin
+ root@DD-WRT:/tmp# cat uboot_for_tp-link_tl-mr3020.md5
+ aaae0f772ce007f7d1542b9233dd765b *uboot_for_tp-link_tl-mr3020.bin
```
-5. Take a backup of the current u-boot partition (`mtd0`):
+4. Make a backup of the current `RedBoot` partition (`mtd0`):
```
- root@OpenWrt:/tmp# dd if=/dev/mtd0 of=uboot_orig.bin
+ root@DD-WRT:/tmp# dd if=/dev/mtd0 of=uboot_factory.bin
256+0 records in
256+0 records out
```
-6. Transfer the backup off the device and to a safe place:
-
- ```
- me@laptop:~# scp root@192.168.1.1:/tmp/uboot_orig.bin .
- uboot_orig.bin 100% 128KB 128.0KB/s 00:00
- ```
+5. Using SCP or other method, transfer backuped `RedBoot` original partition to some safe place (I highly recommended you to save backup somewhere!).
-7. **Beware**: This step may differ for other devices. I'm using TP-Link TL-MR3220v2 and it uses the first 64 KiB block to store compressed U-Boot image. In the second 64 KiB block they store additional information like MAC address, model number and WPS pin number. This means the old backup is bigger than the new one we're going to flash. To store the old settings we're going to modify only the compressed U-Boot image and leave the additional information intact. To do that, take a copy of the original file, and copy the new image over it without truncating the leftover bytes:
+6. You need to combine together original image and the one with U-Boot modification, but it seems that `dd` from DD-WRT does not support `conv=notrunc`, so we will use different approach:
```
- root@OpenWrt:/tmp# cp uboot_orig.bin uboot_new.bin
- root@OpenWrt:/tmp# dd if=uboot_for_tp-link_tl-mr3220_v2.bin of=uboot_new.bin conv=notrunc
- 128+0 records in
- 128+0 records out
- ```
-
-9. **Danger**: This is the point of no return, if you have any errors or problems, please revert the original image at any time using:
+ root@DD-WRT:/tmp# dd if=uboot_factory.bin of=uboot_rest.bin bs=1 skip=$(wc -c < uboot_for_tp-link_tl-mr3020.bin)
+ 5120+0 records in
+ 5120+0 records out
+ root@DD-WRT:/tmp# cat uboot_for_tp-link_tl-mr3020.bin uboot_rest.bin > uboot_new.bin
```
- root@OpenWrt:/tmp# mtd write uboot_orig.bin "u-boot"
- Unlocking u-boot ...
- Writing from uboot_orig.bin to u-boot ...
- ```
-
-10. Now, to actually flash the new image, run:
+7. **Danger**: This is the point of no return, if you have any errors or problems, please revert the original image at any time using:
```
- root@OpenWrt:/tmp# mtd write uboot_new.bin "u-boot"
- Unlocking u-boot ...
-
- Writing from uboot_new.bin to u-boot ...
+ root@DD-WRT:/tmp# mtd write uboot_factory.bin "RedBoot"
+ Unlocking RedBoot ...
+ Writing from uboot_orig.bin to RedBoot ...
```
-11. To verify that the image was flashed correctly, you should verify it:
+8. Now, to actually flash the new image, run:
```
- root@OpenWrt:/tmp# mtd verify uboot_new.bin "u-boot"
- Verifying u-boot against uboot_new.bin ...
- a80c3a8683345a3fb311555c5d4194c5 - u-boot
- a80c3a8683345a3fb311555c5d4194c5 - uboot_new.bin
- Success
+ root@DD-WRT:/tmp# mtd write uboot_new.bin "RedBoot"
+ Unlocking RedBoot ...
+ Writing from uboot_new.bin to RedBoot ...
```
-12. To restart with the new bootloader, reboot the router:
+9. If you are sure that everything went OK, you may reboot the device:
```
- root@OpenWrt:/tmp# reboot
+ root@DD-WRT:/tmp# reboot
```
-### Using DD-WRT
-
-[TODO]
-
How to use it?
--------------
You can use one of the free toolchains:
-- [Sourcery CodeBench Lite Edition for MIPS GNU/Linux](https://sourcery.mentor.com/GNUToolchain/subscription3130?lite=MIPS),
-- [OpenWrt Toolchain for AR71xx MIPS](http://downloads.openwrt.org/attitude_adjustment/12.09/ar71xx/generic/OpenWrt-Toolchain-ar71xx-for-mips_r2-gcc-4.6-linaro_uClibc-0.9.33.2.tar.bz2),
+- [OpenWrt Toolchain for AR71xx MIPS](https://downloads.openwrt.org/snapshots/trunk/ar71xx/generic/OpenWrt-Toolchain-ar71xx-generic_gcc-5.3.0_musl-1.1.14.Linux-x86_64.tar.bz2),
+- ~~[Sourcery CodeBench Lite Edition for MIPS GNU/Linux](https://sourcery.mentor.com/GNUToolchain/subscription3130?lite=MIPS)~~,
- [ELDK (Embedded Linux Development Kit)](ftp://ftp.denx.de/pub/eldk/),
- or any others...
-I am using **Sourcery CodeBench Lite Edition for MIPS GNU/Linux** on **Ubuntu 12.04 LTS** (32-bit, virtual machine) and all released binary images were/will be built using this set.
+I am using **OpenWrt Toolchain for AR71xx MIPS** (32-bit, virtual machine) and all released binary images were/will be built using this set.
All you need to do, after choosing a toolchain, is to modify [Makefile](Makefile) - change or remove `export MAKECMD` and if needed add `export PATH`. For example, to use OpenWrt Toolchain instead of Sourcery CodeBench Lite, download it and extract into `toolchain` folder, inside the top dir and change first lines in [Makefile](Makefile):
#### 5. My device does not boot after upgrade!
-*I told you... bootloader, in this case U-Boot, is the most important piece of code inside your device. It is responsible for hardware initialization and booting an OS (kernel in this case), i.e. it's the bridge head for delegating to / flashing kernel and rootfs images. So, if during the upgrade something went wrong, your device will not boot any more. The only way to recover from such a situation in a mild way is via a JTAG adapter connection. In case of a lack of JTAG connection, you would even need to remove the FLASH chip, load proper image using an external programmer and solder it back.*
+*I told you... bootloader, in this case U-Boot, is the most important piece of code inside your device. It is responsible for hardware initialization and booting an OS (kernel in this case), i.e. it is the bridge head for delegating to / flashing kernel and rootfs images. So, if during the upgrade something went wrong, your device will not boot any more. The only way to recover from such a situation in a mild way is via a JTAG adapter connection. In case of a lack of JTAG connection, you would even need to remove the FLASH chip, load proper image using an external programmer and solder it back.*
License, outdated sources etc.
------------------------------
Credits
-------
+- Thanks to M-K O'Connell for donating a router with QCA9563
+- Thanks to Krzysztof M. for donating a TL-WDR3600 router
- Thanks to *pupie* from OpenWrt forum for his great help
- Thanks for all donators and for users who contributed in code development
- [Modyfikacje, zmiany](#modyfikacje-zmiany)
- [Serwer web](#serwer-web)
- [Konsola sieciowa](#konsola-sieciowa)
+ - [Zapisywalne zmienne środowiskowe](#zapisywalne-zmienne-środowiskowe)
- [Inne](#inne)
- [Automatycznie rozpoznawane kości FLASH](#automatycznie-rozpoznawane-kości-flash)
- [Jak to zainstalować?](#jak-to-zainstalować)
Wstęp
-----
-W dużym skrócie, projekt ten jest modyfikacją źródeł **U-Boot 1.1.4**, przede wszystkim z archiwum udostęþnionego przez firmę **TP-Link**. Niektóre fragmenty kodu zostały zaczerpnięte również ze źródeł innych producentów, np. **D-Link**.
+W dużym skrócie, projekt ten jest modyfikacją źródeł **U-Boot 1.1.4**, przede wszystkim z archiwum udostęþnionego przez firmę **TP-Link**. Niektóre fragmenty kodu zostały zaczerpnięte również ze źródeł innych producentów, takich jak **D-Link**, **Netgear**, **ZyXEL** i **Belkin**. Wszystkie te firmy korzystają z SDK Qualcomm/Atheros, które zawiera właśnie zmodyfikowane źródła **U-Boot 1.1.4**.
Oryginalne wersje źródeł można pobrać z poniższych stron:
- [TP-Link GPL Code Center](http://www.tp-link.com/en/support/gpl/ "TP-Link GPL Code Center")
- [D-Link GPL Source Code Support](http://tsd.dlink.com.tw/GPL.asp "D-Link GPL Source Code Support")
+- [NETGEAR Open Source Code for Programmers (GPL)](http://kb.netgear.com/app/answers/detail/a_id/2649/~/netgear-open-source-code-for-programmers-%28gpl%29 "NETGEAR Open Source Code for Programmers (GPL)")
+- [ZyXEL GPL-OSS](http://www.zyxel.com/us/en/form/gpl_oss_form.shtml "ZyXEL GPL-OSS")
+- [Belkin Open Source Code Center](http://www.belkin.com/us/support-article?articleNum=51238 "Belkin Open Source Code Center")
+
Pomysł na tę modyfikację został zaczerpnięty z innego projektu, przeznaczonego dla bardzo popularnego, małego routera mobilnego **TP-Link TL-WR703N**, w którym autor umieścił tryb ratunkowy dostępny przez przeglądarkę: **[wr703n-uboot-with-web-failsafe](http://code.google.com/p/wr703n-uboot-with-web-failsafe/)**. Przez jakiś czas z powodzeniem używałem tej modyfikacji, ale postanowiłem ją ulepszyć, dodać kilka opcji i wsparcie dla innych modeli oraz wszystkich przeglądarek.
-Pierwszą wersję mojej modyfikacji zaprezentowałem na forum **OpenWrt**, w [tym wątku](https://forum.openwrt.org/viewtopic.php?id=43237), pod koniec marca 2013 roku. Zawierała ona wsparcie wyłącznie dla modeli TP-Link z układem SoC **Atheros AR9331**. Obecnie, wspierane są również urządzenia innych producentów, w tym z układem SoC **Atheros AR934x** (**TP-Link TL-WDR3600**, **TL-WDR43x0**, **TL-WR841N/D v8**, **TL-WA830RE v2**), a inne (w najbliższych planach jest wsparcie dla routerów z układami z serii **Qualcomm Atheros QCA955x**) są w trakcie opracowania.
+Pierwszą wersję mojej modyfikacji zaprezentowałem na forum **OpenWrt**, w [tym wątku](https://forum.openwrt.org/viewtopic.php?id=43237), pod koniec marca 2013 roku. Zawierała ona wsparcie wyłącznie dla modeli TP-Link z układem SoC **Atheros AR9331**. Obecnie, wspierane są również urządzenia innych producentów, w tym z układami SoC **Atheros AR934x**, **Qualcomm Atheros QCA953x**, **Qualcomm Atheros QCA955x**, a inne (w najbliższych planach jest wsparcie dla routerów z układami z serii **Qualcomm Atheros QCA956x** oraz **MediaTek MT762x**) są w trakcie opracowania.
Dodatkowe informacje o niniejszej modyfikacji można znaleźć również na [moim blogu](http://www.tech-blog.pl), w [tym artykule](http://www.tech-blog.pl/2013/03/29/zmodyfikowany-u-boot-dla-routerow-tp-link-z-atheros-ar9331-z-trybem-aktualizacji-oprogramowania-przez-www-i-konsola-sieciowa-netconsole/).
- Dragino 2 (MS14)
- Village Telco Mesh Potato 2 (bazuje na Dragino MS14)
- GL.iNet 64xxA ([zdjęcia w mojej galerii](http://galeria.tech-blog.pl/GLiNet/))
+ - Black Swift
- **Atheros AR1311 (bliźniaczy układ AR9331)**
- D-Link DIR-505 H/W ver. A1 ([zdjęcia w mojej galerii](http://galeria.tech-blog.pl/D-Link_DIR-505/))
- TP-Link TL-WDR43x0 v1
- TP-Link TL-WDR3500 v1
+- **Qualcomm Atheros QCA953x**:
+ - TP-Link TL-WR841N/D v9
+ - TP-Link TL-WR820N (wersja przeznaczona na rynek chiński)
+ - TP-Link TL-WR802N
+
Przetestowałem swoją modyfikację na większości z wymienionych powyżej urządzeń, z obrazami OpenWrt i oficjalnym firmware producenta. Jeżeli nie jesteś pewien wersji sprzętowej swojego urządzenia, proszę skontaktuj się ze mną **zanim** dokonasz wymiany obrazu bootloadera. Zmiana na niewłaściwą wersję najprawdopodobniej doprowadzi do uszkodzenia Twojego urządzenia i jedyną możliwością jego ponownego uruchomienia będzie przeprogramowanie kości FLASH w zewnętrznym programatorze.
Dodatkowe informacje o wspieranych urządzeniach:
| [Dragino 2 (MS14)](http://wiki.openwrt.org/toh/dragino/ms14) | AR9331 | 16 MiB | 64 MiB DDR1 | 192 KiB | R/W |
| Village Telco Mesh Potato 2 | AR9331 | 16 MiB | 64 MiB DDR1 | 192 KiB | R/W |
| [GL.iNet](http://wiki.openwrt.org/toh/gl-inet/gl-inet) | AR9331 | 8/16 MiB | 64 MiB DDR1 | 64 KiB | RO |
+| [Black Swift](http://www.black-swift.com) | AR9331 | 16 MiB | 64 MiB DDR2 | 128 KiB, LZMA | R/W |
| [TP-Link TL-MR3420 v2](http://wikidevi.com/wiki/TP-LINK_TL-MR3420_v2) | AR9341 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
| [TP-Link TL-WR841N/D v8](http://wiki.openwrt.org/toh/tp-link/tl-wr841nd) | AR9341 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
| [TP-Link TL-WA830RE v2](http://wikidevi.com/wiki/TP-LINK_TL-WA830RE_v2) | AR9341 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
| [TP-Link TL-WDR43x0 v1](http://wiki.openwrt.org/toh/tp-link/tl-wdr4300) | AR9344 | 8 MiB | 128 MiB DDR2 | 64 KiB, LZMA | RO |
| [TP-Link TL-WDR3500 v1](http://wiki.openwrt.org/toh/tp-link/tl-wdr3500) | AR9344 | 8 MiB | 128 MiB DDR2 | 64 KiB, LZMA | RO |
| [D-Link DIR-505 H/W ver. A1](http://wiki.openwrt.org/toh/d-link/dir-505) | AR1311 | 8 MiB | 64 MiB DDR2 | 64 KiB, LZMA | RO |
+| [TP-Link TL-WR841N/D v9](https://wiki.openwrt.org/toh/tp-link/tl-wr841nd) | QCA9533 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
+| [TP-Link TL-WR820N](https://wiki.openwrt.org/toh/tp-link/tl-wr820n) | QCA9531 | 4 MiB | 64 MiB DDR2 | 64 KiB, LZMA | RO |
+| [TP-Link TL-WR802N](https://wikidevi.com/wiki/TP-LINK_TL-WR802N_v1.0) | QCA9533 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
*(LZMA) - obraz binarny U-Boot został dodatkowo skompresowany przy pomocy LZMA.*
*(R/W) - zmienne środowiskowe przechowywane są w osobnym bloku FLASH, co pozwala na ich zachowanie po odłączeniu zasilaniu.*
6. fail.html
7. style.css
-
+
+
+
+
+
### Konsola sieciowa
+### Zapisywalne zmienne środowiskowe
+
+U-Boot wykorzystuje tak zwane "**zmienne środowiskowe**", w których przechowywane są wartości wielu ustawień, takich jak adresy IP urządzenia i serwera zdalnego dla transakcji TFTP, prędkość konsoli szeregowej, polecenie do załadowania kernela itd. Zmienne te zapisywane są zazwyczaj w osobnym sektorze FLASH lub w jego części, co umożliwia zachowanie zmian na stałe.
+
+Żaden z popularnych producentów nie udostępnia tej funkcjonalności i w swoich wersjach U-Boot wykorzystuje zmienne środowiskowe "**tylko do odczytu**" (wartości zmiennych są wbudowane w obraz U-Boot), co oznacza że wszelkie zmiany wprowadzone w trakcie pracy bootloadera zostaną utracone po ponownym uruchomieniu urządzenia i nie ma żadnej możliwość zapisania ich w pamięci FLASH.
+
+Ta modyfikacja używa zapisywalnych zmiennych środowiskowych w prawie wszystkich wspieranych urządzeniach, co daje możliwość wykonania na przykład:
+
+```
+uboot> setenv ipaddr 192.168.1.100
+uboot> saveenv
+Saving environment to FLASH...
+
+Erase FLASH from 0x9F010000 to 0x9F01FFFF in bank #1
+Erasing: #
+
+Erased sectors: 1
+
+Writting at address: 0x9F010000
+
+uboot> reset
+```
+
+Spowoduje to zmianę adresu IP urządzenia i zapisanie zmienionych zmiennych środowiskowych we FLASH. Od kolejnego uruchomienia urządzenie będzie wykorzystywać nowy adres.
+
+Wykorzystując polecenie **run** i zmienne środowiskowe możesz pisać niestandardowe, niewielkie skrypty jak ten poniżej, wykorzystywany do aktualizacji firmware metodą TFTP:
+
+```
+uboot> printenv
+[...]
+firmware_addr=0x9F020000
+firmware_name=firmware.bin
+firmware_upg=if ping $serverip; then tftp $loadaddr $firmware_name && erase $firmware_addr +$filesize && cp.b $loadaddr $firmware_addr $filesize && echo OK!; else echo ERROR! Server not reachable!; fi
+[...]
+
+uboot> run firmware_upg
+Ethernet mode (duplex/speed): 1/100 Mbps
+Using eth0 device
+
+Ping OK, host 192.168.1.2 is alive!
+
+
+TFTP from IP: 192.168.1.2
+ Our IP: 192.168.1.1
+ Filename: 'firmware.bin'
+Load address: 0x80800000
+ Using: eth0
+
+ Loading: ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ ########################################
+ #########
+
+TFTP transfer complete!
+
+Bytes transferred: 3932160 (0x3c0000)
+Erase FLASH from 0x9F020000 to 0x9F3DFFFF in bank #1
+Erasing: #######################################
+ #####################
+
+Erased sectors: 60
+
+Copying to FLASH...
+Writting at address: 0x9F020000
+
+Done!
+
+OK!
+uboot>
+```
+
### Inne
Ponadto:
- Automatyczne rozpoznawanie zastosowanej kości FLASH na podstawie JEDEC ID
- MAC adres dla interfejsów sieciowych jest pobierany z FLASH, a nie ustawiany na sztywno
- Ładowanie firmware może być przerwane przy pomocy dowolnego klawisza
+- Lepszy sterownik konsoli szeregowej UART ze wsparciem dla wielu prędkości
- Wciśnij i przytrzymaj przycisk aby uruchomić:
- Werwer web (min. 3 sekundy)
- Konsolę szeregową U-Boot (min. 5 sekundy)
- Konsolę sieciową U-Boot (min. 7 sekundy)
- Dodatkowe komendy (w odniesieniu do wersji producenta; dostępność zależy od modelu):
+ - defenv
- httpd
+ - itest
+ - loadb
+ - loady
- printmac
- setmac
- printmodel
- printpin
- startnc
- startsc
- - eraseenv
- ping
- dhcp
- sntp
Automatyczna detekcja typu zastosowanej kości FLASH może być bardzo przydatna jeżeli wymieniłeś FLASH w swoim routerze. Nie musisz dokonywać zmian w oficjalnych źródłach i kompilować ich żeby mieć dostęp do całej zawartości FLASH z poziomu konsoli U-Boot.
-Jeżeli wykorzystasz kość, której nie ma na poniższej liście, moja wersja U-Boot będzie traktować ją tak jakby miała rozmiar zgodny z rozmiarem domyślnie zastosowanej kości w danym modelu. W większości urządzeń nie będziesz też miał możliwości aktualizacji obrazu danych kalibracyjnych układu radiowego (ART).
+Jeżeli wykorzystasz kość, której nie ma na poniższej liście, moja wersja U-Boot spróbuje odczytać jej parametry wykorzystując standard **Serial Flash Discoverable Parameter** (**SFDP**, więcej informacji: https://www.jedec.org/standards-documents/docs/jesd216b). Jeżeli Twoja kość nie wspiera SFDP, ta modyfikacja będzie traktować ją tak jakby miała rozmiar zgodny z rozmiarem domyślnie zastosowanej kości w danym modelu. W większości urządzeń nie będziesz też miał możliwości aktualizacji obrazu danych kalibracyjnych układu radiowego (ART).
Pełna lista obsługiwanych kości FLASH:
- Winbond W25Q128 (16 MB, JEDEC ID: EF 4018)*
- Macronix MX25L128 (16 MB, JEDEC ID: C2 2018, C2 2618)
- Spansion S25FL127S (16 MB, JEDEC ID: 01 2018)*
+- Micron N25Q128 (16 MB, JEDEC ID: 20 BA18)
(*) przetestowane
mtd5: 00fd0000 00010000 "firmware"
```
-Jak widać powyżej, partycja o nazwie `u-boot` ma rozmiar **0x20000** (128 KiB), z kolei publikowane przeze mnie gotowe obrazy dla tego modelu mają rozmiar **0x10000** (64 KiB). Jest to bardzo istotna różnica i powinieneś o niej pamiętać, jeżeli do zmiany U-Boot zamierzasz wykorzystać narzędzie `mtd`.
+Jak widać powyżej, partycja o nazwie `u-boot` ma rozmiar **0x20000** (128 KiB), z kolei publikowane przeze mnie gotowe obrazy dla tego modelu mają mniejszy rozmiar: **0x1EC00** (123 KiB). Jest to bardzo istotna różnica i powinieneś o niej pamiętać, jeżeli do zmiany U-Boot zamierzasz wykorzystać narzędzie `mtd` lub konsolę szeregową i wiersz poleceń U-Boot.
W celu skopiowania zawartości partycji `u-boot` do pamięci RAM, wykonaj:
Jeżeli dysponujesz programatorem kości FLASH (wszystkie wspierane urządzenia posiadają kości typu **SPI NOR FLASH**), najpewniej wiesz jak z niego korzystać. Pobierz archiwum zawierające gotowe obrazy binarne lub samodzielnie skompiluj kod źródłowy, wybierz odpowiedni plik dla swojego urządzenia i wgraj go na sam początek kości (ofset `0x00000`). Musisz pamiętać jedynie o skasowaniu bloku(ów) przed wgraniem obrazu - jeżeli wykorzystujesz gotowe oprogramowanie dla programatora, w trybie automatycznym, prawdopodobnie odpowiedni obszar zostanie automatycznie wykasowany przed wgraniem wskazanego obrazu.
-Wszystkie publikowane przeze mnie gotowe obrazy binarne są dopełnione wartościami 0xFF, tak żeby ich rozmiar finalny był zawsze **wielokrotnością rozmiaru pojedynczego bloku 64 KiB** i nie przekraczał rozmiaru oryginalnej partycji z U-Boot. Przykładowo, **TP-Link** w większości swoich nowych urządzeń wykorzystuje tylko pierwszy **64 KiB** blok do przechowywania skompresowanego obrazu U-Boot. W kolejnym 64 KiB bloku umieszcza takie informacje jak adres MAC, numer i wersję modelu oraz czasami pin WPS.
+Wszystkie publikowane przeze mnie gotowe obrazy binarne są dopełnione wartościami 0xFF i od zmiany "****", dla większości wspieranych urządzeń, **nie są już wielokrotnością rozmiaru pojedynczego bloku 64 KiB**. Przykładowo, **TP-Link** w większości swoich nowych urządzeń wykorzystuje tylko pierwszy **64 KiB** blok do przechowywania skompresowanego obrazu U-Boot. W kolejnym 64 KiB bloku umieszcza takie informacje jak adres MAC, numer i wersję modelu oraz czasami pin WPS. Ta modyfikacja wykorzystuje oba sektory na obraz U-Boot oraz dodatkowe dane, w tym niewielki blok na zapisywalne zmienne środowiskowe.
+
+Poniższy fragment początkowy mapy pamięci FLASH dla modelu TP-Link TL-MR3020 pokazuje różnice pomiędzy wersją producenta i modyfikacją.
+
+
Z drugiej strony, obraz U-Boot w module **8devices Carambola 2** może mieć maksymalnie **256 KiB** (4 bloki po 64 KiB każdy), ale obraz nie jest skompresowany. Zaraz za nim, w kolejnym 64 KiB bloku, znajdują się zmienne środowiskowe - partycja ta w OpenWrt, w tym konkretnym przypadku, nosi nazwę `u-boot-env`:
### Przy pomocy UART, konsoli U-Boot i serwera TFTP
+**UWAGA! Ta metoda jest zdecydowanie niezalecana!**
+
Jest to prawdopodobnie najczęściej wykorzystywana metoda do wgrania firmware w przypadku problemów z uruchomieniem wersji znajdującej się w urządzeniu lub po nieudanej aktualizacji. Istotną wadą tego podejścia jest potrzeba rozebrania routera i połączenia się z nim przy pomocy interfejsu szeregowego UART (w przypadku Carambola 2 w wersji z płytką developerską sprawa jest ułatwiona, ponieważ adapter USB-UART bazujący na FTDI FT232RQ znajduje się już na PCB).
#### Ważna informacja!
serverip=192.168.1.2
```
-7. Pobierz z serwera TFTP i umieść w pamięci RAM urządzenia właściwy dla swojego modelu obraz U-Boot, wykorzystując polecenie `tftpboot` (na przykładzie **TP-Link TL-MR3020**):
+7. Ze względu na różnice w mapie pamięci i rozmiarze obrazu oryginalnej i zmodyfikowanej wersji U-Boot, musisz najpierw wykonać kopię zapasową partycji z oryginalną wersją, w pamięci RAM. **Pominięcie lub nieprawidłowe wykonanie tego kroku prawdopodobnie zakończy się uszkodzeniem Twojego urządzenia!**
+
+ Ten krok różni się w zależności od modelu, dlatego powinieneś zwrócić szczególną uwagę na rozmiar obrazu zmodyfikowanej wersji, **zaokrąglić go w górę, do najbliższej wielokrotności 64 KiB** i używać tej wartości we wszystkich kolejnych krokach.
+ Przykładowo, jeżeli obraz modyfikacji ma **123 KiB** (**0x1EC00**) powinieneś najpierw wykonać kopię zapasową **128 KiB** (**0x20000**) w pamięci RAM, pod tym samym adresem, do którego później zostanie pobrany ten obraz:
+
+ ```
+ hornet> cp.b 0x9F000000 0x80800000 0x20000
```
- tftpboot 0x80800000 uboot_for_tp-link_tl-mr3020.bin
+ Wykorzystanie tego samego adresu w pamięci RAM spowoduje "sklejenie" obu obrazów i zachowanie dodatkowych, oryginalnych danych, takich jak adres MAC, numer modelu i PIN.
+
+8. Pobierz z serwera TFTP i umieść w pamięci RAM urządzenia właściwy dla swojego modelu obraz U-Boot, wykorzystując polecenie `tftpboot` (na przykładzie **TP-Link TL-MR3020**):
+
+ ```
+ hornet> tftpboot 0x80800000 uboot_for_tp-link_tl-mr3020.bin
eth1 link down
Using eth0 device
TFTP from server 192.168.1.2; our IP address is 192.168.1.1
Filename 'uboot_for_tp-link_tl-mr3020.bin'.
Load address: 0x80800000
- Loading: #############
+ Loading: #########################
done
- Bytes transferred = 65536 (10000 hex)
+ Bytes transferred = 125952 (1ec00 hex)
+
hornet>
```
-8. Kolejny krok jest bardzo ryzykowny! Wykonując następne polecenia, najpierw skasujesz oryginalny obraz U-Boot z pamięci FLASH, a następnie skopiujesz w to miejsce nowy obraz, z pamięci RAM. Jeżeli w trakcie tego procesu coś pójdzie nie tak (na przykład dojdzie do awarii zasilania), Twój router najprawdopodobniej już się nie uruchomi ponownie!
+9. Kolejny krok jest bardzo ryzykowny! Wykonując następne polecenia, najpierw skasujesz oryginalny obraz U-Boot z pamięci FLASH, a następnie skopiujesz w to miejsce nowy obraz, z pamięci RAM. Jeżeli w trakcie tego procesu coś pójdzie nie tak (na przykład dojdzie do awarii zasilania), Twój router najprawdopodobniej już się nie uruchomi ponownie!
- Powinieneś też zwrócić uwagę na rozmiar pobieranego obrazu. Dla wspieranych modeli routerów **TP-Link** i **D-Link** będzie on miał zawsze rozmiar **0x10000** (64 KiB), z kolei w przypadku modułu Carambola 2, rozmiar obrazu jest inny: **0x40000** (256 KiB). We wszystkich przypadkach, adres początkowy pamięci FLASH i RAM to odpowiednio: **0x9F000000** i **0x80000000**. Jak mogłeś zauważyć, w poprzednim kroku, do zapisania pobranego przez sieć obrazu, nie wykorzystałem początkowego adresu pamięci RAM i również nie powinieneś tego robić.
+ Powinieneś też zwrócić uwagę na rozmiar i wykorzystać wartość, którą obliczyłeś w kroku 7. We wszystkich przypadkach, adres początkowy pamięci FLASH i RAM to odpowiednio: **0x9F000000** i **0x80000000**. Jak mogłeś zauważyć, w poprzednim kroku, do zapisania pobranego przez sieć obrazu, nie wykorzystałem początkowego adresu pamięci RAM i również nie powinieneś tego robić.
Nie popełnij żadnych błędów w rozmiarach i adresach (ofsetach), w kolejnych krokach!
-9. Skasuj odpowiedni obszar w pamięci FLASH (to polecenie usunie oryginalny obraz U-Boot!):
+10. Skasuj odpowiedni obszar w pamięci FLASH (to polecenie usunie oryginalny obraz U-Boot!):
```
- hornet> erase 0x9F000000 +0x10000
+ hornet> erase 0x9F000000 +0x20000
- First 0x0 last 0x0 sector size 0x10000
- 0
- Erased 1 sectors
+ First 0x0 last 0x1 sector size 0x10000
+ Erased 2 sectors
+ hornet>
```
-10. W tej chwili Twój router nie posiada żadnego bootloadera, dlatego skopiuj do FLASH z pamięci RAM pobrany wcześniej, nowy obraz:
+11. W tej chwili Twój router nie posiada żadnego bootloadera, dlatego skopiuj do FLASH z pamięci RAM pobrany wcześniej, nowy obraz:
```
- hornet> cp.b 0x80800000 0x9F000000 0x10000
+ hornet> cp.b 0x80800000 0x9F000000 0x20000
Copy to Flash... write addr: 9f000000
done
```
-11. Jeżeli chcesz, możesz wyświetlić w konsoli U-Boot zawartość pamięci FLASH i porównać ją z obrazem na komputerze. W tym celu należy skorzystać z komendy `md`, która spowoduje wyświetlenie 256 bajtów danych w postaci szesnastkowej i tekstowej, począwszy od podanego w argumencie adresu. Kolejne wywołanie tego samego polecenia, tym razem bez parametru, spowoduje wyświetlenie kolejnej porcji danych.
+12. Jeżeli chcesz, możesz wyświetlić w konsoli U-Boot zawartość pamięci FLASH i porównać ją z obrazem na komputerze. W tym celu należy skorzystać z komendy `md`, która spowoduje wyświetlenie 256 bajtów danych w postaci szesnastkowej i tekstowej, począwszy od podanego w argumencie adresu. Kolejne wywołanie tego samego polecenia, tym razem bez parametru, spowoduje wyświetlenie kolejnej porcji danych.
```
hornet> md 0x9F000000
9f0000f0: 100001ea 00000000 100001e8 00000000 ................
```
-12. Jeżeli jesteś pewien, że wszystko przebiegło prawidłowo, możesz zrestartować urządzenie:
+13. Jeżeli jesteś pewien, że wszystko przebiegło prawidłowo, możesz zrestartować urządzenie przy pomocy poniższego polecenia lub restartując zasilanie:
```
hornet> reset
### Przy pomocy OpenWrt
-[TODO]
+**Ta metoda jest zalecana!**
+
+Począwszy od oficjalnego wydania "**[2014-11-19](https://github.com/pepe2k/u-boot_mod/releases/tag/2014-11-19)**", wewnątrz archiwum znajdziesz przygotowane obrazy **OpenWrt** z odblokowaną możliwością zapisu na partycji `u-boot`, gotowym obrazem U-Boot oraz niewielkim, dedykowanym skryptem do prostej aktualizacji bootloadera. Jedyne, co należy zrobić to pobrać ostatnie oficjalne wydanie tej modyfikacji, wybrać i zainstalować odpowiedni obraz OpenWrt i wywołać skrypt poleceniem `u-boot-upgrade`:
+
+```
+root@OpenWrt:/# u-boot-upgrade
+
+=================================================================
+ DISCLAIMER: you are using this script at your own risk!
+
+ The author of U-Boot modification and this script takes
+ no responsibility for any of the results of using them.
+
+ Updating U-Boot is a very dangerous operation
+ and may damage your device! You have been warned!
+=================================================================
+ Are you sure you want to continue (type 'yes' or 'no')? yes
+=================================================================
+
+[ ok ] Found U-Boot image file: uboot_for_tp-link_tl-mr3020.bin
+ Do you want to use this file (type 'yes' or 'no')? yes
+[ ok ] MD5 checksum of new U-Boot image file is correct
+[ ok ] Backup of /dev/mtd0 successfully created
+ Do you want to store backup in /etc/u-boot_mod/backup/ (recommended, type 'yes' or 'no')? no
+[ ok ] New U-Boot image successfully combined with backup file
+[info] New U-Boot image is ready to be written into FLASH
+ Are you sure you want to continue (type 'yes' or 'no')? yes
+[ ok ] New U-Boot image successfully written info FLASH
+[ ok ] MD5 checksum of mtd0 and new U-Boot image are equal
+[info] Done!
+```
### Przy pomocy DD-WRT
-[TODO]
+**UWAGA! Ta metoda jest niezalecana!**
+
+1. Zaloguj się do routera przy pomocy SSH lub telnetu i sprawdź, która z partycji mtd jest pierwsza. W DD-WRT najczęściej będzie to `RedBoot`:
+
+ ```
+ root@DD-WRT:~# cat /proc/mtd
+ dev: size erasesize name
+ mtd0: 00020000 00010000 "RedBoot"
+ mtd1: 003c0000 00010000 "linux"
+ mtd2: 002c0000 00010000 "rootfs"
+ mtd3: 00010000 00010000 "ddwrt"
+ mtd4: 00010000 00010000 "nvram"
+ mtd5: 00010000 00010000 "board_config"
+ mtd6: 00400000 00010000 "fullflash"
+ mtd7: 00020000 00010000 "fullboot"
+ ```
+
+ W przypadku **TP-Link TL-MR3020**, partycja `RedBoot` zawiera obraz U-Boot oraz dodatkowe dane, takie jak adres MAC, numer modelu oraz PIN.
+
+ **Uwaga!** Jeżeli rozmiar pierwszej partycji jest mniejszy niż rozmiar obrazu zmodyfikowanej wersji U-Boot, nie kontynuuj!
+
+2. Przy pomocy SCP lub innej metody skopiuj obraz U-Boot i odpowiedni plik z sumą MD5 do folderu `/tmp` na urządzeniu.
+
+ ```
+ root@DD-WRT:/tmp# ls -la
+ [...]
+ -rw-r--r-- 1 root root 125952 Nov 5 2015 uboot_for_tp-link_tl-mr3020.bin
+ -rw-r--r-- 1 root root 66 Nov 5 2015 uboot_for_tp-link_tl-mr3020.md5
+ [...]
+ ```
+
+3. Sprawdź sumę kontrolną MD5 pliku z obrazem:
+
+ ```
+ root@DD-WRT:/tmp# md5sum uboot_for_tp-link_tl-mr3020.bin
+ aaae0f772ce007f7d1542b9233dd765b uboot_for_tp-link_tl-mr3020.bin
+
+ root@DD-WRT:/tmp# cat uboot_for_tp-link_tl-mr3020.md5
+ aaae0f772ce007f7d1542b9233dd765b *uboot_for_tp-link_tl-mr3020.bin
+ ```
+
+4. Utwórz kopię zapasową partycji `RedBoot` (`mtd0`):
+
+ ```
+ root@DD-WRT:/tmp# dd if=/dev/mtd0 of=uboot_factory.bin
+ 256+0 records in
+ 256+0 records out
+ ```
+
+5. Przy pomocy SCP lub innej metody, skopiuj utworzoną kopię zapasową w jakieś bezpieczne miejsce (zdecydowanie zalecam zapisanie gdzieś tego pliku!).
+
+6. Potrzebujesz utworzyć plik składający się z oryginalnego i zmodyfikowaneg obrazu, ale `dd` z DD-WRT prawdopodobnie nie obsługuje `conv=notrunc`, dlatego wykorzystamy inne podejście:
+
+ ```
+ root@DD-WRT:/tmp# dd if=uboot_factory.bin of=uboot_rest.bin bs=1 skip=$(wc -c < uboot_for_tp-link_tl-mr3020.bin)
+ 5120+0 records in
+ 5120+0 records out
+
+ root@DD-WRT:/tmp# cat uboot_for_tp-link_tl-mr3020.bin uboot_rest.bin > uboot_new.bin
+ ```
+
+7. **Uwaga**: To jest punkt bez powrotu. Jeżeli podczas dotychczasowych kroków wystąpiły jakieś błędy lub problemy, wgraj kopię oryginalnej partycji z powrotem, przy pomocy polecenia:
+
+ ```
+ root@DD-WRT:/tmp# mtd write uboot_factory.bin "RedBoot"
+ Unlocking RedBoot ...
+ Writing from uboot_orig.bin to RedBoot ...
+ ```
+
+8. W celu wgrania nowego obrazu, wykonaj poniższe polecenie:
+
+ ```
+ root@DD-WRT:/tmp# mtd write uboot_new.bin "RedBoot"
+ Unlocking RedBoot ...
+ Writing from uboot_new.bin to RedBoot ...
+ ```
+
+9. Jeżeli jesteś pewien, że do tej pory wszystko przebiegło pomyślnie, możesz zrestartować urządzenie:
+
+ ```
+ root@DD-WRT:/tmp# reboot
+ ```
### Jak korzystać z tej modyfikacji?
Możesz wykorzystać jeden z dostępnych, bezpłatnych i gotowych narzędzi (tzw. toolchain):
-- [Sourcery CodeBench Lite Edition for MIPS GNU/Linux](https://sourcery.mentor.com/GNUToolchain/subscription3130?lite=MIPS),
-- [OpenWrt Toolchain for AR71xx MIPS](http://downloads.openwrt.org/attitude_adjustment/12.09/ar71xx/generic/OpenWrt-Toolchain-ar71xx-for-mips_r2-gcc-4.6-linaro_uClibc-0.9.33.2.tar.bz2),
+- [OpenWrt Toolchain for AR71xx MIPS](https://downloads.openwrt.org/snapshots/trunk/ar71xx/generic/OpenWrt-Toolchain-ar71xx-generic_gcc-5.3.0_musl-1.1.14.Linux-x86_64.tar.bz2),
+- ~~[Sourcery CodeBench Lite Edition for MIPS GNU/Linux](https://sourcery.mentor.com/GNUToolchain/subscription3130?lite=MIPS)~~,
- [ELDK (Embedded Linux Development Kit)](ftp://ftp.denx.de/pub/eldk/),
- lub innych...
-Do kompilacji korzystam z **Sourcery CodeBench Lite Edition for MIPS GNU/Linux**, na maszynie wirtualnej z zainstalowanym **Ubuntu 12.04 LTS** (32-bit). Wszystkie publikowane przeze mnie obrazy budowane są na tej konfiguracji.
+Do kompilacji korzystam z **OpenWrt Toolchain for AR71xx MIPS**, na maszynie wirtualnej z zainstalowanym **Ubuntu 12.04 LTS** (32-bit). Wszystkie publikowane przeze mnie obrazy budowane są na tej konfiguracji.
Wszystko co musisz zrobić, po wybraniu zestawu narzędzi, to dostosowanie pliku [Makefile](Makefile) do własnej konfiguracji (czyli zmiana lub usunięcie `export MAKECMD` i ewentualnie dodanie `export PATH`). Przykładowo, w celu zbudowania obrazów przy pomocy OpenWrt Toolchain, zamiast Sourcery CodeBench Lite, pobierz odpowiednie archiwum i rozpakuj jego zawartość do folderu `toolchain`, w głównym katalogu ze źródłami, a następnie zmień początek pliku [Makefile](Makefile), jak poniżej:
Podziękowania
-------------
+- Dziękuję M-K O'Connell za przekazanie routera z QCA9563
+- Dziękuję Krzysztofowi M. za przekazanie routera TL-WDR3600
- Dziękuję użytkownikowi *pupie* z forum OpenWrt za jego nieocenioną pomoc
-- Dziękuję wszystkim darczyńcom i osobom wspierającym rozwój tej modyfikacji
\ No newline at end of file
+- Dziękuję wszystkim darczyńcom i osobom wspierającym rozwój tej modyfikacji
VERSION = 1
PATCHLEVEL = 1
SUBLEVEL = 4
-EXTRAVERSION =
-U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+EXTRAVERSION = -$(shell git rev-parse --short=8 HEAD)
+ISREPODIRTY = $(shell if git diff-files | read dummy; then echo 1; else echo 0; fi)
VERSION_FILE = include/version_autogenerated.h
+# Show in version string if we are not building from clean repository
+ifeq ($(ISREPODIRTY), 1)
+U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)"-dirty"
+else
+U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)"-clean"
+endif
+
HOSTARCH := $(shell uname -m | \
sed -e s/i.86/i386/ \
-e s/sun4u/sparc64/ \
#########################################################################
common_config :
@ >include/config.h
+ @echo "/* Temporary solution */" >> include/config.h
+ @echo "/* AR933x */" >> include/config.h
+ @echo "#define QCA_AR9330_SOC 0x00001" >> include/config.h
+ @echo "#define QCA_AR9331_SOC 0x00002" >> include/config.h
+ @echo "#define QCA_AR933X_SOC (QCA_AR9330_SOC | QCA_AR9331_SOC)" >> include/config.h
+ @echo "/* AR934x */" >> include/config.h
+ @echo "#define QCA_AR9341_SOC 0x00010" >> include/config.h
+ @echo "#define QCA_AR9342_SOC 0x00020" >> include/config.h
+ @echo "#define QCA_AR9344_SOC 0x00040" >> include/config.h
+ @echo "#define QCA_AR934X_SOC (QCA_AR9341_SOC | QCA_AR9342_SOC | QCA_AR9344_SOC)" >> include/config.h
+ @echo "/* QCA953x */" >> include/config.h
+ @echo "#define QCA_QCA9531_SOC 0x00100" >> include/config.h
+ @echo "#define QCA_QCA9533_SOC 0x00200" >> include/config.h
+ @echo "#define QCA_QCA953X_SOC (QCA_QCA9531_SOC | QCA_QCA9533_SOC)" >> include/config.h
+ @echo "/* QCA956x */" >> include/config.h
+ @echo "#define QCA_QCA9561_SOC 0x01000" >> include/config.h
+ @echo "#define QCA_QCA9563_SOC 0x02000" >> include/config.h
+ @echo "#define QCA_QCA956X_SOC (QCA_QCA9561_SOC | QCA_QCA9563_SOC)" >> include/config.h
+ @echo "/* QCA955x */" >> include/config.h
+ @echo "#define QCA_QCA9557_SOC 0x10000" >> include/config.h
+ @echo "#define QCA_QCA9558_SOC 0x20000" >> include/config.h
+ @echo "#define QCA_QCA955X_SOC (QCA_QCA9557_SOC | QCA_QCA9558_SOC)" >> include/config.h
+ @echo "" >> include/config.h
ifdef CONFIG_BOOTDELAY
@echo "#define CONFIG_BOOTDELAY "$(CONFIG_BOOTDELAY) >> include/config.h
@echo "#define CONFIG_MAX_UBOOT_SIZE_KB "$(CONFIG_MAX_UBOOT_SIZE_KB) >> include/config.h
endif
-ifdef CFG_PLL_FREQ
- @echo "#define CFG_PLL_FREQ "$(CFG_PLL_FREQ) >> include/config.h
-endif
-
ifdef DISABLE_CONSOLE_OUTPUT
@echo "#define CONFIG_SILENT_CONSOLE 1" >> include/config.h
endif
@echo "#define CFG_CONSOLE_INFO_QUIET" >> include/config.h
hornet_common_config : common_config
- @echo "#define CONFIG_AR7240 1" >> include/config.h
+ @echo "#define SOC_TYPE QCA_AR933X_SOC" >> include/config.h
@echo "#define CONFIG_MACH_HORNET 1" >> include/config.h
- @echo "#define CONFIG_HORNET_1_1_WAR 1" >> include/config.h
wr703n_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-WR703N at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_TPLINK_WR703N_V1 1" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-WR703N\"" >> include/config.h
-
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-WR703N\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
-wr720n_v3_CH_config : unconfig hornet_common_config
- @/bin/echo -e '\e[32m> Configuring for TP-Link TL-WR720N v3 CH at:' `date` '\e[0m'
+wr720n_v3_CN_config : unconfig hornet_common_config
+ @/bin/echo -e '\e[32m> Configuring for TP-Link TL-WR720N v3 CN at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_TPLINK_WR720N_V3 1" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-WR720N v3 CH\"" >> include/config.h
-
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-WR720N v3 CN\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
wr710n_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-WR710N at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_TPLINK_WR710N_V1 1" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-WR710N\"" >> include/config.h
-
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-WR710N\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
mr3020_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-MR3020 at:' `date`.'\e[0m'
@echo "#define CONFIG_FOR_TPLINK_MR3020_V1 1" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_BIT 27" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_ON 0" >> include/config.h
- @echo "#define GPIO_WPS_LED_BIT 26" >> include/config.h
- @echo "#define GPIO_WPS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_BIT 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_ON 1" >> include/config.h
- @echo "#define GPIO_ETH_LED_BIT 17" >> include/config.h
- @echo "#define GPIO_ETH_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-MR3020\"" >> include/config.h
-
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-MR3020\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
mr3040_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-MR3040 at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_TPLINK_MR3040_V1V2 1" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_BIT 27" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_ON 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_BIT 26" >> include/config.h
- @echo "#define GPIO_WLAN_LED_ON 0" >> include/config.h
- @echo "#define GPIO_ETH_LED_BIT 17" >> include/config.h
- @echo "#define GPIO_ETH_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-MR3040\"" >> include/config.h
-
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-MR3040\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
mr10u_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-MR10U at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_TPLINK_MR10U_V1 1" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-MR10U\"" >> include/config.h
-
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-MR10U\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
mr13u_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-MR13U at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_TPLINK_MR13U_V1 1" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-MR13U\"" >> include/config.h
-
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-MR13U\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
wr740n_v4_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-WR740N v4 at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_TPLINK_WR740N_V4 1" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_BIT 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_ON 1" >> include/config.h
- @echo "#define GPIO_LAN1_LED_BIT 14" >> include/config.h
- @echo "#define GPIO_LAN1_LED_ON 1" >> include/config.h
- @echo "#define GPIO_LAN2_LED_BIT 15" >> include/config.h
- @echo "#define GPIO_LAN2_LED_ON 1" >> include/config.h
- @echo "#define GPIO_LAN3_LED_BIT 16" >> include/config.h
- @echo "#define GPIO_LAN3_LED_ON 1" >> include/config.h
- @echo "#define GPIO_LAN4_LED_BIT 17" >> include/config.h
- @echo "#define GPIO_LAN4_LED_ON 0" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_BIT 13" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_ON 1" >> include/config.h
- @echo "#define GPIO_QSS_LED_BIT 1" >> include/config.h
- @echo "#define GPIO_QSS_LED_ON 1" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-WR74xN/D v4\"" >> include/config.h
-
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-WR74xN/D v4\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
mr3220_v2_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-MR3220 v2 at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_TPLINK_MR3220_V2 1" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_BIT 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_ON 1" >> include/config.h
- @echo "#define GPIO_LAN1_LED_BIT 14" >> include/config.h
- @echo "#define GPIO_LAN1_LED_ON 1" >> include/config.h
- @echo "#define GPIO_LAN2_LED_BIT 15" >> include/config.h
- @echo "#define GPIO_LAN2_LED_ON 1" >> include/config.h
- @echo "#define GPIO_LAN3_LED_BIT 16" >> include/config.h
- @echo "#define GPIO_LAN3_LED_ON 1" >> include/config.h
- @echo "#define GPIO_LAN4_LED_BIT 17" >> include/config.h
- @echo "#define GPIO_LAN4_LED_ON 0" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_BIT 13" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_ON 1" >> include/config.h
- @echo "#define GPIO_QSS_LED_BIT 1" >> include/config.h
- @echo "#define GPIO_QSS_LED_ON 1" >> include/config.h
- @echo "#define GPIO_USB_LED_BIT 26" >> include/config.h
- @echo "#define GPIO_USB_LED_ON 1" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-MR3220 v2\"" >> include/config.h
-
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-MR3220 v2\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
dir505_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for D-Link DIR-505 at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_DLINK_DIR505_A1 1" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
-
- # we will use WPS button instead of reset
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_IS_ACTIVE_LOW 1" >> include/config.h
-
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for DIR-505\"" >> include/config.h
-
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"D-Link DIR-505\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
gs_oolite_v1_dev_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for GS-Oolite v1 with dev board at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_GS_OOLITE_V1_DEV 1" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_WAN_LED_BIT 17" >> include/config.h
- @echo "#define GPIO_WAN_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN1_LED_BIT 13" >> include/config.h
- @echo "#define GPIO_LAN1_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN2_LED_BIT 15" >> include/config.h
- @echo "#define GPIO_LAN2_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 16" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for GS-Oolite v1\"" >> include/config.h
-
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 16" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"Gainstrong GS-Oolite v1\"" >> include/config.h
+
+ @./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
+
+black_swift_board_config : unconfig hornet_common_config
+ @echo '======= Configuring for Black Swift board (128K compressed) at:' `date` '======='
+ @echo "#define CONFIG_FOR_BLACK_SWIFT_BOARD 1" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 16" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"Black Swift board\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
carambola2_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for 8devices Carambola 2 at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_8DEVICES_CARAMBOLA2 1" >> include/config.h
-
- # Carambola 2 uses uncompressed version
@echo "#undef COMPRESSED_UBOOT" >> include/config.h
-
- # Carambola 2 uses 40 MHz oscillator
@echo "#define CONFIG_40MHZ_XTAL_SUPPORT 1" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 16" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"8devices Carambola2 v1\"" >> include/config.h
- @echo "#define GPIO_WLAN_LED_BIT 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
-
- # Carambola 2 development board has RST button pulled up, so it is active at low
- @echo "#define GPIO_RST_BUTTON_IS_ACTIVE_LOW 1" >> include/config.h
-
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 16" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for CARAMBOLA2 v1\"" >> include/config.h
-
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
dragino_v2_ms14_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for Dragino Dragino v2 (MS14) at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_DRAGINO_V2 1" >> include/config.h
@echo "#undef COMPRESSED_UBOOT" >> include/config.h
- @echo "#define GPIO_WLAN_LED_BIT 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_ON 1" >> include/config.h
- @echo "#define GPIO_WAN_LED_BIT 17" >> include/config.h
- @echo "#define GPIO_WAN_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN_LED_BIT 13" >> include/config.h
- @echo "#define GPIO_LAN_LED_ON 0" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_BIT 28" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_ON 1" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_IS_ACTIVE_LOW 1" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 16" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 16" >> include/config.h
@echo "#define WEBFAILSAFE_DISABLE_ART_UPGRADE 1" >> include/config.h
@echo "#define WEBFAILSAFE_DISABLE_UBOOT_UPGRADE 1" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for Dragino v2 MS14\"" >> include/config.h
-
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"Dragino v2 MS14\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
villagetelco_mp2_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for Village Telco Mesh Potato 2 at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_MESH_POTATO_V2 1" >> include/config.h
@echo "#undef COMPRESSED_UBOOT" >> include/config.h
- @echo "#define GPIO_WLAN_LED_BIT 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_ON 1" >> include/config.h
- @echo "#define GPIO_WAN_LED_BIT 17" >> include/config.h
- @echo "#define GPIO_WAN_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN_LED_BIT 13" >> include/config.h
- @echo "#define GPIO_LAN_LED_ON 0" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_BIT 28" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_ON 1" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_IS_ACTIVE_LOW 1" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 16" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 16" >> include/config.h
@echo "#define WEBFAILSAFE_DISABLE_ART_UPGRADE 1" >> include/config.h
@echo "#define WEBFAILSAFE_DISABLE_UBOOT_UPGRADE 1" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for Village Telco Mesh Potato 2\"" >> include/config.h
-
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"Village Telco Mesh Potato 2\"" >> include/config.h
+
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
gl-inet_config : unconfig hornet_common_config
@/bin/echo -e '\e[32m> Configuring for GL.iNet at:' `date` '\e[0m'
@echo "#define CONFIG_FOR_GL_INET 1" >> include/config.h
- @echo "#define GPIO_WLAN_LED_BIT 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_ON 1" >> include/config.h
- @echo "#define GPIO_LAN_LED_BIT 13" >> include/config.h
- @echo "#define GPIO_LAN_LED_ON 1" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for GL.iNet\"" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 11" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"GL.iNet\"" >> include/config.h
@./mkconfig -a ap121 mips mips ap121 ar7240 ar7240
wasp_common_config : common_config
- @echo "#define CONFIG_AR7240 1" >> include/config.h
@echo "#define CONFIG_WASP 1" >> include/config.h
@echo "#define CONFIG_WASP_SUPPORT 1" >> include/config.h
wdr3600_43x0_config : unconfig wasp_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-WDR3600/43x0 at:' `date` '\e[0m'
+ @echo "#define SOC_TYPE QCA_AR9344_SOC" >> include/config.h
@echo "#define CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1 1" >> include/config.h
@echo "#define DDR2_32BIT_SUPPORT 1" >> include/config.h
@echo "#define CFG_ATHRS17_PHY 1" >> include/config.h
@echo "#define CFG_AG7240_NMACS 1" >> include/config.h
@echo "#define CFG_DUAL_PHY_SUPPORT 1" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 14" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_WLAN_2G_LED_BIT 13" >> include/config.h
- @echo "#define GPIO_WLAN_2G_LED_ON 0" >> include/config.h
- @echo "#define GPIO_USB1_LED_BIT 11" >> include/config.h
- @echo "#define GPIO_USB1_LED_ON 0" >> include/config.h
- @echo "#define GPIO_USB2_LED_BIT 12" >> include/config.h
- @echo "#define GPIO_USB2_LED_ON 0" >> include/config.h
- @echo "#define GPIO_QSS_LED_BIT 15" >> include/config.h
- @echo "#define GPIO_QSS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 16" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_IS_ACTIVE_LOW 1" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"DB120 (AR9344) U-Boot for TL-WDR3600/43x0\"" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 16" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-WDR3600/43x0\"" >> include/config.h
@./mkconfig -a db12x mips mips db12x ar7240 ar7240
wdr3500_config : unconfig wasp_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-WDR3500 at:' `date` '\e[0m'
+ @echo "#define SOC_TYPE QCA_AR9344_SOC" >> include/config.h
@echo "#define CONFIG_FOR_TPLINK_WDR3500_V1 1" >> include/config.h
@echo "#define DDR2_32BIT_SUPPORT 1" >> include/config.h
@echo "#define CFG_ATHRS27_PHY 1" >> include/config.h
@echo "#define CFG_AG7240_NMACS 2" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 14" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_WLAN_2G_LED_BIT 13" >> include/config.h
- @echo "#define GPIO_WLAN_2G_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN1_LED_BIT 19" >> include/config.h
- @echo "#define GPIO_LAN1_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN2_LED_BIT 20" >> include/config.h
- @echo "#define GPIO_LAN2_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN3_LED_BIT 21" >> include/config.h
- @echo "#define GPIO_LAN3_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN4_LED_BIT 22" >> include/config.h
- @echo "#define GPIO_LAN4_LED_ON 0" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_BIT 18" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_ON 0" >> include/config.h
- @echo "#define GPIO_QSS_LED_BIT 15" >> include/config.h
- @echo "#define GPIO_QSS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_USB_LED_BIT 11" >> include/config.h
- @echo "#define GPIO_USB_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 16" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_IS_ACTIVE_LOW 1" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"DB120 (AR9344) U-Boot for TL-WDR3500\"" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 16" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-WDR3500\"" >> include/config.h
@./mkconfig -a db12x mips mips db12x ar7240 ar7240
mr3420_v2_config : unconfig wasp_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-MR3420 v2 at:' `date` '\e[0m'
+ @echo "#define SOC_TYPE QCA_AR9341_SOC" >> include/config.h
@echo "#define CONFIG_FOR_TPLINK_MR3420_V2 1" >> include/config.h
@echo "#define CONFIG_AP123 1" >> include/config.h
@echo "#define DDR2_32BIT_SUPPORT 1" >> include/config.h
@echo "#define CFG_ATHRS27_PHY 1" >> include/config.h
@echo "#define CFG_AG7240_NMACS 2" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 14" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_BIT 13" >> include/config.h
- @echo "#define GPIO_WLAN_LED_ON 0" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_BIT 18" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN1_LED_BIT 19" >> include/config.h
- @echo "#define GPIO_LAN1_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN2_LED_BIT 20" >> include/config.h
- @echo "#define GPIO_LAN2_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN3_LED_BIT 21" >> include/config.h
- @echo "#define GPIO_LAN3_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN4_LED_BIT 12" >> include/config.h
- @echo "#define GPIO_LAN4_LED_ON 0" >> include/config.h
- @echo "#define GPIO_USB_LED_BIT 11" >> include/config.h
- @echo "#define GPIO_USB_LED_ON 0" >> include/config.h
- @echo "#define GPIO_QSS_LED_BIT 15" >> include/config.h
- @echo "#define GPIO_QSS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 17" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_IS_ACTIVE_LOW 1" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP123 (AR9341) U-Boot for TL-MR3420 v2\"" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 17" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-MR3420 v2\"" >> include/config.h
@./mkconfig -a db12x mips mips db12x ar7240 ar7240
wr841n_v8_config : unconfig wasp_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-WR841N/D v8 at:' `date` '\e[0m'
+ @echo "#define SOC_TYPE QCA_AR9341_SOC" >> include/config.h
@echo "#define CONFIG_FOR_TPLINK_WR841N_V8 1" >> include/config.h
@echo "#define CONFIG_AP123 1" >> include/config.h
@echo "#define DDR2_32BIT_SUPPORT 1" >> include/config.h
@echo "#define CFG_ATHRS27_PHY 1" >> include/config.h
@echo "#define CFG_AG7240_NMACS 2" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 14" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_BIT 13" >> include/config.h
- @echo "#define GPIO_WLAN_LED_ON 0" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_BIT 18" >> include/config.h
- @echo "#define GPIO_INTERNET_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN1_LED_BIT 19" >> include/config.h
- @echo "#define GPIO_LAN1_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN2_LED_BIT 20" >> include/config.h
- @echo "#define GPIO_LAN2_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN3_LED_BIT 21" >> include/config.h
- @echo "#define GPIO_LAN3_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN4_LED_BIT 12" >> include/config.h
- @echo "#define GPIO_LAN4_LED_ON 0" >> include/config.h
- @echo "#define GPIO_QSS_LED_BIT 15" >> include/config.h
- @echo "#define GPIO_QSS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 17" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_IS_ACTIVE_LOW 1" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP123 (AR9341) U-Boot for TL-WR841N/D v8\"" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 17" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-WR841N/D v8\"" >> include/config.h
@./mkconfig -a db12x mips mips db12x ar7240 ar7240
wa830re_v2_wa801nd_v2_config : unconfig wasp_common_config
@/bin/echo -e '\e[32m> Configuring for TP-Link TL-WA830RE/TL-WA801ND v2 at:' `date` '\e[0m'
+ @echo "#define SOC_TYPE QCA_AR9341_SOC" >> include/config.h
@echo "#define CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2 1" >> include/config.h
@echo "#define CONFIG_AP123 1" >> include/config.h
@echo "#define DDR2_32BIT_SUPPORT 1" >> include/config.h
@echo "#define CFG_ATHRS27_PHY 1" >> include/config.h
@echo "#define CFG_AG7240_NMACS 2" >> include/config.h
- @echo "#define GPIO_SYS_LED_BIT 14" >> include/config.h
- @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_LAN_LED_BIT 18" >> include/config.h
- @echo "#define GPIO_LAN_LED_ON 0" >> include/config.h
- @echo "#define GPIO_WLAN_LED_BIT 13" >> include/config.h
- @echo "#define GPIO_WLAN_LED_ON 0" >> include/config.h
- @echo "#define GPIO_QSS_LED_BIT 15" >> include/config.h
- @echo "#define GPIO_QSS_LED_ON 0" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_BIT 17" >> include/config.h
- @echo "#define GPIO_RST_BUTTON_IS_ACTIVE_LOW 1" >> include/config.h
- @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
- @echo "#define BOARD_CUSTOM_STRING \"AP123 (AR9341) U-Boot for TL-WA830RE/TL-WA801ND v2\"" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 17" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-WA830RE/TL-WA801ND v2\"" >> include/config.h
@./mkconfig -a db12x mips mips db12x ar7240 ar7240
+ap143_common_config : common_config
+ @echo "#define CONFIG_ATHEROS 1" >> include/config.h
+ @echo "#define CONFIG_MACH_QCA953x 1" >> include/config.h
+
+wr820n_CN_config : unconfig ap143_common_config
+ @/bin/echo -e '\e[32m> Configuring for TP-Link TL-WR820N CN at:' `date` '\e[0m'
+ @echo "#define SOC_TYPE QCA_QCA953X_SOC" >> include/config.h
+ @echo "#define CONFIG_FOR_TPLINK_WR820N_CN 1" >> include/config.h
+ @echo "#define CFG_ATHRS27_PHY 1" >> include/config.h
+ @echo "#define CFG_ATH_GMAC_NMACS 2" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 12" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-WR820N CN\"" >> include/config.h
+
+ @./mkconfig -a ap143 mips mips ap143 ar7240 ar7240
+
+wr802n_config : unconfig ap143_common_config
+ @/bin/echo -e '\e[32m> Configuring for TP-Link TL-WR802N at:' `date` '\e[0m'
+ @echo "#define SOC_TYPE QCA_QCA953X_SOC" >> include/config.h
+ @echo "#define CONFIG_FOR_TPLINK_WR802N 1" >> include/config.h
+ @echo "#define CFG_ATHRS27_PHY 1" >> include/config.h
+ @echo "#define CFG_ATH_GMAC_NMACS 2" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 12" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-WR802N\"" >> include/config.h
+
+ @./mkconfig -a ap143 mips mips ap143 ar7240 ar7240
+
+wr841n_v9_config : unconfig ap143_common_config
+ @/bin/echo -e '\e[32m> Configuring for TP-Link TL-WR841N/D v9 at:' `date` '\e[0m'
+ @echo "#define SOC_TYPE QCA_QCA953X_SOC" >> include/config.h
+ @echo "#define CONFIG_FOR_TPLINK_WR841N_V9 1" >> include/config.h
+ @echo "#define CFG_ATHRS27_PHY 1" >> include/config.h
+ @echo "#define CFG_ATH_GMAC_NMACS 2" >> include/config.h
+ @echo "#define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN 12" >> include/config.h
+ @echo "#define CONFIG_GPIO_RESET_BTN_ACTIVE_LOW 1" >> include/config.h
+ @echo "#define CONFIG_TPLINK_IMAGE_HEADER 1" >> include/config.h
+ @echo "#define CONFIG_BOARD_CUSTOM_STRING \"TP-Link TL-WR841N/D v9\"" >> include/config.h
+
+ @./mkconfig -a ap143 mips mips ap143 ar7240 ar7240
+
#########################################################################
#########################################################################
#########################################################################
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o ../common/ar7240_flash.o ../common/ar7240_s26_phy.o
-SOBJS = ../common/lowlevel_init.o
-
-ifeq ($(BOARD), ap121)
-SOBJS += hornet_pll_init.o
-endif
+OBJS = $(BOARD).o ../common/spi_flash.o ../common/ar7240_s26_phy.o ../common/common.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
+/*
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
#include <common.h>
-#include <command.h>
-#include <asm/mipsregs.h>
#include <asm/addrspace.h>
-#include <config.h>
-#include <version.h>
-#include "ar7240_soc.h"
-
-#if !defined(COMPRESSED_UBOOT)
-extern void hornet_ddr_init(void);
-#endif
-
-extern int ar7240_ddr_find_size(void);
-extern void hornet_ddr_tap_init(void);
-
-#define SETBITVAL(val, pos, bit) do {ulong bitval = (bit) ? 0x1 : 0x0; (val) = ((val) & ~(0x1 << (pos))) | ( (bitval) << (pos));} while(0)
-
-void led_toggle(void){
- unsigned int gpio;
-
- gpio = ar7240_reg_rd(AR7240_GPIO_OUT);
-
-#if defined(CONFIG_FOR_TPLINK_MR3020_V1)
- gpio ^= 1 << GPIO_WPS_LED_BIT;
-#elif defined(CONFIG_FOR_TPLINK_WR703N_V1) || defined(CONFIG_FOR_TPLINK_WR720N_V3) || defined(CONFIG_FOR_TPLINK_WR710N_V1)
- gpio ^= 1 << GPIO_SYS_LED_BIT;
-#elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2)
- gpio ^= 1 << GPIO_INTERNET_LED_BIT;
-#elif defined(CONFIG_FOR_TPLINK_MR10U_V1) || defined(CONFIG_FOR_TPLINK_MR13U_V1)
- gpio ^= 1 << GPIO_SYS_LED_BIT;
-#elif defined(CONFIG_FOR_TPLINK_WR740N_V4) || defined(CONFIG_FOR_TPLINK_MR3220_V2)
- gpio ^= 1 << GPIO_SYS_LED_BIT;
-#elif defined(CONFIG_FOR_DLINK_DIR505_A1)
- gpio ^= 1 << GPIO_SYS_LED_BIT;
-#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
- gpio ^= 1 << GPIO_SYS_LED_BIT;
-#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
- gpio ^= 1 << GPIO_WLAN_LED_BIT;
-#elif defined(CONFIG_FOR_DRAGINO_V2) || defined(CONFIG_FOR_MESH_POTATO_V2)
- gpio ^= 1 << GPIO_WLAN_LED_BIT;
-#elif defined(CONFIG_FOR_GL_INET)
- gpio ^= 1 << GPIO_WLAN_LED_BIT;
-#else
- #error "Custom GPIO in leg_toggle() not defined!"
-#endif
-
- ar7240_reg_wr(AR7240_GPIO_OUT, gpio);
-}
-
-void all_led_on(void){
- unsigned int gpio;
-
- gpio = ar7240_reg_rd(AR7240_GPIO_OUT);
-
-#if defined(CONFIG_FOR_TPLINK_MR3020_V1)
- SETBITVAL(gpio, GPIO_WPS_LED_BIT, GPIO_WPS_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_ETH_LED_BIT, GPIO_ETH_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_WR703N_V1) || defined(CONFIG_FOR_TPLINK_WR720N_V3) || defined (CONFIG_FOR_TPLINK_WR710N_V1)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2)
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_ETH_LED_BIT, GPIO_ETH_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_MR10U_V1) || defined(CONFIG_FOR_TPLINK_MR13U_V1)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_WR740N_V4) || defined(CONFIG_FOR_TPLINK_MR3220_V2)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_LAN1_LED_BIT, GPIO_LAN1_LED_ON);
- SETBITVAL(gpio, GPIO_LAN2_LED_BIT, GPIO_LAN2_LED_ON);
- SETBITVAL(gpio, GPIO_LAN3_LED_BIT, GPIO_LAN3_LED_ON);
- SETBITVAL(gpio, GPIO_LAN4_LED_BIT, GPIO_LAN4_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_QSS_LED_BIT, GPIO_QSS_LED_ON);
-
- #ifdef CONFIG_FOR_TPLINK_MR3220_V2
- SETBITVAL(gpio, GPIO_USB_LED_BIT, GPIO_USB_LED_ON);
- #endif
-#elif defined(CONFIG_FOR_DLINK_DIR505_A1)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
-#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WAN_LED_BIT, GPIO_WAN_LED_ON);
- SETBITVAL(gpio, GPIO_LAN1_LED_BIT, GPIO_LAN1_LED_ON);
- SETBITVAL(gpio, GPIO_LAN2_LED_BIT, GPIO_LAN2_LED_ON);
-#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
-#elif defined(CONFIG_FOR_DRAGINO_V2) || defined(CONFIG_FOR_MESH_POTATO_V2)
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_WAN_LED_BIT, GPIO_WAN_LED_ON);
- SETBITVAL(gpio, GPIO_LAN_LED_BIT, GPIO_LAN_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
-#elif defined(CONFIG_FOR_GL_INET)
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_LAN_LED_BIT, GPIO_LAN_LED_ON);
-#else
- #error "Custom GPIO in all_led_on() not defined!"
-#endif
-
- ar7240_reg_wr(AR7240_GPIO_OUT, gpio);
-}
-
-void all_led_off(void){
- unsigned int gpio;
-
- gpio = ar7240_reg_rd(AR7240_GPIO_OUT);
-
-#if defined(CONFIG_FOR_TPLINK_MR3020_V1)
- SETBITVAL(gpio, GPIO_WPS_LED_BIT, !GPIO_WPS_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, !GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_ETH_LED_BIT, !GPIO_ETH_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_WR703N_V1) || defined(CONFIG_FOR_TPLINK_WR720N_V3) || defined (CONFIG_FOR_TPLINK_WR710N_V1)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2)
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, !GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_ETH_LED_BIT, !GPIO_ETH_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_MR10U_V1) || defined(CONFIG_FOR_TPLINK_MR13U_V1)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_WR740N_V4) || defined(CONFIG_FOR_TPLINK_MR3220_V2)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_LAN1_LED_BIT, !GPIO_LAN1_LED_ON);
- SETBITVAL(gpio, GPIO_LAN2_LED_BIT, !GPIO_LAN2_LED_ON);
- SETBITVAL(gpio, GPIO_LAN3_LED_BIT, !GPIO_LAN3_LED_ON);
- SETBITVAL(gpio, GPIO_LAN4_LED_BIT, !GPIO_LAN4_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, !GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_QSS_LED_BIT, !GPIO_QSS_LED_ON);
-
- #ifdef CONFIG_FOR_TPLINK_MR3220_V2
- SETBITVAL(gpio, GPIO_USB_LED_BIT, !GPIO_USB_LED_ON);
- #endif
-#elif defined(CONFIG_FOR_DLINK_DIR505_A1)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON);
-#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WAN_LED_BIT, !GPIO_WAN_LED_ON);
- SETBITVAL(gpio, GPIO_LAN1_LED_BIT, !GPIO_LAN1_LED_ON);
- SETBITVAL(gpio, GPIO_LAN2_LED_BIT, !GPIO_LAN2_LED_ON);
-#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON);
-#elif defined(CONFIG_FOR_DRAGINO_V2) || defined(CONFIG_FOR_MESH_POTATO_V2)
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_WAN_LED_BIT, !GPIO_WAN_LED_ON);
- SETBITVAL(gpio, GPIO_LAN_LED_BIT, !GPIO_LAN_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, !GPIO_INTERNET_LED_ON);
-#elif defined(CONFIG_FOR_GL_INET)
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_LAN_LED_BIT, !GPIO_LAN_LED_ON);
-#else
- #error "Custom GPIO in all_led_off() not defined!"
-#endif
-
- ar7240_reg_wr(AR7240_GPIO_OUT, gpio);
-}
-
-// get button status
-#ifndef GPIO_RST_BUTTON_BIT
- #error "GPIO_RST_BUTTON_BIT not defined!"
-#endif
-int reset_button_status(void){
- unsigned int gpio;
-
- gpio = ar7240_reg_rd(AR7240_GPIO_IN);
-
- if(gpio & (1 << GPIO_RST_BUTTON_BIT)){
-#if defined(GPIO_RST_BUTTON_IS_ACTIVE_LOW)
- return(0);
-#else
- return(1);
-#endif
- } else {
-#if defined(GPIO_RST_BUTTON_IS_ACTIVE_LOW)
- return(1);
-#else
- return(0);
-#endif
- }
-}
-
-void gpio_config(void){
-#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
- /* Disable clock obs
- * clk_obs1(gpio13/bit8), clk_obs2(gpio14/bit9), clk_obs3(gpio15/bit10),
- * clk_obs4(gpio16/bit11), clk_obs5(gpio17/bit12)
- * clk_obs0(gpio1/bit19), 6(gpio11/bit20)
- */
- ar7240_reg_wr(AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & ~((0x1f<<8)|(0x3<<19))));
-
-
- /* Enable eth Switch LEDs */
- ar7240_reg_wr(AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | (0x1f<<3)));
-
-
- //Turn on status leds:
- //set output enable
- ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) |(1<<0)));
-
- //set WLAN LED output to low (reverse polarity LED)
- //ar7240_reg_wr(AR7240_GPIO_CLEAR, (1<<0));
-
- /* Clear AR7240_GPIO_FUNC BIT2 to ensure that software can control LED5(GPIO16) and LED6(GPIO17) */
- ar7240_reg_wr(AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & ~(0x1<<2)));
-#else
- /* Disable clock obs
- * clk_obs1(gpio13/bit8), clk_obs2(gpio14/bit9), clk_obs3(gpio15/bit10),
- * clk_obs4(gpio16/bit11), clk_obs5(gpio17/bit12)
- * clk_obs0(gpio1/bit19), 6(gpio11/bit20)
- */
-
- ar7240_reg_wr(AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xEF84E0FB));
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- /* Disable EJTAG functionality to enable GPIO functionality */
- ar7240_reg_wr(AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | 0x8001));
-#endif
-
- /* Set HORNET_BOOTSTRAP_STATUS BIT18 to ensure that software can control GPIO26 and GPIO27 */
- ar7240_reg_wr(HORNET_BOOTSTRAP_STATUS, (ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) | (0x1<<18)));
-#endif
-
-#if defined(CONFIG_FOR_TPLINK_MR3020_V1)
-
- /* LED's GPIOs on MR3020:
- *
- * 0 => WLAN
- * 17 => ETH
- * 26 => WPS
- * 27 => INTERNET
- *
- */
-
- /* set OE, added by zcf, 20110509 */
- ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xC020001));
-
- /* Disable clock obs, added by zcf, 20110509 */
- //ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e07f));
-#elif defined(CONFIG_FOR_TPLINK_WR703N_V1) || defined(CONFIG_FOR_TPLINK_WR720N_V3) || defined(CONFIG_FOR_TPLINK_WR710N_V1)
+#include <soc/qca_soc_common.h>
- /* LED's GPIOs on WR703N/WR720Nv3/WR710N:
- *
- * 27 => SYS
- *
- */
-
- /* set OE, added by zcf, 20110714 */
- ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0x8000000));
-#elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2)
-
- /* LED's GPIOs on MR3040:
- *
- * 26 => WLAN
- * 17 => ETH
- * 27 => INTERNET
- *
- */
-
- /* set OE, added by zcf, 20110509 */
- ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xC020000));
-
- /* Disable clock obs, added by zcf, 20110509 */
- //ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e07f));
-#elif defined(CONFIG_FOR_TPLINK_MR10U_V1) || defined(CONFIG_FOR_TPLINK_MR13U_V1)
-
- /* LED's GPIOs on MR10U/MR13U:
- *
- * 27 => SYS
- *
- */
-
- /* set OE, added by zcf, 20110714 */
- ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0x8000000));
-#elif defined(CONFIG_FOR_TPLINK_WR740N_V4)
-
- /* LED's GPIOs on WR740Nv4:
- *
- * 0 => WLAN
- * 1 => QSS
- * 13 => INTERNET
- * 14 => LAN1
- * 15 => LAN2
- * 16 => LAN3
- * 17 => LAN4
- * 27 => SYS
- *
- */
-
- /* set OE, added by zcf, 20110509 */
- ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0x803E003));
-
- /* Disable clock obs, added by zcf, 20110509 */
- //ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e07f));
-#elif defined(CONFIG_FOR_TPLINK_MR3220_V2)
-
- /* LED's GPIOs on MR3220v2:
- *
- * 0 => WLAN
- * 1 => QSS
- * 13 => INTERNET
- * 14 => LAN1
- * 15 => LAN2
- * 16 => LAN3
- * 17 => LAN4
- * 26 => USB
- * 27 => SYS
- *
- */
-
- /* set OE, added by zcf, 20110509 */
- ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xC03E003));
-
- /* Disable clock obs, added by zcf, 20110509 */
- //ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e07f));
-#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
- // TODO: check GPIO config for C2
-#elif defined(CONFIG_FOR_DRAGINO_V2) || defined(CONFIG_FOR_MESH_POTATO_V2)
-
- /* LED's GPIOs on MR3220v2:
- *
- * 0 => WLAN
- * 13 => LAN
- * 17 => WAN
- * 28 => INTERNET
- *
- */
-
- /* set GPIO_OE */
- ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0x10022001));
-
-#elif defined(CONFIG_FOR_DLINK_DIR505_A1)
-
- /* LED's GPIOs on DIR-505:
- *
- * 26 => RED LED
- * 27 => GREEN LED
- *
- */
-
- // set GPIO_OE
- ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xC000000));
-
- // turn off RED LED, we don't need it
- ar7240_reg_wr(AR7240_GPIO_OUT, (ar7240_reg_rd(AR7240_GPIO_OUT) | (0x1 << 26)));
-#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
-
- /* LED's GPIOs on GS-Oolite v1 with development board:
- *
- * 13 => LAN2
- * 15 => LAN1
- * 17 => WAN
- * 27 => SYS LED (green on dev board, red on module)
- *
- * I/O on development board:
- * 0 => RED LED (active low)
- * 1 => RED LED (active low)
- * 6 => Switch 8
- * 7 => Switch 7
- * 8 => USB power
- * 11 => Reset switch
- * 14 => RED LED (active low)
- * 16 => RED LED (active low)
- * 18 => RED LED (active low)
- * 19 => RED LED (active low)
- * 20 => RED LED (active low)
- * 21 => RED LED (active low)
- * 22 => RED LED (active low)
- * 23 => Relay 1
- * 24 => Relay 2
- * 26 => RED LED (active low)
- *
- */
-
- // set GPIO_OE
- ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xDFFE103));
-
- // turn on power on USB and turn off RED LEDs
- ar7240_reg_wr(AR7240_GPIO_SET, 0x47D4103);
-#elif defined(CONFIG_FOR_GL_INET)
-
- /* LED's GPIOs on GL.iNet:
- *
- * 0 => WLAN
- * 13 => LAN
- *
- */
-
- /* set GPIO_OE */
- ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0x2001));
-
-#else
- #error "Custom GPIO config in gpio_config() not defined!"
-#endif
-}
-
-int ar7240_mem_config(void){
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- #ifndef COMPRESSED_UBOOT
- hornet_ddr_init();
- #endif
-
- /* Default tap values for starting the tap_init*/
- ar7240_reg_wr(AR7240_DDR_TAP_CONTROL0, CFG_DDR_TAP0_VAL);
- ar7240_reg_wr(AR7240_DDR_TAP_CONTROL1, CFG_DDR_TAP1_VAL);
-#endif
-
- gpio_config();
- all_led_off();
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- hornet_ddr_tap_init();
-#endif
-
- // return memory size
- return(ar7240_ddr_find_size());
-}
-
-long int initdram(){
- return((long int)ar7240_mem_config());
-}
-
-#ifndef COMPRESSED_UBOOT
-int checkboard(void){
- printf(BOARD_CUSTOM_STRING"\n\n");
- return(0);
-}
-#endif
-
-/*
- * Returns a string with memory type preceded by a space sign
- */
-const char* print_mem_type(void){
/*
- * WR720N v3 (CH version) has wrong bootstrap configuration,
- * so the memory type cannot be recognized automatically
+ * DRAM init
*/
-#if defined(CONFIG_FOR_TPLINK_WR720N_V3)
- return " DDR 16-bit";
-#else
- unsigned int reg_val;
-
- reg_val = (ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & HORNET_BOOTSTRAP_MEM_TYPE_MASK) >> HORNET_BOOTSTRAP_MEM_TYPE_SHIFT;
-
- switch(reg_val){
- case 0:
- return " SDRAM";
- break;
-
- case 1:
- return " DDR 16-bit";
- break;
-
- case 2:
- return " DDR2 16-bit";
- break;
+long int dram_init()
+{
+ qca_dram_init();
- default:
- return "";
- break;
- }
-#endif /* defined(CONFIG_FOR_TPLINK_WR720N_V3) */
+ return (long int)qca_dram_size();
}
+++ /dev/null
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <ar7240_soc.h>
-
- .globl hornet_pll_init
- .text
- .align 4
-
-#define CLEAR_BIT(val, bit) ((val) & ~(1 << (bit)))
-#define SET_BIT(val, bit) ((val) | (1 << (bit)))
-
-#define CLEAR_PLL_POWER_DOWN(reg_val) CLEAR_BIT(reg_val, 30)
-#define SET_PLL_POWER_DOWN(reg_val) SET_BIT(reg_val, 30)
-#define SET_AHB_DIV_TO_4(reg_val) SET_BIT(SET_BIT(reg_val, 15), 16)
-#define CLEAR_PLL_BYPASS(reg_val) CLEAR_BIT(reg_val, 2)
-#define SET_PLL_BYPASS(reg_val) SET_BIT(reg_val, 2)
-
-/*
- * Helper macros.
- * These Clobber t7, t8 and t9
- * or t8, t8, t9;
- */
-#define set_reg(_reg, _val) \
- li t7, KSEG1ADDR(_reg); \
- lw t8, 0(t7); \
- li t9, _val; \
- sw t9, 0(t7);
-
-/* if reset button is active low -> use bne (branch on not equal) */
-#ifdef GPIO_RST_BUTTON_IS_ACTIVE_LOW
- #define recovery_jump(_branch) \
- bne t1, (1 << GPIO_RST_BUTTON_BIT), _branch;
-#else
- #define recovery_jump(_branch) \
- beq t1, (1 << GPIO_RST_BUTTON_BIT), _branch;
-#endif
-
-hornet_pll_init:
-
-#if 1
-/* These three wlan reset will avoid original issue,
- * so full chip reset isn't needed here.
- *
- * WLAN_RESET in RST_RESET (AR7240_RESET) register
- * 0x00C06B30 -> BIT(11) is set
- * 0x00C06330 -> BIT(11) is not set
- */
- set_reg(AR7240_RESET, 0x00C06B30)
- nop
- set_reg(AR7240_RESET, 0x00C06330)
- nop
- set_reg(AR7240_RESET, 0x00C06B30)
- nop
- set_reg(AR7240_RESET, 0x00C06330)
- nop
-
-reset_wlan:
- set_reg(AR7240_RESET, 0x00C06B30)
- nop
- set_reg(AR7240_RESET, 0x00C06330)
- nop
- li t5, 0x20
-
-check_val:
- beq zero, t5, reset_wlan
- addi t5, t5, -1
- li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS)
- lw t7, 0(t6)
- li t8, 0x10
- and t7, t7, t8
- bne zero, t7, check_val
- set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110E)
- nop
-#else
-/* clear wlan reset bit in RESET_Register 0x1c */
- set_reg(AR7240_RESET, 0x00C06B30)
- nop
- set_reg(AR7240_RESET, 0x00C06330)
- nop
-
-/* cleck bootstrap status, wait for bit4 on, then clear bit16 */
-wait_loop0:
- li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS)
- lw t7, 0(t6)
- li t8, 0x10
- and t7, t7, t8
- bne zero, t7, wait_loop0
- nop
- set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110E)
- nop
-#endif
-
-/* RTC reset */
-/* 0x1810704C -> RTC_FORCE_WAKE (RTC Force Wake) */
- set_reg(0x1810704C, 0x00000003)
- nop
- nop
-/* 0x18107040 -> RTC_RESET (RTC Reset and Force Sleep and Force Wakeup) */
- set_reg(0x18107040, 0x00000000)
- nop
- nop
- set_reg(0x18107040, 0x00000001)
- nop
-
-wait_loop1:
-/* 0x18107044 -> RTC_STATUS (RTC Sleep Status) */
- li t6, KSEG1ADDR(0x18107044)
- lw t7, 0(t6)
- li t8, 0x2
- and t7, t7, t8
- bne t8, t7, wait_loop1
- nop
-
-/*
- * AHB/APH reset
- * TODO: 0x18104000 is "Reset the Host Interface (HOST_INTF_RESET_CONTROL)" and bits 0:7 are RESERVED!
- */
-/*
- set_reg(0x18104000, 0x00000003)
- nop
- set_reg(0x18104000, 0x00000000)
- nop
-*/
-/*
- * MAC reset (TODO: ?? AR9344 has 0x18107000 register -> AR9344_RTC_BASE)
- */
-/*
- set_reg(0x18107000, 0x0000000F)
- nop
- set_reg(0x18107000, 0x00000000)
- nop
-*/
-
-#if 1 /* fetch pmu1.refv and ctrl2.tx from OTP */
- li t1, KSEG1ADDR(0x18114014)
- lw t2, 0(t1)
-
-otp_loop0:
- li t3, KSEG1ADDR(0x18115F18)
- lw t4, 0(t3)
- nop
- li t5, 0x7
- and t4, t4, t5
- li t5, 0x4
- bne t4, t5, otp_loop0
- nop
- li t6, KSEG1ADDR(0x18115F1C)
- lw t7, 0(t6)
- nop
- li t8, 0x80000080
- and t9, t7, t8
- beq t8, t9, fetch_otp
-
-otp_loop0_end:
- li t1, KSEG1ADDR(0x18114004)
- lw t2, 0(t1)
-
-otp_loop1:
- li t3, KSEG1ADDR(0x18115F18)
- lw t4, 0(t3)
- nop
- li t5, 0x7
- and t4, t4, t5
- li t5, 0x4
- bne t4, t5, otp_loop1
- nop
- li t6, KSEG1ADDR(0x18115F1C)
- lw t7, 0(t6)
- nop
- li t8, 0x80000080
- and t9, t7, t8
-
-default_pmu:
- li t5, 0x80 /* default 0x031c4386 */
- bne t8, t9, otp_end
-
-fetch_otp:
- srl t8, t7, 0x18
- li t1, 0xf
- and t2, t1, t7 /* USB */
- and t5, t1, t8 /* PMU */
-
-check_pmu:
- li t0, 0x4 /* PMU range should be 0x4~0xa */
- bgt t0, t5, default_pmu
- nop
- li t0, 0xa /* PMU range should be 0x4~0xa */
- blt t0, t5, default_pmu
- nop
- li t0, 0x4
- sll t5, t5, t0
-
-otp_end:
-#endif
-
-#if 1 /* Program PMU */
-#define PMU_TEST_NO 1000
- li t6, KSEG1ADDR(0x18116C40)
- li t9, 0xbd000010
- li t0, 0
- li t1, 0
- li t2, 0
- li t3, PMU_TEST_NO
- sw t3, 12(t9)
-
-pmu_loop0:
- beq zero, t3, pmu_loop0_end
- nop
- addi t3, t3, -1
- li t7, 0x10180000 /* ldo_tune 0x3 */
- nop
- sw t7, 4(t6)
- nop
- lw t8, 4(t6)
- nop
- beq t8, t7, pmu_loop0_end
- nop
- addiu t0, t0, 1
- b pmu_loop0
- nop
-
-pmu_loop0_end:
- li t3, PMU_TEST_NO
-
-pmu_loop1:
- beq zero, t3, pmu_loop1_end
- nop
- addi t3, t3, -1
- //li t7, 0x031c4326 /* 1.100V */
- //li t7, 0x031c4336 /* 1.125V */
- //li t7, 0x031c4346 /* 1.150V */
- //li t7, 0x031c4356 /* 1.175V */
- //li t7, 0x031c4366 /* 1.200V */
- //li t7, 0x031c4376 /* 1.225V */
- li t7, 0x031c4386 /* 1.250V (DEFAULT) */
- //li t7, 0x031c4396 /* 1.275V */
- //li t7, 0x031c43a6 /* 1.300V */
- nop
-
-#if 1 /* from OTP */
- li t8, 0xFFFFFF0F
- and t7, t7, t8
- or t7, t7, t5
-#endif
- sw t7, 0(t6)
- nop
- lw t8, 0(t6)
- nop
- beq t8, t7, pmu_loop1_end
- nop
- addiu t1, t1, 1
- b pmu_loop1
- nop
-
-pmu_loop1_end:
- li t3, PMU_TEST_NO
-
-pmu_loop2:
- beq zero, t3, pmu_loop2_end
- nop
- addi t3, t3, -1
- li t7, 0x10380000 /* ldo_tune 0x3 */
- nop
- sw t7, 4(t6)
- nop
- lw t8, 4(t6)
- nop
- beq t8, t7, pmu_loop2_end
- nop
- addiu t2, t2, 1
- b pmu_loop2
- nop
-
-pmu_loop2_end:
- sw t0, 0(t9)
- nop
- sw t1, 4(t9)
- nop
- sw t2, 8(t9)
- nop
-#endif
-
-#if 1 /* Program ki, kd */
-// TODO: ??
-/* Program ki/kd */
-#if CONFIG_40MHZ_XTAL_SUPPORT
- set_reg(0x18116244, 0x19e82f01)
-#else
- set_reg(0x18116244, 0x18e82f01)
-#endif
- nop
-
-/* Program phase shift */
- li t6, KSEG1ADDR(0x18116248)
- lw t7, 0(t6)
- li t8, 0xc07fffff
- and t7, t7, t8
- li t8, 0x800000
- or t7, t7, t8
- sw t7, 0(t6)
- nop
-#endif
-
-/* max AHB Master wait time out ... */
- set_reg(0x1800009C, 0xfffff)
- nop
-
-/*
- * O/C recovery mode
- *
- * If RESET BUTTON is pressed and hold during power on
- * we will use default PLL and clocks configuration (400/400/200)
- *
- * Using t0 and t1 (t1 indicates if recovery mode was turned on)
- */
-pll_clock_control_oc_recovery:
- li t0, KSEG1ADDR(AR7240_GPIO_IN)
- lw t1, 0(t0)
- and t1, t1, (1 << GPIO_RST_BUTTON_BIT)
- recovery_jump(pll_clock_control_default)
- nop
-
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
-/*
- * PLL and CLOCK configuration from FLASH
- *
- * Using t0, t2 and t3 (t2 stores magic value from flash)
- */
-pll_clock_control_flash:
- li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
- lw t2, 0(t0) // load PLL_IN_FLASH_MAGIC value from FLASH
- bne t2, PLL_IN_FLASH_MAGIC, pll_clock_control // jump if we don't have PLL_MAGIC value in FLASH
- nop
- lw t3, 8(t0) // load CLOCK_CONTROL register value from FLASH
- or t3, t3, 0x18004 // set BYPASS bit and make AHB_POST_DIV = 4
- li t0, KSEG1ADDR(AR7240_CPU_CLOCK_CONTROL) // load CLOCK_CONTROL register address
- sw t3, 0(t0) // store value in CLOCK_CONTROL register
- j pll_settle_time // jump to pll_settle_time
- nop
-#endif
-
-pll_clock_control:
-/* set PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */
-/* in some cases, the SoC doesn't start with higher clock on AHB */
- set_reg(AR7240_CPU_CLOCK_CONTROL, SET_AHB_DIV_TO_4(SET_PLL_BYPASS(CPU_CLK_CONTROL_VAL)))
- j pll_settle_time
- nop
-
-pll_clock_control_default:
-/* set PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */
-/* in some cases, the SoC doesn't start with higher clock on AHB */
- set_reg(AR7240_CPU_CLOCK_CONTROL, SET_AHB_DIV_TO_4(SET_PLL_BYPASS(CPU_CLK_CONTROL_VAL_DEFAULT)))
- nop
-
-pll_settle_time:
-/* set SETTLE_TIME in CPU PLL */
- set_reg(AR7240_USB_PLL_CONFIG, CPU_PLL_SETTLE_TIME_VAL)
- nop
-
-pll_unlock_handler_oc_recovery:
- recovery_jump(pll_unlock_handler_default)
- nop
-
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
-pll_unlock_handler_flash:
- bne t2, PLL_IN_FLASH_MAGIC, pll_unlock_handler // jump if we don't have PLL_MAGIC value in FLASH
- nop
- li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
- lw t3, 4(t0) // load CPU_PLL_CONFIG register value from FLASH
- or t3, t3, 0x40000000 // set CPU_PLLPWD bit (power down for CPU PLL)
- li t0, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) // load CPU_PLL_CONFIG register address
- sw t3, 0(t0) // store value in CPU_PLL_CONFIG register
- j wait_loop2 // jump to wait_loop2
- nop
-#endif
-
-pll_unlock_handler:
-/* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */
- set_reg(AR7240_CPU_PLL_CONFIG, SET_PLL_POWER_DOWN(CPU_PLL_CONFIG_VAL))
- j wait_loop2
- nop
-
-pll_unlock_handler_default:
-/* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */
- set_reg(AR7240_CPU_PLL_CONFIG, SET_PLL_POWER_DOWN(CPU_PLL_CONFIG_VAL_DEFAULT))
- nop
-
-wait_loop2:
- li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG)
- lw t7, 0(t6)
- li t8, 0x80000000
- and t7, t7, t8
- bne zero, t7, wait_loop2
- nop
-
-/* put frac bit19:10 configuration */
-/* TODO: do we need this? */
- set_reg(AR7240_PCIE_PLL_CONFIG, CPU_PLL_DITHER_FRAC_VAL)
- nop
-
-pll_lock_handler_oc_recovery:
- recovery_jump(pll_lock_handler_default)
- nop
-
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
-pll_lock_handler_flash:
- bne t2, PLL_IN_FLASH_MAGIC, pll_lock_handler // jump if we don't have PLL_MAGIC value in FLASH
- nop
- li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
- lw t3, 4(t0) // load CPU_PLL_CONFIG register value from FLASH
- li t0, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) // load CPU_PLL_CONFIG register address
- sw t3, 0(t0) // store value in CPU_PLL_CONFIG register
- j wait_loop3 // jump to wait_loop3
- nop
-#endif
-
-pll_lock_handler:
-/* clear PLL power down bit in CPU PLL configuration */
- set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL)
- j wait_loop3
- nop
-
-pll_lock_handler_default:
-/* clear PLL power down bit in CPU PLL configuration */
- set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL_DEFAULT)
- nop
-
-wait_loop3:
-/* wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
- li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG)
- lw t7, 0(t6)
- li t8, 0x80000000
- and t7, t7, t8
- bne zero, t7, wait_loop3
- nop
-
-/* confirm DDR PLL lock */
- li t3, 100
- li t4, 0
-
-start_meas0:
- addi t4, t4, 1
- bgt t4, t3, pll_unlock_handler_oc_recovery
- nop
- li t5, 5
-
-start_meas:
- li t6, KSEG1ADDR(0x18116248)
- lw t7, 0(t6)
- li t8, 0xBFFFFFFF
- and t7, t7, t8
- sw t7, 0(t6)
- nop
-
-/* delay */
- li t9, 10
-
-delayloop0:
- subu t9, t9, 1
- bne t9, zero, delayloop0
- nop
- li t8, 0x40000000
- or t7, t7, t8
- sw t7, 0(t6)
- nop
-
-meas_done_statue:
- li t6, KSEG1ADDR(0x1811624C)
- lw t7, 0(t6)
- li t8, 0x8
- and t7, t7, t8
- beq zero, t7, meas_done_statue
- nop
-
-meas_result:
- li t6, KSEG1ADDR(0x18116248)
- lw t7, 0(t6)
- li t8, 0x007FFFF8
- and t7, t7, t8
- srl t7, t7, 3
- li t8, 0x4000
- bgt t7, t8, start_meas0
- nop
- addi t5, t5, -1
- bne zero, t5, start_meas
- nop
-
-pll_clear_bypass_oc_recovery:
- recovery_jump(pll_clear_bypass_default)
- nop
-
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
-pll_clear_bypass_flash:
- bne t2, PLL_IN_FLASH_MAGIC, pll_clear_bypass // jump if we don't have PLL_MAGIC value in FLASH
- nop
- li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address
- lw t3, 8(t0) // load CLOCK_CONTROL register value from FLASH
- li t0, KSEG1ADDR(AR7240_CPU_CLOCK_CONTROL) // load CLOCK_CONTROL register address
- sw t3, 0(t0) // store value in CLOCK_CONTROL register
- j end // jump to end
- nop
-#endif
-
-pll_clear_bypass:
-/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
- set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL)
- j end
- nop
-
-pll_clear_bypass_default:
-/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
- set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL_DEFAULT)
- nop
-
-/* Sync mode, Set Bit 8 of DDR Tap Conrtol 3 register */
-/*
- * TODO: something is wrong here?
- * There is no AR7240_DDR_TAP_CONTROL3 in AR9331 datasheet!
- */
-/*
- set_reg(AR7240_DDR_TAP_CONTROL3, 0x10105);
- nop
-*/
-
-end:
- jr ra
- nop
--- /dev/null
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o ../common/spi_flash.o ../common/common.o ../common/qca-eth-953x.o ../common/ath_pci.o
+
+ifeq ($(ETH_CONFIG), _s27)
+OBJS += ../common/athr_s27_phy.o
+endif
+
+$(LIB): .depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/addrspace.h>
+#include <soc/qca_soc_common.h>
+
+/*
+ * DRAM init
+ */
+long int dram_init()
+{
+ qca_dram_init();
+
+ return (long int)qca_dram_size();
+}
--- /dev/null
+# ROM version
+ifdef COMPRESSED_UBOOT
+ TEXT_BASE = 0x80010000
+ BOOTSTRAP_TEXT_BASE = 0x9F000000
+# RAM version
+else
+ ifdef CONFIG_SKIP_LOWLEVEL_INIT
+ TEXT_BASE = 0x80100000
+ else
+ TEXT_BASE = 0x9F000000
+ endif
+endif
\ No newline at end of file
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start_bootstrap)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .sdata : { *(.sdata) }
+
+ . = ALIGN(16);
+ _gp = .;
+ __got_start_bootstrap = .;
+ .got : { *(.got) }
+ __got_end_bootstrap = .;
+
+
+ .sdata : { *(.sdata) }
+
+ uboot_end_data_bootstrap = .;
+ num_got_entries = (__got_end_bootstrap - __got_start_bootstrap) >> 2;
+
+ . = ALIGN(4);
+ .sbss : { *(.sbss) }
+ .bss : { *(.bss) }
+ uboot_end_bootstrap = .;
+}
--- /dev/null
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .sdata : { *(.sdata) }
+
+ . = ALIGN(16);
+ _gp = .;
+ __got_start = .;
+ .got : { *(.got) }
+ __got_end = .;
+
+
+ .sdata : { *(.sdata) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ uboot_end_data = .;
+ num_got_entries = (__got_end - __got_start) >> 2;
+
+ . = ALIGN(4);
+ .sbss : { *(.sbss) }
+ .bss : { *(.bss) }
+ uboot_end = .;
+}
+++ /dev/null
-#include <common.h>
-#include <jffs2/jffs2.h>
-#include <asm/addrspace.h>
-#include <asm/types.h>
-#include "ar7240_soc.h"
-#include "ar7240_flash.h"
-
-#define SIZE_INBYTES_4MBYTES (4 * 1024 * 1024)
-#define SIZE_INBYTES_8MBYTES (2 * SIZE_INBYTES_4MBYTES)
-#define SIZE_INBYTES_16MBYTES (2 * SIZE_INBYTES_8MBYTES)
-
-#define SIZE_INBYTES_4KBYTES (4 * 1024)
-#define SIZE_INBYTES_64KBYTES (16 * SIZE_INBYTES_4KBYTES)
-
-#ifndef DEFAULT_FLASH_SIZE_IN_MB
-#error "DEFAULT_FLASH_SIZE_IN_MB not defined!"
-#endif
-
-extern void led_toggle(void);
-extern void all_led_off(void);
-extern int reset_button_status(void);
-
-/*
- * globals
- */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-
-/*
- * statics
- */
-static void ar7240_spi_write_enable(void);
-static void ar7240_spi_poll(void);
-static void ar7240_spi_write_page(uint32_t addr, uint8_t * data, int len);
-static void ar7240_spi_sector_erase(uint32_t addr);
-
-/*
- * Returns JEDEC ID from SPI flash
- */
-static ulong read_id(void){
- unsigned int flashid = 0;
-
- ar7240_reg_wr_nf(AR7240_SPI_FS, 1);
- ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS);
-
- ar7240_spi_bit_banger(0x9F);
-
- ar7240_spi_delay_8();
- ar7240_spi_delay_8();
- ar7240_spi_delay_8();
- ar7240_spi_delay_8();
-
- flashid = ar7240_reg_rd(AR7240_SPI_RD_STATUS);
-
- /*
- * We have 3 bytes:
- * - manufacture ID (1b)
- * - product ID (2b)
- */
- flashid = flashid >> 8;
-
- ar7240_spi_done();
-
- return((ulong)flashid);
-}
-
-static void flash_set_geom(int size, int sector_count, int sector_size){
- int i;
- flash_info_t *info = &flash_info[0];
-
- info->size = size;
- info->sector_count = sector_count;
- info->sector_size = sector_size;
-
- for(i = 0; i < info->sector_count; i++){
- info->start[i] = CFG_FLASH_BASE + (i * info->sector_size);
- }
-}
-
-unsigned long flash_init(void){
- flash_info_t *info;
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
- u32 pll_magic, spi_control;
-
- pll_magic = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET);
-
- // read SPI CONTROL Configuration register (SPI_CONTROL) value stored in FLASH (PLL_IN_FLASH_MAGIC_OFFSET + 12)
- spi_control = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET + 12);
-#endif
-
- info = &flash_info[0];
-
- // spi flash clock
- ar7240_reg_wr(AR7240_SPI_FS, 0x01);
-
- // if reset button is pressed -> write default CLOCK_DIVIDER for SPI CLOCK
- if(reset_button_status()){
- ar7240_reg_wr(AR7240_SPI_CLOCK, AR7240_SPI_CONTROL_DEFAULT);
- } else {
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
- // do we have PLL_MAGIC in FLASH?
- if(pll_magic == PLL_IN_FLASH_MAGIC){
- ar7240_reg_wr(AR7240_SPI_CLOCK, spi_control);
- } else {
-#endif
- ar7240_reg_wr(AR7240_SPI_CLOCK, AR7240_SPI_CONTROL);
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
- }
-#endif
- }
-
- ar7240_reg_wr(AR7240_SPI_FS, 0x0);
-
- // get flash id
- info->flash_id = read_id();
-
- puts("FLASH: ");
-
- // fill flash info based on JEDEC ID
- switch(info->flash_id){
- /*
- * 4M flash chips
- */
- case 0x010215: // tested
- flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES);
- puts("Spansion S25FL032P (4 MB)");
- break;
-
- case 0x1F4700:
- flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES);
- puts("Atmel AT25DF321 (4 MB)");
- break;
-
- case 0x1C3016: // tested
- flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES);
- puts("EON EN25Q32 (4 MB)");
- break;
-
- case 0x1C3116: // tested
- flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES);
- puts("EON EN25F32 (4 MB)");
- break;
-
- case 0x202016:
- flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES);
- puts("Micron M25P32 (4 MB)");
- break;
-
- case 0xEF4016:
- flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES);
- puts("Winbond W25Q32 (4 MB)");
- break;
-
- case 0xC22016:
- flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES);
- puts("Macronix MX25L320 (4 MB)");
- break;
-
- /*
- * 8M flash chips
- */
- case 0x010216:
- flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES);
- puts("Spansion S25FL064P (8 MB)");
- break;
-
- case 0x1F4800:
- flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES);
- puts("Atmel AT25DF641 (8 MB)");
- break;
-
- case 0x1C3017: // tested
- flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES);
- puts("EON EN25Q64 (8 MB)");
- break;
-
- case 0x202017:
- flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES);
- puts("Micron M25P64 (8 MB)");
- break;
-
- case 0xEF4017: // tested
- flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES);
- puts("Winbond W25Q64 (8 MB)");
- break;
-
- case 0xC22017: // tested
- case 0xC22617:
- flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES);
- puts("Macronix MX25L64 (8 MB)");
- break;
-
- /*
- * 16M flash chips
- */
- case 0xEF4018: // tested
- flash_set_geom(SIZE_INBYTES_16MBYTES, 256, SIZE_INBYTES_64KBYTES);
- puts("Winbond W25Q128 (16 MB)");
- break;
-
- case 0xC22018:
- case 0xC22618:
- flash_set_geom(SIZE_INBYTES_16MBYTES, 256, SIZE_INBYTES_64KBYTES);
- puts("Macronix MX25L128 (16 MB)");
- break;
-
- case 0x012018:
- flash_set_geom(SIZE_INBYTES_16MBYTES, 256, SIZE_INBYTES_64KBYTES);
- puts("Spansion S25FL127S (16 MB)");
- break;
-
- case 0x20BA18:
- flash_set_geom(SIZE_INBYTES_16MBYTES, 256, SIZE_INBYTES_64KBYTES);
- puts("Micron N25Q128 (16 MB)");
- break;
-
- /*
- * Unknown flash
- */
- default:
-#if (DEFAULT_FLASH_SIZE_IN_MB == 4)
- flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES);
- puts("Unknown type (using only 4 MB)\n");
-#elif (DEFAULT_FLASH_SIZE_IN_MB == 8)
- flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES);
- puts("Unknown type (using only 8 MB)\n");
-#elif (DEFAULT_FLASH_SIZE_IN_MB == 16)
- flash_set_geom(SIZE_INBYTES_16MBYTES, 256, SIZE_INBYTES_64KBYTES);
- puts("Unknown type (using only 16 MB)\n");
-#endif
- printf("\nPlease, send request to add support\nfor your FLASH - JEDEC ID: 0x%06lX\n", info->flash_id);
- info->flash_id = FLASH_CUSTOM;
- break;
- }
-
- puts("\n");
-
- return(info->size);
-}
-
-int flash_erase(flash_info_t *info, int s_first, int s_last){
- int i, j, sector_size = info->size / info->sector_count;
-
- printf("Erasing: ");
-
- j = 0;
-
- for(i = s_first; i <= s_last; i++){
- ar7240_spi_sector_erase(i * sector_size);
-
- if(j == 39){
- puts("\n ");
- j = 0;
- }
- puts("#");
- led_toggle();
- j++;
- }
-
- ar7240_spi_done();
- all_led_off();
- printf("\n\n");
-
- return(0);
-}
-
-/*
- * Write a buffer from memory to flash:
- * 0. Assumption: Caller has already erased the appropriate sectors.
- * 1. call page programming for every 256 bytes
- */
-int write_buff(flash_info_t *info, uchar *source, ulong addr, ulong len){
- int total = 0, len_this_lp, bytes_this_page;
- ulong dst;
- uchar *src;
-
- printf("Writting at address: 0x%08lX\n", addr);
- addr = addr - CFG_FLASH_BASE;
-
- while(total < len){
- src = source + total;
- dst = addr + total;
- bytes_this_page = AR7240_SPI_PAGE_SIZE - (addr % AR7240_SPI_PAGE_SIZE);
- len_this_lp = ((len - total) > bytes_this_page) ? bytes_this_page : (len - total);
- ar7240_spi_write_page(dst, src, len_this_lp);
- total += len_this_lp;
- }
-
- ar7240_spi_done();
- printf("\n");
-
- return(0);
-}
-
-static void ar7240_spi_write_enable(){
- ar7240_reg_wr_nf(AR7240_SPI_FS, 1);
- ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS);
- ar7240_spi_bit_banger(AR7240_SPI_CMD_WREN);
- ar7240_spi_go();
-}
-
-static void ar7240_spi_poll(){
- int rd;
-
- do {
- ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS);
- ar7240_spi_bit_banger(AR7240_SPI_CMD_RD_STATUS);
- ar7240_spi_delay_8();
- rd = (ar7240_reg_rd(AR7240_SPI_RD_STATUS) & 1);
- } while(rd);
-}
-
-static void ar7240_spi_write_page(uint32_t addr, uint8_t *data, int len){
- int i;
- uint8_t ch;
-
- ar7240_spi_write_enable();
- ar7240_spi_bit_banger(AR7240_SPI_CMD_PAGE_PROG);
- ar7240_spi_send_addr(addr);
-
- for(i = 0; i < len; i++){
- ch = *(data + i);
- ar7240_spi_bit_banger(ch);
- }
-
- ar7240_spi_go();
- ar7240_spi_poll();
-}
-
-static void ar7240_spi_sector_erase(uint32_t addr){
- ar7240_spi_write_enable();
- ar7240_spi_bit_banger(AR7240_SPI_CMD_SECTOR_ERASE);
- ar7240_spi_send_addr(addr);
- ar7240_spi_go();
- ar7240_spi_poll();
-}
+++ /dev/null
-#ifndef _FLASH_H
-#define _FLASH_H
-
-#include "ar7240_soc.h"
-
-#define AR7240_SPI_FS 0x1F000000
-#define AR7240_SPI_CLOCK 0x1F000004
-#define AR7240_SPI_WRITE 0x1F000008
-#define AR7240_SPI_READ 0x1F000000
-#define AR7240_SPI_RD_STATUS 0x1F00000c
-
-#define AR7240_SPI_CS_DIS 0x70000
-#define AR7240_SPI_CE_LOW 0x60000
-#define AR7240_SPI_CE_HIGH 0x60100
-
-#define AR7240_SPI_CMD_WRITE_SR 0x01
-#define AR7240_SPI_CMD_WREN 0x06
-#define AR7240_SPI_CMD_RD_STATUS 0x05
-#define AR7240_SPI_CMD_FAST_READ 0x0B
-#define AR7240_SPI_CMD_PAGE_PROG 0x02
-#define AR7240_SPI_CMD_SECTOR_ERASE 0xD8
-#define AR7240_SPI_CMD_CHIP_ERASE 0xC7
-
-#define AR7240_SPI_PAGE_SIZE 256
-
-#define display(_x) ar7240_reg_wr_nf(0x18040008, (_x))
-
-/*
- * primitives
- */
-#define ar7240_be_msb(_val, _i) (((_val) & (1 << (7 - _i))) >> (7 - _i))
-
-#define ar7240_spi_bit_banger(_byte) do{ \
- int i; \
- for(i = 0; i < 8; i++){ \
- ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CE_LOW | ar7240_be_msb(_byte, i)); \
- ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CE_HIGH | ar7240_be_msb(_byte, i)); \
- } \
-} while(0);
-
-#define ar7240_spi_go() do { \
- ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CE_LOW); \
- ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS); \
-} while(0);
-
-#define ar7240_spi_send_addr(__a) do { \
- ar7240_spi_bit_banger(((__a & 0xff0000) >> 16)); \
- ar7240_spi_bit_banger(((__a & 0x00ff00) >> 8)); \
- ar7240_spi_bit_banger(__a & 0x0000ff); \
-} while (0)
-
-#define ar7240_spi_delay_8() ar7240_spi_bit_banger(0)
-#define ar7240_spi_done() ar7240_reg_wr_nf(AR7240_SPI_FS, 0)
-
-#endif /*_FLASH_H*/
--- /dev/null
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <config.h>
+#include <version.h>
+#include <pci.h>
+#include <atheros.h>
+
+/*
+** PCI controller "hose" value
+*/
+
+static struct pci_controller hose;
+
+static int ath_local_read_config(int where, int size, uint32_t *value);
+static int ath_local_write_config(int where, int size, uint32_t value);
+
+static int
+ath_local_read_config(int where, int size, uint32_t *value)
+{
+ *value = ath_reg_rd(ATH_PCI_CRP + where);
+ return 0;
+}
+
+static int
+ath_local_write_config(int where, int size, uint32_t value)
+{
+ ath_reg_wr((ATH_PCI_CRP + where),value);
+ return 0;
+}
+
+static int
+ath_pci_read_config(struct pci_controller *hose,
+ pci_dev_t dev, int where, uint32_t *value)
+{
+ *value = ath_reg_rd(ATH_PCI_DEV_CFGBASE + where);
+ return 0;
+}
+
+static int
+ath_pci_write_config(struct pci_controller *hose,
+ pci_dev_t dev, int where, uint32_t value)
+{
+ ath_reg_wr((ATH_PCI_DEV_CFGBASE + where), value);
+ return 0;
+}
+
+#ifdef PCIE2_APP_ADDRESS
+static int
+ath_local_read_config_rc2(int where, int size, uint32_t *value)
+{
+ *value = ath_reg_rd(0x18250000 + where);
+ return 0;
+}
+
+static int
+ath_local_write_config_rc2(int where, int size, uint32_t value)
+{
+ ath_reg_wr((0x18250000 + where),value);
+ return 0;
+}
+
+static int
+ath_pci_read_config_rc2(struct pci_controller *hose,
+ pci_dev_t dev, int where, uint32_t *value)
+{
+ *value = ath_reg_rd(0xb6000000 + where);
+ return 0;
+}
+
+static int
+ath_pci_write_config_rc2(struct pci_controller *hose,
+ pci_dev_t dev, int where, uint32_t value)
+{
+ ath_reg_wr((0xb6000000 + where), value);
+ return 0;
+}
+#endif
+
+/*
+** We will use the ART configuration information stored in flash to initialize
+** these devices as required.
+*/
+
+void plat_dev_init(void)
+{
+ u32 val;
+ u32 addr;
+ u32 BaseAddr = 0x10000000;
+ u32 CalAddr = WLANCAL;
+ volatile u16 *calData;
+
+ /*
+ * Copy the device ID from Flash to device config space.
+ */
+
+ calData = (u16 *)CalAddr;
+
+#ifndef CONFIG_PCI_CONFIG_DATA_IN_OTP
+ if (calData[0] != 0xa55a && calData[0] != 0x5aa5)
+ {
+#ifndef COMPRESSED_UBOOT
+ prmsg("BOARD IS NOT CALIBRATED!!!\n");
+#endif
+ return;
+ }
+#else
+ return;
+#endif
+ /*
+ ** Need to setup the PCI device to access the internal registers
+ */
+ if ((is_ar7241() || is_ar7242()))
+ ath_pci_write_config(&hose, NULL, 0x10, 0x1000ffff);
+ else
+ ath_pci_write_config(&hose, NULL, 0x10, 0xffff);
+
+ ath_pci_write_config(&hose, NULL, 0x04, 0x6);
+
+#ifdef PCIE2_APP_ADDRESS
+ ath_pci_write_config_rc2(&hose, NULL, 0x10, 0xffff);
+
+ ath_pci_write_config_rc2(&hose, NULL, 0x04, 0x6);
+#endif
+
+ /*
+ ** Set pointer to first reg address
+ */
+
+ calData += ATH_ART_PCICFG_OFFSET;
+
+ while(*calData != 0xffff)
+ {
+ u16 cd;
+
+ cd = *calData++;
+ addr = BaseAddr + cd;
+ val = *calData++;
+ val |= (*calData++) << 16;
+
+ ath_reg_wr_nf(addr,val);
+ udelay(100);
+ }
+
+ return;
+}
+
+
+/******************************************************************************/
+/*!
+** \brief pci host initialization
+**
+** Sets up the PCI controller on the host. For AR7240 this may not be necessary,
+** but this function is required for board support.
+**
+** We want a 1:1 mapping between PCI and DDR for inbound and outbound.
+** The PCI<---AHB decoding works as follows:
+**
+** 8 registers in the DDR unit provide software configurable 32 bit offsets
+** for each of the eight 16MB PCI windows in the 128MB. The offsets will be
+** added to any address in the 16MB segment before being sent to the PCI unit.
+**
+** Essentially for any AHB address generated by the CPU,
+** 1. the MSB four bits are stripped off, [31:28],
+** 2. Bit 27 is used to decide between the lower 128Mb (PCI) or the rest of
+** the AHB space
+** 3. Bits 26:24 are used to access one of the 8 window registers and are
+** masked off.
+** 4. If it is a PCI address, then the WINDOW offset in the WINDOW register
+** corresponding to the next 3 bits (bit 26:24) is ADDED to the address,
+** to generate the address to PCI unit.
+**
+** eg. CPU address = 0x100000ff
+** window 0 offset = 0x10000000
+** This points to lowermost 16MB window in PCI space.
+** So the resulting address would be 0x000000ff+0x10000000
+** = 0x100000ff
+**
+** eg2. CPU address = 0x120000ff
+** WINDOW 2 offset = 0x12000000
+** resulting address would be 0x000000ff+0x12000000
+** = 0x120000ff
+**
+** There is no translation for inbound access (PCI device as a master)
+**
+** \return N/A
+*/
+
+#ifdef COMPRESSED_UBOOT
+# define PCI_INIT_RET_TYPE int
+# define PCI_INIT_RETURN return 0
+#else
+# define PCI_INIT_RET_TYPE void
+# define PCI_INIT_RETURN return
+#endif
+
+PCI_INIT_RET_TYPE
+pci_init_board (void)
+{
+
+ /**
+ * We never used pci & pci-e, and sometimes should not initialize with
+ * it, or fail to startup
+ * 20141216
+ */
+ return 0;
+
+#ifdef CONFIG_ATH_EMULATION
+ prmsg("--- Skipping %s for emulation\n", __func__);
+#else
+ uint32_t cmd;
+
+ if (is_drqfn() && !is_qca953x()) {
+ /*
+ * Dont enable PCIe in DRQFN package as it has some issues
+ * related to PCIe
+ */
+ PCI_INIT_RETURN;
+ }
+
+#if defined(CONFIG_MACH_QCA953x)
+ if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) {
+ ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
+
+ ath_reg_wr(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_RESET_1);
+ ath_reg_wr(PCIE_PHY_REG_3_ADDRESS, PCIE_PHY_REG_3_RESET_1);
+
+ ath_reg_rmw_set(PCIE_PWR_MGMT_ADDRESS, PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(1));
+
+ ath_reg_rmw_set(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
+
+ ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
+ ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
+
+ ath_reg_rmw_clear(RST_CLKGAT_EN_ADDRESS, RST_CLKGAT_EN_PCIE_RC_SET(1));
+
+ PCI_INIT_RETURN;
+ } else {
+ /* Honeybee -The PCIe reference clock frequency is being changed
+ to vary from 99.968MHz to 99.999MHz using SS modulation */
+ ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
+ PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
+ PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
+ PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
+ PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
+
+ ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
+ PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84)|
+ PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
+ }
+#else
+
+#if defined(CONFIG_MACH_QCA956x)
+
+ ath_reg_rmw_set(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_S_SET(PCIE_PHY_REG_1_S_RESET));
+
+ ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
+ PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
+ PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
+ PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
+
+ ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
+ PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84) |
+ PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
+#else
+ // common for rc1 and rc2
+ ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
+ PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
+ PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
+ PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x14) |
+ PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3ff));
+
+ ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
+ PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x14));
+#endif
+
+#endif
+
+ ath_reg_wr_nf(PCIE_PLL_CONFIG_ADDRESS,
+ PCIE_PLL_CONFIG_REFDIV_SET(1) |
+ PCIE_PLL_CONFIG_BYPASS_SET(1) |
+ PCIE_PLL_CONFIG_PLLPWD_SET(1));
+ udelay(10000);
+
+ ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
+ udelay(1000);
+ ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_BYPASS_SET(1));
+ udelay(1000);
+
+#if !defined(CONFIG_MACH_QCA956x)
+
+#ifdef PCIE2_APP_ADDRESS
+ if (!(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)) {
+ pci_rc2_init_board();
+ return;
+ }
+#endif
+
+ ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
+ udelay(10000);
+
+ ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
+ udelay(10000);
+
+#ifdef PCIE2_APP_ADDRESS
+ ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
+ udelay(10000);
+#endif
+
+ ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0); // Put endpoint in reset
+ udelay(100000);
+
+#ifdef PCIE2_APP_ADDRESS
+ ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
+ udelay(10000);
+#endif
+
+ ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
+ udelay(10000);
+
+ ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
+ udelay(10000);
+
+ ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) |
+ PCIE_APP_CFG_BE_SET(0xf) |
+ PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
+ PCIE_APP_LTSSM_ENABLE_SET(1));
+
+ cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
+ PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
+
+ ath_local_write_config(PCI_COMMAND, 4, cmd);
+ ath_local_write_config(0x20, 4, 0x1ff01000);
+ ath_local_write_config(0x24, 4, 0x1ff01000);
+
+ ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4); // Pull endpoint out of reset
+ udelay(100000);
+
+ /*
+ * Check if the WLAN PCI-E H/W is present, If the
+ * WLAN H/W is not present, skip the PCI platform
+ * initialization code and return
+ */
+ if (((ath_reg_rd(PCIE_RESET_ADDRESS)) & 0x1) == 0x0) {
+ prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n");
+ }
+#endif
+
+#ifdef PCIE2_APP_ADDRESS
+ pci_rc2_init_board();
+#endif
+
+#ifndef COMPRESSED_UBOOT
+ /*
+ * Now, configure for u-boot tools
+ */
+
+ hose.first_busno = 0;
+ hose.last_busno = 0xff;
+
+ /* System space */
+ pci_set_region( &hose.regions[0],
+ 0x80000000,
+ 0x00000000,
+ 32 * 1024 * 1024,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* PCI memory space */
+ pci_set_region( &hose.regions[1],
+ 0x10000000,
+ 0x10000000,
+ 128 * 1024 * 1024,
+ PCI_REGION_MEM);
+
+ hose.region_count = 2;
+
+ pci_register_hose(&hose);
+
+ pci_set_ops( &hose,
+ pci_hose_read_config_byte_via_dword,
+ pci_hose_read_config_word_via_dword,
+ ath_pci_read_config,
+ pci_hose_write_config_byte_via_dword,
+ pci_hose_write_config_word_via_dword,
+ ath_pci_write_config);
+#endif
+ plat_dev_init();
+#endif /* CONFIG_ATH_EMULATION */
+
+ PCI_INIT_RETURN;
+}
+
+#ifdef PCIE2_APP_ADDRESS
+void
+pci_rc2_init_board (void)
+{
+#if defined(CONFIG_MACH_QCA956x)
+ ath_reg_rmw_clear(GPIO_OE_ADDRESS, 0x1);
+ udelay(10000);
+ ath_reg_rmw_set(GPIO_OUT_FUNCTION0_ADDRESS, GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(0x73));
+ udelay(10000);
+ ath_reg_rmw_set(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
+ RST_RESET_PCIE_RESET_SET(1));
+
+ udelay(10000);
+ ath_reg_rmw_clear(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
+ RST_RESET_PCIE_RESET_SET(1));
+
+ udelay(10000);
+ ath_reg_rmw_set(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
+ RST_RESET_PCIE_RESET_SET(1));
+
+ udelay(10000);
+ ath_reg_rmw_clear(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
+ RST_RESET_PCIE_RESET_SET(1));
+
+ udelay(10000);
+ ath_reg_wr(PCIE2_RESET_ADDRESS,PCIE2_RESET_EP_RESET_L_SET(1));
+ udelay(10000);
+ ath_reg_wr(ATH_PCI_CRP_WRDATA,0x6);
+ udelay(10000);
+ ath_reg_wr(PCIE_APP_ADDRESS,PCIE_APP_LTSSM_ENABLE_SET(1) |
+ PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
+ PCIE_APP_CFG_BE_SET(0xf) |
+ PCIE_APP_PCIE_BAR_MSN_SET(1));
+ udelay(10000);
+ ath_reg_wr(PCIE_INT_MASK_ADDRESS,PCIE_INT_MASK_CORR_ERR_SET(1) |
+ PCIE_INT_MASK_NONFATAL_ERR_SET(1) |
+ PCIE_INT_MASK_FATAL_ERR_SET(1) |
+ PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_SET(1) |
+ PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_SET(1) |
+ PCIE_INT_MASK_INTA_SET(1) |
+ PCIE_INT_MASK_INTB_SET(1) |
+ PCIE_INT_MASK_INTC_SET(1) |
+ PCIE_INT_MASK_INTD_SET(1) |
+ PCIE_INT_MASK_MSI_SET(1) |
+ PCIE_INT_MASK_MSI_ERR_SET(1) |
+ PCIE_INT_MASK_AER_INT_SET(1) |
+ PCIE_INT_MASK_AER_MSI_SET(1) |
+ PCIE_INT_MASK_SYS_ERR_SET(1) |
+ PCIE_INT_MASK_INTAL_SET(1) |
+ PCIE_INT_MASK_INTBL_SET(1) |
+ PCIE_INT_MASK_INTCL_SET(1) |
+ PCIE_INT_MASK_INTDL_SET(1));
+ udelay(10000);
+ ath_local_write_config_rc2(0x70c, 4, 0x1b403200);
+ udelay(10000);
+ ath_reg_wr(PCIE_DEBUG_ADDRESS,PCIE_DEBUG_BYTESWAP_SET(1));
+ udelay(10000);
+
+ ath_reg_rmw_set(XTAL2_SEC_ADDRESS, XTAL2_SEC_SPARE_SET(0xc));
+ udelay(10000);
+ ath_reg_rmw_clear(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KI_SET(0x3) |
+ PCIe_DPLL2_KD_SET(0xF));
+ udelay(10000);
+ ath_reg_rmw_set(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KD_SET(0x4));
+ udelay(10000);
+
+#else
+
+ uint32_t cmd;
+
+ ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_PHY_RESET_SET(1));
+ udelay(10000);
+
+ ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_RESET_SET(1));
+ udelay(10000);
+
+ ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1));
+ udelay(10000);
+
+ ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 0); // Put endpoint in reset
+ udelay(100000);
+
+ ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1));
+ udelay(10000);
+
+ ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
+ udelay(10000);
+
+ ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
+ udelay(10000);
+
+ ath_reg_wr_nf(PCIE2_APP_ADDRESS, PCIE2_APP_PCIE2_BAR_MSN_SET(1) |
+ PCIE2_APP_CFG_BE_SET(0xf) |
+ PCIE2_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
+ PCIE2_APP_LTSSM_ENABLE_SET(1));
+
+ cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
+ PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
+
+ ath_local_write_config_rc2(PCI_COMMAND, 4, cmd);
+ ath_local_write_config_rc2(0x20, 4, 0x1ff01000);
+ ath_local_write_config_rc2(0x24, 4, 0x1ff01000);
+
+ ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 4); // Pull endpoint out of reset
+ udelay(100000);
+
+#endif
+ /*
+ * Check if the WLAN PCI-E H/W is present, If the
+ * WLAN H/W is not present, skip the PCI platform
+ * initialization code and return
+ */
+ if (((ath_reg_rd(PCIE2_RESET_ADDRESS)) & 0x1) == 0x0) {
+ prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n");
+ return;
+ }
+}
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Manage the atheros ethernet PHY.
+ *
+ * All definitions in this file are operating system independent!
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <common.h>
+#include <miiphy.h>
+
+#include <asm/addrspace.h>
+#include <atheros.h>
+#include "athr_s27_phy.h"
+
+
+//#include "phy.h" !!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+#define ath_gmac_unit2name(_unit) (_unit ? "eth1" : "eth0")
+
+extern int ath_gmac_miiphy_read(char *devname, uint32_t phaddr, uint8_t reg, uint16_t *data);
+extern int ath_gmac_miiphy_write(char *devname, uint32_t phaddr, uint8_t reg, uint16_t data);
+
+#define phy_reg_read(base, addr, reg) \
+ ath_gmac_miiphy_read(ath_gmac_unit2name(base), addr, reg, NULL)
+
+#define phy_reg_write(base, addr, reg, data) \
+ ath_gmac_miiphy_write(ath_gmac_unit2name(base), addr, reg, data)
+
+
+#ifdef S27_PHY_DEBUG
+ #undef S27_PHY_DEBUG
+#endif
+
+
+
+
+/* PHY selections and access functions */
+
+typedef enum {
+ PHY_SRCPORT_INFO,
+ PHY_PORTINFO_SIZE,
+} PHY_CAP_TYPE;
+
+typedef enum {
+ PHY_SRCPORT_NONE,
+ PHY_SRCPORT_VLANTAG,
+ PHY_SRCPORT_TRAILER,
+} PHY_SRCPORT_TYPE;
+
+#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6)
+#define DRV_MSG(x,a,b,c,d,e,f)
+#define DRV_PRINT(DBG_SW,X)
+
+#define ATHR_LAN_PORT_VLAN 1
+#define ATHR_WAN_PORT_VLAN 2
+#define ENET_UNIT_LAN 1
+#define ENET_UNIT_WAN 0
+
+#define TRUE 1
+#define FALSE 0
+
+#define ATHR_PHY0_ADDR 0x0
+#define ATHR_PHY1_ADDR 0x1
+#define ATHR_PHY2_ADDR 0x2
+#define ATHR_PHY3_ADDR 0x3
+#define ATHR_PHY4_ADDR 0x4
+
+#define MODULE_NAME "ATHRS27"
+
+/*
+ * Track per-PHY port information.
+ */
+
+
+typedef struct {
+ BOOL isEnetPort; /* normal enet port */
+ BOOL isPhyAlive; /* last known state of link */
+ int ethUnit; /* MAC associated with this phy port */
+ uint32_t phyBase;
+ uint32_t phyAddr; /* PHY registers associated with this phy port */
+ uint32_t VLANTableSetting; /* Value to be written to VLAN table */
+} athrPhyInfo_t;
+
+/*
+ * Per-PHY information, indexed by PHY unit number.
+ */
+static athrPhyInfo_t athrPhyInfo[] = {
+
+ {TRUE, /* port 1 -- LAN port 1 */
+ FALSE,
+ ENET_UNIT_LAN,
+ 0,
+ ATHR_PHY0_ADDR,
+ ATHR_LAN_PORT_VLAN
+ },
+
+ {TRUE, /* port 2 -- LAN port 2 */
+ FALSE,
+ ENET_UNIT_LAN,
+ 0,
+ ATHR_PHY1_ADDR,
+ ATHR_LAN_PORT_VLAN
+ },
+
+ {TRUE, /* port 3 -- LAN port 3 */
+ FALSE,
+ ENET_UNIT_LAN,
+ 0,
+ ATHR_PHY2_ADDR,
+ ATHR_LAN_PORT_VLAN
+ },
+
+
+ {TRUE, /* port 4 -- LAN port 4 */
+ FALSE,
+ ENET_UNIT_LAN,
+ 0,
+ ATHR_PHY3_ADDR,
+ ATHR_LAN_PORT_VLAN /* Send to all ports */
+ },
+
+ {TRUE, /* port 5 -- WAN Port 5 */
+ FALSE,
+ ENET_UNIT_WAN,
+ 0,
+ ATHR_PHY4_ADDR,
+ ATHR_LAN_PORT_VLAN /* Send to all ports */
+ },
+
+ {FALSE, /* port 0 -- cpu port 0 */
+ TRUE,
+ ENET_UNIT_LAN,
+ 0,
+ 0x00,
+ ATHR_LAN_PORT_VLAN
+ },
+
+};
+
+
+#define ATHR_GLOBALREGBASE 0
+
+#define ATHR_PHY_MAX 5
+
+/* Range of valid PHY IDs is [MIN..MAX] */
+#define ATHR_ID_MIN 0
+#define ATHR_ID_MAX (ATHR_PHY_MAX-1)
+
+
+/* Convenience macros to access myPhyInfo */
+#define ATHR_IS_ENET_PORT(phyUnit) (athrPhyInfo[phyUnit].isEnetPort)
+#define ATHR_IS_PHY_ALIVE(phyUnit) (athrPhyInfo[phyUnit].isPhyAlive)
+#define ATHR_ETHUNIT(phyUnit) (athrPhyInfo[phyUnit].ethUnit)
+#define ATHR_PHYBASE(phyUnit) (athrPhyInfo[phyUnit].phyBase)
+#define ATHR_PHYADDR(phyUnit) (athrPhyInfo[phyUnit].phyAddr)
+#define ATHR_VLAN_TABLE_SETTING(phyUnit) (athrPhyInfo[phyUnit].VLANTableSetting)
+
+
+#define ATHR_IS_ETHUNIT(phyUnit, ethUnit) \
+ (ATHR_IS_ENET_PORT(phyUnit) && \
+ ATHR_ETHUNIT(phyUnit) == (ethUnit))
+
+#define ATHR_IS_WAN_PORT(phyUnit) (!(ATHR_ETHUNIT(phyUnit)==ENET_UNIT_LAN))
+
+/* Forward references */
+BOOL athrs27_phy_is_link_alive(int phyUnit);
+uint32_t athrs27_reg_read(uint32_t reg_addr);
+void athrs27_reg_write(uint32_t reg_addr, uint32_t reg_val);
+unsigned int s27_rd_phy(unsigned int phy_addr, unsigned int reg_addr);
+void s27_wr_phy(unsigned int phy_addr, unsigned int reg_addr, unsigned int write_data);
+
+
+void athrs27_powersave_off(int phy_addr)
+{
+ s27_wr_phy(phy_addr,ATHR_DEBUG_PORT_ADDRESS,0x29);
+ s27_wr_phy(phy_addr,ATHR_DEBUG_PORT_DATA,0x36c0);
+
+}
+void athrs27_sleep_off(int phy_addr)
+{
+ s27_wr_phy(phy_addr,ATHR_DEBUG_PORT_ADDRESS,0xb);
+ s27_wr_phy(phy_addr,ATHR_DEBUG_PORT_DATA,0x3c00);
+}
+
+void athrs27_force_100M(int phyAddr,int duplex)
+{
+ /*
+ * Force MDI and MDX to alternate ports
+ * Phy 0,2 and 4 -- MDI
+ * Phy 1 and 3 -- MDX
+ */
+
+ if(phyAddr%2) {
+ s27_wr_phy(phyAddr,ATHR_PHY_FUNC_CONTROL,0x820);
+ }
+ else {
+ s27_wr_phy(phyAddr,ATHR_PHY_FUNC_CONTROL,0x800);
+ }
+
+ s27_wr_phy(phyAddr,0x1d,0x29);
+ s27_wr_phy(phyAddr,0x1e,0x0);
+ s27_wr_phy(phyAddr,0x10,0xc60);
+ s27_wr_phy(phyAddr,ATHR_PHY_CONTROL,(0xa000|(duplex << 8)));
+}
+
+void athrs27_force_10M(int phyAddr,int duplex)
+{
+
+ athrs27_powersave_off(phyAddr);
+ athrs27_sleep_off(phyAddr);
+
+ s27_wr_phy(phyAddr,ATHR_PHY_CONTROL,(0x8000 |(duplex << 8)));
+}
+
+int athrs27_reg_init(void)
+{
+#ifdef S27_PHY_DEBUG
+ uint32_t rd_val;
+#endif
+
+ /* if using header for register configuration, we have to */
+ /* configure s27 register after frame transmission is enabled */
+ athrs27_reg_rmw(0x8,(1<<28)); /* Set WAN port is connected to GE0 */
+
+#if defined(S27_FORCE_100M)
+ athrs27_force_100M(ATHR_PHY4_ADDR,1);
+#elif defined(S27_FORCE_10M)
+ athrs27_force_10M(ATHR_PHY4_ADDR,1);
+#else
+ s27_wr_phy(ATHR_PHY4_ADDR,ATHR_PHY_CONTROL,0x9000);
+
+#endif
+#ifdef S27_PHY_DEBUG
+ printf(MODULE_NAME":OPERATIONAL_MODE_REG0:%x\n",athrs27_reg_read(OPERATIONAL_MODE_REG0));
+ printf(MODULE_NAME":REG 0x4-->:%x\n",athrs27_reg_read(0x4));
+ printf(MODULE_NAME":REG 0x2c-->:%x\n",athrs27_reg_read(0x2c));
+ printf(MODULE_NAME":REG 0x8-->:%x\n",athrs27_reg_read(0x8));
+#endif
+
+ return 0;
+}
+
+int athrs27_reg_init_lan(void)
+{
+ int i = 60;
+#if S26_PHY_DEBUG
+ uint32_t rd_val;
+#endif
+ int phyUnit;
+ uint32_t phyBase = 0;
+ BOOL foundPhy = FALSE;
+ uint32_t phyAddr = 0;
+
+
+ /* reset switch */
+ //printf(MODULE_NAME ": resetting s27\n");
+ athrs27_reg_write(0x0, athrs27_reg_read(0x0)|0x80000000);
+
+ while(i--) {
+ sysMsDelay(100);
+ if(!(athrs27_reg_read(0x0)&0x80000000))
+ break;
+ }
+ //printf(MODULE_NAME ": s27 reset done\n");
+ athrs27_reg_write(PORT_STATUS_REGISTER0,0x4e);
+
+ athrs27_reg_rmw(OPERATIONAL_MODE_REG0,(1<<6)); /* Set GMII mode */
+
+ if (is_emu() || is_wasp()) {
+ athrs27_reg_rmw(0x2c,((1<<26)| (1<<16) | 0x1)); /* FiX ME: EBU debug */
+ }
+
+ for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
+
+ foundPhy = TRUE;
+ phyBase = ATHR_PHYBASE(phyUnit);
+ phyAddr = ATHR_PHYADDR(phyUnit);
+
+#if defined(S27_FORCE_100M)
+ athrs27_force_100M(phyAddr,1);
+#elif defined(S27_FORCE_10M)
+ athrs27_force_10M(phyAddr,1);
+#else
+ s27_wr_phy(phyAddr,ATHR_PHY_CONTROL,0x9000);
+#endif
+
+#ifdef S27_PHY_DEBUG
+ rd_val = s27_rd_phy(phyAddr,ATHR_PHY_FUNC_CONTROL);
+ printf("S27 ATHR_PHY_FUNC_CONTROL (%d):%x\n",phyAddr,rd_val);
+ rd_val = s27_rd_phy(phyAddr,ATHR_PHY_ID1);
+ printf("S27 PHY ID (%d) :%x\n",phyAddr, rd_val);
+ rd_val = s27_rd_phy(phyAddr,ATHR_PHY_SPEC_STATUS);
+ printf("S27 PHY CTRL (%d) :%x\n",phyAddr, rd_val);
+ rd_val = s27_rd_phy(phyAddr,ATHR_PHY_STATUS);
+ printf("S27 ATHR PHY STATUS (%d) :%x\n",phyAddr, rd_val);
+#endif
+ }
+
+ /*
+ * status[1:0]=2'h2; - (0x10 - 1000 Mbps , 0x01 - 100Mbps, 0x0 - 10 Mbps)
+ * status[2]=1'h1; - Tx Mac En
+ * status[3]=1'h1; - Rx Mac En
+ * status[4]=1'h1; - Tx Flow Ctrl En
+ * status[5]=1'h1; - Rx Flow Ctrl En
+ * status[6]=1'h1; - Duplex Mode
+ */
+ athrs27_reg_write(PORT_STATUS_REGISTER1, 0x200); /* LAN - 1 */
+ athrs27_reg_write(PORT_STATUS_REGISTER2, 0x200); /* LAN - 2 */
+ athrs27_reg_write(PORT_STATUS_REGISTER3, 0x200); /* LAN - 3 */
+ athrs27_reg_write(PORT_STATUS_REGISTER4, 0x200); /* LAN - 4 */
+
+ if (is_emu()) {
+ athrs27_reg_write(PORT_STATUS_REGISTER1, 0x4C); /* LAN - 1 */
+ athrs27_reg_write(PORT_STATUS_REGISTER2, 0x4c); /* LAN - 2 */
+ athrs27_reg_write(PORT_STATUS_REGISTER3, 0x4c); /* LAN - 3 */
+ athrs27_reg_write(PORT_STATUS_REGISTER4, 0x4c); /* LAN - 4 */
+ }
+
+ /* QM Control */
+ athrs27_reg_write(0x38, 0xc000050e);
+
+ /*
+ * status[11]=1'h0; - CPU Disable
+ * status[7] = 1'b1; - Learn One Lock
+ * status[14] = 1'b0; - Learn Enable
+ */
+#ifdef ATHEROS_HEADER_EN
+ athrs27_reg_write(PORT_CONTROL_REGISTER0, 0x4804);
+#else
+ /* Atheros Header Disable */
+ athrs27_reg_write(PORT_CONTROL_REGISTER0, 0x4004);
+#endif
+
+ /* Tag Priority Mapping */
+ athrs27_reg_write(0x70, 0xfa50);
+
+ /* Enable ARP packets to CPU port */
+ athrs27_reg_write(S27_ARL_TBL_CTRL_REG,(athrs27_reg_read(S27_ARL_TBL_CTRL_REG) | 0x100000));
+
+ /* Enable Broadcast packets to CPU port */
+ athrs27_reg_write(S27_FLD_MASK_REG,(athrs27_reg_read(S27_FLD_MASK_REG) |
+ S27_ENABLE_CPU_BROADCAST | S27_ENABLE_CPU_BCAST_FWD ));
+
+ return 0;
+}
+
+/******************************************************************************
+*
+* athrs27_phy_is_link_alive - test to see if the specified link is alive
+*
+* RETURNS:
+* TRUE --> link is alive
+* FALSE --> link is down
+*/
+BOOL
+athrs27_phy_is_link_alive(int phyUnit)
+{
+ uint16_t phyHwStatus;
+ uint32_t phyBase;
+ uint32_t phyAddr;
+
+ phyBase = ATHR_PHYBASE(phyUnit);
+ phyAddr = ATHR_PHYADDR(phyUnit);
+ phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_SPEC_STATUS);
+
+ if (phyHwStatus & ATHR_STATUS_LINK_PASS)
+ return TRUE;
+
+ return FALSE;
+}
+
+/******************************************************************************
+*
+* athrs27_phy_setup - reset and setup the PHY associated with
+* the specified MAC unit number.
+*
+* Resets the associated PHY port.
+*
+* RETURNS:
+* TRUE --> associated PHY is alive
+* FALSE --> no LINKs on this ethernet unit
+*/
+BOOL
+athrs27_phy_setup(int ethUnit)
+{
+ int phyUnit;
+ uint16_t phyHwStatus;
+ uint16_t timeout;
+ int liveLinks = 0;
+ uint32_t phyBase = 0;
+ BOOL foundPhy = FALSE;
+ uint32_t phyAddr = 0;
+//#if S27_PHY_DEBUG
+ uint32_t rd_val = 0;
+//#endif
+ uint32_t ar7240_revid;
+
+
+ /* See if there's any configuration data for this enet */
+ /* start auto negogiation on each phy */
+ for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
+
+ foundPhy = TRUE;
+ phyBase = ATHR_PHYBASE(phyUnit);
+ phyAddr = ATHR_PHYADDR(phyUnit);
+
+ if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
+ continue;
+ }
+ if (!is_emu()) {
+ s27_wr_phy(phyAddr, ATHR_AUTONEG_ADVERT,ATHR_ADVERTISE_ALL);
+
+ s27_wr_phy(phyAddr, ATHR_PHY_CONTROL,ATHR_CTRL_AUTONEGOTIATION_ENABLE
+ | ATHR_CTRL_SOFTWARE_RESET);
+ }
+ else {
+ //printf("############ is emulation ############\n");
+
+ if(ATHR_ETHUNIT(phyUnit) == ENET_UNIT_WAN) {
+ s27_wr_phy(phyAddr, ATHR_AUTONEG_ADVERT,ATHR_ADVERTISE_ALL);
+ s27_wr_phy(phyAddr,0x9, 0x0); //donot advertise 1000Mbps mode
+ s27_wr_phy(phyAddr, ATHR_PHY_CONTROL,0x0);
+ s27_wr_phy(phyAddr, ATHR_PHY_CONTROL,ATHR_CTRL_AUTONEGOTIATION_ENABLE
+ | ATHR_CTRL_SOFTWARE_RESET);
+ }
+ else {
+
+ s27_wr_phy(phyAddr, ATHR_AUTONEG_ADVERT,(ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE |
+ ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL));
+ s27_wr_phy(phyAddr,0x9, 0x0); //donot advertise 1000Mbps mode
+ s27_wr_phy(phyAddr, ATHR_PHY_CONTROL,0x0);
+ s27_wr_phy(phyAddr, ATHR_PHY_CONTROL,ATHR_CTRL_AUTONEGOTIATION_ENABLE
+ | ATHR_CTRL_SOFTWARE_RESET);
+ }
+ }
+ rd_val = s27_rd_phy(phyAddr,ATHR_PHY_CONTROL);
+ //printf("%s ATHR_PHY_CONTROL %d :%x\n",__func__,phyAddr,rd_val);
+ rd_val = s27_rd_phy(phyAddr,ATHR_PHY_SPEC_STATUS);
+ //printf("%s ATHR_PHY_SPEC_STAUS %d :%x\n",__func__,phyAddr,rd_val);
+ }
+ if (!foundPhy) {
+ return FALSE; /* No PHY's configured for this ethUnit */
+ }
+
+ /*
+ * After the phy is reset, it takes a little while before
+ * it can respond properly.
+ */
+ if (ethUnit == ENET_UNIT_LAN)
+ sysMsDelay(100);
+ else
+ sysMsDelay(300);
+
+ /*
+ * Wait up to 3 seconds for ALL associated PHYs to finish
+ * autonegotiation. The only way we get out of here sooner is
+ * if ALL PHYs are connected AND finish autonegotiation.
+ */
+ for (phyUnit=0; (phyUnit < ATHR_PHY_MAX) /*&& (timeout > 0) */; phyUnit++) {
+ if (ATHR_ETHUNIT(phyUnit) == ENET_UNIT_WAN)
+ continue;
+
+ timeout=20;
+ for (;;) {
+ phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_CONTROL);
+
+ if (ATHR_RESET_DONE(phyHwStatus)) {
+ DRV_PRINT(DRV_DEBUG_PHYSETUP,
+ ("Port %d, Neg Success\n", phyUnit));
+ break;
+ }
+ if (timeout == 0) {
+ DRV_PRINT(DRV_DEBUG_PHYSETUP,
+ ("Port %d, Negogiation timeout\n", phyUnit));
+ break;
+ }
+ if (--timeout == 0) {
+ DRV_PRINT(DRV_DEBUG_PHYSETUP,
+ ("Port %d, Negogiation timeout\n", phyUnit));
+ break;
+ }
+
+ sysMsDelay(150);
+ }
+ /* extend the cable length */
+ s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_ADDRESS, 0x14);
+ s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_DATA, 0xf52);
+
+ /* Force Class A setting phys */
+ s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_ADDRESS, 4);
+ s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_DATA, 0xebbb);
+ s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_ADDRESS, 5);
+ s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_DATA, 0x2c47);
+
+ /* fine-tune PHYs */
+ s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_ADDRESS, 0x3c);
+ s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_DATA, 0x1c1);
+ s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_ADDRESS, 0x37);
+ s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_DATA, 0xd600);
+
+
+#ifdef S27_VER_1_0
+ /* turn off power saving */
+ s27_wr_phy(phyUnit, 29, 41);
+ s27_wr_phy(phyUnit, 30, 0);
+ //printf("def_ S27_VER_1_0\n");
+#endif
+ }
+
+ /*
+ * All PHYs have had adequate time to autonegotiate.
+ * Now initialize software status.
+ *
+ * It's possible that some ports may take a bit longer
+ * to autonegotiate; but we can't wait forever. They'll
+ * get noticed by mv_phyCheckStatusChange during regular
+ * polling activities.
+ */
+ for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
+ if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
+ continue;
+ }
+
+ if (athrs27_phy_is_link_alive(phyUnit)) {
+ liveLinks++;
+ ATHR_IS_PHY_ALIVE(phyUnit) = TRUE;
+ } else {
+ ATHR_IS_PHY_ALIVE(phyUnit) = FALSE;
+ }
+ DRV_PRINT(DRV_DEBUG_PHYSETUP,
+ ("eth%d: Phy Specific Status=%4.4x\n",
+ ethUnit,
+ s27_rd_phy(ATHR_PHYADDR(phyUnit),ATHR_PHY_SPEC_STATUS)));
+ }
+
+ return (liveLinks > 0);
+}
+
+/******************************************************************************
+*
+* athrs27_phy_is_fdx - Determines whether the phy ports associated with the
+* specified device are FULL or HALF duplex.
+*
+* RETURNS:
+* 1 --> FULL
+* 0 --> HALF
+*/
+int
+athrs27_phy_is_fdx(int ethUnit,int phyUnit)
+{
+ uint32_t phyBase;
+ uint32_t phyAddr;
+ uint16_t phyHwStatus;
+ int ii = 200;
+
+ if (ethUnit == ENET_UNIT_LAN)
+ return TRUE;
+
+ for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
+ if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
+ continue;
+ }
+
+ if (athrs27_phy_is_link_alive(phyUnit)) {
+
+ phyBase = ATHR_PHYBASE(phyUnit);
+ phyAddr = ATHR_PHYADDR(phyUnit);
+
+ do {
+ phyHwStatus = s27_rd_phy (phyAddr, ATHR_PHY_SPEC_STATUS);
+ if(phyHwStatus & ATHR_STATUS_RESOVLED)
+ break;
+ sysMsDelay(10);
+ } while(--ii);
+ if (phyHwStatus & ATHER_STATUS_FULL_DUPLEX) {
+ return TRUE;
+ }
+ }
+ }
+
+ return FALSE;
+}
+/******************************************************************************
+*
+* athrs27_phy_speed - Determines the speed of phy ports associated with the
+* specified device.
+*
+* RETURNS:
+* ATHR_PHY_SPEED_10T, AG7240_PHY_SPEED_100T;
+* ATHR_PHY_SPEED_1000T;
+*/
+
+int
+athrs27_phy_speed(int ethUnit,int phyUnit)
+{
+ uint16_t phyHwStatus;
+ uint32_t phyBase;
+ uint32_t phyAddr;
+ int ii = 200;
+ int phySpeed;
+ for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
+ if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
+ continue;
+ }
+
+
+ phyBase = ATHR_PHYBASE(phyUnit);
+ phyAddr = ATHR_PHYADDR(phyUnit);
+ phySpeed = _10BASET;
+
+ if (athrs27_phy_is_link_alive(phyUnit)) {
+
+ do {
+ phyHwStatus = s27_rd_phy(phyAddr,
+ ATHR_PHY_SPEC_STATUS);
+ if(phyHwStatus & ATHR_STATUS_RESOVLED)
+ break;
+ sysMsDelay(10);
+ }while(--ii);
+
+ phyHwStatus = ((phyHwStatus & ATHER_STATUS_LINK_MASK) >>
+ ATHER_STATUS_LINK_SHIFT);
+
+ switch(phyHwStatus) {
+ case 0:
+ phySpeed = _10BASET;
+ break;
+ case 1:
+ phySpeed = _100BASET;
+ break;
+ case 2:
+ phySpeed = _1000BASET;
+ break;
+ default:
+ printf("Unkown speed read!\n");
+ }
+ }
+
+ phy_reg_write(1,phyAddr, ATHR_DEBUG_PORT_ADDRESS, 0x18);
+
+ if(phySpeed == _100BASET) {
+ phy_reg_write(1,phyAddr, ATHR_DEBUG_PORT_DATA, 0xba8);
+ } else {
+ phy_reg_write(1,phyAddr, ATHR_DEBUG_PORT_DATA, 0x2ea);
+ }
+ }
+
+ if (ethUnit == ENET_UNIT_LAN)
+ phySpeed = _1000BASET;
+
+ return phySpeed;
+}
+
+/*****************************************************************************
+*
+* athr_phy_is_up -- checks for significant changes in PHY state.
+*
+* A "significant change" is:
+* dropped link (e.g. ethernet cable unplugged) OR
+* autonegotiation completed + link (e.g. ethernet cable plugged in)
+*
+* When a PHY is plugged in, phyLinkGained is called.
+* When a PHY is unplugged, phyLinkLost is called.
+*/
+
+int
+athrs27_phy_is_up(int ethUnit)
+{
+
+ uint16_t phyHwStatus, phyHwControl;
+ athrPhyInfo_t *lastStatus;
+ int linkCount = 0;
+ int lostLinks = 0;
+ int gainedLinks = 0;
+ uint32_t phyBase;
+ uint32_t phyAddr;
+ int phyUnit;
+
+ for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
+ if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
+ continue;
+ }
+
+ phyBase = ATHR_PHYBASE(phyUnit);
+ phyAddr = ATHR_PHYADDR(phyUnit);
+
+ lastStatus = &athrPhyInfo[phyUnit];
+ if (lastStatus->isPhyAlive) { /* last known link status was ALIVE */
+ phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_SPEC_STATUS);
+
+ /* See if we've lost link */
+ if (phyHwStatus & ATHR_STATUS_LINK_PASS) {
+ linkCount++;
+ } else {
+ lostLinks++;
+ DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d down\n",
+ ethUnit, phyUnit));
+ printf("enet%d port%d down\n",ethUnit, phyUnit);
+ lastStatus->isPhyAlive = FALSE;
+ }
+ } else { /* last known link status was DEAD */
+ /* Check for reset complete */
+ if(is_emu())
+ {
+ phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_STATUS);
+ if(phyAddr%2) {
+ s27_wr_phy(phyAddr,ATHR_PHY_FUNC_CONTROL,0x820);
+ }
+ else {
+ s27_wr_phy(phyAddr,ATHR_PHY_FUNC_CONTROL,0x800);
+ }
+
+ if((phyHwStatus & 0x4)==0)
+ {
+ s27_wr_phy(phyAddr,0x9,0x0);
+ if(phyAddr !=0x4)
+ s27_wr_phy(phyAddr,0x4,0x41);
+ s27_wr_phy(phyAddr,0x0,0x9000);
+ }
+ }
+
+ phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_CONTROL);
+ if (!ATHR_RESET_DONE(phyHwStatus))
+ continue;
+
+ phyHwControl = s27_rd_phy(phyAddr, ATHR_PHY_CONTROL);
+ phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_STATUS);
+
+ /* Check for AutoNegotiation complete */
+ if ((!(phyHwControl & ATHR_CTRL_AUTONEGOTIATION_ENABLE))
+ || ATHR_AUTONEG_DONE(phyHwStatus)) {
+ phyHwStatus = s27_rd_phy(phyAddr,
+ ATHR_PHY_SPEC_STATUS);
+
+ if (phyHwStatus & ATHR_STATUS_LINK_PASS) {
+ gainedLinks++;
+ linkCount++;
+ printf("enet%d port%d up\n",ethUnit, phyUnit);
+ DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d up\n",
+ ethUnit, phyUnit));
+ lastStatus->isPhyAlive = TRUE;
+ }
+ }
+ }
+ }
+ return (linkCount);
+}
+
+unsigned int athrs27_reg_read(unsigned int s27_addr)
+{
+ unsigned int addr_temp;
+ unsigned int s27_rd_csr_low, s27_rd_csr_high, s27_rd_csr;
+ unsigned int data,unit = 0;
+ unsigned int phy_address, reg_address;
+
+ addr_temp = s27_addr >>2;
+ data = addr_temp >> 7;
+
+ phy_address = 0x1f;
+ reg_address = 0x10;
+
+ if (is_ar7240()) {
+ unit = 0;
+ }
+ else if(is_ar7241() || is_ar7242() || is_wasp() || is_qca953x() || is_qca956x()) {
+ unit = 1;
+ }
+
+ phy_reg_write(unit,phy_address, reg_address, data);
+
+ phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
+ reg_address = ((addr_temp << 1) & 0x1e);
+ s27_rd_csr_low = (uint32_t) phy_reg_read(unit,phy_address, reg_address);
+
+ reg_address = reg_address | 0x1;
+ s27_rd_csr_high = (uint32_t) phy_reg_read(unit,phy_address, reg_address);
+ s27_rd_csr = (s27_rd_csr_high << 16) | s27_rd_csr_low ;
+
+ return(s27_rd_csr);
+}
+
+void athrs27_reg_write(unsigned int s27_addr, unsigned int s27_write_data)
+{
+ unsigned int addr_temp;
+ unsigned int data;
+ unsigned int phy_address, reg_address,unit = 0;
+
+ addr_temp = (s27_addr ) >>2;
+ data = addr_temp >> 7;
+
+ phy_address = 0x1f;
+ reg_address = 0x10;
+
+ if (is_ar7240()) {
+ unit = 0;
+ }
+ else if(is_ar7241() || is_ar7242() || is_wasp() || is_qca953x() || is_qca956x()) {
+ unit = 1;
+ }
+ phy_reg_write(unit,phy_address, reg_address, data);
+
+ phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
+
+ reg_address = (((addr_temp << 1) & 0x1e) | 0x1);
+ data = (s27_write_data >> 16) & 0xffff;
+ phy_reg_write(unit,phy_address, reg_address, data);
+
+ reg_address = ((addr_temp << 1) & 0x1e);
+ data = s27_write_data & 0xffff;
+ phy_reg_write(unit,phy_address, reg_address, data);
+
+}
+
+void athrs27_reg_rmw(unsigned int s27_addr, unsigned int s27_write_data)
+{
+ int val = athrs27_reg_read(s27_addr);
+ athrs27_reg_write(s27_addr,(val | s27_write_data));
+}
+
+unsigned int s27_rd_phy(unsigned int phy_addr, unsigned int reg_addr)
+{
+ int unit, val = 0;
+
+ if (is_ar7240()) {
+ unit = 0;
+ } else if(is_ar7241() || is_ar7242() || is_wasp() || is_qca953x() || is_qca956x()) {
+ unit = 1;
+ }
+ val = (uint32_t) phy_reg_read(unit, phy_addr, reg_addr);
+ return val;
+}
+
+void s27_wr_phy(unsigned int phy_addr, unsigned int reg_addr, unsigned int write_data)
+{
+ int unit;
+
+ if (is_ar7240()) {
+ unit = 0;
+ } else if(is_ar7241() || is_ar7242() || is_wasp() || is_qca953x() || is_qca956x()) {
+ unit = 1;
+ }
+
+ phy_reg_write(unit, phy_addr, reg_addr, write_data);
+}
+int athrs27_mdc_check()
+{
+ int i;
+
+ for (i=0; i<4000; i++) {
+ if(athrs27_reg_read(0x10c) != 0x18007fff)
+ return -1;
+ }
+ return 0;
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ATHRS27_PHY_H
+#define _ATHRS27_PHY_H
+
+
+/*****************/
+/* PHY Registers */
+/*****************/
+#define ATHR_PHY_CONTROL 0
+#define ATHR_PHY_STATUS 1
+#define ATHR_PHY_ID1 2
+#define ATHR_PHY_ID2 3
+#define ATHR_AUTONEG_ADVERT 4
+#define ATHR_LINK_PARTNER_ABILITY 5
+#define ATHR_AUTONEG_EXPANSION 6
+#define ATHR_NEXT_PAGE_TRANSMIT 7
+#define ATHR_LINK_PARTNER_NEXT_PAGE 8
+#define ATHR_1000BASET_CONTROL 9
+#define ATHR_1000BASET_STATUS 10
+#define ATHR_PHY_FUNC_CONTROL 16
+#define ATHR_PHY_SPEC_STATUS 17
+#define ATHR_DEBUG_PORT_ADDRESS 29
+#define ATHR_DEBUG_PORT_DATA 30
+#define ATHR_PHY_INTR_ENABLE 0x12
+#define ATHR_PHY_INTR_STATUS 0x13
+
+/* ATHR_PHY_CONTROL fields */
+#define ATHR_CTRL_SOFTWARE_RESET 0x8000
+#define ATHR_CTRL_SPEED_LSB 0x2000
+#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000
+#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200
+#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100
+#define ATHR_CTRL_SPEED_MSB 0x0040
+
+#define ATHR_RESET_DONE(phy_control) \
+ (((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0)
+
+/* Phy status fields */
+#define ATHR_STATUS_AUTO_NEG_DONE 0x0020
+
+#define ATHR_AUTONEG_DONE(ip_phy_status) \
+ (((ip_phy_status) & \
+ (ATHR_STATUS_AUTO_NEG_DONE)) == \
+ (ATHR_STATUS_AUTO_NEG_DONE))
+
+/* Link Partner ability */
+#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100
+#define ATHR_LINK_100BASETX 0x0080
+#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040
+#define ATHR_LINK_10BASETX 0x0020
+
+/* Advertisement register. */
+#define ATHR_ADVERTISE_NEXT_PAGE 0x8000
+#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800
+#define ATHR_ADVERTISE_PAUSE 0x0400
+#define ATHR_ADVERTISE_100FULL 0x0100
+#define ATHR_ADVERTISE_100HALF 0x0080
+#define ATHR_ADVERTISE_10FULL 0x0040
+#define ATHR_ADVERTISE_10HALF 0x0020
+
+#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE | \
+ ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \
+ ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL)
+
+/* 1000BASET_CONTROL */
+#define ATHR_ADVERTISE_1000FULL 0x0200
+#define ATHR_ADVERTISE_1000HALF 0x0100
+
+/* Phy Specific status fields */
+#define ATHER_STATUS_LINK_MASK 0xC000
+#define ATHER_STATUS_LINK_SHIFT 14
+#define ATHER_STATUS_FULL_DUPLEX 0x2000
+#define ATHR_STATUS_LINK_PASS 0x0400
+#define ATHR_LATCH_LINK_PASS 0x0004
+#define ATHR_STATUS_RESOVLED 0x0800
+
+/*phy debug port register */
+#define ATHER_DEBUG_SERDES_REG 5
+
+/* Serdes debug fields */
+#define ATHER_SERDES_BEACON 0x0100
+
+#define OPERATIONAL_MODE_REG0 0x4
+
+/* S27 CSR Registers */
+
+#define PORT_STATUS_REGISTER0 0x0100
+#define PORT_STATUS_REGISTER1 0x0200
+#define PORT_STATUS_REGISTER2 0x0300
+#define PORT_STATUS_REGISTER3 0x0400
+#define PORT_STATUS_REGISTER4 0x0500
+#define PORT_STATUS_REGISTER5 0x0600
+
+#define RATE_LIMIT_REGISTER0 0x010C
+#define RATE_LIMIT_REGISTER1 0x020C
+#define RATE_LIMIT_REGISTER2 0x030C
+#define RATE_LIMIT_REGISTER3 0x040C
+#define RATE_LIMIT_REGISTER4 0x050C
+#define RATE_LIMIT_REGISTER5 0x060C
+
+#define PORT_CONTROL_REGISTER0 0x0104
+#define PORT_CONTROL_REGISTER1 0x0204
+#define PORT_CONTROL_REGISTER2 0x0304
+#define PORT_CONTROL_REGISTER3 0x0404
+#define PORT_CONTROL_REGISTER4 0x0504
+#define PORT_CONTROL_REGISTER5 0x0604
+
+#define CPU_PORT_REGISTER 0x0078
+#define MDIO_CTRL_REGISTER 0x0098
+
+#define S27_ARL_TBL_FUNC_REG0 0x0050
+#define S27_ARL_TBL_FUNC_REG1 0x0054
+#define S27_ARL_TBL_FUNC_REG2 0x0058
+#define S27_FLD_MASK_REG 0x002c
+#define S27_ARL_TBL_CTRL_REG 0x005c
+#define S27_GLOBAL_INTR_REG 0x10
+#define S27_GLOBAL_INTR_MASK_REG 0x14
+
+
+#define S27_ENABLE_CPU_BROADCAST (1 << 26)
+#define S27_ENABLE_CPU_BCAST_FWD (1 << 25)
+
+#define PHY_LINK_CHANGE_REG 0x4
+#define PHY_LINK_UP 0x400
+#define PHY_LINK_DOWN 0x800
+#define PHY_LINK_DUPLEX_CHANGE 0x2000
+#define PHY_LINK_SPEED_CHANGE 0x4000
+#define PHY_LINK_INTRS (PHY_LINK_UP | PHY_LINK_DOWN | PHY_LINK_DUPLEX_CHANGE | PHY_LINK_SPEED_CHANGE)
+
+/* SWITCH QOS REGISTERS */
+
+#define ATHR_QOS_PORT_0 0x110 /* CPU PORT */
+#define ATHR_QOS_PORT_1 0x210
+#define ATHR_QOS_PORT_2 0x310
+#define ATHR_QOS_PORT_3 0x410
+#define ATHR_QOS_PORT_4 0x510
+
+#define ATHR_ENABLE_TOS (1 << 16)
+
+#define ATHR_QOS_MODE_REGISTER 0x030
+#define ATHR_QOS_FIXED_PRIORITY ((0 << 31) | (0 << 28))
+#define ATHR_QOS_WEIGHTED ((1 << 31) | (0 << 28)) /* Fixed weight 8,4,2,1 */
+#define ATHR_QOS_MIXED ((1 << 31) | (1 << 28)) /* Q3 for managment; Q2,Q1,Q0 - 4,2,1 */
+
+#ifndef BOOL
+#define BOOL int
+#endif
+
+#define sysMsDelay(_x) udelay((_x) * 1000)
+#define mdelay(_x) sysMsDelay(_x)
+
+#undef S27_VER_1_0
+
+/*
+ * Atheros header defines
+ */
+#ifndef _ATH_HEADER_CONF
+#define _ATH_HEADER_CONF
+
+typedef enum {
+ NORMAL_PACKET,
+ RESERVED0,
+ MIB_1ST,
+ RESERVED1,
+ RESERVED2,
+ READ_WRITE_REG,
+ READ_WRITE_REG_ACK,
+ RESERVED3
+} AT_HEADER_TYPE;
+
+typedef struct {
+ uint16_t reserved0 :2;
+ uint16_t priority :2;
+ uint16_t type :4;
+ uint16_t broadcast :1;
+ uint16_t from_cpu :1;
+ uint16_t reserved1 :2;
+ uint16_t port_num :4;
+}at_header_t;
+
+#define ATHR_HEADER_LEN 2
+
+#endif // _ATH_HEADER_CONF
+
+typedef enum {
+ PORT_EG_UNMODIFIED = 0, /**< egress transmit packets unmodified */
+ PORT_EG_UNTAGGED, /**< egress transmit packets without vlan tag */
+ PORT_EG_TAGGED, /**< egress transmit packets with vlan tag */
+} port_1q_egmode_t;
+
+extern void set_packet_inspection_flag(int flag);
+
+#endif
/* PHY selections and access functions */
#define DRV_PRINT(DBG_SW,X)
+#ifdef S27_PHY_DEBUG
+ #undef S27_PHY_DEBUG
+#endif
+
#define ATHR_LAN_PORT_VLAN 1
#define ATHR_WAN_PORT_VLAN 2
#define ENET_UNIT_LAN 1
int i = 60;
int phyUnit;
uint32_t phyAddr = 0;
- #if S27_PHY_DEBUG
+ #ifdef S27_PHY_DEBUG
uint32_t rd_val;
#endif
/* reset switch */
-#if S27_PHY_DEBUG
+#ifdef S27_PHY_DEBUG
printf(MODULE_NAME ": resetting s27\n");
#endif
}
}
-#if S27_PHY_DEBUG
+#ifdef S27_PHY_DEBUG
printf(MODULE_NAME ": s27 reset done\n");
#endif
s27_wr_phy(phyAddr, ATHR_PHY_CONTROL, 0x9000);
#endif
-#if S27_PHY_DEBUG
+#ifdef S27_PHY_DEBUG
rd_val = s27_rd_phy(phyAddr, ATHR_PHY_FUNC_CONTROL);
printf("S27 ATHR_PHY_FUNC_CONTROL (%d):%x\n", phyAddr, rd_val);
uint16_t phyHwStatus;
uint16_t timeout;
uint32_t phyAddr = 0;
-#if S27_PHY_DEBUG
+#ifdef S27_PHY_DEBUG
uint32_t rd_val = 0;
#endif
}
}
-#if S27_PHY_DEBUG
+#ifdef S27_PHY_DEBUG
rd_val = s27_rd_phy(phyAddr,ATHR_PHY_CONTROL);
printf("%s ATHR_PHY_CONTROL %d: 0x%x\n",__func__,phyAddr,rd_val);
--- /dev/null
+/*
+ * Common functions for QC/A WiSoCs based boards support
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * Partially based on:
+ * Linux/arch/mips/ath79/setup.c
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <common.h>
+#include <flash.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <soc/qca_soc_common.h>
+
+#ifndef CONFIG_BOARD_CUSTOM_STRING
+ #define CONFIG_BOARD_CUSTOM_STRING "Unknown/OEM"
+#endif
+
+#define ALIGN_SIZE "8"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 mac_is_not_valid = 1;
+
+/*
+ * Put QCA SOC name, version and revision in buffer
+ */
+void qca_soc_name_rev(char *buf)
+{
+ u32 id;
+ u32 major;
+ u32 rev = 0;
+
+ if (buf == NULL)
+ return;
+
+ /* Get revision ID value */
+ id = qca_soc_reg_read(QCA_RST_REVISION_ID_REG);
+
+ major = id & QCA_RST_REVISION_ID_MAJOR_MASK;
+ rev = id & QCA_RST_REVISION_ID_REV_MASK;
+
+ switch (major) {
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ case QCA_RST_REVISION_ID_MAJOR_AR9330_VAL:
+ sprintf(buf, "AR9330 rev. %d", rev);
+ break;
+ case QCA_RST_REVISION_ID_MAJOR_AR9331_VAL:
+ sprintf(buf, "AR9331 rev. %d", rev);
+ break;
+#endif
+#if (SOC_TYPE & QCA_AR934X_SOC)
+ case QCA_RST_REVISION_ID_MAJOR_AR9341_VAL:
+ sprintf(buf, "AR9341 rev. %d", rev);
+ break;
+ case QCA_RST_REVISION_ID_MAJOR_AR9344_VAL:
+ sprintf(buf, "AR9344 rev. %d", rev);
+ break;
+#endif
+#if (SOC_TYPE & QCA_QCA953X_SOC)
+ case QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL:
+ sprintf(buf, "QCA953x ver. 1 rev. %d", rev);
+ break;
+ case QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL:
+ sprintf(buf, "QCA953x ver. 2 rev. %d", rev);
+ break;
+#endif
+#if (SOC_TYPE & QCA_QCA955X_SOC)
+ case QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL:
+ sprintf(buf, "QCA9558 rev. %d", rev);
+ break;
+#endif
+ default:
+ sprintf(buf, "Unknown");
+ break;
+ }
+}
+
+/*
+ * Prints available information about the board
+ */
+void print_board_info(void)
+{
+ u32 ahb_clk, cpu_clk, ddr_clk, spi_clk, ref_clk;
+ u32 bank;
+ bd_t *bd = gd->bd;
+ char buffer[24];
+
+ /* Board name */
+ printf("%" ALIGN_SIZE "s %s\n", "BOARD:", CONFIG_BOARD_CUSTOM_STRING);
+
+ /* SOC name, version and revision */
+ qca_soc_name_rev(buffer);
+ printf("%" ALIGN_SIZE "s %s\n", "SOC:", buffer);
+
+ /* MIPS CPU type */
+ cpu_name(buffer);
+ printf("%" ALIGN_SIZE "s %s\n", "CPU:", buffer);
+
+ /* RAM size and type */
+ printf("%" ALIGN_SIZE "s ", "RAM:");
+ print_size(bd->bi_memsize, "");
+
+ switch (qca_dram_type()) {
+ case RAM_MEMORY_TYPE_SDR:
+ puts(" SDR ");
+ break;
+ case RAM_MEMORY_TYPE_DDR1:
+ puts(" DDR1 ");
+ break;
+ case RAM_MEMORY_TYPE_DDR2:
+ puts(" DDR2 ");
+ break;
+ default:
+ break;
+ }
+
+ /* DDR interface width */
+ printf("%d-bit ", qca_dram_ddr_width());
+
+ /* tCL-tRCD-tRP-tRAS latency */
+ printf("CL%d-%d-%d-%d\n", qca_dram_cas_lat(),
+ qca_dram_trcd_lat(),
+ qca_dram_trp_lat(),
+ qca_dram_tras_lat());
+
+ /* SPI NOR FLASH sizes and types */
+ printf("%" ALIGN_SIZE "s ", "FLASH:");
+
+ for (bank = 0; bank < CFG_MAX_FLASH_BANKS; bank++) {
+ if (flash_info[bank].size == 0)
+ continue;
+
+ if (bank > 0)
+ printf("%" ALIGN_SIZE "s ", " ");
+
+ print_size(flash_info[bank].size, "");
+
+ if (flash_info[bank].manuf_name != NULL)
+ printf(" %s", flash_info[bank].manuf_name);
+
+ if (flash_info[bank].model_name != NULL)
+ printf(" %s", flash_info[bank].model_name);
+
+ puts("\n");
+ }
+
+ /* MAC address */
+ printf("%" ALIGN_SIZE "s %02X:%02X:%02X:%02X:%02X:%02X", "MAC:",
+ bd->bi_enetaddr[0],bd->bi_enetaddr[1], bd->bi_enetaddr[2],
+ bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
+
+ if (mac_is_not_valid) {
+ puts(" (fixed)\n");
+ } else {
+ puts("\n");
+ }
+
+ /* System clocks */
+ printf("%" ALIGN_SIZE "s CPU/RAM/AHB/SPI/REF\n", "CLOCKS:");
+
+ qca_sys_clocks(&cpu_clk, &ddr_clk, &ahb_clk, &spi_clk, &ref_clk);
+ cpu_clk = cpu_clk / 1000000;
+ ddr_clk = ddr_clk / 1000000;
+ ahb_clk = ahb_clk / 1000000;
+ spi_clk = spi_clk / 1000000;
+ ref_clk = ref_clk / 1000000;
+
+ printf("%" ALIGN_SIZE "s %3d/%3d/%3d/%3d/%3d MHz\n",
+ " ", cpu_clk, ddr_clk, ahb_clk, spi_clk, ref_clk);
+
+ puts("\n");
+}
+
+/*
+ * Reads MAC address if available or uses fixed one
+ */
+void macaddr_init(u8 *mac_addr)
+{
+ u8 buffer[6];
+ u8 fixed_mac[6] = {0x00, 0x03, 0x7F, 0x09, 0x0B, 0xAD};
+
+#if defined(OFFSET_MAC_ADDRESS)
+ memcpy(buffer, (void *)(CFG_FLASH_BASE
+ + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6);
+
+ /*
+ * Check first LSBit (I/G bit) and second LSBit (U/L bit) in MSByte of vendor part
+ * both of them should be 0:
+ * I/G bit == 0 -> Individual MAC address (unicast address)
+ * U/L bit == 0 -> Burned-In-Address (BIA) MAC address
+ */
+ if (CHECK_BIT((buffer[0] & 0xFF), 0) != 0 ||
+ CHECK_BIT((buffer[0] & 0xFF), 1) != 0) {
+ memcpy(buffer, fixed_mac, 6);
+ } else {
+ mac_is_not_valid = 0;
+ }
+#else
+ memcpy(buffer, fixed_mac, 6);
+#endif
+
+ memcpy(mac_addr, buffer, 6);
+}
+
+/*
+ * Returns "reset button" status:
+ * 1 -> button is pressed
+ * 0 -> button is not pressed
+ */
+int reset_button_status(void)
+{
+#ifdef CONFIG_GPIO_RESET_BTN
+ u32 gpio;
+
+ gpio = qca_soc_reg_read(QCA_GPIO_IN_REG);
+
+ if (gpio & (1 << CONFIG_GPIO_RESET_BTN)) {
+ #if defined(CONFIG_GPIO_RESET_BTN_ACTIVE_LOW)
+ return 0;
+ #else
+ return 1;
+ #endif
+ } else {
+ #if defined(CONFIG_GPIO_RESET_BTN_ACTIVE_LOW)
+ return 1;
+ #else
+ return 0;
+ #endif
+ }
+#else
+ return 0;
+#endif
+}
+
+/*
+ * Returns main CPU clock in Hz
+ */
+u32 main_cpu_clk(void)
+{
+ u32 cpu_clk;
+
+ qca_sys_clocks(&cpu_clk, NULL, NULL, NULL, NULL);
+
+ return cpu_clk;
+}
+
+/*
+ * Calls full chip reset
+ */
+void full_reset(void)
+{
+ qca_full_chip_reset();
+}
+++ /dev/null
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <ar7240_soc.h>
-
-/*
- * Helper macros.
- * These Clobber t7, t8 and t9
- */
-#define clear_mask(_reg, _mask) \
- li t7, KSEG1ADDR(_reg); \
- lw t8, 0(t7); \
- li t9, ~_mask; \
- and t8, t8, t9; \
- sw t8, 0(t7)
-
-#define set_val(_reg, _mask, _val) \
- li t7, KSEG1ADDR(_reg); \
- lw t8, 0(t7); \
- li t9, ~_mask; \
- and t8, t8, t9; \
- li t9, _val; \
- or t8, t8, t9; \
- sw t8, 0(t7)
-
-#define set_val_f(_reg, _mask, _val) \
- li t7, KSEG1ADDR(_reg); \
- lw t8, 0(t7); \
- li t9, ~_mask; \
- and t8, t8, t9; \
- li t6, KSEG1ADDR(_val); \
- lw t9, 0(t6); \
- or t8, t8, t9; \
- sw t8, 0(t7)
-
-
-#define get_val(_reg, _mask, _shift, _res_reg) \
- li t7, KSEG1ADDR(_reg); \
- lw t8, 0(t7); \
- li t9, _mask; \
- and t8, t8, t9; \
- srl _res_reg, t8, _shift \
-
-#define pll_clr(_mask) \
- clear_mask(AR7240_CPU_PLL_CONFIG, _mask)
-
-#define pll_set(_mask, _val) \
- set_val(AR7240_CPU_PLL_CONFIG, _mask, _val)
-
-#define pll_set_f(_mask, _val) \
- set_val_f(AR7240_CPU_PLL_CONFIG, _mask, _val)
-
-#define pll_get(_mask, _shift, _res_reg) \
- get_val(AR7240_CPU_PLL_CONFIG, _mask, _shift, _res_reg)
-
-#define clk_clr(_mask) \
- clear_mask(AR7240_CPU_CLOCK_CONTROL, _mask)
-
-#define clk_set(_mask, _val) \
- set_val(AR7240_CPU_CLOCK_CONTROL, _mask, _val)
-
-#define clk_get(_mask, _shift, _res_reg) \
- get_val(AR7240_CPU_CLOCK_CONTROL, _mask, _shift, _res_reg)
-
-
-/******************************************************************************
- * first level initialization:
- *
- * 0) If clock cntrl reset switch is already set, we're recovering from
- * "divider reset"; goto 3.
- * 1) Setup divide ratios.
- * 2) Reset.
- * 3) Setup pll's, wait for lock.
- *
- *****************************************************************************/
-
-.globl lowlevel_init
-
-lowlevel_init:
- /*
- * The code below is for the real chip. Wont work on FPGA
- */
-
- b hornet_pll_init
- jr ra
- nop
-
+++ /dev/null
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <ar7240_soc.h>
-
-/*
- * Helper macros.
- * These Clobber t7, t8 and t9
- */
-#define cpu_ddr_control_set(_mask, _val) set_val(AR934X_CPU_DDR_CLOCK_CONTROL, _mask, _val)
-
-#define set_val(_reg, _mask, _val) \
- li t7, KSEG1ADDR(_reg); \
- lw t8, 0(t7); \
- li t9, ~_mask; \
- and t8, t8, t9; \
- li t9, _val; \
- or t8, t8, t9; \
- sw t8, 0(t7)
-
-#define set_bb_pll(reg, val) \
- li t7, KSEG1ADDR(reg); \
- li t8, val; \
- sw t8, 0(t7);
-
-#define set_srif_pll(reg, val) \
- li t7, KSEG1ADDR(reg); \
- li t8, val; \
- sw t8, 0(t7);
-
-#define set_srif_pll_reg(reg, _r) \
- li t7, KSEG1ADDR(reg); \
- sw _r, 0(t7);
-
-#define inc_loop_count(loc) \
- li t9, loc; \
- lw t7, 0(t9); \
- addi t7, t7, 1; \
- sw t7, 0(t9);
-
-#define clear_loop_count(loc) \
- li t9, loc; \
- sw zero, 0(t9);
-
-/******************************************************************************
- * first level initialization:
- *
- * 0) If clock cntrl reset switch is already set, we're recovering from
- * "divider reset"; goto 3.
- * 1) Setup divide ratios.
- * 2) Reset.
- * 3) Setup pll's, wait for lock.
- *
- *****************************************************************************/
-
-.globl lowlevel_init
- .type lowlevel_init, @function
- .text
- .align 4
-
-lowlevel_init:
- set_bb_pll(DPLL2_ADDRESS_c4, 0x13210f00); // 0x181161c4 (AR934X_SRIF_CPU_DPLL2_REG)
- set_bb_pll(DPLL3_ADDRESS_c8, 0x03000000); // 0x181161c8 (AR934X_SRIF_CPU_DPLL3_REG)
- set_bb_pll(DPLL2_ADDRESS_44, 0x13210f00); // 0x18116244 (AR934X_SRIF_DDR_DPLL2_REG)
- set_bb_pll(DPLL3_ADDRESS_48, 0x03000000); // 0x18116248 (AR934X_SRIF_DDR_DPLL3_REG)
- set_bb_pll(DPLL3_ADDRESS_88, 0x03000000); // 0x18116188 (??)
-
-ref_recognition:
- li t5, KSEG1ADDR(WASP_BOOTSTRAP_REG);
- li t6, WASP_REF_CLK_25
- lw t7, 0(t5);
- and t6, t7, t6
- beq zero, t6, setup_ref25_val
- nop
-
-setup_ref40_val:
- li t5, CPU_PLL_CONFIG_NINT_VAL_40
- li t6, DDR_PLL_CONFIG_NINT_VAL_40
- li t7, CPU_PLL_NFRAC_40
- li t9, DDR_PLL_NFRAC_40
- b 1f
- nop
-
-setup_ref25_val:
- li t5, CPU_PLL_CONFIG_NINT_VAL_25
- li t6, DDR_PLL_CONFIG_NINT_VAL_25
- li t7, CPU_PLL_NFRAC_25
- li t9, DDR_PLL_NFRAC_25
-
-1:
- li t4, (CPU_PLL_DITHER_DITHER_EN_SET(0) | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf));
- or t4, t4, t7
-
- li t8, (CPU_PLL_CONFIG_REF_DIV_VAL | CPU_PLL_CONFIG_RANGE_VAL | CPU_PLL_CONFIG_OUT_DIV_VAL2);
- or t5, t5, t8
-
- li t8, (DDR_PLL_CONFIG_REF_DIV_VAL | DDR_PLL_CONFIG_RANGE_VAL | DDR_PLL_CONFIG_OUT_DIV_VAL2);
- or t6, t6, t8
-
- li t3, (DDR_PLL_DITHER_DITHER_EN_SET(0) | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf));
- or t3, t3, t9
-
-pll_bypass_set:
- cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1));
- cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1));
- cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
-
-init_cpu_pll:
- li t7, KSEG1ADDR(AR934X_CPU_PLL_CONFIG);
- li t8, CPU_PLL_CONFIG_PLLPWD_SET(1)
- or t8, t8, t5
- sw t8, 0(t7);
-
-init_ddr_pll:
- li t7, KSEG1ADDR(AR934X_DDR_PLL_CONFIG);
- li t8, DDR_PLL_CONFIG_PLLPWD_SET(1)
- or t8, t8, t6
- sw t8, 0(t7);
-
-init_ahb_pll:
- li t7, KSEG1ADDR(AR934X_CPU_DDR_CLOCK_CONTROL);
- li t8, (CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL | \
- CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR | \
- CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR | \
- CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU | \
- CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV | \
- CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV | \
- CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1) | \
- CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) | \
- CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
- sw t8, 0(t7);
-
- /* Use built in values, based on ref clock */
- li t5, KSEG1ADDR(WASP_BOOTSTRAP_REG);
- li t6, WASP_REF_CLK_25
- lw t7, 0(t5);
- and t6, t7, t6
- beq zero, t6, 1f
- nop
-#if !defined(CONFIG_AP123)
- /* refdiv nint nfrac */
- li t4, ((0x8 << 27) | (112 << 18) | 0);// cpu freq = (40 MHz refclk/refdiv 8) * Nint
- li t5, ((0x8 << 27) | (90 << 18) | 0); // ddr freq = (40 MHz refclk/refdiv 8) * Nint
- j 2f
- nop
-1:
- li t4, ((0x5 << 27) | (112 << 18) | 0);// cpu freq = (25 MHz refclk/refdiv 5) * Nint
- li t5, ((0x5 << 27) | (90 << 18) | 0); // ddr freq = (25 MHz refclk/refdiv 5) * Nint
- j 2f
- nop
-#else /* defined(CONFIG_AP123) */
- /* refdiv nint nfrac */
- li t4, ((0x8 << 27) | (107 << 18) | 0);// cpu freq = (40 MHz refclk/refdiv 8) * Nint
- li t5, ((0x8 << 27) | (160 << 18) | 0);// ddr freq = (40 MHz refclk/refdiv 8) * Nint
- j 2f
- nop
-1:
- li t4, ((0x5 << 27) | (107 << 18) | 0);// cpu freq = (25 MHz refclk/refdiv 5) * Nint
- li t5, ((0x5 << 27) | (160 << 18) | 0);// ddr freq = (25 MHz refclk/refdiv 5) * Nint
- j 2f
- nop
-#endif /* !defined(CONFIG_AP123) */
-
-/* CPU */
-2:
- clear_loop_count(ATH_CPU_COUNT_LOC);
-
-cpu_pll_is_not_locked:
- inc_loop_count(ATH_CPU_COUNT_LOC);
- set_srif_pll(0xb81161c4, (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16));
- set_srif_pll_reg(0xb81161c0, t4);
- set_srif_pll(0xb81161c4, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16));
- set_srif_pll(0xb81161c8, (6 << 23));
- set_srif_pll(0xb81161c4, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7));
-
-cpu_clear_do_meas1:
- li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS)
- lw t8, 0(t7)
- li t9, ~CPU_DPLL3_DO_MEAS_SET(1)
- and t8, t8, t9
- sw t8, 0(t7)
-
-cpu_set_do_meas:
- li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS)
- lw t8, 0(t7)
- li t9, CPU_DPLL3_DO_MEAS_SET(1)
- or t8, t8, t9
- sw t8, 0(t7)
- li t7, KSEG1ADDR(CPU_DPLL4_ADDRESS)
-
-cpu_wait_for_meas_done:
- lw t8, 0(t7)
- andi t8, t8, CPU_DPLL4_MEAS_DONE_SET(1)
- beqz t8, cpu_wait_for_meas_done
- nop
-
-cpu_clear_do_meas2:
- li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS)
- lw t8, 0(t7)
- li t9, ~CPU_DPLL3_DO_MEAS_SET(1)
- and t8, t8, t9
- sw t8, 0(t7)
-
-cpu_read_sqsum_dvc:
- li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS)
- lw t8, 0(t7)
- li t9, CPU_DPLL3_SQSUM_DVC_MASK
- and t8, t8, t9
- sra t8, t8, CPU_DPLL3_SQSUM_DVC_LSB
- li t9, 0x40000
- subu t8, t8, t9
- bgez t8, cpu_pll_is_not_locked
- nop
-
-/* DDR */
- clear_loop_count(ATH_DDR_COUNT_LOC)
-
-ddr_pll_is_not_locked:
- inc_loop_count(ATH_DDR_COUNT_LOC)
-#if !defined(CONFIG_AP123)
- set_srif_pll(0xb8116244, (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16));
- set_srif_pll_reg(0xb8116240, t5);
- set_srif_pll(0xb8116244, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16));
- set_srif_pll(0xb8116248, (6 << 23));
- set_srif_pll(0xb8116244, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7));
-#else /* defined(CONFIG_AP123) */
- /* AP123 uses outdiv = 1 for ddr pll */
- set_srif_pll(0xb8116244, (0x4 << 26) | (0x10 << 19) | (1 << 13) | (0x1e << 7) | (1 << 16));
- set_srif_pll_reg(0xb8116240, t5);
- set_srif_pll(0xb8116244, (0x1 << 30) | (0x4 << 26) | (0x10 << 19) | (1 << 13) | (0x1e << 7) | (1 << 16));
- set_srif_pll(0xb8116248, (6 << 23));
- set_srif_pll(0xb8116244, (0x1 << 30) | (0x4 << 26) | (0x10 << 19) | (1 << 13) | (0x1e << 7));
-#endif /* !defined(CONFIG_AP123) */
-
-ddr_clear_do_meas1:
- li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS)
- lw t8, 0(t7)
- li t9, ~DDR_DPLL3_DO_MEAS_SET(1)
- and t8, t8, t9
- sw t8, 0(t7)
-
-ddr_set_do_meas:
- li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS)
- lw t8, 0(t7)
- li t9, DDR_DPLL3_DO_MEAS_SET(1)
- or t8, t8, t9
- sw t8, 0(t7)
- li t7, KSEG1ADDR(DDR_DPLL4_ADDRESS)
-
-ddr_wait_for_meas_done:
- lw t8, 0(t7)
- andi t8, t8, DDR_DPLL4_MEAS_DONE_SET(1)
- beqz t8, ddr_wait_for_meas_done
- nop
-
-ddr_clear_do_meas2:
- li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS)
- lw t8, 0(t7)
- li t9, ~DDR_DPLL3_DO_MEAS_SET(1)
- and t8, t8, t9
- sw t8, 0(t7)
-
-ddr_read_sqsum_dvc:
- li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS)
- lw t8, 0(t7)
- li t9, DDR_DPLL3_SQSUM_DVC_MASK
- and t8, t8, t9
- sra t8, t8, DDR_DPLL3_SQSUM_DVC_LSB
- li t9, 0x40000
- subu t8, t8, t9
- bgez t8, ddr_pll_is_not_locked
- nop
-
-pll_bypass_unset:
- cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0));
- cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0));
- cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0));
-
-ddr_pll_dither_unset:
- li t7, KSEG1ADDR(AR934X_DDR_PLL_DITHER);
- sw t3, 0(t7);
-
-cpu_pll_dither_unset:
- li t7, KSEG1ADDR(AR934X_CPU_PLL_DITHER);
- sw t4, 0(t7);
-
- jr ra
- nop
--- /dev/null
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+
+#include <atheros.h>
+#include "qca-eth-953x.h"
+#include "qca-eth-953x_phy.h"
+#define SGMII_LINK_WAR_MAX_TRY 10
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <miiphy.h>
+#endif
+#define ath_gmac_unit2mac(_unit) ath_gmac_macs[(_unit)]
+#define ath_gmac_name2mac(name) is_drqfn() ? ath_gmac_unit2mac(1):strcmp(name,"eth0") ? ath_gmac_unit2mac(1) : ath_gmac_unit2mac(0)
+
+int ath_gmac_miiphy_read(char *devname, uint32_t phaddr, uint8_t reg, uint16_t *data);
+int ath_gmac_miiphy_write(char *devname, uint32_t phaddr, uint8_t reg, uint16_t data);
+extern void ath_sys_frequency(uint32_t *, uint32_t *, uint32_t *);
+
+#ifndef CFG_ATH_GMAC_NMACS
+#define CFG_ATH_GMAC_NMACS 1
+#endif /* CFG_ATH_GMAC_NMACS */
+
+ath_gmac_mac_t *ath_gmac_macs[CFG_ATH_GMAC_NMACS];
+
+
+
+#ifdef CFG_ATHRS27_PHY
+#define is_s27() 1
+
+#else
+#define is_s27() 0
+
+#endif
+#ifdef CFG_ATHRS27_PHY
+extern void athrs27_reg_init(void);
+extern void athrs27_reg_init_wan(void);
+#endif
+
+#ifdef CONFIG_VIR_PHY
+extern int athr_vir_phy_setup(int unit);
+extern int athr_vir_phy_is_up(int unit);
+extern int athr_vir_phy_is_fdx(int unit);
+extern int athr_vir_phy_speed(int unit);
+extern void athr_vir_reg_init(void);
+#endif
+
+static int
+ath_gmac_send(struct eth_device *dev, volatile void *packet, int length)
+{
+ int i;
+
+ ath_gmac_mac_t *mac = (ath_gmac_mac_t *)dev->priv;
+
+ ath_gmac_desc_t *f = mac->fifo_tx[mac->next_tx];
+
+ f->pkt_size = length;
+ f->res1 = 0;
+ f->pkt_start_addr = virt_to_phys(packet);
+
+ ath_gmac_tx_give_to_dma(f);
+ flush_cache((u32) packet, length);
+ ath_gmac_reg_wr(mac, ATH_DMA_TX_DESC, virt_to_phys(f));
+ ath_gmac_reg_wr(mac, ATH_DMA_TX_CTRL, ATH_TXE);
+
+ for (i = 0; i < MAX_WAIT; i++) {
+ udelay(10);
+ if (!ath_gmac_tx_owned_by_dma(f))
+ break;
+ }
+ if (i == MAX_WAIT)
+ printf("Tx Timed out\n");
+
+ f->pkt_start_addr = 0;
+ f->pkt_size = 0;
+
+ if (++mac->next_tx >= NO_OF_TX_FIFOS)
+ mac->next_tx = 0;
+
+ return (0);
+}
+
+static int ath_gmac_recv(struct eth_device *dev)
+{
+ int length;
+ ath_gmac_desc_t *f;
+ ath_gmac_mac_t *mac;
+ volatile int dmaed_pkt=0;
+ int count = 0;
+
+ mac = (ath_gmac_mac_t *)dev->priv;
+
+ for (;;) {
+ f = mac->fifo_rx[mac->next_rx];
+ if (ath_gmac_rx_owned_by_dma(f)) {
+ /* check if the current Descriptor is_empty is 1,But the DMAed count is not-zero
+ then move to desciprot where the packet is available */
+ dmaed_pkt = (ath_gmac_reg_rd(mac, 0x194) >> 16);
+ if (!dmaed_pkt) {
+ break ;
+ } else {
+ if (f->is_empty == 1) {
+ while (count < NO_OF_RX_FIFOS) {
+ if (++mac->next_rx >= NO_OF_RX_FIFOS) {
+ mac->next_rx = 0;
+ }
+ f = mac->fifo_rx[mac->next_rx];
+ /*
+ * Break on valid data in the desc by checking
+ * empty bit.
+ */
+ if (!f->is_empty) {
+ count = 0;
+ break;
+ }
+ count++;
+ }
+ }
+ }
+ }
+
+ length = f->pkt_size;
+
+ NetReceive(NetRxPackets[mac->next_rx] , length - 4);
+ flush_cache((u32) NetRxPackets[mac->next_rx] , PKTSIZE_ALIGN);
+
+ ath_gmac_reg_wr(mac,0x194,1);
+ ath_gmac_rx_give_to_dma(f);
+
+ if (++mac->next_rx >= NO_OF_RX_FIFOS)
+ mac->next_rx = 0;
+ }
+
+ if (!(ath_gmac_reg_rd(mac, ATH_DMA_RX_CTRL))) {
+ ath_gmac_reg_wr(mac, ATH_DMA_RX_DESC, virt_to_phys(f));
+ ath_gmac_reg_wr(mac, ATH_DMA_RX_CTRL, 1);
+ }
+
+ return (0);
+}
+
+void ath_gmac_mii_setup(ath_gmac_mac_t *mac)
+{
+ u32 mgmt_cfg_val;
+
+ ath_reg_wr(SWITCH_CLOCK_SPARE_ADDRESS, 0x231);
+ //ath_reg_wr(SWITCH_CLOCK_SPARE_ADDRESS, 0x520);
+ if ((mac->mac_unit == 1)) {
+ //printf("Honey Bee ----> MAC 1 S27 PHY *\n");
+ ath_reg_wr(ATH_ETH_CFG, ETH_CFG_ETH_RXDV_DELAY_SET(3) |
+ ETH_CFG_ETH_RXD_DELAY_SET(3)|
+ ETH_CFG_RGMII_GE0_SET(1));
+
+ ath_reg_wr(ETH_XMII_ADDRESS, ETH_XMII_TX_INVERT_SET(1) |
+ ETH_XMII_RX_DELAY_SET(2) |
+ ETH_XMII_TX_DELAY_SET(1) |
+ ETH_XMII_GIGE_SET(1));
+ mgmt_cfg_val = 2;
+ udelay(1000);
+ ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+ return;
+ }
+
+ if (is_vir_phy()) {
+ //printf("Honey Bee ---->VIR PHY*\n");
+
+ ath_reg_wr(ATH_ETH_CFG, ETH_CFG_ETH_RXDV_DELAY_SET(3) |
+ ETH_CFG_ETH_RXD_DELAY_SET(3)|
+ ETH_CFG_RGMII_GE0_SET(1));
+ ath_reg_wr(ETH_XMII_ADDRESS, ETH_XMII_TX_INVERT_SET(1) |
+ ETH_XMII_RX_DELAY_SET(2) |
+ ETH_XMII_TX_DELAY_SET(1) |
+ ETH_XMII_GIGE_SET(1));
+ udelay(1000);
+ ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+
+ return;
+ }
+ if (is_s27()) {
+ mgmt_cfg_val = 2;
+ //printf("Scorpion ---->S27 PHY*\n");
+ ath_reg_wr(ETH_CFG_ADDRESS, ETH_CFG_MII_GE0_SET(1)|
+ ETH_CFG_MII_GE0_SLAVE_SET(1));
+ udelay(1000);
+ ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+
+ }
+
+
+
+
+}
+
+
+static void ath_gmac_hw_start(ath_gmac_mac_t *mac)
+{
+
+
+ if(mac->mac_unit)
+ {
+ ath_gmac_reg_rmw_set(mac, ATH_MAC_CFG2, (ATH_MAC_CFG2_PAD_CRC_EN |
+ ATH_MAC_CFG2_LEN_CHECK | ATH_MAC_CFG2_IF_1000));
+ } else {
+
+
+ ath_gmac_reg_rmw_set(mac, ATH_MAC_CFG2, (ATH_MAC_CFG2_PAD_CRC_EN |
+ ATH_MAC_CFG2_LEN_CHECK | ATH_MAC_CFG2_IF_10_100));
+ }
+ ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_0, 0x1f00);
+
+
+ ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_1, 0x10ffff);
+ ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_2, 0xAAA0555);
+
+ ath_gmac_reg_rmw_set(mac, ATH_MAC_FIFO_CFG_4, 0x3ffff);
+ /*
+ * Setting Drop CRC Errors, Pause Frames,Length Error frames
+ * and Multi/Broad cast frames.
+ */
+
+ ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_5, 0x7eccf);
+
+ ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_3, 0x1f00140);
+
+ //printf(": cfg1 %#x cfg2 %#x\n", ath_gmac_reg_rd(mac, ATH_MAC_CFG1),
+ // ath_gmac_reg_rd(mac, ATH_MAC_CFG2));
+
+
+}
+
+static int ath_gmac_check_link(ath_gmac_mac_t *mac)
+{
+ int link, duplex, speed;
+
+ ath_gmac_phy_link(mac->mac_unit, &link);
+ ath_gmac_phy_duplex(mac->mac_unit, &duplex);
+ ath_gmac_phy_speed(mac->mac_unit, &speed);
+
+ mac->link = link;
+
+ if(!mac->link) {
+ printf("%s link down\n",mac->dev->name);
+ return 0;
+ }
+
+ switch (speed)
+ {
+ case _1000BASET:
+ ath_gmac_set_mac_if(mac, 1);
+ ath_gmac_reg_rmw_set(mac, ATH_MAC_FIFO_CFG_5, (1 << 19));
+ break;
+
+ case _100BASET:
+ ath_gmac_set_mac_if(mac, 0);
+ ath_gmac_set_mac_speed(mac, 1);
+ ath_gmac_reg_rmw_clear(mac, ATH_MAC_FIFO_CFG_5, (1 << 19));
+ break;
+
+ case _10BASET:
+ ath_gmac_set_mac_if(mac, 0);
+ ath_gmac_set_mac_speed(mac, 0);
+ ath_gmac_reg_rmw_clear(mac, ATH_MAC_FIFO_CFG_5, (1 << 19));
+ break;
+
+ default:
+ printf("Invalid speed detected\n");
+ return 0;
+ }
+
+ if (mac->link && (duplex == mac->duplex) && (speed == mac->speed))
+ return 1;
+
+ mac->duplex = duplex;
+ mac->speed = speed;
+
+ printf("dup %d speed %d\n", duplex, speed);
+
+ ath_gmac_set_mac_duplex(mac,duplex);
+
+ return 1;
+}
+
+/*
+ * For every command we re-setup the ring and start with clean h/w rx state
+ */
+static int ath_gmac_clean_rx(struct eth_device *dev, bd_t * bd)
+{
+
+ int i;
+ ath_gmac_desc_t *fr;
+ ath_gmac_mac_t *mac = (ath_gmac_mac_t*)dev->priv;
+
+ if (!ath_gmac_check_link(mac))
+ return 0;
+
+ mac->next_rx = 0;
+
+ ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_0, 0x1f00);
+ ath_gmac_reg_wr(mac, ATH_MAC_CFG1, (ATH_MAC_CFG1_RX_EN | ATH_MAC_CFG1_TX_EN));
+
+ for (i = 0; i < NO_OF_RX_FIFOS; i++) {
+ fr = mac->fifo_rx[i];
+ fr->pkt_start_addr = virt_to_phys(NetRxPackets[i]);
+ flush_cache((u32) NetRxPackets[i], PKTSIZE_ALIGN);
+ ath_gmac_rx_give_to_dma(fr);
+ }
+
+ ath_gmac_reg_wr(mac, ATH_DMA_RX_DESC, virt_to_phys(mac->fifo_rx[0]));
+ ath_gmac_reg_wr(mac, ATH_DMA_RX_CTRL, ATH_RXE); /* rx start */
+ udelay(1000 * 1000);
+
+
+ return 1;
+
+}
+
+static int ath_gmac_alloc_fifo(int ndesc, ath_gmac_desc_t ** fifo)
+{
+ int i;
+ u32 size;
+ uchar *p = NULL;
+
+ size = sizeof(ath_gmac_desc_t) * ndesc;
+ size += CFG_CACHELINE_SIZE - 1;
+
+ if ((p = malloc(size)) == NULL) {
+ //printf("Cant allocate fifos\n");
+ return -1;
+ }
+
+ p = (uchar *) (((u32) p + CFG_CACHELINE_SIZE - 1) &
+ ~(CFG_CACHELINE_SIZE - 1));
+ p = UNCACHED_SDRAM(p);
+
+ for (i = 0; i < ndesc; i++)
+ fifo[i] = (ath_gmac_desc_t *) p + i;
+
+ return 0;
+}
+
+static int ath_gmac_setup_fifos(ath_gmac_mac_t *mac)
+{
+ int i;
+
+ if (ath_gmac_alloc_fifo(NO_OF_TX_FIFOS, mac->fifo_tx))
+ return 1;
+
+ for (i = 0; i < NO_OF_TX_FIFOS; i++) {
+ mac->fifo_tx[i]->next_desc = (i == NO_OF_TX_FIFOS - 1) ?
+ virt_to_phys(mac->fifo_tx[0]) : virt_to_phys(mac->fifo_tx[i + 1]);
+ ath_gmac_tx_own(mac->fifo_tx[i]);
+ }
+
+ if (ath_gmac_alloc_fifo(NO_OF_RX_FIFOS, mac->fifo_rx))
+ return 1;
+
+ for (i = 0; i < NO_OF_RX_FIFOS; i++) {
+ mac->fifo_rx[i]->next_desc = (i == NO_OF_RX_FIFOS - 1) ?
+ virt_to_phys(mac->fifo_rx[0]) : virt_to_phys(mac->fifo_rx[i + 1]);
+ }
+
+ return (1);
+}
+
+static void ath_gmac_halt(struct eth_device *dev)
+{
+ ath_gmac_mac_t *mac = (ath_gmac_mac_t *)dev->priv;
+ ath_gmac_reg_rmw_clear(mac, ATH_MAC_CFG1,(ATH_MAC_CFG1_RX_EN | ATH_MAC_CFG1_TX_EN));
+ ath_gmac_reg_wr(mac,ATH_MAC_FIFO_CFG_0,0x1f1f);
+ ath_gmac_reg_wr(mac,ATH_DMA_RX_CTRL, 0);
+ while (ath_gmac_reg_rd(mac, ATH_DMA_RX_CTRL));
+}
+
+unsigned char *
+ath_gmac_mac_addr_loc(void)
+{
+#ifdef BOARDCAL
+ /*
+ ** BOARDCAL environmental variable has the address of the cal sector
+ */
+
+ return ((unsigned char *)BOARDCAL);
+
+#else
+ /* MAC address is store in the 2nd 4k of last sector */
+ return ((unsigned char *)
+ (KSEG1ADDR(ATH_SPI_BASE) + (4 * 1024) +
+ flash_info[0].size - (64 * 1024) /* sector_size */ ));
+#endif
+}
+
+static void ath_gmac_get_ethaddr(struct eth_device *dev)
+{
+ unsigned char *eeprom;
+ unsigned char *mac = dev->enetaddr;
+#ifndef CONFIG_ATH_EMULATION
+
+ eeprom = ath_gmac_mac_addr_loc();
+
+ if (strcmp(dev->name, "eth0") == 0) {
+ memcpy(mac, eeprom, 6);
+ } else if (strcmp(dev->name, "eth1") == 0) {
+ eeprom += 6;
+ memcpy(mac, eeprom, 6);
+ } else {
+ //printf("%s: unknown ethernet device %s\n", __func__, dev->name);
+ return;
+ }
+ /* Use fixed address if the above address is invalid */
+ if (mac[0] != 0x00 || (mac[0] == 0xff && mac[5] == 0xff))
+#else
+ if (1)
+#endif
+ {
+ mac[0] = 0xba;
+ mac[1] = 0xbe;
+ mac[2] = 0xfa;
+ mac[3] = 0xce;
+ mac[4] = 0x08;
+ mac[5] = 0x41;
+ /*printf("No valid address in Flash. Using fixed address\n");*/
+ }
+}
+
+void
+athr_mgmt_init(void)
+{
+
+#ifdef CONFIG_MGMT_INIT
+ uint32_t rddata;
+
+ rddata = ath_reg_rd(GPIO_IN_ENABLE3_ADDRESS)&
+ ~GPIO_IN_ENABLE3_MII_GE1_MDI_MASK;
+ rddata |= GPIO_IN_ENABLE3_MII_GE1_MDI_SET(19);
+ ath_reg_wr(GPIO_IN_ENABLE3_ADDRESS, rddata);
+
+ ath_reg_rmw_clear(GPIO_OE_ADDRESS, (1 << 19));
+
+ ath_reg_rmw_clear(GPIO_OE_ADDRESS, (1 << 17));
+
+
+ rddata = ath_reg_rd(GPIO_OUT_FUNCTION4_ADDRESS) &
+ ~ (GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK |
+ GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK);
+
+ rddata |= GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(0x20) |
+ GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(0x21);
+
+ ath_reg_wr(GPIO_OUT_FUNCTION4_ADDRESS, rddata);
+#endif
+ //printf ("%s ::done\n",__func__);
+}
+
+int ath_gmac_enet_initialize(bd_t * bis)
+{
+ struct eth_device *dev[CFG_ATH_GMAC_NMACS];
+ u32 mask, mac_h, mac_l;
+ int i;
+
+ //printf("%s...\n", __func__);
+
+ /* Switch Analog and digital reset seq */
+ mask = ATH_RESET_GE1_PHY | ATH_RESET_GE0_PHY;
+ ath_reg_rmw_set(RST_RESET_ADDRESS, mask);
+
+ udelay(1000 * 100);
+ mask = ATH_RESET_GE1_PHY ;
+ ath_reg_rmw_clear(RST_RESET_ADDRESS, mask);
+
+ udelay(1000 * 100);
+ mask = ATH_RESET_GE0_PHY ;
+ ath_reg_rmw_clear(RST_RESET_ADDRESS, mask);
+ udelay(100);
+
+
+ for (i = 0;i < CFG_ATH_GMAC_NMACS;i++) {
+
+ if ((dev[i] = (struct eth_device *) malloc(sizeof (struct eth_device))) == NULL) {
+ puts("malloc failed\n");
+ return 0;
+ }
+
+ if ((ath_gmac_macs[i] = (ath_gmac_mac_t *) malloc(sizeof (ath_gmac_mac_t))) == NULL) {
+ puts("malloc failed\n");
+ return 0;
+ }
+
+ memset(ath_gmac_macs[i], 0, sizeof(ath_gmac_macs[i]));
+ memset(dev[i], 0, sizeof(dev[i]));
+
+ sprintf(dev[i]->name, "eth%d", i);
+ ath_gmac_get_ethaddr(dev[i]);
+
+ ath_gmac_macs[i]->mac_unit = i;
+ ath_gmac_macs[i]->mac_base = i ? ATH_GE1_BASE : ATH_GE0_BASE ;
+ ath_gmac_macs[i]->dev = dev[i];
+
+ dev[i]->iobase = 0;
+ dev[i]->init = ath_gmac_clean_rx;
+ dev[i]->halt = ath_gmac_halt;
+ dev[i]->send = ath_gmac_send;
+ dev[i]->recv = ath_gmac_recv;
+ dev[i]->priv = (void *)ath_gmac_macs[i];
+ }
+
+ for (i = 0;i < CFG_ATH_GMAC_NMACS;i++) {
+
+ if(!i) {
+ mask = (ATH_RESET_GE0_MAC | ATH_RESET_GE1_MAC | ATH_RESET_GE0_MDIO | ATH_RESET_GE1_MDIO);
+
+
+ //printf("%s: reset mask:%x \n", __func__, mask);
+
+ ath_reg_rmw_set(RST_RESET_ADDRESS, mask);
+ udelay(1000 * 100);
+
+ mask = mask | ATH_RESET_GE0_MDIO | ATH_RESET_GE1_MDIO;
+ ath_reg_rmw_clear(RST_RESET_ADDRESS, mask);
+ udelay(1000 * 100);
+
+ udelay(10 * 1000);
+ }
+#if defined(CONFIG_MGMT_INIT) && defined (CONFIG_ATHR_SWITCH_ONLY_MODE) || defined ATH_MDC_GPIO
+ if (!i)
+ athr_mgmt_init();
+
+ if (ath_gmac_macs[i]->mac_unit == 0)
+ continue;
+#endif
+ eth_register(dev[i]);
+#if(CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register(dev[i]->name, ath_gmac_miiphy_read, ath_gmac_miiphy_write);
+#endif
+ ath_gmac_mii_setup(ath_gmac_macs[i]);
+
+ /* if using header for register configuration, we have to */
+ /* configure s26 register after frame transmission is enabled */
+
+ if (ath_gmac_macs[i]->mac_unit == 0) { /* WAN Phy */
+#ifdef CFG_ATHRS27_PHY
+ //printf("S27 reg init\n");
+ athrs27_reg_init();
+ mask = ATH_RESET_GE0_MAC;
+ ath_reg_rmw_clear(RST_RESET_ADDRESS, mask);
+#endif
+
+#ifdef CONFIG_VIR_PHY
+ //printf("VIRPhy reg init \n");
+ athr_vir_reg_init();
+#endif
+ } else {
+#ifdef CFG_ATHRS27_PHY
+ //printf("S27 reg init\n");
+ athrs27_reg_init_lan();
+ mask = ATH_RESET_GE1_MAC;
+ ath_reg_rmw_clear(RST_RESET_ADDRESS, mask);
+#endif
+
+ }
+
+ ath_gmac_reg_rmw_set(ath_gmac_macs[i], ATH_MAC_CFG1, ATH_MAC_CFG1_SOFT_RST
+ | ATH_MAC_CFG1_RX_RST | ATH_MAC_CFG1_TX_RST);
+
+
+ ath_gmac_hw_start(ath_gmac_macs[i]);
+ ath_gmac_setup_fifos(ath_gmac_macs[i]);
+
+
+
+ udelay(100 * 1000);
+
+ {
+ unsigned char *mac = dev[i]->enetaddr;
+
+ //printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name,
+ // mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff,
+ // mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
+ }
+ mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
+ mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) |
+ (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
+
+ ath_gmac_reg_wr(ath_gmac_macs[i], ATH_GE_MAC_ADDR1, mac_l);
+ ath_gmac_reg_wr(ath_gmac_macs[i], ATH_GE_MAC_ADDR2, mac_h);
+
+
+ ath_gmac_phy_setup(ath_gmac_macs[i]->mac_unit);
+ //printf("%s up\n",dev[i]->name);
+ }
+
+
+ return 1;
+}
+
+//#if (CONFIG_COMMANDS & CFG_CMD_MII)
+int
+ath_gmac_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t *data)
+{
+ ath_gmac_mac_t *mac = ath_gmac_name2mac(devname);
+ uint16_t addr = (phy_addr << ATH_ADDR_SHIFT) | reg, val;
+ volatile int rddata;
+ uint16_t ii = 0xFFFF;
+
+
+ /*
+ * Check for previous transactions are complete. Added to avoid
+ * race condition while running at higher frequencies.
+ */
+ do
+ {
+ udelay(5);
+ rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1;
+ }while(rddata && --ii);
+
+ if (ii == 0)
+ printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
+
+
+ ath_gmac_reg_wr(mac, ATH_MII_MGMT_CMD, 0x0);
+ ath_gmac_reg_wr(mac, ATH_MII_MGMT_ADDRESS, addr);
+ ath_gmac_reg_wr(mac, ATH_MII_MGMT_CMD, ATH_MGMT_CMD_READ);
+
+ do
+ {
+ udelay(5);
+ rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1;
+ }while(rddata && --ii);
+
+ if(ii==0)
+ printf("Error!!! Leave ath_gmac_miiphy_read without polling correct status!\n");
+
+ val = ath_gmac_reg_rd(mac, ATH_MII_MGMT_STATUS);
+ ath_gmac_reg_wr(mac, ATH_MII_MGMT_CMD, 0x0);
+
+ if (data != NULL)
+ *data = val;
+
+ return val;
+}
+
+int
+ath_gmac_miiphy_write(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t data)
+{
+ ath_gmac_mac_t *mac = ath_gmac_name2mac(devname);
+ uint16_t addr = (phy_addr << ATH_ADDR_SHIFT) | reg;
+ volatile int rddata;
+ uint16_t ii = 0xFFFF;
+
+
+ /*
+ * Check for previous transactions are complete. Added to avoid
+ * race condition while running at higher frequencies.
+ */
+ do {
+ udelay(5);
+ rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1;
+ } while (rddata && --ii);
+
+ if (ii == 0)
+ printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
+
+ ath_gmac_reg_wr(mac, ATH_MII_MGMT_ADDRESS, addr);
+ ath_gmac_reg_wr(mac, ATH_MII_MGMT_CTRL, data);
+
+ do {
+ rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1;
+ } while (rddata && --ii);
+
+ if (ii == 0)
+ printf("Error!!! Leave ath_gmac_miiphy_write without polling correct status!\n");
+
+ return 0;
+}
+//#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
--- /dev/null
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __QCA_ETH_953X_H
+#define __QCA_ETH_953X_H
+
+#include <linux/types.h>
+
+#ifdef ATH_RGMII_CAL
+#define rgmii_cal_alg() rgmii_calib(mac);
+#else
+#define rgmii_cal_alg()
+#endif
+
+/*
+ * h/w descriptor
+ */
+typedef struct {
+ uint32_t pkt_start_addr,
+ is_empty : 1,
+ res1 : 10,
+ ftpp_override : 5,
+ res2 : 4,
+ pkt_size : 12,
+ next_desc;
+} ath_gmac_desc_t;
+
+#define NO_OF_TX_FIFOS 8
+#define NO_OF_RX_FIFOS 8
+
+typedef struct {
+ ath_gmac_desc_t *fifo_tx[NO_OF_TX_FIFOS],
+ *fifo_rx[NO_OF_RX_FIFOS];
+ struct eth_device *dev;
+ uint32_t next_tx,
+ next_rx,
+ link,
+ duplex,
+ speed,
+ mac_unit,
+ mac_base;
+} ath_gmac_mac_t;
+
+#define ath_gmac_reg_wr(_mac, _x, _y) ath_reg_wr(((_x) + _mac->mac_base), (_y))
+#define ath_gmac_reg_rd(_mac, _x) ath_reg_rd(((_x) + _mac->mac_base))
+
+#define ath_gmac_reg_rmw_set(_mac, _x, _y) \
+ ath_reg_rmw_set(((_x) + _mac->mac_base ), (_y))
+#define ath_gmac_reg_rmw_clear(_mac, _x, _y) \
+ ath_reg_rmw_clear(((_x) + _mac->mac_base), (_y))
+
+#ifdef COMPRESSED_UBOOT
+#define _1000BASET 1000
+#define _100BASET 100
+#define _10BASET 10
+#endif /* #ifdef COMPRESSED_UBOOT */
+
+/*
+ * spd is _1000BASET, _100BASET etc. defined in include/miiphy.h
+ */
+#define mii_reg(_mac) (ATH_MII0_CTRL + ((_mac)->mac_unit * 4))
+#define mii_if(_mac) (((_mac)->mac_unit == 0) ? mii0_if : mii1_if)
+
+#define ath_gmac_set_mii_ctrl_speed(_mac, _spd) do { \
+ ath_reg_rmw_clear(mii_reg(_mac), (3 << 4)); \
+ ath_reg_rmw_set(mii_reg(_mac), ((_spd) << 4)); \
+} while (0)
+
+#if defined (CFG_MII0_GMII)
+# define ath_gmac_get_mii_if() 0
+#elif defined (CFG_MII0_MII)
+# define ath_gmac_get_mii_if() 0
+#elif defined (CFG_MII0_RGMII)
+# define ath_gmac_get_mii_if() 0
+#elif defined (CFG_MII0_RMII)
+# define ath_gmac_get_mii_if() 0
+#endif
+
+#define MAX_WAIT 1000
+
+/*
+ * Config/Mac Register definitions
+ */
+#define ATH_MAC_CFG1 0x00
+#define ATH_MAC_CFG2 0x04
+#define ATH_MAC_IFCTL 0x38
+
+/*
+ * fifo control registers
+ */
+#define ATH_MAC_FIFO_CFG_0 0x48
+#define ATH_MAC_FIFO_CFG_1 0x4c
+#define ATH_MAC_FIFO_CFG_2 0x50
+#define ATH_MAC_FIFO_CFG_3 0x54
+#define ATH_MAC_FIFO_CFG_4 0x58
+
+#define ATH_MAC_FIFO_CFG_5 0x5c
+#define ATH_BYTE_PER_CLK_EN (1 << 19)
+
+#define ATH_MAC_FIFO_RAM_0 0x60
+#define ATH_MAC_FIFO_RAM_1 0x64
+#define ATH_MAC_FIFO_RAM_2 0x68
+#define ATH_MAC_FIFO_RAM_3 0x6c
+#define ATH_MAC_FIFO_RAM_4 0x70
+#define ATH_MAC_FIFO_RAM_5 0x74
+#define ATH_MAC_FIFO_RAM_6 0x78
+#define ATH_MAC_FIFO_RAM_7 0x7c
+
+/*
+ * fields
+ */
+#define ATH_MAC_CFG1_SOFT_RST (1 << 31)
+#define ATH_MAC_CFG1_RX_RST (1 << 19)
+#define ATH_MAC_CFG1_TX_RST (1 << 18)
+#define ATH_MAC_CFG1_LOOPBACK (1 << 8)
+#define ATH_MAC_CFG1_RX_EN (1 << 2)
+#define ATH_MAC_CFG1_TX_EN (1 << 0)
+
+#define ATH_MAC_CFG2_FDX (1 << 0)
+#define ATH_MAC_CFG2_PAD_CRC_EN (1 << 2)
+#define ATH_MAC_CFG2_LEN_CHECK (1 << 4)
+#define ATH_MAC_CFG2_HUGE_FRAME_EN (1 << 5)
+#define ATH_MAC_CFG2_IF_1000 (1 << 9)
+#define ATH_MAC_CFG2_IF_10_100 (1 << 8)
+
+#define ATH_MAC_IFCTL_SPEED (1 << 16)
+
+/*
+ * DMA (tx/rx) register defines
+ */
+#define ATH_DMA_TX_CTRL 0x180
+#define ATH_DMA_TX_DESC 0x184
+#define ATH_DMA_TX_STATUS 0x188
+#define ATH_DMA_RX_CTRL 0x18c
+#define ATH_DMA_RX_DESC 0x190
+#define ATH_DMA_RX_STATUS 0x194
+#define ATH_DMA_INTR_MASK 0x198
+#define ATH_DMA_INTR 0x19c
+
+/*
+ * tx/rx ctrl and status bits
+ */
+#define ATH_TXE (1 << 0)
+#define ATH_TX_STATUS_PKTCNT_SHIFT 16
+#define ATH_TX_STATUS_PKT_SENT 0x1
+#define ATH_TX_STATUS_URN 0x2
+#define ATH_TX_STATUS_BUS_ERROR 0x8
+
+#define ATH_RXE (1 << 0)
+
+#define ATH_RX_STATUS_PKTCNT_MASK 0xff0000
+#define ATH_RX_STATUS_PKT_RCVD (1 << 0)
+#define ATH_RX_STATUS_OVF (1 << 2)
+#define ATH_RX_STATUS_BUS_ERROR (1 << 3)
+
+/*
+ * Int and int mask
+ */
+#define ATH_INTR_TX (1 << 0)
+#define ATH_INTR_TX_URN (1 << 1)
+#define ATH_INTR_TX_BUS_ERROR (1 << 3)
+#define ATH_INTR_RX (1 << 4)
+#define ATH_INTR_RX_OVF (1 << 6)
+#define ATH_INTR_RX_BUS_ERROR (1 << 7)
+
+/*
+ * MII registers
+ */
+#define ATH_MAC_MII_MGMT_CFG 0x20
+#define ATH_MGMT_CFG_CLK_DIV_20 0x07
+
+#define ATH_MII_MGMT_CMD 0x24
+#define ATH_MGMT_CMD_READ 0x1
+
+#define ATH_MII_MGMT_ADDRESS 0x28
+#define ATH_ADDR_SHIFT 8
+
+#define ATH_MII_MGMT_CTRL 0x2c
+#define ATH_MII_MGMT_STATUS 0x30
+
+#define ATH_MII_MGMT_IND 0x34
+#define ATH_MGMT_IND_BUSY (1 << 0)
+#define ATH_MGMT_IND_INVALID (1 << 2)
+
+#define ATH_GE_MAC_ADDR1 0x40
+#define ATH_GE_MAC_ADDR2 0x44
+
+/*
+ * Ethernet config registers
+ */
+#define ATH_ETH_CFG 0x18070000
+#define ATH_ETH_CFG_RGMII_GE0 (1<<0)
+#define ATH_ETH_CFG_MII_GE0 (1<<1)
+#define ATH_ETH_CFG_GMII_GE0 (1<<2)
+#define ATH_ETH_CFG_RMII_GE0 (1<<10)
+#define ATH_ETH_CFG_RMII_HISPD_GE0 (1<<11)
+#define ATH_ETH_CFG_RMII_MASTER_MODE (1<<12)
+#define ATH_ETH_CFG_MII_GE0_MASTER (1<<3)
+#define ATH_ETH_CFG_MII_GE0_SLAVE (1<<4)
+#define ATH_ETH_CFG_GE0_ERR_EN (1<<5)
+#define ATH_ETH_CFG_SW_ONLY_MODE (1<<6)
+#define ATH_ETH_CFG_SW_PHY_SWAP (1<<7)
+#define ATH_ETH_CFG_SW_PHY_ADDR_SWAP (1<<8)
+#define ATH_ETH_CFG_RXD_DELAY (1 << 14)
+#define ATH_ETH_CFG_RDV_DELAY (1 << 16)
+#define ATH_ETH_SWITCH_CLK_SPARE 0x18050024
+
+#define ETH_CFG_ETH_SPARE_MSB 31
+#define ETH_CFG_ETH_SPARE_LSB 22
+#define ETH_CFG_ETH_SPARE_MASK 0xffc00000
+#define ETH_CFG_ETH_SPARE_GET(x) (((x) & ETH_CFG_ETH_SPARE_MASK) >> ETH_CFG_ETH_SPARE_LSB)
+#define ETH_CFG_ETH_SPARE_SET(x) (((x) << ETH_CFG_ETH_SPARE_LSB) & ETH_CFG_ETH_SPARE_MASK)
+#define ETH_CFG_ETH_SPARE_RESET 0x0 // 0
+#define ETH_CFG_ETH_TXEN_DELAY_MSB 21
+#define ETH_CFG_ETH_TXEN_DELAY_LSB 20
+#define ETH_CFG_ETH_TXEN_DELAY_MASK 0x00300000
+#define ETH_CFG_ETH_TXEN_DELAY_GET(x) (((x) & ETH_CFG_ETH_TXEN_DELAY_MASK) >> ETH_CFG_ETH_TXEN_DELAY_LSB)
+#define ETH_CFG_ETH_TXEN_DELAY_SET(x) (((x) << ETH_CFG_ETH_TXEN_DELAY_LSB) & ETH_CFG_ETH_TXEN_DELAY_MASK)
+#define ETH_CFG_ETH_TXEN_DELAY_RESET 0x0 // 0
+#define ETH_CFG_ETH_TXD_DELAY_MSB 19
+#define ETH_CFG_ETH_TXD_DELAY_LSB 18
+#define ETH_CFG_ETH_TXD_DELAY_MASK 0x000c0000
+#define ETH_CFG_ETH_TXD_DELAY_GET(x) (((x) & ETH_CFG_ETH_TXD_DELAY_MASK) >> ETH_CFG_ETH_TXD_DELAY_LSB)
+#define ETH_CFG_ETH_TXD_DELAY_SET(x) (((x) << ETH_CFG_ETH_TXD_DELAY_LSB) & ETH_CFG_ETH_TXD_DELAY_MASK)
+#define ETH_CFG_ETH_TXD_DELAY_RESET 0x0 // 0
+#define ETH_CFG_ETH_RXDV_DELAY_MSB 17
+#define ETH_CFG_ETH_RXDV_DELAY_LSB 16
+#define ETH_CFG_ETH_RXDV_DELAY_MASK 0x00030000
+#define ETH_CFG_ETH_RXDV_DELAY_GET(x) (((x) & ETH_CFG_ETH_RXDV_DELAY_MASK) >> ETH_CFG_ETH_RXDV_DELAY_LSB)
+#define ETH_CFG_ETH_RXDV_DELAY_SET(x) (((x) << ETH_CFG_ETH_RXDV_DELAY_LSB) & ETH_CFG_ETH_RXDV_DELAY_MASK)
+#define ETH_CFG_ETH_RXDV_DELAY_RESET 0x0 // 0
+#define ETH_CFG_ETH_RXD_DELAY_MSB 15
+#define ETH_CFG_ETH_RXD_DELAY_LSB 14
+#define ETH_CFG_ETH_RXD_DELAY_MASK 0x0000c000
+#define ETH_CFG_ETH_RXD_DELAY_GET(x) (((x) & ETH_CFG_ETH_RXD_DELAY_MASK) >> ETH_CFG_ETH_RXD_DELAY_LSB)
+#define ETH_CFG_ETH_RXD_DELAY_SET(x) (((x) << ETH_CFG_ETH_RXD_DELAY_LSB) & ETH_CFG_ETH_RXD_DELAY_MASK)
+#define ETH_CFG_ETH_RXD_DELAY_RESET 0x0 // 0
+#define ETH_CFG_RMII_GE0_MASTER_MSB 12
+#define ETH_CFG_RMII_GE0_MASTER_LSB 12
+#define ETH_CFG_RMII_GE0_MASTER_MASK 0x00001000
+#define ETH_CFG_RMII_GE0_MASTER_GET(x) (((x) & ETH_CFG_RMII_GE0_MASTER_MASK) >> ETH_CFG_RMII_GE0_MASTER_LSB)
+#define ETH_CFG_RMII_GE0_MASTER_SET(x) (((x) << ETH_CFG_RMII_GE0_MASTER_LSB) & ETH_CFG_RMII_GE0_MASTER_MASK)
+#define ETH_CFG_RMII_GE0_MASTER_RESET 0x1 // 1
+#define ETH_CFG_MII_CNTL_SPEED_MSB 11
+#define ETH_CFG_MII_CNTL_SPEED_LSB 11
+#define ETH_CFG_MII_CNTL_SPEED_MASK 0x00000800
+#define ETH_CFG_MII_CNTL_SPEED_GET(x) (((x) & ETH_CFG_MII_CNTL_SPEED_MASK) >> ETH_CFG_MII_CNTL_SPEED_LSB)
+#define ETH_CFG_MII_CNTL_SPEED_SET(x) (((x) << ETH_CFG_MII_CNTL_SPEED_LSB) & ETH_CFG_MII_CNTL_SPEED_MASK)
+#define ETH_CFG_MII_CNTL_SPEED_RESET 0x0 // 0
+#define ETH_CFG_RMII_GE0_MSB 10
+#define ETH_CFG_RMII_GE0_LSB 10
+#define ETH_CFG_RMII_GE0_MASK 0x00000400
+#define ETH_CFG_RMII_GE0_GET(x) (((x) & ETH_CFG_RMII_GE0_MASK) >> ETH_CFG_RMII_GE0_LSB)
+#define ETH_CFG_RMII_GE0_SET(x) (((x) << ETH_CFG_RMII_GE0_LSB) & ETH_CFG_RMII_GE0_MASK)
+#define ETH_CFG_RMII_GE0_RESET 0x0 // 0
+#define ETH_CFG_GE0_SGMII_MSB 6
+#define ETH_CFG_GE0_SGMII_LSB 6
+#define ETH_CFG_GE0_SGMII_MASK 0x00000040
+#define ETH_CFG_GE0_SGMII_GET(x) (((x) & ETH_CFG_GE0_SGMII_MASK) >> ETH_CFG_GE0_SGMII_LSB)
+#define ETH_CFG_GE0_SGMII_SET(x) (((x) << ETH_CFG_GE0_SGMII_LSB) & ETH_CFG_GE0_SGMII_MASK)
+#define ETH_CFG_GE0_SGMII_RESET 0x0 // 0
+#define ETH_CFG_GE0_ERR_EN_MSB 5
+#define ETH_CFG_GE0_ERR_EN_LSB 5
+#define ETH_CFG_GE0_ERR_EN_MASK 0x00000020
+#define ETH_CFG_GE0_ERR_EN_GET(x) (((x) & ETH_CFG_GE0_ERR_EN_MASK) >> ETH_CFG_GE0_ERR_EN_LSB)
+#define ETH_CFG_GE0_ERR_EN_SET(x) (((x) << ETH_CFG_GE0_ERR_EN_LSB) & ETH_CFG_GE0_ERR_EN_MASK)
+#define ETH_CFG_GE0_ERR_EN_RESET 0x0 // 0
+#define ETH_CFG_MII_GE0_SLAVE_MSB 4
+#define ETH_CFG_MII_GE0_SLAVE_LSB 4
+#define ETH_CFG_MII_GE0_SLAVE_MASK 0x00000010
+#define ETH_CFG_MII_GE0_SLAVE_GET(x) (((x) & ETH_CFG_MII_GE0_SLAVE_MASK) >> ETH_CFG_MII_GE0_SLAVE_LSB)
+#define ETH_CFG_MII_GE0_SLAVE_SET(x) (((x) << ETH_CFG_MII_GE0_SLAVE_LSB) & ETH_CFG_MII_GE0_SLAVE_MASK)
+#define ETH_CFG_MII_GE0_SLAVE_RESET 0x0 // 0
+#define ETH_CFG_MII_GE0_MASTER_MSB 3
+#define ETH_CFG_MII_GE0_MASTER_LSB 3
+#define ETH_CFG_MII_GE0_MASTER_MASK 0x00000008
+#define ETH_CFG_MII_GE0_MASTER_GET(x) (((x) & ETH_CFG_MII_GE0_MASTER_MASK) >> ETH_CFG_MII_GE0_MASTER_LSB)
+#define ETH_CFG_MII_GE0_MASTER_SET(x) (((x) << ETH_CFG_MII_GE0_MASTER_LSB) & ETH_CFG_MII_GE0_MASTER_MASK)
+#define ETH_CFG_MII_GE0_MASTER_RESET 0x0 // 0
+#define ETH_CFG_GMII_GE0_MSB 2
+#define ETH_CFG_GMII_GE0_LSB 2
+#define ETH_CFG_GMII_GE0_MASK 0x00000004
+#define ETH_CFG_GMII_GE0_GET(x) (((x) & ETH_CFG_GMII_GE0_MASK) >> ETH_CFG_GMII_GE0_LSB)
+#define ETH_CFG_GMII_GE0_SET(x) (((x) << ETH_CFG_GMII_GE0_LSB) & ETH_CFG_GMII_GE0_MASK)
+#define ETH_CFG_GMII_GE0_RESET 0x0 // 0
+#define ETH_CFG_MII_GE0_MSB 1
+#define ETH_CFG_MII_GE0_LSB 1
+#define ETH_CFG_MII_GE0_MASK 0x00000002
+#define ETH_CFG_MII_GE0_GET(x) (((x) & ETH_CFG_MII_GE0_MASK) >> ETH_CFG_MII_GE0_LSB)
+#define ETH_CFG_MII_GE0_SET(x) (((x) << ETH_CFG_MII_GE0_LSB) & ETH_CFG_MII_GE0_MASK)
+#define ETH_CFG_MII_GE0_RESET 0x0 // 0
+#define ETH_CFG_RGMII_GE0_MSB 0
+#define ETH_CFG_RGMII_GE0_LSB 0
+#define ETH_CFG_RGMII_GE0_MASK 0x00000001
+#define ETH_CFG_RGMII_GE0_GET(x) (((x) & ETH_CFG_RGMII_GE0_MASK) >> ETH_CFG_RGMII_GE0_LSB)
+#define ETH_CFG_RGMII_GE0_SET(x) (((x) << ETH_CFG_RGMII_GE0_LSB) & ETH_CFG_RGMII_GE0_MASK)
+#define ETH_CFG_RGMII_GE0_RESET 0x0 // 0
+#define ETH_CFG_ADDRESS 0x18070000
+
+
+
+
+/*
+ * ownership of descriptors between DMA and cpu
+ */
+#define ath_gmac_rx_owned_by_dma(_ds) ((_ds)->is_empty == 1)
+#define ath_gmac_rx_give_to_dma(_ds) ((_ds)->is_empty = 1)
+#define ath_gmac_tx_owned_by_dma(_ds) ((_ds)->is_empty == 0)
+#define ath_gmac_tx_give_to_dma(_ds) ((_ds)->is_empty = 0)
+#define ath_gmac_tx_own(_ds) ((_ds)->is_empty = 1)
+
+/*
+ * link settings
+ */
+#define ath_gmac_set_mac_duplex(_mac, _fdx) do { \
+ if ((_fdx)) { \
+ ath_gmac_reg_rmw_set(_mac, \
+ ATH_MAC_CFG2, ATH_MAC_CFG2_FDX);\
+ } else { \
+ ath_gmac_reg_rmw_clear(_mac, \
+ ATH_MAC_CFG2, ATH_MAC_CFG2_FDX);\
+ } \
+} while (0)
+
+#define ath_gmac_set_mac_if(_mac, _isXGMII) do { \
+ ath_gmac_reg_rmw_clear(_mac, ATH_MAC_CFG2, \
+ ATH_MAC_CFG2_IF_1000 | \
+ ATH_MAC_CFG2_IF_10_100); \
+ if ((_isXGMII)) { \
+ ath_gmac_reg_rmw_set(_mac, ATH_MAC_CFG2, \
+ ATH_MAC_CFG2_IF_1000); \
+ ath_gmac_reg_rmw_set(_mac, ATH_MAC_FIFO_CFG_5, \
+ ATH_BYTE_PER_CLK_EN); \
+ } else { \
+ ath_gmac_reg_rmw_set(_mac, ATH_MAC_CFG2, \
+ ATH_MAC_CFG2_IF_10_100); \
+ ath_gmac_reg_rmw_clear(_mac, ATH_MAC_FIFO_CFG_5,\
+ ATH_BYTE_PER_CLK_EN); \
+ } \
+} while (0)
+
+#define ath_gmac_set_mac_speed(_mac, _is100) do { \
+ if ((_is100)) { \
+ ath_gmac_reg_rmw_set(_mac, ATH_MAC_IFCTL, \
+ ATH_MAC_IFCTL_SPEED); \
+ } else { \
+ ath_gmac_reg_rmw_clear(_mac, ATH_MAC_IFCTL, \
+ ATH_MAC_IFCTL_SPEED); \
+ } \
+} while (0)
+
+#endif /* __QCA_ETH_953X_H */
--- /dev/null
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _QCA_ETH_953x_PHY_H
+#define _QCA_ETH_953x_PHY_H
+#include <miiphy.h>
+
+
+#ifdef CONFIG_ATHR_8033_PHY
+extern int athrs_ar8033_reg_init(void *arg);
+extern int athrs_ar8033_phy_setup(void *arg);
+extern int athrs_ar8033_phy_is_fdx(int ethUnit);
+extern int athrs_ar8033_phy_is_link_alive(int phyUnit);
+extern int athrs_ar8033_phy_is_up(int ethUnit);
+extern int athrs_ar8033_phy_speed(int ethUnit,int phyUnit);
+#endif
+
+#ifdef CFG_ATHRS27_PHY
+extern int athrs27_phy_setup(int ethUnit);
+extern int athrs27_phy_is_up(int ethUnit);
+extern int athrs27_phy_is_fdx(int ethUnit);
+extern int athrs27_phy_speed(int ethUnit);
+#endif
+
+#ifdef CONFIG_ATHRS17_PHY
+extern int athrs17_phy_setup(int ethUnit);
+extern int athrs17_phy_is_up(int ethUnit);
+extern int athrs17_phy_is_fdx(int ethUnit);
+extern int athrs17_phy_speed(int ethUnit);
+#endif
+
+static inline void ath_gmac_phy_setup(int unit)
+{
+#ifdef CFG_ATHRS27_PHY
+ athrs27_phy_setup(unit);
+#endif
+#ifdef CONFIG_VIR_PHY
+ athr_vir_phy_setup(unit);
+#endif
+}
+
+static inline void ath_gmac_phy_link(int unit, int *link)
+{
+
+#ifdef CFG_ATHRS27_PHY
+ *link = athrs27_phy_is_up(unit);
+#endif
+
+#ifdef CONFIG_VIR_PHY
+ *link = athr_vir_phy_is_up(unit);
+#endif
+}
+
+static inline void ath_gmac_phy_duplex(int unit, int *duplex)
+{
+#ifdef CFG_ATHRS27_PHY
+ *duplex = athrs27_phy_is_fdx(unit);
+#endif
+#ifdef CONFIG_VIR_PHY
+ *duplex = athr_vir_phy_is_fdx(unit);
+#endif
+}
+
+static inline void ath_gmac_phy_speed(int unit, int *speed)
+{
+#ifdef CFG_ATHRS27_PHY
+ *speed = athrs27_phy_speed(unit);
+#endif
+
+#ifdef CONFIG_VIR_PHY
+ *speed = athr_vir_phy_speed(unit);
+#endif
+
+}
+
+#endif /* _QCA_ETH_953x_PHY_H */
--- /dev/null
+/*
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <common.h>
+#include <flash.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <soc/qca_soc_common.h>
+
+/* Use 4 MB by default */
+#ifndef CONFIG_DEFAULT_FLASH_SIZE_IN_MB
+ #define CONFIG_DEFAULT_FLASH_SIZE_IN_MB 4
+#endif
+
+/*
+ * Find SPI NOR FLASH chip info for selected bank,
+ * based on JEDEC ID and copy data to global flash_info variable
+ */
+static u32 flash_info_find(flash_info_t *info, u32 jedec_id)
+{
+ u32 i;
+
+ for (i = 0; i < spi_nor_ids_count; i++) {
+ if (jedec_id == spi_nor_ids[i].flash_id) {
+ info->model_name = spi_nor_ids[i].model_name;
+ info->size = spi_nor_ids[i].size;
+ info->sector_size = spi_nor_ids[i].sector_size;
+ info->page_size = spi_nor_ids[i].page_size;
+ info->erase_cmd = spi_nor_ids[i].erase_cmd;
+ info->sector_count = info->size / info->sector_size;
+
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+/*
+ * Scan all configured FLASH banks one by one
+ * and try to get information about the chips
+ */
+u32 flash_init(void)
+{
+ u32 bank, i, jedec_id, sfdp_size, sfdp_ss;
+ u32 total_size = 0;
+ flash_info_t *info;
+ u8 sfdp_ec;
+
+ for (bank = 0; bank < CFG_MAX_FLASH_BANKS; bank++) {
+ info = &flash_info[bank];
+
+ jedec_id = qca_sf_jedec_id(bank);
+
+ if (jedec_id == 0) {
+ printf("## Error: SPI NOR FLASH chip in bank #%d\n"
+ " is not responding, skipping\n\n", bank + 1);
+ continue;
+ }
+
+ info->manuf_name = (char *)flash_manuf_name(jedec_id);
+ info->flash_id = jedec_id;
+ info->bank = bank;
+
+ if (flash_info_find(info, jedec_id) != 0) {
+ /* Try to get some info about FLASH from SFDP */
+ if (qca_sf_sfdp_info(bank, &sfdp_size, &sfdp_ss, &sfdp_ec) == 0) {
+ info->size = sfdp_size;
+ info->sector_size = sfdp_ss;
+ info->erase_cmd = sfdp_ec;
+
+ printf("** Warning: SPI NOR FLASH in bank #%d is\n"
+ " unknown, JEDEC ID: 0x%06X\n\n", bank + 1, jedec_id);
+
+ printf(" Information provided in SFDP:\n"
+ " - FLASH size: ");
+ print_size(sfdp_size, "\n");
+
+ printf(" - erase sector size: ");
+ print_size(sfdp_ss, "\n");
+
+ printf(" - erase sector command: 0x%02X\n\n", sfdp_ec);
+ } else {
+ #if (CONFIG_DEFAULT_FLASH_SIZE_IN_MB == 4)
+ info->size = SIZE_4MiB;
+ #elif (CONFIG_DEFAULT_FLASH_SIZE_IN_MB == 8)
+ info->size = SIZE_8MiB;
+ #elif (CONFIG_DEFAULT_FLASH_SIZE_IN_MB == 16)
+ info->size = SIZE_16MiB;
+ #else
+ #error "Not supported CONFIG_DEFAULT_FLASH_SIZE_IN_MB value!"
+ #endif
+
+ printf("## Error: SPI NOR FLASH chip in bank #%d\n"
+ " is unknown, JEDEC ID: 0x%06X, will\n"
+ " use fixed/predefined size: ", bank + 1, jedec_id);
+ print_size(info->size, "\n\n");
+
+ /*
+ * Use 64 KiB erase sector/block size for unknown chip
+ * Hopefully will work in most cases
+ */
+ info->sector_size = SIZE_64KiB;
+ info->erase_cmd = SPI_FLASH_CMD_ES_64KB;
+ info->flash_id = FLASH_CUSTOM;
+ }
+
+ /* We assume page size to be 256 bytes */
+ info->page_size = 256;
+ info->model_name = "unknown model";
+ info->sector_count = info->size / info->sector_size;
+ }
+
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = CFG_FLASH_BASE
+ + total_size + (i * info->sector_size);
+ }
+
+ total_size += flash_info[bank].size;
+ }
+
+ return total_size;
+}
+
+/*
+ * Erase all FLASH sectors in provided range
+ *
+ * TODO:
+ * - use some LED for indication that we are erasing?
+ */
+u32 flash_erase(flash_info_t *info,
+ u32 s_first,
+ u32 s_last)
+{
+ u32 i, j;
+
+ printf("Erasing: ");
+
+ j = 0;
+ for (i = s_first; i <= s_last; i++) {
+ qca_sf_sect_erase(info->bank, i * info->sector_size,
+ info->sector_size, info->erase_cmd);
+
+ if (j == 39) {
+ puts("\n ");
+ j = 0;
+ }
+ puts("#");
+
+ j++;
+ }
+
+ printf("\n\n");
+
+ return 0;
+}
+
+/*
+ * Write a buffer from memory to a FLASH:
+ * call page program for every <= 256 bytes
+ *
+ * Assumption: caller has already erased the appropriate sectors
+ */
+u32 write_buff(flash_info_t *info, uchar *source, ulong addr, ulong len)
+{
+ u32 total = 0, len_this_lp, bytes_this_page;
+ u32 dst;
+ u8 *src;
+
+ printf("Writting at address: 0x%08lX\n", addr);
+ addr = addr - CFG_FLASH_BASE;
+
+ while (total < len) {
+ src = source + total;
+ dst = addr + total;
+ bytes_this_page = info->page_size - (addr % info->page_size);
+ len_this_lp = ((len - total) > bytes_this_page) ? bytes_this_page : (len - total);
+
+ qca_sf_write_page(info->bank, dst, len_this_lp, src);
+
+ total += len_this_lp;
+ }
+
+ puts("\n");
+
+ return 0;
+}
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o ../common/ar7240_pci.o ../common/ar7240_flash.o
+OBJS = $(BOARD).o ../common/ar7240_pci.o ../common/spi_flash.o ../common/common.o
ifeq ($(ETH_CONFIG), _s17)
OBJS += ../common/athrs17_phy.o
OBJS += ../common/athrs27_phy.o
endif
-SOBJS = ../common/lowlevel_init_934x.o
-
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
+/*
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
#include <common.h>
-#include <command.h>
-#include <asm/mipsregs.h>
#include <asm/addrspace.h>
-#include <config.h>
-#include <version.h>
-#include "ar7240_soc.h"
-
-extern int wasp_ddr_initial_config(uint32_t refresh);
-extern int ar7240_ddr_find_size(void);
-
-#define SETBITVAL(val, pos, bit) do {ulong bitval = (bit) ? 0x1 : 0x0; (val) = ((val) & ~(0x1 << (pos))) | ( (bitval) << (pos));} while(0)
-
-void led_toggle(void){
- unsigned int gpio;
-
- gpio = ar7240_reg_rd(AR934X_GPIO_OUT);
-
-#if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) || \
- defined(CONFIG_FOR_TPLINK_WDR3500_V1) || \
- defined(CONFIG_FOR_TPLINK_WR841N_V8) || \
- defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2) || \
- defined(CONFIG_FOR_TPLINK_MR3420_V2)
- gpio ^= 1 << GPIO_SYS_LED_BIT;
-#else
- #error "Custom GPIO in leg_toggle() not defined!"
-#endif
-
- ar7240_reg_wr(AR934X_GPIO_OUT, gpio);
-}
-
-void all_led_on(void){
- unsigned int gpio;
-
- gpio = ar7240_reg_rd(AR934X_GPIO_OUT);
-
-#if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_2G_LED_BIT, GPIO_WLAN_2G_LED_ON);
- SETBITVAL(gpio, GPIO_USB1_LED_BIT, GPIO_USB1_LED_ON);
- SETBITVAL(gpio, GPIO_USB2_LED_BIT, GPIO_USB2_LED_ON);
- //SETBITVAL(gpio, GPIO_QSS_LED_BIT, GPIO_QSS_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_WDR3500_V1)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_2G_LED_BIT, GPIO_WLAN_2G_LED_ON);
- SETBITVAL(gpio, GPIO_LAN1_LED_BIT, GPIO_LAN1_LED_ON);
- SETBITVAL(gpio, GPIO_LAN2_LED_BIT, GPIO_LAN2_LED_ON);
- SETBITVAL(gpio, GPIO_LAN3_LED_BIT, GPIO_LAN3_LED_ON);
- SETBITVAL(gpio, GPIO_LAN4_LED_BIT, GPIO_LAN4_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_QSS_LED_BIT, GPIO_QSS_LED_ON);
- SETBITVAL(gpio, GPIO_USB_LED_BIT, GPIO_USB_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_WR841N_V8)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_LAN1_LED_BIT, GPIO_LAN1_LED_ON);
- SETBITVAL(gpio, GPIO_LAN2_LED_BIT, GPIO_LAN2_LED_ON);
- SETBITVAL(gpio, GPIO_LAN3_LED_BIT, GPIO_LAN3_LED_ON);
- SETBITVAL(gpio, GPIO_LAN4_LED_BIT, GPIO_LAN4_LED_ON);
- SETBITVAL(gpio, GPIO_QSS_LED_BIT, GPIO_QSS_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_LAN1_LED_BIT, GPIO_LAN1_LED_ON);
- SETBITVAL(gpio, GPIO_LAN2_LED_BIT, GPIO_LAN2_LED_ON);
- SETBITVAL(gpio, GPIO_LAN3_LED_BIT, GPIO_LAN3_LED_ON);
- SETBITVAL(gpio, GPIO_LAN4_LED_BIT, GPIO_LAN4_LED_ON);
- SETBITVAL(gpio, GPIO_USB_LED_BIT, GPIO_USB_LED_ON);
- SETBITVAL(gpio, GPIO_QSS_LED_BIT, GPIO_QSS_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_LAN_LED_BIT, GPIO_LAN_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_QSS_LED_BIT, GPIO_QSS_LED_ON);
-#else
- #error "Custom GPIO in all_led_on() not defined!"
-#endif
-
- ar7240_reg_wr(AR934X_GPIO_OUT, gpio);
-}
-
-void all_led_off(void){
- unsigned int gpio;
-
- gpio = ar7240_reg_rd(AR934X_GPIO_OUT);
-
-#if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_2G_LED_BIT, !GPIO_WLAN_2G_LED_ON);
- SETBITVAL(gpio, GPIO_USB1_LED_BIT, !GPIO_USB1_LED_ON);
- SETBITVAL(gpio, GPIO_USB2_LED_BIT, !GPIO_USB2_LED_ON);
- //SETBITVAL(gpio, GPIO_QSS_LED_BIT, !GPIO_QSS_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_WDR3500_V1)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_2G_LED_BIT, !GPIO_WLAN_2G_LED_ON);
- SETBITVAL(gpio, GPIO_LAN1_LED_BIT, !GPIO_LAN1_LED_ON);
- SETBITVAL(gpio, GPIO_LAN2_LED_BIT, !GPIO_LAN2_LED_ON);
- SETBITVAL(gpio, GPIO_LAN3_LED_BIT, !GPIO_LAN3_LED_ON);
- SETBITVAL(gpio, GPIO_LAN4_LED_BIT, !GPIO_LAN4_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, !GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_QSS_LED_BIT, !GPIO_QSS_LED_ON);
- SETBITVAL(gpio, GPIO_USB_LED_BIT, !GPIO_USB_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_WR841N_V8)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, !GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_LAN1_LED_BIT, !GPIO_LAN1_LED_ON);
- SETBITVAL(gpio, GPIO_LAN2_LED_BIT, !GPIO_LAN2_LED_ON);
- SETBITVAL(gpio, GPIO_LAN3_LED_BIT, !GPIO_LAN3_LED_ON);
- SETBITVAL(gpio, GPIO_LAN4_LED_BIT, !GPIO_LAN4_LED_ON);
- SETBITVAL(gpio, GPIO_QSS_LED_BIT, !GPIO_QSS_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, !GPIO_INTERNET_LED_ON);
- SETBITVAL(gpio, GPIO_LAN1_LED_BIT, !GPIO_LAN1_LED_ON);
- SETBITVAL(gpio, GPIO_LAN2_LED_BIT, !GPIO_LAN2_LED_ON);
- SETBITVAL(gpio, GPIO_LAN3_LED_BIT, !GPIO_LAN3_LED_ON);
- SETBITVAL(gpio, GPIO_LAN4_LED_BIT, !GPIO_LAN4_LED_ON);
- SETBITVAL(gpio, GPIO_USB_LED_BIT, !GPIO_USB_LED_ON);
- SETBITVAL(gpio, GPIO_QSS_LED_BIT, !GPIO_QSS_LED_ON);
-#elif defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
- SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON);
- SETBITVAL(gpio, GPIO_LAN_LED_BIT, !GPIO_LAN_LED_ON);
- SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON);
- SETBITVAL(gpio, GPIO_QSS_LED_BIT, !GPIO_QSS_LED_ON);
-#else
- #error "Custom GPIO in all_led_off() not defined!"
-#endif
-
- ar7240_reg_wr(AR934X_GPIO_OUT, gpio);
-}
-
-// get button status
-#ifndef GPIO_RST_BUTTON_BIT
- #error "GPIO_RST_BUTTON_BIT not defined!"
-#endif
-int reset_button_status(void){
- unsigned int gpio;
-
- gpio = ar7240_reg_rd(AR934X_GPIO_IN);
-
- if(gpio & (1 << GPIO_RST_BUTTON_BIT)){
-#if defined(GPIO_RST_BUTTON_IS_ACTIVE_LOW)
- return(0);
-#else
- return(1);
-#endif
- } else {
-#if defined(GPIO_RST_BUTTON_IS_ACTIVE_LOW)
- return(1);
-#else
- return(0);
-#endif
- }
-}
-
-void ath_set_tuning_caps(void){
- typedef struct {
- u_int8_t pad[0x28];
- u_int8_t params_for_tuning_caps[2];
- u_int8_t featureEnable;
- } __attribute__((__packed__)) ar9300_eeprom_t;
-
- ar9300_eeprom_t *eep = (ar9300_eeprom_t *)WLANCAL;
- uint32_t val = 0;
-
- /* checking feature enable bit 6 and caldata is valid */
- if((eep->featureEnable & 0x40) && (eep->pad[0x0] != 0xff)){
- /* xtal_capin -bit 17:23 and xtag_capout -bit 24:30*/
- val = (eep->params_for_tuning_caps[0] & 0x7f) << 17;
- val |= (eep->params_for_tuning_caps[0] & 0x7f) << 24;
- } else {
- /* default when no caldata available*/
- /* checking clock in bit 4 */
- if(ar7240_reg_rd(RST_BOOTSTRAP_ADDRESS) & 0x10){
- val = (0x1020 << 17); /*default 0x2040 for 40Mhz clock*/
- } else {
- val = (0x2040 << 17); /*default 0x4080 for 25Mhz clock*/
- }
- }
-
- val |= (ar7240_reg_rd(XTAL_ADDRESS) & (((1 << 17) - 1) | (1 << 31)));
- ar7240_reg_wr(XTAL_ADDRESS, val);
-
- //prmsg("Setting 0xb8116290 to 0x%x\n", val);
- return;
-}
-
-int wasp_mem_config(void){
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- unsigned int reg32;
-
- wasp_ddr_initial_config(CFG_DDR_REFRESH_VAL);
-
- /* Take WMAC out of reset */
- reg32 = ar7240_reg_rd(AR7240_RESET);
- reg32 = reg32 & ~AR7240_RESET_WMAC;
-
- ar7240_reg_wr_nf(AR7240_RESET, reg32);
-
- /* Switching regulator settings */
- ar7240_reg_wr_nf(0x18116c40, 0x633c8176); /* AR_PHY_PMU1 */
- ar7240_reg_wr_nf(0x18116c44, 0x10380000); /* AR_PHY_PMU2 */
-
- //wasp_usb_initial_config();
-
- /* Needed here not to mess with Ethernet clocks */
- ath_set_tuning_caps();
-
-#endif
- // return memory size
- return(ar7240_ddr_find_size());
-}
-
-long int initdram(){
- return((long int)wasp_mem_config());
-}
-
-#ifndef COMPRESSED_UBOOT
-int checkboard(void){
- printf(BOARD_CUSTOM_STRING"\n\n");
- return(0);
-}
-#endif
+#include <soc/qca_soc_common.h>
/*
- * Returns a string with memory type preceded by a space sign
+ * DRAM init
*/
-const char* print_mem_type(void){
- unsigned int reg;
-
- reg = ar7240_reg_rd(WASP_BOOTSTRAP_REG);
+long int dram_init()
+{
+ qca_dram_init();
- // if SDRAM is disabled -> we are using DDR
- if(reg & WASP_BOOTSTRAP_SDRAM_DISABLE_MASK){
-
- // 1 -> DDR1
- if(reg & WASP_BOOTSTRAP_DDR_SELECT_MASK){
- if(reg & WASP_BOOTSTRAP_DDR_WIDTH_MASK){
- return " DDR 32-bit";
- } else {
- return " DDR 16-bit";
- }
- } else {
- if(reg & WASP_BOOTSTRAP_DDR_WIDTH_MASK){
- return " DDR2 32-bit";
- } else {
- return " DDR2 16-bit";
- }
- }
-
- } else {
- return " SDRAM";
- }
-}
\ No newline at end of file
+ return (long int)qca_dram_size();
+}
cmd_nvedit.o \
cmd_itest.o \
cmd_load.o \
+ cmd_qcaclk.o \
command.o \
console.o \
devices.o \
#include <command.h>
#include <image.h>
#include <malloc.h>
-#include <zlib.h>
-#include <bzlib.h>
#include <LzmaWrapper.h>
#include <environment.h>
#include <asm/byteorder.h>
+#include <tinf.h>
DECLARE_GLOBAL_DATA_PTR;
image_header_t header;
ulong load_addr = CFG_LOAD_ADDR; /* default load address */
-#if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) && \
- !defined(CONFIG_FOR_DLINK_DIR505_A1) && \
- !defined(CONFIG_FOR_DRAGINO_V2) && \
- !defined(CONFIG_FOR_MESH_POTATO_V2)
+#ifdef CONFIG_TPLINK_IMAGE_HEADER
void fake_image_header(image_header_t *hdr, tplink_image_header_t *tpl_hdr){
memset(hdr, 0, sizeof(image_header_t));
strncpy((char *)hdr->ih_name, (char *)tpl_hdr->signiture_1, IH_NMLEN);
}
-#endif /* if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) && !defined(CONFIG_FOR_DLINK_DIR505_A1) && !defined(CONFIG_FOR_DRAGINO_V2) && !defined(CONFIG_FOR_MESH_POTATO_V2) */
+#endif /* CONFIG_TPLINK_IMAGE_HEADER */
int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
ulong addr, data, len;
uint unc_len = CFG_BOOTM_LEN;
int i;
image_header_t *hdr = &header;
-#if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) && \
- !defined(CONFIG_FOR_DLINK_DIR505_A1) && \
- !defined(CONFIG_FOR_DRAGINO_V2) && \
- !defined(CONFIG_FOR_MESH_POTATO_V2)
+#ifdef CONFIG_TPLINK_IMAGE_HEADER
tplink_image_header_t *fileTag;
#endif
printf("Booting image at: 0x%08lX\n", addr);
-#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || \
- defined(CONFIG_FOR_DLINK_DIR505_A1) || \
- defined(CONFIG_FOR_DRAGINO_V2) || \
- defined(CONFIG_FOR_MESH_POTATO_V2)
+#ifndef CONFIG_TPLINK_IMAGE_HEADER
memmove(&header, (char *)addr, sizeof(image_header_t));
print_image_hdr(hdr);
fake_image_header(hdr, fileTag);
data = addr + TAG_LEN;
-#endif
+#endif /* !CONFIG_TPLINK_IMAGE_HEADER */
len = ntohl(hdr->ih_size);
eth_halt();
#endif
-#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240)
+ /* TODO: should we flush caches for kernel? */
/*
* Flush everything, restore caches for linux
*/
/* XXX - this causes problems when booting from flash */
/* dcache_disable(); */
-#endif
/* case IH_COMP_LZMA:*/
puts("Uncompressing kernel image... ");
}
#endif /* CONFIG_SILENT_CONSOLE */
-#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || \
- defined(CONFIG_FOR_DLINK_DIR505_A1) || \
- defined(CONFIG_FOR_DRAGINO_V2) || \
- defined(CONFIG_FOR_MESH_POTATO_V2)
+#ifndef CONFIG_TPLINK_IMAGE_HEADER
static void print_type(image_header_t *hdr){
char *os, *arch, *type, *comp;
print_size(ntohl(hdr->kernelLen), "\n");
printf(" Load address: 0x%08X\n Entry point: 0x%08X\n\n", ntohl(hdr->kernelTextAddr), ntohl(hdr->kernelEntryPoint));
}
-#endif /* defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || defined(CONFIG_FOR_DLINK_DIR505_A1) || defined(CONFIG_FOR_DRAGINO_V2) || defined(CONFIG_FOR_MESH_POTATO_V2) */
+#endif /* !CONFIG_TPLINK_IMAGE_HEADER */
#if (CONFIG_COMMANDS & CFG_CMD_BOOTD)
int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if(crc32(0, (uchar *)data, len) != checksum){
+ if(tinf_crc32((uchar *)data, len) != checksum){
puts("## Error: bad header checksum!\n");
return 1;
}
puts(" Verifying checksum... ");
- if(crc32(0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)){
+ if(tinf_crc32((uchar *)data, len) != ntohl(hdr->ih_dcrc)){
puts("bad data CRC!\n");
return(1);
}
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <ar7240_soc.h>
-#include "../board/ar7240/common/ar7240_flash.h"
-extern void ar933x_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq);
+/* TODO: remove extern and include header file*/
+extern void qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk,
+ u32 *spi_clk, u32 *ref_clk);
#if defined(OFFSET_MAC_ADDRESS)
/*
U_BOOT_CMD(defenv, 1, 0, do_default_env, "reset environment variables to their default values\n", NULL);
#endif /* if !defined(CONFIG_FOR_DLINK_DIR505_A1) */
-
-#if defined(PLL_IN_FLASH_MAGIC_OFFSET)
-
-typedef struct {
- // Clocks in MHz
- unsigned short cpu_clock;
- unsigned short ram_clock;
- unsigned short ahb_clock;
- unsigned short spi_clock;
-
- // Registers values
- // (more info in includes/configs/ap121.h)
- unsigned int cpu_clk_control;
- unsigned int cpu_pll_config;
- unsigned int spi_control;
-} ar9331_clock_profile;
-
-static const ar9331_clock_profile oc_profiles[] = {
- {
- 200, 200, 100, 25,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 2),
-#else
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 2),
-#endif
- MAKE_AR9331_SPI_CONTROL_VAL(4)
- },
-
- {
- 200, 200, 200, 33,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1),
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 2),
-#else
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 2),
-#endif
- MAKE_AR9331_SPI_CONTROL_VAL(6)
- },
-
-#if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 225, 225, 112, 28,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 2),
- MAKE_AR9331_SPI_CONTROL_VAL(4)
- },
-
- {
- 225, 225, 225, 28,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 2),
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-#endif
-
- {
- 250, 250, 125, 31,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 2),
-#else
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1),
-#endif
- MAKE_AR9331_SPI_CONTROL_VAL(4)
- },
-
- {
- 250, 250, 250, 31,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1),
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 2),
-#else
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1),
-#endif
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-
- {
- 300, 300, 150, 25,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(15, 1, 0, 1),
-#else
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(24, 1, 0, 1),
-#endif
- MAKE_AR9331_SPI_CONTROL_VAL(6)
- },
-
-#if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 325, 325, 162, 27,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(26, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(6)
- },
-
- {
- 350, 350, 175, 29,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(28, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(6)
- },
-#endif
-
- {
- 360, 360, 180, 30,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(18, 1, 0, 1),
-#else
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(29, 1, 0, 1),
-#endif
- MAKE_AR9331_SPI_CONTROL_VAL(6)
- },
-
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 380, 380, 190, 32,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(19, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(6)
- },
-#endif
-
- {
- 400, 400, 200, 33,
- CPU_CLK_CONTROL_VAL_DEFAULT,
- CPU_PLL_CONFIG_VAL_DEFAULT,
- AR7240_SPI_CONTROL_DEFAULT
- },
-
-#if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 412, 412, 206, 34,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(33, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(6)
- },
-#endif
-
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 420, 420, 210, 35,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(21, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(6)
- },
-#endif
-
-#if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 425, 425, 212, 35,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(34, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(6)
- },
-
- {
- 437, 437, 218, 27,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(35, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-#endif
-
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 440, 440, 220, 27,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(22, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-#endif
-
-#if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 450, 450, 225, 28,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-#endif
-
- {
- 460, 460, 230, 29,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(23, 1, 0, 1),
-#else
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(37, 1, 0, 1),
-#endif
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-
-#if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 475, 475, 237, 30,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(38, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-#endif
-
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 480, 480, 240, 30,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(24, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-#endif
-
-#if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 487, 487, 243, 30,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(39, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-#endif
-
- {
- 500, 500, 250, 31,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 1),
-#else
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(40, 1, 0, 1),
-#endif
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-
- {
- 500, 250, 250, 31,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 2),
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 1),
-#else
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(40, 1, 0, 1),
-#endif
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 520, 520, 260, 32,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(26, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(8)
- },
-#endif
-
-#if !defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 525, 262, 131, 33,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(42, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(4)
- },
-#endif
-
- {
- 560, 280, 140, 35,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4),
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(28, 1, 0, 1),
-#else
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(45, 1, 0, 1),
-#endif
- MAKE_AR9331_SPI_CONTROL_VAL(4)
- },
-
-#if defined(CONFIG_40MHZ_XTAL_SUPPORT)
- {
- 580, 290, 145, 36,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4),
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(29, 1, 0, 1),
- MAKE_AR9331_SPI_CONTROL_VAL(4)
- },
-#endif
-
- {
- 600, 300, 200, 33,
- MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 3),
-#if CONFIG_40MHZ_XTAL_SUPPORT
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(30, 1, 0, 1),
-#else
- MAKE_AR9331_CPU_PLL_CONFIG_VAL(48, 1, 0, 1),
-#endif
- MAKE_AR9331_SPI_CONTROL_VAL(6)
- },
-};
-
-/*
- * Set and store PLL configuration in FLASH
- */
-int do_set_clocks(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
- unsigned int cpu_pll_config_flash, cpu_clock_control_flash, spi_control_flash, reg;
- unsigned int ahb_freq, ddr_freq, cpu_freq, spi_freq;
- unsigned int *data_pointer;
- int i, index, profiles_count;
- char buf[128];
-
- profiles_count = sizeof(oc_profiles) / sizeof(ar9331_clock_profile);
-
- // print all available profiles and current settings
- if(argc == 1){
-
- // read clocks
- ar933x_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
-
- // calculate SPI clock (we need to set bit 0 to 1 in SPI_FUNC_SELECT to access SPI registers)
- ar7240_reg_wr(AR7240_SPI_FS, 0x01);
- spi_freq = ahb_freq / (((ar7240_reg_rd(AR7240_SPI_CLOCK) & 0x3F) + 1) * 2);
- ar7240_reg_wr(AR7240_SPI_FS, 0x0);
-
- // make MHz from Hz
- cpu_freq /= 1000000;
- ddr_freq /= 1000000;
- ahb_freq /= 1000000;
- spi_freq /= 1000000;
-
- printf("Current clocks (approximated):\n- CPU: %3d MHz\n", cpu_freq);
- printf("- RAM: %3d MHz\n", ddr_freq);
- printf("- AHB: %3d MHz\n", ahb_freq);
- printf("- SPI: %3d MHz\n", spi_freq);
-
- // reference clock
- if(ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & HORNET_BOOTSTRAP_SEL_25M_40M_MASK){
- puts("- REF: 40 MHz\n\n");
- } else {
- puts("- REF: 25 MHz\n\n");
- }
-
- // do we have PLL_MAGIC in FLASH?
- reg = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET);
-
- // read all register values stored in FLASH
- cpu_pll_config_flash = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET + 4);
- cpu_clock_control_flash = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET + 8);
- spi_control_flash = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET + 12);
-
- printf("Available PLL and clocks configurations: %d\n\n", profiles_count);
-
- puts(" | CPU | RAM | AHB | SPI | [ ]\n ---------------------------------\n");
-
- for(i = 0; i < profiles_count; i++){
- printf("%4d. |%4d |%4d |%4d |%4d | ", i + 1,
- oc_profiles[i].cpu_clock,
- oc_profiles[i].ram_clock,
- oc_profiles[i].ahb_clock,
- oc_profiles[i].spi_clock);
-
- if(reg == PLL_IN_FLASH_MAGIC &&
- oc_profiles[i].cpu_pll_config == cpu_pll_config_flash &&
- oc_profiles[i].cpu_clk_control == cpu_clock_control_flash &&
- oc_profiles[i].spi_control == spi_control_flash){
- puts("[*]\n");
- } else {
- puts("[ ]\n");
- }
- }
-
- puts("\n[*] = currently selected profile (stored in FLASH).\nAll clocks in MHz, run 'setclk X' to choose one.\n\n");
- puts("** Notice:\n you should always make a backup of your device\n entire FLASH content before making any changes\n\n");
-
- return(0);
- } else {
- // selected index
- index = simple_strtoul(argv[1], NULL, 10);
-
- if(index > profiles_count || index < 1){
- printf("## Error: selected index should be in range 1..%d!\n", profiles_count);
- return(1);
- }
-
- printf("You have selected profile: %d.\n\n", index);
-
- // array is zero-based indexing
- index--;
-
- // backup entire block in which we store PLL/CLK settings
- data_pointer = (unsigned int *)WEBFAILSAFE_UPLOAD_RAM_ADDRESS;
-
- if(!data_pointer){
- puts("## Error: couldn't allocate RAM for data block backup!\n");
- return(1);
- }
-
- memcpy((void *)data_pointer, (void *)(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET), PLL_IN_FLASH_DATA_BLOCK_LENGTH);
-
- // save PLL_IN_FLASH_MAGIC and PLL/clocks registers values
- data_pointer = (unsigned int *)(WEBFAILSAFE_UPLOAD_RAM_ADDRESS + PLL_IN_FLASH_MAGIC_OFFSET);
- *data_pointer = PLL_IN_FLASH_MAGIC;
-
- data_pointer++;
- *data_pointer = oc_profiles[index].cpu_pll_config;
-
- data_pointer++;
- *data_pointer = oc_profiles[index].cpu_clk_control;
-
- data_pointer++;
- *data_pointer = oc_profiles[index].spi_control;
-
- // erase FLASH, copy data from RAM
- sprintf(buf,
- "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX",
- CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
- PLL_IN_FLASH_DATA_BLOCK_LENGTH,
- WEBFAILSAFE_UPLOAD_RAM_ADDRESS,
- CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
- PLL_IN_FLASH_DATA_BLOCK_LENGTH);
-
- printf("Executing: %s\n\n", buf);
-
- return(run_command(buf, 0));
- }
-}
-
-U_BOOT_CMD(setclk, 2, 0, do_set_clocks, "select clocks configuration from predefined list\n",
- "index\n"
- "\t- save 'index' configuration in FLASH\n"
- "setclk\n"
- "\t- prints available clocks configurations and current settings\n");
-
-/*
- * Remove (clear) PLL and clock settings in FLASH
- */
-int do_clear_clocks(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
- unsigned char *data_pointer;
- int i;
- char buf[128];
- unsigned int reg = 0;
-
- // do we have PLL_MAGIC in FLASH?
- reg = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET);
-
- if(reg == PLL_IN_FLASH_MAGIC){
- // backup entire block in which we store PLL/CLK settings
- data_pointer = (unsigned char *)WEBFAILSAFE_UPLOAD_RAM_ADDRESS;
-
- if(!data_pointer){
- puts("## Error: couldn't allocate RAM for data block backup!\n");
- return(1);
- }
-
- memcpy((void *)data_pointer, (void *)(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET), PLL_IN_FLASH_DATA_BLOCK_LENGTH);
-
- // 16 bytes (4x 32-bit values)
- for(i = 0; i < 16; i++){
- data_pointer[PLL_IN_FLASH_MAGIC_OFFSET + i] = 0xFF;
- }
-
- // erase FLASH, copy data from RAM
- sprintf(buf,
- "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX",
- CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
- PLL_IN_FLASH_DATA_BLOCK_LENGTH,
- WEBFAILSAFE_UPLOAD_RAM_ADDRESS,
- CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
- PLL_IN_FLASH_DATA_BLOCK_LENGTH);
-
- printf("Executing: %s\n\n", buf);
-
- return(run_command(buf, 0));
- } else {
- puts("** Warning: there is no PLL and clocks configuration in FLASH!\n");
- return(1);
- }
-}
-
-U_BOOT_CMD(clearclk, 1, 0, do_clear_clocks, "remove PLL and clocks configuration from FLASH\n", NULL);
-#endif /* #if defined(PLL_IN_FLASH_MAGIC_OFFSET) */
--- /dev/null
+/*
+ * Commands related with PLL/clocks settings
+ * for Qualcomm/Atheros WiSoCs
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <cmd_qcaclk.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+
+#ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET
+
+static void print_reg_values(const clk_cfg_flash *cfg)
+{
+ puts("Target values:\n");
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ printf(" SPI_CTRL: 0x%08lX\n", cfg->spi_ctrl);
+ printf(" CPU_PLL_CFG: 0x%08lX\n", cfg->regs.cpu_pll_cfg);
+ printf("CPU_CLOCK_CONTROL: 0x%08lX\n", cfg->regs.cpu_clk_ctrl);
+ puts("\n");
+ printf("NFRAC_MIN in PLL_DITHER_FRAC: %d/%d\n",
+ (cfg->regs.cpu_pll_dit & QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK)
+ >> QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT,
+ (QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK
+ >> QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT) + 1);
+#else
+ printf(" SPI_CTRL: 0x%08lX\n", cfg->spi_ctrl);
+ printf(" CPU_PLL_CFG: 0x%08lX\n", cfg->regs.cpu_pll_cfg);
+ printf(" DDR_PLL_CFG: 0x%08lX\n", cfg->regs.ddr_pll_cfg);
+ printf("CPU_DDR_CLK_CTRL: 0x%08lX\n", cfg->regs.cpu_ddr_clk_ctrl);
+ puts("\n");
+ printf("NFRAC_MIN in CPU_PLL_DITHER: %d/%d\n",
+ (cfg->regs.cpu_pll_dit & QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK)
+ >> QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT,
+ (QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK
+ >> QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT) + 1);
+
+ printf("NFRAC_MIN in DDR_PLL_DITHER: %d/%d\n",
+ (cfg->regs.ddr_pll_dit & QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK)
+ >> QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT,
+ (QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK
+ >> QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT) + 1);
+#endif /* SOC_TYPE & QCA_AR933X_SOC */
+
+ puts("\n");
+}
+
+static u32 compare_pll_regs(const pll_regs *from_flash,
+ const pll_regs *to_compare)
+{
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ if (from_flash->cpu_pll_cfg == to_compare->cpu_pll_cfg &&
+ from_flash->cpu_pll_dit == to_compare->cpu_pll_dit &&
+ from_flash->cpu_clk_ctrl == to_compare->cpu_clk_ctrl)
+ return 1;
+#else
+ if (from_flash->cpu_pll_cfg == to_compare->cpu_pll_cfg &&
+ from_flash->ddr_pll_cfg == to_compare->ddr_pll_cfg &&
+ from_flash->cpu_pll_dit == to_compare->cpu_pll_dit &&
+ from_flash->ddr_pll_dit == to_compare->ddr_pll_dit &&
+ from_flash->cpu_ddr_clk_ctrl == to_compare->cpu_ddr_clk_ctrl)
+ return 1;
+#endif /* SOC_TYPE & QCA_AR933X_SOC */
+
+ return 0;
+}
+
+/* Set and store PLL configuration in FLASH */
+int do_set_clk(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u32 ahb_clk, cpu_clk, ddr_clk, ref_clk, reg, spi_clk;
+ clk_cfg_flash from_flash, to_flash;
+ const pll_regs *pll_registers;
+ char buf[128];
+ int i;
+ u8 *c;
+
+ /* Read current clocks and make MHz from Hz */
+ qca_sys_clocks(&cpu_clk, &ddr_clk, &ahb_clk, &spi_clk, &ref_clk);
+
+ cpu_clk /= 1000000;
+ ddr_clk /= 1000000;
+ ahb_clk /= 1000000;
+ spi_clk /= 1000000;
+ ref_clk /= 1000000;
+
+ /* Print all available profiles and current settings */
+ if (argc == 1) {
+ printf("Current configuration:\n");
+ printf("- CPU: %3d MHz\n", cpu_clk);
+ printf("- RAM: %3d MHz\n", ddr_clk);
+ printf("- AHB: %3d MHz\n", ahb_clk);
+ printf("- SPI: %3d MHz\n", spi_clk);
+ printf("- REF: %3d MHz\n", ref_clk);
+ puts("\n");
+
+ /* If we have PLL_MAGIC in FLASH, copy configuration from FLASH */
+ reg = qca_soc_reg_read(CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET);
+
+ /* PLL configuration starts _after_ PLL_MAGIC value */
+ if (reg == QCA_PLL_IN_FLASH_MAGIC) {
+ c = (u8 *)(CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET + 4);
+ memcpy(&from_flash, (void *)c, sizeof(clk_cfg_flash));
+ }
+
+ puts("Clocks in MHz, run 'setclk #' to select\n");
+ puts("one configuration from the below table:\n\n");
+ puts(" # [ ] | CPU | RAM | AHB | SPI \n"
+ " ---------------------------------\n");
+
+ for (i = 0; i < clk_profiles_cnt; i++) {
+ printf("%5d", i + 1);
+
+ if (reg == QCA_PLL_IN_FLASH_MAGIC) {
+ if (ref_clk == 25) {
+ pll_registers = &(clk_profiles[i].xtal_25mhz);
+ } else {
+ pll_registers = &(clk_profiles[i].xtal_40mhz);
+ }
+
+ if (from_flash.spi_ctrl == clk_profiles[i].spi_ctrl &&
+ compare_pll_regs(&(from_flash.regs), pll_registers)) {
+ puts(" [*] |");
+ } else {
+ puts(" [ ] |");
+ }
+ } else {
+ puts(" [ ] |");
+ }
+
+ printf("%4d |%4d |%4d |%4d\n",
+ clk_profiles[i].cpu_clk,
+ clk_profiles[i].ddr_clk,
+ clk_profiles[i].ahb_clk,
+ clk_profiles[i].spi_clk);
+ }
+
+ puts("\n[*] profile currently stored in FLASH\n\n");
+
+ /* Show some additional information */
+ puts("** Notice:\n");
+ printf(" configuration is stored in FLASH at: 0x%08lX\n",
+ CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET);
+
+ printf(" magic value is: 0x%08lX, block size is: %2d B\n",
+ QCA_PLL_IN_FLASH_MAGIC, sizeof(clk_cfg_flash));
+
+ puts("\n");
+
+ puts("** Notice:\n");
+ puts(" you should always make a backup of your devices\n");
+ puts(" entire FLASH content, before making any changes\n");
+
+#ifndef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+ puts("\n");
+ puts("** Warning:");
+ puts(" your device does not support O/C revovery mode!\n");
+#endif
+
+ puts("\n");
+ } else {
+ /* Configuration selected by user */
+ i = simple_strtoul(argv[1], NULL, 10);
+
+ if (i > clk_profiles_cnt || i < 1) {
+ printf("## Error: selected profile should be in range 1..%d!\n\n",
+ clk_profiles_cnt);
+ return 1;
+ }
+
+ /* Array is zero-based indexed */
+ printf("Selected profile %d:\n", i);
+ i--;
+
+ /* Copy target values */
+ to_flash.spi_ctrl = clk_profiles[i].spi_ctrl;
+
+ if (ref_clk == 25) {
+ to_flash.regs = clk_profiles[i].xtal_25mhz;
+ } else {
+ to_flash.regs = clk_profiles[i].xtal_40mhz;
+ }
+
+ printf("- CPU: %3d MHz\n", clk_profiles[i].cpu_clk);
+ printf("- RAM: %3d MHz\n", clk_profiles[i].ddr_clk);
+ printf("- AHB: %3d MHz\n", clk_profiles[i].ahb_clk);
+ printf("- SPI: %3d MHz\n", clk_profiles[i].spi_clk);
+ puts("\n");
+
+ print_reg_values(&to_flash);
+
+ /* First, backup in RAM entire block where we store PLL config */
+ sprintf(buf, "cp.b 0x%lX 0x%lX 0x%lX",
+ CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET,
+ CONFIG_LOADADDR,
+ CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE);
+
+ if (run_command(buf, 0) < 0) {
+ puts("## Error: could not make data backup in RAM!\n\n");
+ return 1;
+ }
+
+ /* Overwrite PLL configuration block in RAM */
+ c = (u8 *)(CONFIG_LOADADDR +
+ (CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET
+ - CFG_FLASH_BASE
+ - CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET));
+
+ reg = QCA_PLL_IN_FLASH_MAGIC;
+ memcpy((void *)c, ®, sizeof(reg));
+
+ c += 4;
+
+ if (ref_clk == 25) {
+ memcpy((void *)c, &to_flash, sizeof(clk_cfg_flash));
+ } else {
+ memcpy((void *)c, &to_flash, sizeof(clk_cfg_flash));
+ }
+
+ /* Erase FLASH and copy modified data back */
+ sprintf(buf,
+ "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX",
+ CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET,
+ CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE,
+ CONFIG_LOADADDR,
+ CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET,
+ CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE);
+
+ if (run_command(buf, 0) < 0) {
+ puts("## Error: could not erase FLASH and copy data back from RAM!\n\n");
+ return 1;
+ }
+
+ puts("** Notice:\n");
+ puts(" selected clocks configuration saved in FLASH,\n"
+ " you can restart the device with 'res' command\n");
+
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+ puts("\n");
+ puts(" If the device does not start, use recovery mode\n");
+ #ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW
+ printf(" with button connected to GPIO%d (active in low)\n",
+ CONFIG_QCA_GPIO_OC_RECOVERY_BTN);
+ #else
+ printf(" with button connected to GPIO%d (active in high)\n",
+ CONFIG_QCA_GPIO_OC_RECOVERY_BTN);
+ #endif
+#else
+ puts("\n");
+ puts("** Warning:");
+ puts(" your device does not support O/C revovery mode!\n");
+#endif /* CONFIG_QCA_GPIO_OC_RECOVERY_BTN */
+
+ puts("\n");
+ }
+
+ return 0;
+}
+
+/* Remove clock configuration from FLASH */
+int do_clear_clk(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ char buf[128];
+ u32 reg;
+ u8 *c;
+
+ /* Do we have PLL_MAGIC in FLASH? */
+ reg = qca_soc_reg_read(CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET);
+
+ if (reg == QCA_PLL_IN_FLASH_MAGIC) {
+ /* First, backup in RAM entire block where we store PLL config */
+ sprintf(buf, "cp.b 0x%lX 0x%lX 0x%lX",
+ CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET,
+ CONFIG_LOADADDR,
+ CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE);
+
+ if (run_command(buf, 0) < 0) {
+ puts("## Error: could not make data backup in RAM!\n\n");
+ return 1;
+ }
+
+ /* Clear magic value and whole configuration */
+ c = (u8 *)(CONFIG_LOADADDR +
+ (CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET
+ - CFG_FLASH_BASE
+ - CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET));
+
+ memset((void *)c, 0xFF, sizeof(clk_cfg_flash) + 4);
+
+ /* Erase FLASH and copy modified data back */
+ sprintf(buf,
+ "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX",
+ CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET,
+ CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE,
+ CONFIG_LOADADDR,
+ CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET,
+ CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE);
+
+ if (run_command(buf, 0) < 0) {
+ puts("## Error: could not erase FLASH and copy data back from RAM!\n\n");
+ return 1;
+ }
+ } else {
+ puts("** Warning: clock configuration is not stored in FLASH!\n\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(setclk, 2, 0, do_set_clk,
+ "select clocks configuration from predefined list\n",
+ "index\n"
+ "\t- save 'index' configuration in FLASH\n"
+ "setclk\n"
+ "\t- prints available clocks configurations and current settings\n");
+
+U_BOOT_CMD(clearclk, 1, 0, do_clear_clk,
+ "remove PLL and clocks configuration from FLASH\n", NULL);
+
+#endif /* CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET */
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Command Processor Table
+ * SPDX-License-Identifier: GPL-2.0
*/
+/* Command Processor Table */
#include <common.h>
#include <command.h>
-int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
+int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
extern char version_string[];
- printf("%s\n\n", version_string);
- return(0);
+ puts("Version and build date:\n");
+ printf(" %s\n " __DATE__ ", " __TIME__ "\n\n", version_string);
+
+ puts("Modification by:\n");
+ puts(" Piotr Dymacz <piotr@dymacz.pl>\n");
+ puts(" https://github.com/pepe2k/u-boot_mod\n\n");
+
+ return 0;
}
-U_BOOT_CMD(version, 1, 1, do_version, "print U-Boot version\n", NULL);
+U_BOOT_CMD(version, 1, 1, do_version,
+ "print U-Boot version\n",
+ NULL);
#if (CONFIG_COMMANDS & CFG_CMD_ECHO)
-int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
+int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
int i, putnl = 1;
- for(i = 1; i < argc; i++){
+ for (i = 1; i < argc; i++) {
char *p = argv[i], c;
- if(i > 1){
+ if (i > 1)
putc(' ');
- }
- while((c = *p++) != '\0'){
- if(c == '\\' && *p == 'c'){
+ while ((c = *p++) != '\0') {
+ if (c == '\\' && *p == 'c') {
putnl = 0;
p++;
} else {
}
}
- if(putnl){
+ if (putnl)
putc('\n');
- }
- return(0);
+ return 0;
}
-U_BOOT_CMD(echo, CFG_MAXARGS, 1, do_echo, "echo args to console\n", "[args..]\n" "\t- echo args to console; \\c suppresses newline\n");
-#endif /* CFG_CMD_ECHO */
+U_BOOT_CMD(echo, CFG_MAXARGS, 1, do_echo,
+ "echo args to console\n",
+ "[args..]\n" "\t- echo args to console; \\c suppresses newline\n");
+#endif /* CFG_CMD_ECHO */
#ifdef CFG_HUSH_PARSER
-int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
- char **ap;
+int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
int left, adv, expr, last_expr, neg, last_cmp;
+ char **ap;
/* args? */
- if (argc < 3){
- return(1);
- }
-
-#if 0
- printf("test:");
- left = 1;
- while (argv[left]){
- printf(" %s", argv[left++]);
- }
-#endif
+ if (argc < 3)
+ return 1;
last_expr = 0;
- left = argc - 1; ap = argv + 1;
+ left = argc - 1;
+ ap = argv + 1;
- if(left > 0 && strcmp(ap[0], "!") == 0){
+ if (left > 0 && strcmp(ap[0], "!") == 0) {
neg = 1;
ap++;
left--;
last_cmp = -1;
last_expr = -1;
- while(left > 0){
-
- if(strcmp(ap[0], "-o") == 0 || strcmp(ap[0], "-a") == 0){
+ while (left > 0) {
+ if (strcmp(ap[0], "-o") == 0 || strcmp(ap[0], "-a") == 0) {
adv = 1;
- } else if(strcmp(ap[0], "-z") == 0 || strcmp(ap[0], "-n") == 0){
+ } else if (strcmp(ap[0], "-z") == 0 || strcmp(ap[0], "-n") == 0) {
adv = 2;
} else {
adv = 3;
}
- if(left < adv){
+ if (left < adv) {
expr = 1;
break;
}
- if(adv == 1){
- if (strcmp(ap[0], "-o") == 0){
+ if (adv == 1) {
+ if (strcmp(ap[0], "-o") == 0) {
last_expr = expr;
last_cmp = 0;
- } else if(strcmp(ap[0], "-a") == 0){
+ } else if (strcmp(ap[0], "-a") == 0) {
last_expr = expr;
last_cmp = 1;
} else {
}
}
- if(adv == 2){
- if (strcmp(ap[0], "-z") == 0){
+ if (adv == 2) {
+ if (strcmp(ap[0], "-z") == 0) {
expr = strlen(ap[1]) == 0 ? 1 : 0;
- } else if(strcmp(ap[0], "-n") == 0){
+ } else if (strcmp(ap[0], "-n") == 0) {
expr = strlen(ap[1]) == 0 ? 0 : 1;
} else {
expr = 1;
break;
}
- if(last_cmp == 0){
+ if (last_cmp == 0) {
expr = last_expr || expr;
- } else if(last_cmp == 1){
+ } else if (last_cmp == 1) {
expr = last_expr && expr;
}
+
last_cmp = -1;
}
- if(adv == 3){
- if(strcmp(ap[1], "=") == 0){
+ if (adv == 3) {
+ if (strcmp(ap[1], "=") == 0) {
expr = strcmp(ap[0], ap[2]) == 0;
- } else if(strcmp(ap[1], "!=") == 0){
+ } else if (strcmp(ap[1], "!=") == 0) {
expr = strcmp(ap[0], ap[2]) != 0;
- } else if(strcmp(ap[1], ">") == 0){
+ } else if (strcmp(ap[1], ">") == 0) {
expr = strcmp(ap[0], ap[2]) > 0;
- } else if(strcmp(ap[1], "<") == 0){
+ } else if (strcmp(ap[1], "<") == 0) {
expr = strcmp(ap[0], ap[2]) < 0;
- } else if(strcmp(ap[1], "-eq") == 0){
+ } else if (strcmp(ap[1], "-eq") == 0) {
expr = simple_strtol(ap[0], NULL, 10) == simple_strtol(ap[2], NULL, 10);
- } else if(strcmp(ap[1], "-ne") == 0){
+ } else if (strcmp(ap[1], "-ne") == 0) {
expr = simple_strtol(ap[0], NULL, 10) != simple_strtol(ap[2], NULL, 10);
- } else if(strcmp(ap[1], "-lt") == 0){
+ } else if (strcmp(ap[1], "-lt") == 0) {
expr = simple_strtol(ap[0], NULL, 10) < simple_strtol(ap[2], NULL, 10);
- } else if(strcmp(ap[1], "-le") == 0){
+ } else if (strcmp(ap[1], "-le") == 0) {
expr = simple_strtol(ap[0], NULL, 10) <= simple_strtol(ap[2], NULL, 10);
- } else if(strcmp(ap[1], "-gt") == 0){
+ } else if (strcmp(ap[1], "-gt") == 0) {
expr = simple_strtol(ap[0], NULL, 10) > simple_strtol(ap[2], NULL, 10);
- } else if(strcmp(ap[1], "-ge") == 0){
+ } else if (strcmp(ap[1], "-ge") == 0) {
expr = simple_strtol(ap[0], NULL, 10) >= simple_strtol(ap[2], NULL, 10);
} else {
expr = 1;
break;
}
- if(last_cmp == 0){
+ if (last_cmp == 0) {
expr = last_expr || expr;
- } else if(last_cmp == 1){
+ } else if (last_cmp == 1) {
expr = last_expr && expr;
}
+
last_cmp = -1;
}
ap += adv; left -= adv;
}
- if(neg){
+ if (neg)
expr = !expr;
- }
expr = !expr;
-#if 0
- printf(": returns %d\n", expr);
-#endif
-
- return(expr);
+ return expr;
}
-U_BOOT_CMD(test, CFG_MAXARGS, 1, do_test, "minimal test like /bin/sh\n", "[args..]\n"
-"\t- test functionality\n");
+U_BOOT_CMD(test, CFG_MAXARGS, 1, do_test,
+ "minimal test like /bin/sh\n",
+ "[args..]\n\t- test functionality\n");
-int do_exit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
+int do_exit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
int r = 0;
- if(argc > 1){
+ if (argc > 1)
r = simple_strtoul(argv[1], NULL, 10);
- }
- return(-r - 2);
+ return (-r - 2);
}
-U_BOOT_CMD(exit, 2, 1, do_exit, "exit script\n", "\n\t- exit functionality\n");
+U_BOOT_CMD(exit, 2, 1, do_exit,
+ "exit script\n",
+ "\n\t- exit functionality\n");
#endif /* CFG_HUSH_PARSER */
/*
* Use puts() instead of printf() to avoid printf buffer overflow
* for long help messages
*/
-int do_help(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
+int do_help(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
int i;
int rcode = 0;
- if(argc == 1){ /*show list of commands */
+ /* Show list of commands */
+ if (argc == 1) {
+ /* Pointer arith! */
+ int cmd_items = &__u_boot_cmd_end - &__u_boot_cmd_start;
- int cmd_items = &__u_boot_cmd_end - &__u_boot_cmd_start; /* pointer arith! */
cmd_tbl_t *cmd_array[cmd_items];
int i, j, swaps, max_len = 0;
/* Make array of commands from .uboot_cmd section */
cmdtp = &__u_boot_cmd_start;
- for(i = 0; i < cmd_items; i++){
+ for (i = 0; i < cmd_items; i++) {
cmd_array[i] = cmdtp++;
}
/* Sort command list (trivial bubble sort) */
- for(i = cmd_items - 1; i > 0; --i){
+ for (i = cmd_items - 1; i > 0; --i) {
swaps = 0;
- for(j = 0; j < i; ++j){
-
+ for (j = 0; j < i; ++j) {
const char *name = cmd_array[j]->name;
- if(strlen(name) >= max_len){
+ if (strlen(name) >= max_len)
max_len = strlen(name);
- }
- if(strcmp(cmd_array[j]->name, cmd_array[j + 1]->name) > 0){
+ if (strcmp(cmd_array[j]->name, cmd_array[j + 1]->name) > 0) {
cmd_tbl_t *tmp;
tmp = cmd_array[j];
cmd_array[j] = cmd_array[j + 1];
}
}
- if(!swaps){
+ if (!swaps)
break;
- }
}
- /* print short help (usage) */
- for(i = 0; i < cmd_items; i++){
+ /* Print short help (usage) */
+ for (i = 0; i < cmd_items; i++) {
const char *usage = cmd_array[i]->usage;
const char *name = cmd_array[i]->name;
- /* allow user abort */
- if(ctrlc()){
- return(1);
- }
+ /* Allow user abort */
+ if (ctrlc())
+ return 1;
- if(usage == NULL){
+ if (usage == NULL)
continue;
- }
- /* print aligned command name and usage */
+
+ /* Print aligned command name and usage */
printf("%-*s - ", max_len, name);
puts(usage);
}
- printf("\n");
-
- return(0);
+ puts("\n");
+ return 0;
}
- /*
- * command help (long version)
- */
- for(i = 1; i < argc; ++i){
- if((cmdtp = find_cmd(argv[i])) != NULL){
+
+ /* Command help (long version) */
+ for (i = 1; i < argc; ++i) {
+ if ((cmdtp = find_cmd(argv[i])) != NULL) {
#ifdef CFG_LONGHELP
- /* found - print (long) help info */
+ /* Found - print (long) help info */
puts(cmdtp->name);
putc(' ');
- if(cmdtp->help){
+ if (cmdtp->help) {
puts(cmdtp->help);
} else {
puts("- there is no help for this command\n");
}
putc('\n');
-#else /* no long help available */
- if(cmdtp->usage){
+#else
+ if (cmdtp->usage)
puts(cmdtp->usage);
- }
#endif /* CFG_LONGHELP */
} else {
printf("Unknown command '%s' - try 'help' without arguments\n\n", argv[i]);
}
}
- return(rcode);
+ return rcode;
}
-U_BOOT_CMD(help, CFG_MAXARGS, 1, do_help, "print embedded help\n",
- "[command ...]\n"
- "\t- show help information (for 'command')\n"
+U_BOOT_CMD(help, CFG_MAXARGS, 1, do_help,
+ "print embedded help\n",
+ "[command ...]\n"
+ "\t- show help information (for 'command')\n"
"\twithout arguments, it prints a short usage message for available commands.\n");
/* This do not ust the U_BOOT_CMD macro as ? can't be used in symbol names */
cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {"?", CFG_MAXARGS, 1, do_help, "alias for 'help'\n"};
#endif /* CFG_LONGHELP */
-/***************************************************************************
- * find command table entry for a command
+/*
+ * Find command table entry for a command
*/
-cmd_tbl_t *find_cmd(const char *cmd){
+cmd_tbl_t *find_cmd(const char *cmd)
+{
cmd_tbl_t *cmdtp;
cmd_tbl_t *cmdtp_temp = &__u_boot_cmd_start; /*Init value */
const char *p;
*/
len = ((p = strchr(cmd, '.')) == NULL) ? strlen(cmd) : (p - cmd);
- for(cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++){
- if(strncmp(cmd, cmdtp->name, len) == 0){
- if(len == strlen(cmdtp->name)){
- return(cmdtp); /* full match */
- }
+ for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
+ if (strncmp(cmd, cmdtp->name, len) == 0) {
+ /* Full match? */
+ if (len == strlen(cmdtp->name))
+ return cmdtp;
- cmdtp_temp = cmdtp; /* abbreviated command ? */
+ /* Abbreviated command ? */
+ cmdtp_temp = cmdtp;
n_found++;
}
}
- if(n_found == 1){ /* exactly one match */
+
+ /* Exactly one match */
+ if (n_found == 1)
return(cmdtp_temp);
- }
- return(NULL); /* not found or ambiguous command */
+ /* Not found or ambiguous command */
+ return NULL;
}
#include <environment.h>
#include <linux/stddef.h>
#include <malloc.h>
+#include <tinf.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
void env_crc_update(void){
- env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
+ env_ptr->crc = tinf_crc32(env_ptr->data, ENV_SIZE);
}
static uchar env_get_char_init(int index){
#include <environment.h>
#include <linux/stddef.h>
#include <malloc.h>
+#include <tinf.h>
DECLARE_GLOBAL_DATA_PTR;
ulong addr1 = (ulong)&(flash_addr->data);
ulong addr2 = (ulong)&(flash_addr_new->data);
- crc1_ok = (crc32(0, flash_addr->data, ENV_SIZE) == flash_addr->crc);
- crc2_ok = (crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc);
+ crc1_ok = (tinf_crc32(flash_addr->data, ENV_SIZE) == flash_addr->crc);
+ crc2_ok = (tinf_crc32(flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc);
if(crc1_ok && !crc2_ok){
gd->env_addr = addr1;
#else /* ! CFG_ENV_ADDR_REDUND */
int env_init(void){
- if(crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc){
+ if(tinf_crc32(env_ptr->data, ENV_SIZE) == env_ptr->crc){
gd->env_addr = (ulong)&(env_ptr->data);
gd->env_valid = 1;
end_addr_new = ltmp;
}
- if(flash_addr_new->flags != OBSOLETE_FLAG && crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc){
+ if(flash_addr_new->flags != OBSOLETE_FLAG && tinf_crc32(flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc){
char flag = OBSOLETE_FLAG;
gd->env_valid = 2;
/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2005 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:GPL-2.0
*/
-/* #define DEBUG */
-
#include <common.h>
#include <flash.h>
-#if !defined(CFG_NO_FLASH)
+#ifndef CFG_NO_FLASH
-extern flash_info_t flash_info[]; /* info for FLASH chips */
+/* Info for FLASH chips */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-/*-----------------------------------------------------------------------
- * Functions
- */
-flash_info_t * addr2info(ulong addr){
+/* List of supported and known SPI NOR FLASH chips */
+static char VENDOR_ATMEL[] = "Atmel";
+static char VENDOR_EON[] = "EON";
+static char VENDOR_MACRONIX[] = "Macronix";
+static char VENDOR_MICRON[] = "Micron";
+static char VENDOR_SPANSION[] = "Spansion";
+static char VENDOR_WINBOND[] = "Winbond";
+
+const spi_nor_ids_info_t spi_nor_ids[] = {
+ /* 4 MiB */
+ { "AT25DF321", 0x1F4700, SIZE_4MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "EN25Q32", 0x1C3016, SIZE_4MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "EN25F32", 0x1C3116, SIZE_4MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "MX25L320", 0xC22016, SIZE_4MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "M25P32", 0x202016, SIZE_4MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "S25FL032P", 0x010215, SIZE_4MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "W25Q32", 0xEF4016, SIZE_4MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+
+ /* 8 MiB */
+ { "AT25DF641", 0x1F4800, SIZE_8MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "EN25Q64", 0x1C3017, SIZE_8MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "MX25L64", 0xC22017, SIZE_8MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "MX25L64", 0xC22617, SIZE_8MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "M25P64", 0x202017, SIZE_8MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "S25FL064P", 0x010216, SIZE_8MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "W25Q64", 0xEF4017, SIZE_8MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+
+ /* 16 MiB */
+ { "MX25L128", 0xC22018, SIZE_16MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "MX25L128", 0xC22618, SIZE_16MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "N25Q128", 0x20BA18, SIZE_16MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "S25FL127S", 0x012018, SIZE_16MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+ { "W25Q128", 0xEF4018, SIZE_16MiB, SIZE_64KiB, 256, SPI_FLASH_CMD_ES_64KB },
+};
+
+const u32 spi_nor_ids_count = sizeof(spi_nor_ids) / sizeof(spi_nor_ids_info_t);
+
+const char *flash_manuf_name(u32 jedec_id)
+{
+ switch (jedec_id >> 16) {
+ case FLASH_VENDOR_JEDEC_ATMEL:
+ return VENDOR_ATMEL;
+ break;
+ case FLASH_VENDOR_JEDEC_EON:
+ return VENDOR_EON;
+ break;
+ case FLASH_VENDOR_JEDEC_MACRONIX:
+ return VENDOR_MACRONIX;
+ break;
+ case FLASH_VENDOR_JEDEC_MICRON:
+ return VENDOR_MICRON;
+ break;
+ case FLASH_VENDOR_JEDEC_SPANSION:
+ return VENDOR_SPANSION;
+ break;
+ case FLASH_VENDOR_JEDEC_WINBOND:
+ return VENDOR_WINBOND;
+ break;
+ default:
+ return "Unknown";
+ break;
+ }
+}
+
+flash_info_t *addr2info(ulong addr)
+{
flash_info_t *info;
int i;
- for(i = 0, info = &flash_info[0]; i < CFG_MAX_FLASH_BANKS; ++i, ++info){
- /* WARNING - The '- 1' is needed if the flash
+ for (i = 0, info = &flash_info[0]; i < CFG_MAX_FLASH_BANKS; ++i, ++info) {
+ /*
+ * WARNING - The '- 1' is needed if the flash
* is at the end of the address space, since
* info->start[0] + info->size wraps back to 0.
* Please don't change this unless you understand this.
*/
- if(info->flash_id != FLASH_UNKNOWN && addr >= info->start[0] && addr <= info->start[0] + info->size - 1){
- return(info);
+ if (info->flash_id != FLASH_UNKNOWN
+ && addr >= info->start[0]
+ && addr <= info->start[0] + info->size - 1) {
+ return info;
}
}
- return(NULL);
+
+ return NULL;
}
-/*-----------------------------------------------------------------------
+/*
* Copy memory to flash.
* Make sure all target addresses are within Flash bounds,
* and no protected sectors are hit.
* ERR_PROTECTED 4 - target range includes protected sectors
* ERR_INVAL 8 - target address not in Flash memory
* ERR_ALIGN 16 - target address not aligned on boundary
- * (only some targets require alignment)
+ * (only some targets require alignment)
*/
-int flash_write(char *src, ulong addr, ulong cnt){
+int flash_write(char *src, ulong addr, ulong cnt)
+{
int i;
ulong end = addr + cnt - 1;
flash_info_t *info_first = addr2info(addr);
flash_info_t *info_last = addr2info(end);
flash_info_t *info;
- if(cnt == 0){
- return(ERR_OK);
- }
+ if (cnt == 0)
+ return ERR_OK;
- if(!info_first || !info_last){
- return(ERR_INVAL);
- }
+ if (!info_first || !info_last)
+ return ERR_INVAL;
- /* finally write data to flash */
- for(info = info_first; info <= info_last && cnt > 0; ++info){
- ulong len;
+ /* Finally write data to flash */
+ for (info = info_first; info <= info_last && cnt > 0; ++info) {
+ ulong len = info->start[0] + info->size - addr;
- len = info->start[0] + info->size - addr;
- if(len > cnt){
+ if (len > cnt)
len = cnt;
- }
- if((i = write_buff(info, (uchar *)src, addr, len)) != 0){
- return(i);
- }
- cnt -= len;
+
+ if ((i = write_buff(info, (uchar *)src, addr, len)) != 0)
+ return i;
+
+ cnt -= len;
addr += len;
- src += len;
+ src += len;
}
- return(ERR_OK);
-}
-/*-----------------------------------------------------------------------
- */
+ return ERR_OK;
+}
-void flash_perror(int err){
- switch(err){
- case ERR_OK:
- break;
- case ERR_TIMOUT:
- puts("## Error: timeout writing to FLASH\n");
- break;
- case ERR_NOT_ERASED:
- puts("## Error: FLASH not erased\n");
- break;
- case ERR_INVAL:
- puts("## Error: outside available FLASH\n");
- break;
- case ERR_ALIGN:
- puts("## Error: start and/or end address not on sector boundary\n");
- break;
- case ERR_UNKNOWN_FLASH_VENDOR:
- puts("## Error: unknown vendor of FLASH\n");
- break;
- case ERR_UNKNOWN_FLASH_TYPE:
- puts("## Error: unknown type of FLASH\n");
- break;
- case ERR_PROG_ERROR:
- puts("## Error: general FLASH programming error\n");
- break;
- default:
- printf("## Error: %s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err);
- break;
+void flash_perror(int err)
+{
+ switch (err) {
+ case ERR_OK:
+ break;
+ case ERR_TIMOUT:
+ puts("## Error: timeout writing to FLASH\n");
+ break;
+ case ERR_NOT_ERASED:
+ puts("## Error: FLASH not erased\n");
+ break;
+ case ERR_INVAL:
+ puts("## Error: outside available FLASH\n");
+ break;
+ case ERR_ALIGN:
+ puts("## Error: start and/or end address not on sector boundary\n");
+ break;
+ case ERR_UNKNOWN_FLASH_VENDOR:
+ puts("## Error: unknown vendor of FLASH\n");
+ break;
+ case ERR_UNKNOWN_FLASH_TYPE:
+ puts("## Error: unknown type of FLASH\n");
+ break;
+ case ERR_PROG_ERROR:
+ puts("## Error: general FLASH programming error\n");
+ break;
+ default:
+ printf("## Error: %s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err);
+ break;
}
}
-
-/*-----------------------------------------------------------------------
- */
#endif /* !CFG_NO_FLASH */
*/
#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
static __inline__ int abortboot(int bootdelay){
+#ifdef CONFIG_AUTOBOOT_STOP_CHAR
+ char stopc;
+#endif
int abort = 0;
#ifdef CONFIG_SILENT_CONSOLE
/* we got a key press */
if(tstc()){
+#ifdef CONFIG_AUTOBOOT_STOP_CHAR
+ stopc = getc();
+ if (stopc == CONFIG_AUTOBOOT_STOP_CHAR) {
+ abort = 1;
+ bootdelay = 0;
+
+ break;
+ }
+#else
/* don't auto boot */
abort = 1;
/* no more delay */
/* consume input */
(void) getc();
break;
+#endif /* CONFIG_AUTOBOOT_STOP_CHAR */
}
udelay(10000);
}
-DBUILD_TAG='"$(BUILD_TAG)"'
else
CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
-ifeq ($(COMPRESSED_UBOOT),1)
+ifdef COMPRESSED_UBOOT
CFLAGS += -DCOMPRESSED_UBOOT=1
-else
-CFLAGS += -DCOMPRESSED_UBOOT=0
endif
ifeq ($(BUILD_OPTIMIZED),y)
AFLAGS_DEBUG := -Wa,-gstabs
AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
-ifeq ($(COMPRESSED_UBOOT),1)
+ifdef COMPRESSED_UBOOT
AFLAGS += -DCOMPRESSED_UBOOT=1
-else
-AFLAGS += -DCOMPRESSED_UBOOT=0
endif
LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
-ifeq ($(COMPRESSED_UBOOT), 1)
+ifdef COMPRESSED_UBOOT
LDFLAGS_BOOTSTRAP += -Bstatic -T $(LDSCRIPT_BOOTSTRAP) -Ttext $(BOOTSTRAP_TEXT_BASE) $(PLATFORM_LDFLAGS)
endif
LIB = lib$(SOC).a
START =
+OBJS =
+SOBJS =
-OBJS = meminit.o
+OBJS += qca_common.o
+OBJS += qca_clocks.o
+OBJS += qca_sf.o
+OBJS += qca_dram.o
+SOBJS += qca_gpio_init.o
ifeq ($(BOARD), ap121)
-OBJS += ar933x_serial.o
-OBJS += ar933x_clocks.o
-SOBJS += hornet_ddr_init.o
+ OBJS += qca_hs_uart.o
+ OBJS += ag7240.o
+ SOBJS += ar933x_pll_init.o
else
-OBJS += ar7240_serial.o
+ OBJS += qca_ls_uart.o
endif
ifeq ($(BOARD), db12x)
-OBJS += ag934x.o
-else
-OBJS += ag7240.o
+ OBJS += ag934x.o
+ SOBJS += qca95xx_pll_init.o
endif
-SOBJS +=
+ifeq ($(BOARD), ap143)
+ SOBJS += qca95xx_pll_init.o
+endif
all: .depend $(START) $(LIB)
#include "ag7240.h"
#include "ag7240_phy.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#if (CONFIG_COMMANDS & CFG_CMD_MII)
#include <miiphy.h>
#else
#define _10BASET 10
#endif
-#define ag7240_unit2mac(_unit) ag7240_macs[(_unit)]
-#define ag7240_name2mac(name) strcmp(name,"eth0") ? ag7240_unit2mac(1) : ag7240_unit2mac(0)
-#define CHECK_BIT(var,pos) ((var) & (1<<(pos)))
+#define ag7240_unit2mac(_unit) ag7240_macs[(_unit)]
+#define ag7240_name2mac(name) strcmp(name,"eth0") ? ag7240_unit2mac(1) : ag7240_unit2mac(0)
uint16_t ag7240_miiphy_read(char *devname, uint32_t phaddr, uint8_t reg);
-
void ag7240_miiphy_write(char *devname, uint32_t phaddr, uint8_t reg, uint16_t data);
-
ag7240_mac_t *ag7240_macs[CFG_AG7240_NMACS];
-extern void ar933x_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq);
+/* TODO: remove extern and include header file*/
+extern void qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk,
+ u32 *spi_clk, u32 *ref_clk);
-extern int athrs26_phy_setup(int unit);
-extern int athrs26_phy_is_up(int unit);
-extern int athrs26_phy_is_fdx(int unit);
-extern int athrs26_phy_speed(int unit);
extern void athrs26_reg_init(void);
extern void athrs26_reg_init_lan(void);
extern int athrs26_mdc_check(void);
#ifdef CONFIG_F1E_PHY
-extern int athr_phy_setup(int unit);
-extern int athr_phy_is_up(int unit);
-extern int athr_phy_is_fdx(int unit);
-extern int athr_phy_speed(int unit);
extern void athr_reg_init(void);
#endif
//#define AG7240_DEBUG
-static int ag7240_send(struct eth_device *dev, volatile void *packet, int length) {
+static int ag7240_send(struct eth_device *dev, volatile void *packet, int length)
+{
int i;
- ag7240_mac_t *mac = (ag7240_mac_t *) dev->priv;
+ ag7240_mac_t *mac = (ag7240_mac_t *)dev->priv;
ag7240_desc_t *f = mac->fifo_tx[mac->next_tx];
f->pkt_start_addr = virt_to_phys(packet);
ag7240_tx_give_to_dma(f);
- flush_cache((u32) packet, length);
+ flush_cache((u32)packet, length);
ag7240_reg_wr(mac, AG7240_DMA_TX_DESC, virt_to_phys(f));
ag7240_reg_wr(mac, AG7240_DMA_TX_CTRL, AG7240_TXE);
for (i = 0; i < MAX_WAIT; i++) {
udelay(10);
- if (!ag7240_tx_owned_by_dma(f))
+ if (!ag7240_tx_owned_by_dma(f)) {
break;
+ }
}
if (i == MAX_WAIT) {
mac->next_tx = 0;
}
- return (0);
+ return 0;
}
-static int ag7240_recv(struct eth_device *dev) {
+static int ag7240_recv(struct eth_device *dev)
+{
int length;
ag7240_desc_t *f;
ag7240_mac_t *mac;
- mac = (ag7240_mac_t *) dev->priv;
+ mac = (ag7240_mac_t *)dev->priv;
for (;;) {
f = mac->fifo_rx[mac->next_rx];
-
if (ag7240_rx_owned_by_dma(f)) {
break;
}
length = f->pkt_size;
NetReceive(NetRxPackets[mac->next_rx], length - 4);
- flush_cache((u32) NetRxPackets[mac->next_rx], PKTSIZE_ALIGN);
+ flush_cache((u32)NetRxPackets[mac->next_rx], PKTSIZE_ALIGN);
ag7240_rx_give_to_dma(f);
ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 1);
}
- return (0);
+ return 0;
}
/*
* Called in ag7240_hw_start() function
- * */
-void ag7240_mii_setup(ag7240_mac_t *mac) {
+ */
+void ag7240_mii_setup(ag7240_mac_t *mac)
+{
u32 mgmt_cfg_val;
u32 cpu_freq, ddr_freq, ahb_freq;
u32 check_cnt;
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
} else {
- ar933x_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
+ qca_sys_clocks(&cpu_freq, &ddr_freq, &ahb_freq, NULL, NULL);
switch (ahb_freq / 1000000) {
case 150:
default:
mgmt_cfg_val = 0x7;
}
- if ((is_ar7241() || is_ar7242())) {
+ if ((is_ar7241() || is_ar7242())) {
/* External MII mode */
if (mac->mac_unit == 0 && is_ar7242()) {
mgmt_cfg_val = 0x6;
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
+
/* Virian */
mgmt_cfg_val = 0x4;
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
printf("Virian MDC CFG Value ==> %x\n", mgmt_cfg_val);
-
} else if (is_ar933x()) {
//GE0 receives Rx/Tx clock, and use S26 phy
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);
} else { /* Python 1.0 & 1.1 */
if (mac->mac_unit == 0) {
check_cnt = 0;
+
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
#endif
}
+
if (check_cnt == 11) {
printf("%s: MDC check failed\n", __func__);
}
}
}
-
}
}
-static void ag7240_hw_start(ag7240_mac_t *mac) {
-
+static void ag7240_hw_start(ag7240_mac_t *mac)
+{
if (mac->mac_unit) {
ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN | AG7240_MAC_CFG1_TX_EN));
ag7240_reg_rmw_set(mac, AG7240_MAC_CFG2, (AG7240_MAC_CFG2_PAD_CRC_EN | AG7240_MAC_CFG2_LEN_CHECK | AG7240_MAC_CFG2_IF_1000));
* frames now,the PC first will tx a ARP request packet, it's a broadcast packet.
*/
ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0x66b82);
- /*
+ /*
* Setting Drop CRC Errors, Pause Frames, Length Error frames
* and Multi/Broad cast frames.
*/
//ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0x7eccf);
-
ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_3, 0x1f00140);
//printf("cfg1:\t%#x\ncfg2:\t%#x\n", ag7240_reg_rd(mac, AG7240_MAC_CFG1), ag7240_reg_rd(mac, AG7240_MAC_CFG2));
}
-static int ag7240_check_link(ag7240_mac_t *mac) {
+static int ag7240_check_link(ag7240_mac_t *mac)
+{
int link = 0, duplex = 0, speed = 0;
char *s;
mac->link = link;
if (!mac->link) {
- if((s != NULL) && (strcmp(s, "nc") != 0)){
+ if ((s != NULL) && (strcmp(s, "nc") != 0)){
printf("Link down: %s\n", mac->dev->name);
}
return 0;
if (is_wasp() && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0e000000);
}
-#else
+#else
if (is_wasp() && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x06000000);
}
ag7240_set_mac_if(mac, 0);
ag7240_set_mac_speed(mac, 1);
ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
- if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0)){
+
+ if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0101);
}
break;
return 0;
}
- if (mac->link && (duplex == mac->duplex) && (speed == mac->speed)){
+ if (mac->link && (duplex == mac->duplex) && (speed == mac->speed)) {
return 1;
}
/*
* For every command we re-setup the ring and start with clean h/w rx state
*/
-static int ag7240_clean_rx(struct eth_device *dev, bd_t * bd) {
-
+static int ag7240_clean_rx(struct eth_device *dev, bd_t * bd)
+{
int i;
ag7240_desc_t *fr;
ag7240_mac_t *mac = (ag7240_mac_t*)dev->priv;
- if (!ag7240_check_link(mac)){
+ if (!ag7240_check_link(mac)) {
return 0;
}
for (i = 0; i < NO_OF_RX_FIFOS; i++) {
fr = mac->fifo_rx[i];
fr->pkt_start_addr = virt_to_phys(NetRxPackets[i]);
- flush_cache((u32) NetRxPackets[i], PKTSIZE_ALIGN);
+ flush_cache((u32)NetRxPackets[i], PKTSIZE_ALIGN);
ag7240_rx_give_to_dma(fr);
}
}
return 1;
-
}
-static int ag7240_alloc_fifo(int ndesc, ag7240_desc_t ** fifo) {
+static int ag7240_alloc_fifo(int ndesc, ag7240_desc_t ** fifo)
+{
int i;
u32 size;
uchar *p = NULL;
return -1;
}
- p = (uchar *) (((u32) p + CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1));
+ p = (uchar *)(((u32)p + CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1));
p = UNCACHED_SDRAM(p);
- for (i = 0; i < ndesc; i++)
- fifo[i] = (ag7240_desc_t *) p + i;
+ for (i = 0; i < ndesc; i++) {
+ fifo[i] = (ag7240_desc_t *)p + i;
+ }
return 0;
}
-static int ag7240_setup_fifos(ag7240_mac_t *mac) {
+static int ag7240_setup_fifos(ag7240_mac_t *mac)
+{
int i;
- if (ag7240_alloc_fifo(NO_OF_TX_FIFOS, mac->fifo_tx))
+ if (ag7240_alloc_fifo(NO_OF_TX_FIFOS, mac->fifo_tx)) {
return 1;
+ }
for (i = 0; i < NO_OF_TX_FIFOS; i++) {
mac->fifo_tx[i]->next_desc = (i == NO_OF_TX_FIFOS - 1) ? virt_to_phys(mac->fifo_tx[0]) : virt_to_phys(mac->fifo_tx[i + 1]);
ag7240_tx_own(mac->fifo_tx[i]);
}
- if (ag7240_alloc_fifo(NO_OF_RX_FIFOS, mac->fifo_rx))
+ if (ag7240_alloc_fifo(NO_OF_RX_FIFOS, mac->fifo_rx)) {
return 1;
+ }
for (i = 0; i < NO_OF_RX_FIFOS; i++) {
mac->fifo_rx[i]->next_desc = (i == NO_OF_RX_FIFOS - 1) ? virt_to_phys(mac->fifo_rx[0]) : virt_to_phys(mac->fifo_rx[i + 1]);
}
- return (1);
+ return 1;
}
-static void ag7240_halt(struct eth_device *dev) {
- ag7240_mac_t *mac = (ag7240_mac_t *) dev->priv;
+static void ag7240_halt(struct eth_device *dev)
+{
+ ag7240_mac_t *mac = (ag7240_mac_t *)dev->priv;
ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 0);
while (ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL))
;
/*
* Get MAC address stored in flash
*/
-static void ag7240_get_ethaddr(struct eth_device *dev) {
+static void ag7240_get_ethaddr(struct eth_device *dev)
+{
unsigned char *mac = dev->enetaddr;
-#ifdef OFFSET_MAC_ADDRESS
- unsigned char buffer[6];
-
- // get MAC address from flash and check it
- memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6);
+ bd_t *bd = gd->bd;
- /*
- * check first LSBit (I/G bit) and second LSBit (U/L bit) in MSByte of vendor part
- * both of them should be 0:
- * I/G bit == 0 -> Individual MAC address (unicast address)
- * U/L bit == 0 -> Burned-In-Address (BIA) MAC address
- */
- if(CHECK_BIT((buffer[0] & 0xFF), 0) == 0 && CHECK_BIT((buffer[0] & 0xFF), 1) == 0){
- mac[0] = (buffer[0] & 0xFF);
- mac[1] = (buffer[1] & 0xFF);
- mac[2] = (buffer[2] & 0xFF);
- mac[3] = (buffer[3] & 0xFF);
- mac[4] = (buffer[4] & 0xFF);
- mac[5] = (buffer[5] & 0xFF);
- } else {
- // 00-03-7F (Atheros Communications, Inc.)
- mac[0] = 0x00;
- mac[1] = 0x03;
- mac[2] = 0x7f;
- mac[3] = 0x09;
- mac[4] = 0x0b;
- mac[5] = 0xad;
-
- printf("## Error: MAC address in FLASH is invalid, using fixed!\n");
- }
-#else
- // 00-03-7F (Atheros Communications, Inc.)
- mac[0] = 0x00;
- mac[1] = 0x03;
- mac[2] = 0x7f;
- mac[3] = 0x09;
- mac[4] = 0x0b;
- mac[5] = 0xad;
-#endif
+ memcpy(mac, (void *)bd->bi_enetaddr, 6);
}
-int ag7240_enet_initialize(bd_t * bis) {
+int ag7240_enet_initialize(bd_t * bis)
+{
struct eth_device *dev[CFG_AG7240_NMACS];
u32 mask, mac_h, mac_l;
int i;
return 0;
}
- memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
- memset(dev[i], 0, sizeof(dev[i]));
+ memset(ag7240_macs[i], 0, sizeof(*ag7240_macs[i]));
+ memset(dev[i], 0, sizeof(*dev[i]));
sprintf(dev[i]->name, "eth%d", i);
ag7240_get_ethaddr(dev[i]);
dev[i]->halt = ag7240_halt;
dev[i]->send = ag7240_send;
dev[i]->recv = ag7240_recv;
- dev[i]->priv = (void *) ag7240_macs[i];
+ dev[i]->priv = (void *)ag7240_macs[i];
}
for (i = 0; i < CFG_AG7240_NMACS; i++) {
if (!i) {
mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY);
- if (is_ar7241() || is_ar7242() || is_wasp()){
+ if (is_ar7241() || is_ar7242() || is_wasp()) {
mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
}
/* if using header for register configuration, we have to */
/* configure s26 register after frame transmission is enabled */
-
if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
if (is_ar7242() || is_wasp()) {
}
/* Modified by lsz for reduceing CMD_MII, but ag7240 need this 090306 */
-uint16_t ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg) {
+uint16_t ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg)
+{
ag7240_mac_t *mac = ag7240_name2mac(devname);
uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg, val;
volatile int rddata;
return val;
}
-void ag7240_miiphy_write(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t data) {
+void ag7240_miiphy_write(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t data)
+{
ag7240_mac_t *mac = ag7240_name2mac(devname);
uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg;
volatile int rddata;
-#include <config.h>\r
-#include <common.h>\r
-#include <malloc.h>\r
-#include <net.h>\r
-#include <command.h>\r
-#include <asm/io.h>\r
-#include <asm/addrspace.h>\r
-#include <asm/types.h>\r
-#include "ar7240_soc.h"\r
-#include "ag934x.h"\r
-#include "ag934x_phy.h"\r
-\r
-#define _1000BASET 1000\r
-#define _100BASET 100\r
-#define _10BASET 10\r
-\r
-#define ag7240_unit2mac(_unit) ag7240_macs[(_unit)]\r
-#define ag7240_name2mac(name) strcmp(name,"eth0") ? ag7240_unit2mac(1) : ag7240_unit2mac(0)\r
-#define CHECK_BIT(var,pos) ((var) & (1<<(pos)))\r
-\r
-uint16_t ag7240_miiphy_read(char *devname, uint32_t phaddr, uint8_t reg);\r
-void ag7240_miiphy_write(char *devname, uint32_t phaddr, uint8_t reg, uint16_t data);\r
-ag7240_mac_t *ag7240_macs[CFG_AG7240_NMACS];\r
-extern void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq);\r
-\r
-#ifdef CFG_ATHRS26_PHY\r
-extern int athrs26_phy_setup(int unit);\r
-extern int athrs26_phy_is_up(int unit);\r
-extern int athrs26_phy_is_fdx(int unit);\r
-extern int athrs26_phy_speed(int unit);\r
-extern void athrs26_reg_init(void);\r
-extern void athrs26_reg_init_lan(void);\r
-extern int athrs26_mdc_check(void);\r
-#endif\r
-\r
-#ifdef CFG_ATHRS17_PHY\r
-extern void athrs17_reg_init(void);\r
-#endif\r
-\r
-#ifdef CFG_ATHRS27_PHY\r
-extern int athrs27_phy_setup(int unit);\r
-extern int athrs27_phy_is_up(int unit);\r
-extern int athrs27_phy_is_fdx(int unit);\r
-extern int athrs27_phy_speed(int unit);\r
-extern void athrs27_reg_init(void);\r
-extern void athrs27_reg_init_lan(void);\r
-extern int athrs27_mdc_check(void);\r
-#endif\r
-\r
-#if defined(CONFIG_F1E_PHY) || defined(CONFIG_F2E_PHY)\r
-extern int athr_phy_setup(int unit);\r
-extern int athr_phy_is_up(int unit);\r
-extern int athr_phy_is_fdx(int unit);\r
-extern int athr_phy_speed(int unit);\r
-extern void athr_reg_init(void);\r
-#endif\r
-\r
-#ifdef CONFIG_VIR_PHY\r
-extern int athr_vir_phy_setup(int unit);\r
-extern int athr_vir_phy_is_up(int unit);\r
-extern int athr_vir_phy_is_fdx(int unit);\r
-extern int athr_vir_phy_speed(int unit);\r
-extern void athr_vir_reg_init(void);\r
-#endif\r
-\r
-\r
-static int ag7240_send(struct eth_device *dev, volatile void *packet, int length){\r
- int i;\r
-\r
- ag7240_mac_t *mac = (ag7240_mac_t *)dev->priv;\r
-\r
- ag7240_desc_t *f = mac->fifo_tx[mac->next_tx];\r
-\r
- f->pkt_size = length;\r
- f->res1 = 0;\r
- f->pkt_start_addr = virt_to_phys(packet);\r
-\r
- ag7240_tx_give_to_dma(f);\r
- flush_cache((u32)packet, length);\r
- ag7240_reg_wr(mac, AG7240_DMA_TX_DESC, virt_to_phys(f));\r
- ag7240_reg_wr(mac, AG7240_DMA_TX_CTRL, AG7240_TXE);\r
-\r
- for(i = 0; i < MAX_WAIT; i++){\r
- udelay(10);\r
- if(!ag7240_tx_owned_by_dma(f)){\r
- break;\r
- }\r
- }\r
-\r
- f->pkt_start_addr = 0;\r
- f->pkt_size = 0;\r
-\r
- if(++mac->next_tx >= NO_OF_TX_FIFOS){\r
- mac->next_tx = 0;\r
- }\r
-\r
- return(0);\r
-}\r
-\r
-static int ag7240_recv(struct eth_device *dev){\r
- int length;\r
- ag7240_desc_t *f;\r
- ag7240_mac_t *mac;\r
-\r
- mac = (ag7240_mac_t *)dev->priv;\r
-\r
- for(;;){\r
- f = mac->fifo_rx[mac->next_rx];\r
- if(ag7240_rx_owned_by_dma(f)){\r
- break;\r
- }\r
-\r
- length = f->pkt_size;\r
-\r
- NetReceive(NetRxPackets[mac->next_rx] , length - 4);\r
- flush_cache((u32)NetRxPackets[mac->next_rx] , PKTSIZE_ALIGN);\r
-\r
- ag7240_rx_give_to_dma(f);\r
-\r
- if(++mac->next_rx >= NO_OF_RX_FIFOS)\r
- mac->next_rx = 0;\r
- }\r
-\r
- if(!(ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL))){\r
- ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(f));\r
- ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 1);\r
- }\r
-\r
- return(0);\r
-}\r
-\r
-/*\r
- * Called in ag7240_hw_start() function\r
- */\r
-void ag7240_mii_setup(ag7240_mac_t *mac){\r
- u32 mgmt_cfg_val;\r
- u32 cpu_freq,ddr_freq,ahb_freq;\r
- u32 check_cnt;\r
-\r
- if((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0){\r
-#ifndef CFG_DUAL_PHY_SUPPORT\r
- ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x271);\r
-#endif\r
- } else {\r
- ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x570);\r
- }\r
-\r
-#if defined(CONFIG_AR7242_S16_PHY) || defined(CFG_ATHRS17_PHY)\r
- if(is_wasp() && mac->mac_unit == 0){\r
-#ifdef CONFIG_AR7242_S16_PHY\r
- //printf("WASP ----> S16 PHY *\n");\r
-#else\r
- //printf("WASP ----> S17 PHY *\n");\r
-#endif\r
- mgmt_cfg_val = 4;\r
- \r
- if(mac->mac_unit == 0){\r
- ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);\r
- }\r
-\r
- udelay(1000);\r
-\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);\r
-\r
- return;\r
- }\r
-#endif\r
-\r
-#ifdef CFG_ATHRS27_PHY\r
- if(is_wasp()){\r
- //printf("WASP ----> S27 PHY \n");\r
- mgmt_cfg_val = 2;\r
- ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));\r
- ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);\r
- return;\r
- }\r
-#endif\r
-\r
-#ifdef CONFIG_F2E_PHY\r
- if(is_wasp()){\r
- //printf("WASP ----> F2 PHY *\n");\r
- mgmt_cfg_val = 6;\r
- ar7240_reg_wr(AG7240_ETH_CFG, (AG7240_ETH_CFG_RMII_MASTER_MODE | AG7240_ETH_CFG_RMII_GE0 | AG7240_ETH_CFG_RMII_HISPD_GE0));\r
- \r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);\r
-\r
- return;\r
- }\r
-#endif\r
-\r
-#if defined(CONFIG_F1E_PHY) || defined(CONFIG_VIR_PHY)\r
- if(is_wasp()){\r
-#ifdef CONFIG_VIR_PHY\r
- //printf("WASP ----> VIR PHY *\n");\r
-#else\r
- //printf("WASP ----> F1 PHY *\n");\r
-#endif\r
- if(mac->mac_unit == 0){\r
- ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);\r
- }\r
-\r
- mgmt_cfg_val = 6;\r
-\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);\r
-\r
- return;\r
- }\r
-#endif\r
-\r
- if((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2){\r
- mgmt_cfg_val = 0x2;\r
-\r
- if(mac->mac_unit == 0){\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);\r
- }\r
- } else {\r
- ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);\r
- \r
- // TODO: ??\r
- switch(ahb_freq/1000000){\r
- case 150:\r
- mgmt_cfg_val = 0x7;\r
- break;\r
- case 175:\r
- mgmt_cfg_val = 0x5;\r
- break;\r
- case 200:\r
- mgmt_cfg_val = 0x4;\r
- break;\r
- case 210:\r
- mgmt_cfg_val = 0x9;\r
- break;\r
- case 220:\r
- mgmt_cfg_val = 0x9;\r
- break;\r
- default:\r
- mgmt_cfg_val = 0x7;\r
- }\r
- \r
- if((is_ar7241() || is_ar7242())){\r
- /* External MII mode */\r
- if(mac->mac_unit == 0 && is_ar7242()){\r
- mgmt_cfg_val = 0x6;\r
- ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);\r
- }\r
- \r
- /* Virian */\r
- mgmt_cfg_val = 0x4;\r
- ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));\r
- ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);\r
- //printf("Virian MDC CFG Value ==> %x\n",mgmt_cfg_val);\r
- } else if(is_ar933x()){\r
- //GE0 receives Rx/Tx clock, and use S26 phy\r
- ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);\r
- mgmt_cfg_val = 0xF;\r
- \r
- if(mac->mac_unit == 1){\r
- check_cnt = 0;\r
- while(check_cnt++ < 10){\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);\r
-#ifdef CFG_ATHRS26_PHY\r
- if(athrs26_mdc_check() == 0){\r
- break;\r
- }\r
-#endif\r
- }\r
- \r
- //if(check_cnt == 11)\r
- //printf("%s: MDC check failed\n", __func__);\r
- }\r
- } else { /* Python 1.0 & 1.1 */\r
- if(mac->mac_unit == 0){\r
- check_cnt = 0;\r
- \r
- while(check_cnt++ < 10){\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));\r
- ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);\r
-#ifdef CFG_ATHRS26_PHY\r
- if(athrs26_mdc_check() == 0){\r
- break;\r
- }\r
-#endif\r
- }\r
- \r
- //if(check_cnt == 11)\r
- //printf("%s: MDC check failed\n", __func__);\r
- }\r
- }\r
- }\r
-}\r
-\r
-static void ag7240_hw_start(ag7240_mac_t *mac){\r
-\r
- if(mac->mac_unit){\r
- ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN | AG7240_MAC_CFG1_TX_EN));\r
- ag7240_reg_rmw_set(mac, AG7240_MAC_CFG2, (AG7240_MAC_CFG2_PAD_CRC_EN | AG7240_MAC_CFG2_LEN_CHECK | AG7240_MAC_CFG2_IF_1000));\r
- } else {\r
- ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN | AG7240_MAC_CFG1_TX_EN));\r
- ag7240_reg_rmw_set(mac, AG7240_MAC_CFG2, (AG7240_MAC_CFG2_PAD_CRC_EN | AG7240_MAC_CFG2_LEN_CHECK | AG7240_MAC_CFG2_IF_10_100));\r
- }\r
- \r
- ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_0, 0x1f00);\r
- ag7240_mii_setup(mac);\r
-\r
- ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_1, 0x10ffff);\r
- ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_2, 0xAAA0555);\r
-\r
- ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_4, 0x3ffff);\r
-\r
- // TODO: check this register\r
- /*\r
- * When enable the web failsafe mode in uboot,you can't drop the broadcast\r
- * frames now,the PC first will tx a ARP request packet, it's a broadcast packet.\r
- */\r
- ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0x66b82);\r
- /* \r
- * Setting Drop CRC Errors, Pause Frames,Length Error frames \r
- * and Multi/Broad cast frames. \r
- */\r
- //ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0x7eccf);\r
-\r
- ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_3, 0x1f00140);\r
- //printf(": cfg1 %#x cfg2 %#x\n", ag7240_reg_rd(mac, AG7240_MAC_CFG1), ag7240_reg_rd(mac, AG7240_MAC_CFG2));\r
-}\r
-\r
-static int ag7240_check_link(ag7240_mac_t *mac){\r
- int link = 0, duplex = 0, speed = 0;\r
- char *s;\r
-\r
- s = getenv("stdin");\r
-\r
- ag7240_phy_link(mac->mac_unit, &link);\r
- ag7240_phy_duplex(mac->mac_unit, &duplex);\r
- ag7240_phy_speed(mac->mac_unit, &speed);\r
-\r
- mac->link = link;\r
-\r
- if(!mac->link){\r
- if((s != NULL) && (strcmp(s, "nc") != 0)){\r
- printf("Link down: %s\n", mac->dev->name);\r
- }\r
- return(0);\r
- }\r
-\r
- switch(speed){\r
- case _1000BASET:\r
- ag7240_set_mac_if(mac, 1);\r
- ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));\r
- \r
- if(is_ar7242() && (mac->mac_unit == 0)){\r
- ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x1c000000);\r
- }\r
-#ifdef CONFIG_F1E_PHY\r
- if(is_wasp() && (mac->mac_unit == 0)){\r
- ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0e000000);\r
- }\r
-#elif CONFIG_VIR_PHY\r
- if(is_wasp() && (mac->mac_unit == 0)){\r
- ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x82000000);\r
- ar7240_reg_wr(AG7240_ETH_CFG, 0x000c0001);\r
- }\r
-#else \r
- if(is_wasp() && (mac->mac_unit == 0) && !is_f2e()){\r
- ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x06000000);\r
- }\r
-#endif\r
- if(is_wasp() && mac->mac_unit == 0 && is_f1e() ){\r
- ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RXD_DELAY);\r
- ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RDV_DELAY);\r
- }\r
- break;\r
-\r
- case _100BASET:\r
- ag7240_set_mac_if(mac, 0);\r
- ag7240_set_mac_speed(mac, 1);\r
- ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));\r
- \r
- if((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e()){\r
- ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0101);\r
- }\r
-\r
- if(is_wasp() && mac->mac_unit == 0 && is_f1e()){\r
- ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RXD_DELAY);\r
- ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RDV_DELAY);\r
- }\r
- break;\r
-\r
- case _10BASET:\r
- ag7240_set_mac_if(mac, 0);\r
- ag7240_set_mac_speed(mac, 0);\r
- ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));\r
-\r
- if((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e()){\r
- ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1616);\r
- }\r
-\r
- if(is_wasp() && mac->mac_unit == 0 && is_f1e()){\r
- ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);\r
- ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);\r
- }\r
- \r
- if(is_f2e()){\r
- ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RMII_HISPD_GE0);\r
- }\r
- break;\r
-\r
- default:\r
- if((s != NULL) && (strcmp(s, "nc") != 0)){\r
- printf("## Error: invalid speed detected\n");\r
- }\r
- return(0);\r
- }\r
-\r
- if(mac->link && (duplex == mac->duplex) && (speed == mac->speed)){\r
- return(1);\r
- }\r
-\r
- mac->duplex = duplex;\r
- mac->speed = speed;\r
-\r
- if((s != NULL) && (strcmp(s, "nc") != 0)){\r
- printf("Ethernet mode (duplex/speed): %d/%d Mbps\n", duplex, speed);\r
- }\r
-\r
- ag7240_set_mac_duplex(mac, duplex);\r
-\r
- return(1);\r
-}\r
-\r
-/*\r
- * For every command we re-setup the ring and start with clean h/w rx state\r
- */\r
-static int ag7240_clean_rx(struct eth_device *dev, bd_t * bd){\r
- int i;\r
- ag7240_desc_t *fr;\r
- ag7240_mac_t *mac = (ag7240_mac_t*)dev->priv;\r
-\r
- if(!ag7240_check_link(mac)){\r
- return(0);\r
- }\r
-\r
- mac->next_rx = 0;\r
- \r
- for(i = 0; i < NO_OF_RX_FIFOS; i++){\r
- fr = mac->fifo_rx[i];\r
- fr->pkt_start_addr = virt_to_phys(NetRxPackets[i]);\r
- flush_cache((u32)NetRxPackets[i], PKTSIZE_ALIGN);\r
- ag7240_rx_give_to_dma(fr);\r
- }\r
-\r
- ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(mac->fifo_rx[0]));\r
- ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, AG7240_RXE); /* rx start */\r
- \r
- udelay(1000 * 1000);\r
- return(1);\r
-}\r
-\r
-static int ag7240_alloc_fifo(int ndesc, ag7240_desc_t ** fifo){\r
- int i;\r
- u32 size;\r
- uchar *p = NULL;\r
-\r
- size = sizeof(ag7240_desc_t) * ndesc;\r
- size += CFG_CACHELINE_SIZE - 1;\r
-\r
- if((p = malloc(size)) == NULL){\r
- printf("## Error: cant allocate fifos\n");\r
- return(-1);\r
- }\r
-\r
- p = (uchar *)(((u32)p + CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1));\r
- p = UNCACHED_SDRAM(p);\r
-\r
- for(i = 0; i < ndesc; i++){\r
- fifo[i] = (ag7240_desc_t *)p + i;\r
- }\r
-\r
- return(0);\r
-}\r
-\r
-static int ag7240_setup_fifos(ag7240_mac_t *mac){\r
- int i;\r
-\r
- if(ag7240_alloc_fifo(NO_OF_TX_FIFOS, mac->fifo_tx)){\r
- return(1);\r
- }\r
-\r
- for(i = 0; i < NO_OF_TX_FIFOS; i++){\r
- mac->fifo_tx[i]->next_desc = (i == NO_OF_TX_FIFOS - 1) ? virt_to_phys(mac->fifo_tx[0]) : virt_to_phys(mac->fifo_tx[i + 1]);\r
- ag7240_tx_own(mac->fifo_tx[i]);\r
- }\r
-\r
- if(ag7240_alloc_fifo(NO_OF_RX_FIFOS, mac->fifo_rx)){\r
- return(1);\r
- }\r
-\r
- for(i = 0; i < NO_OF_RX_FIFOS; i++){\r
- mac->fifo_rx[i]->next_desc = (i == NO_OF_RX_FIFOS - 1) ? virt_to_phys(mac->fifo_rx[0]) : virt_to_phys(mac->fifo_rx[i + 1]);\r
- }\r
-\r
- return(1);\r
-}\r
-\r
-static void ag7240_halt(struct eth_device *dev){\r
- ag7240_mac_t *mac = (ag7240_mac_t *)dev->priv;\r
- ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 0);\r
- while(ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL));\r
-}\r
-\r
-/*\r
- * Get MAC address stored in flash\r
- */\r
-static void ag7240_get_ethaddr(struct eth_device *dev){\r
- unsigned char *mac = dev->enetaddr;\r
-#ifdef OFFSET_MAC_ADDRESS\r
- unsigned char buffer[6];\r
-\r
- // get MAC address from flash and check it\r
- memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6);\r
-\r
- /*\r
- * check first LSBit (I/G bit) and second LSBit (U/L bit) in MSByte of vendor part\r
- * both of them should be 0:\r
- * I/G bit == 0 -> Individual MAC address (unicast address)\r
- * U/L bit == 0 -> Burned-In-Address (BIA) MAC address\r
- */\r
- if(CHECK_BIT((buffer[0] & 0xFF), 0) == 0 && CHECK_BIT((buffer[0] & 0xFF), 1) == 0){\r
- mac[0] = (buffer[0] & 0xFF);\r
- mac[1] = (buffer[1] & 0xFF);\r
- mac[2] = (buffer[2] & 0xFF);\r
- mac[3] = (buffer[3] & 0xFF);\r
- mac[4] = (buffer[4] & 0xFF);\r
- mac[5] = (buffer[5] & 0xFF);\r
- } else {\r
- // 00-03-7F (Atheros Communications, Inc.)\r
- mac[0] = 0x00;\r
- mac[1] = 0x03;\r
- mac[2] = 0x7f;\r
- mac[3] = 0x09;\r
- mac[4] = 0x0b;\r
- mac[5] = 0xad;\r
-\r
- printf("## Error: MAC address in FLASH is invalid, using fixed!\n");
- }\r
-#else\r
- // 00-03-7F (Atheros Communications, Inc.)\r
- mac[0] = 0x00;\r
- mac[1] = 0x03;\r
- mac[2] = 0x7f;\r
- mac[3] = 0x09;\r
- mac[4] = 0x0b;\r
- mac[5] = 0xad;\r
-#endif\r
-}\r
-\r
-int ag7240_enet_initialize(bd_t * bis){\r
- struct eth_device *dev[CFG_AG7240_NMACS];\r
- u32 mask, mac_h, mac_l;\r
- int i;\r
-\r
- //printf("ag934x_enet_initialize...\n");\r
-\r
- /*\r
- if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0)){\r
- ar7240_reg_wr(AR7240_RESET,0);\r
- }\r
-\r
- if(is_ar933x()) //Turn on LED\r
- ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28) | (0xF8));\r
- */\r
-\r
- for(i = 0;i < CFG_AG7240_NMACS;i++){\r
- if((dev[i] = (struct eth_device *)malloc(sizeof(struct eth_device))) == NULL){\r
- //puts("malloc failed\n");\r
- return(0);\r
- }\r
-\r
- if((ag7240_macs[i] = (ag7240_mac_t *)malloc(sizeof(ag7240_mac_t))) == NULL){\r
- //puts("malloc failed\n");\r
- return(0);\r
- }\r
-\r
- memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));\r
- memset(dev[i], 0, sizeof(dev[i]));\r
-\r
- sprintf(dev[i]->name, "eth%d", i);\r
- ag7240_get_ethaddr(dev[i]);\r
-\r
- ag7240_macs[i]->mac_unit = i;\r
- ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ;\r
- ag7240_macs[i]->dev = dev[i];\r
-\r
- dev[i]->iobase = 0;\r
- dev[i]->init = ag7240_clean_rx;\r
- dev[i]->halt = ag7240_halt;\r
- dev[i]->send = ag7240_send;\r
- dev[i]->recv = ag7240_recv;\r
- dev[i]->priv = (void *)ag7240_macs[i];\r
- }\r
- \r
- for(i = 0;i < CFG_AG7240_NMACS;i++){\r
- eth_register(dev[i]);\r
- \r
-#if(CONFIG_COMMANDS & CFG_CMD_MII)\r
- miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);\r
-#endif\r
-\r
- ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);\r
-\r
- if(!i){\r
- mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY);\r
-\r
- if(is_ar7241() || is_ar7242() || is_wasp()){\r
- mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;\r
- }\r
-\r
- //printf(" wasp reset mask:%x \n",mask);\r
-\r
- ar7240_reg_rmw_set(AR7240_RESET, mask);\r
- udelay(1000 * 100);\r
-\r
- ar7240_reg_rmw_clear(AR7240_RESET, mask);\r
- udelay(1000 * 100);\r
-\r
- udelay(10 * 1000);\r
- }\r
-\r
- ag7240_hw_start(ag7240_macs[i]);\r
- ag7240_setup_fifos(ag7240_macs[i]);\r
-\r
- udelay(100 * 1000);\r
-\r
- //unsigned char *mac = dev[i]->enetaddr;\r
- //printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);\r
-\r
- mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);\r
- mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);\r
-\r
- ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);\r
- ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);\r
-\r
- /* if using header for register configuration, we have to */\r
- /* configure s26 register after frame transmission is enabled */\r
- if(ag7240_macs[i]->mac_unit == 0){ /* WAN Phy */\r
-#ifdef CONFIG_AR7242_S16_PHY\r
- if(is_ar7242() || is_wasp()){\r
- athrs16_reg_init();\r
- } else\r
-#endif\r
- {\r
-#ifdef CFG_ATHRS17_PHY\r
- athrs17_reg_init();\r
-#endif\r
-\r
-#ifdef CFG_ATHRS26_PHY\r
- athrs26_reg_init();\r
-#endif\r
-\r
-#ifdef CFG_ATHRS27_PHY\r
- //printf("s27 reg init \n");\r
- athrs27_reg_init();\r
-#endif\r
-\r
-#ifdef CONFIG_F1E_PHY\r
- //printf("F1Phy reg init \n");\r
- athr_reg_init();\r
-#endif\r
-\r
-#ifdef CONFIG_VIR_PHY\r
- //printf("VIRPhy reg init \n");\r
- athr_vir_reg_init();\r
-#endif\r
-\r
-#ifdef CONFIG_F2E_PHY\r
- //printf("F2Phy reg init \n");\r
- athr_reg_init();\r
-#endif\r
-\r
- }\r
- } else {\r
-#ifdef CFG_ATHRS26_PHY\r
- athrs26_reg_init_lan();\r
-#endif\r
-\r
-#ifdef CFG_ATHRS27_PHY\r
- //printf("s27 reg init lan \n");\r
- athrs27_reg_init_lan();\r
-#endif\r
- }\r
-\r
- ag7240_phy_setup(ag7240_macs[i]->mac_unit);\r
- //printf("%s up\n",dev[i]->name);\r
- }\r
-\r
- return(1);\r
-}\r
-\r
-uint16_t ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg){\r
- ag7240_mac_t *mac = ag7240_name2mac(devname);\r
- uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg, val;\r
- volatile int rddata;\r
- uint16_t ii = 0xFFFF;\r
-\r
- /*\r
- * Check for previous transactions are complete. Added to avoid\r
- * race condition while running at higher frequencies.\r
- */\r
- do {\r
- udelay(5);\r
- rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;\r
- } while(rddata && --ii);\r
-\r
- //if(ii == 0)\r
- //printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);\r
-\r
- ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);\r
- ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr);\r
- ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, AG7240_MGMT_CMD_READ);\r
-\r
- do {\r
- udelay(5);\r
- rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;\r
- } while(rddata && --ii);\r
-\r
- //if(ii==0)\r
- //printf("Error!!! Leave ag7240_miiphy_read without polling correct status!\n");\r
-\r
- val = ag7240_reg_rd(mac, AG7240_MII_MGMT_STATUS);\r
- ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);\r
-\r
- return(val);\r
-}\r
-\r
-void ag7240_miiphy_write(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t data){\r
- ag7240_mac_t *mac = ag7240_name2mac(devname);\r
- uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg;\r
- volatile int rddata;\r
- uint16_t ii = 0xFFFF;\r
-\r
- /*\r
- * Check for previous transactions are complete. Added to avoid\r
- * race condition while running at higher frequencies.\r
- */\r
- do {\r
- udelay(5);\r
- rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;\r
- } while(rddata && --ii);\r
-\r
- //if(ii == 0)\r
- //printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);\r
-\r
- ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr);\r
- ag7240_reg_wr(mac, AG7240_MII_MGMT_CTRL, data);\r
-\r
- do {\r
- rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;\r
- } while(rddata && --ii);\r
-\r
-}\r
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include "ar7240_soc.h"
+#include "ag934x.h"
+#include "ag934x_phy.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define _1000BASET 1000
+#define _100BASET 100
+#define _10BASET 10
+
+#define ag7240_unit2mac(_unit) ag7240_macs[(_unit)]
+#define ag7240_name2mac(name) strcmp(name,"eth0") ? ag7240_unit2mac(1) : ag7240_unit2mac(0)
+
+uint16_t ag7240_miiphy_read(char *devname, uint32_t phaddr, uint8_t reg);
+void ag7240_miiphy_write(char *devname, uint32_t phaddr, uint8_t reg, uint16_t data);
+ag7240_mac_t *ag7240_macs[CFG_AG7240_NMACS];
+
+/* TODO: remove extern and include header file*/
+extern void qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk,
+ u32 *spi_clk, u32 *ref_clk);
+
+#ifdef CFG_ATHRS26_PHY
+extern void athrs26_reg_init(void);
+extern void athrs26_reg_init_lan(void);
+extern int athrs26_mdc_check(void);
+#endif
+
+#ifdef CFG_ATHRS17_PHY
+extern void athrs17_reg_init(void);
+#endif
+
+#ifdef CFG_ATHRS27_PHY
+extern void athrs27_reg_init(void);
+extern void athrs27_reg_init_lan(void);
+#endif
+
+#if defined(CONFIG_F1E_PHY) || defined(CONFIG_F2E_PHY)
+extern void athr_reg_init(void);
+#endif
+
+#ifdef CONFIG_VIR_PHY
+extern void athr_vir_reg_init(void);
+#endif
+
+static int ag7240_send(struct eth_device *dev, volatile void *packet, int length)
+{
+ int i;
+
+ ag7240_mac_t *mac = (ag7240_mac_t *)dev->priv;
+
+ ag7240_desc_t *f = mac->fifo_tx[mac->next_tx];
+
+ f->pkt_size = length;
+ f->res1 = 0;
+ f->pkt_start_addr = virt_to_phys(packet);
+
+ ag7240_tx_give_to_dma(f);
+ flush_cache((u32)packet, length);
+ ag7240_reg_wr(mac, AG7240_DMA_TX_DESC, virt_to_phys(f));
+ ag7240_reg_wr(mac, AG7240_DMA_TX_CTRL, AG7240_TXE);
+
+ for (i = 0; i < MAX_WAIT; i++) {
+ udelay(10);
+ if (!ag7240_tx_owned_by_dma(f)) {
+ break;
+ }
+ }
+
+ f->pkt_start_addr = 0;
+ f->pkt_size = 0;
+
+ if (++mac->next_tx >= NO_OF_TX_FIFOS) {
+ mac->next_tx = 0;
+ }
+
+ return 0;
+}
+
+static int ag7240_recv(struct eth_device *dev)
+{
+ int length;
+ ag7240_desc_t *f;
+ ag7240_mac_t *mac;
+
+ mac = (ag7240_mac_t *)dev->priv;
+
+ for (;;) {
+ f = mac->fifo_rx[mac->next_rx];
+ if (ag7240_rx_owned_by_dma(f)) {
+ break;
+ }
+
+ length = f->pkt_size;
+
+ NetReceive(NetRxPackets[mac->next_rx], length - 4);
+ flush_cache((u32)NetRxPackets[mac->next_rx], PKTSIZE_ALIGN);
+
+ ag7240_rx_give_to_dma(f);
+
+ if (++mac->next_rx >= NO_OF_RX_FIFOS) {
+ mac->next_rx = 0;
+ }
+ }
+
+ if (!(ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL))) {
+ ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(f));
+ ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 1);
+ }
+
+ return 0;
+}
+
+/*
+ * Called in ag7240_hw_start() function
+ */
+void ag7240_mii_setup(ag7240_mac_t *mac)
+{
+ u32 mgmt_cfg_val;
+ u32 cpu_freq, ddr_freq, ahb_freq;
+ u32 check_cnt;
+
+ if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
+#ifndef CFG_DUAL_PHY_SUPPORT
+ ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x271);
+#endif
+ } else {
+ ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x570);
+ }
+
+#if defined(CONFIG_AR7242_S16_PHY) || defined(CFG_ATHRS17_PHY)
+ if (is_wasp() && mac->mac_unit == 0) {
+#ifdef CONFIG_AR7242_S16_PHY
+ //printf("WASP ----> S16 PHY *\n");
+#else
+ //printf("WASP ----> S17 PHY *\n");
+#endif
+ mgmt_cfg_val = 4;
+
+ if(mac->mac_unit == 0){
+ ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
+ }
+
+ udelay(1000);
+
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+
+ return;
+ }
+#endif
+
+#ifdef CFG_ATHRS27_PHY
+ if (is_wasp()) {
+ //printf("WASP ----> S27 PHY \n");
+ mgmt_cfg_val = 2;
+ ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+ return;
+ }
+#endif
+
+#ifdef CONFIG_F2E_PHY
+ if (is_wasp()) {
+ //printf("WASP ----> F2 PHY *\n");
+ mgmt_cfg_val = 6;
+ ar7240_reg_wr(AG7240_ETH_CFG, (AG7240_ETH_CFG_RMII_MASTER_MODE | AG7240_ETH_CFG_RMII_GE0 | AG7240_ETH_CFG_RMII_HISPD_GE0));
+
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+
+ return;
+ }
+#endif
+
+#if defined(CONFIG_F1E_PHY) || defined(CONFIG_VIR_PHY)
+ if (is_wasp()) {
+#ifdef CONFIG_VIR_PHY
+ //printf("WASP ----> VIR PHY *\n");
+#else
+ //printf("WASP ----> F1 PHY *\n");
+#endif
+ if(mac->mac_unit == 0){
+ ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
+ }
+
+ mgmt_cfg_val = 6;
+
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+
+ return;
+ }
+#endif
+
+ if ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) {
+ mgmt_cfg_val = 0x2;
+ if (mac->mac_unit == 0) {
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+ }
+ } else {
+ qca_sys_clocks(&cpu_freq, &ddr_freq, &ahb_freq, NULL, NULL);
+
+ // TODO: ??
+ switch (ahb_freq / 1000000) {
+ case 150:
+ mgmt_cfg_val = 0x7;
+ break;
+ case 175:
+ mgmt_cfg_val = 0x5;
+ break;
+ case 200:
+ mgmt_cfg_val = 0x4;
+ break;
+ case 210:
+ mgmt_cfg_val = 0x9;
+ break;
+ case 220:
+ mgmt_cfg_val = 0x9;
+ break;
+ default:
+ mgmt_cfg_val = 0x7;
+ }
+
+ if ((is_ar7241() || is_ar7242())) {
+ /* External MII mode */
+ if (mac->mac_unit == 0 && is_ar7242()) {
+ mgmt_cfg_val = 0x6;
+ ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+ }
+
+ /* Virian */
+ mgmt_cfg_val = 0x4;
+ ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+ //printf("Virian MDC CFG Value ==> %x\n",mgmt_cfg_val);
+ } else if (is_ar933x()) {
+ //GE0 receives Rx/Tx clock, and use S26 phy
+ ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);
+ mgmt_cfg_val = 0xF;
+ if (mac->mac_unit == 1) {
+ check_cnt = 0;
+ while (check_cnt++ < 10) {
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+#ifdef CFG_ATHRS26_PHY
+ if (athrs26_mdc_check() == 0) {
+ break;
+ }
+#endif
+ }
+
+ //if(check_cnt == 11)
+ //printf("%s: MDC check failed\n", __func__);
+ }
+ } else { /* Python 1.0 & 1.1 */
+ if (mac->mac_unit == 0) {
+ check_cnt = 0;
+
+ while (check_cnt++ < 10) {
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
+ ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
+#ifdef CFG_ATHRS26_PHY
+ if (athrs26_mdc_check() == 0) {
+ break;
+ }
+#endif
+ }
+
+ //if(check_cnt == 11)
+ //printf("%s: MDC check failed\n", __func__);
+ }
+ }
+ }
+}
+
+static void ag7240_hw_start(ag7240_mac_t *mac)
+{
+ if (mac->mac_unit) {
+ ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN | AG7240_MAC_CFG1_TX_EN));
+ ag7240_reg_rmw_set(mac, AG7240_MAC_CFG2, (AG7240_MAC_CFG2_PAD_CRC_EN | AG7240_MAC_CFG2_LEN_CHECK | AG7240_MAC_CFG2_IF_1000));
+ } else {
+ ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN | AG7240_MAC_CFG1_TX_EN));
+ ag7240_reg_rmw_set(mac, AG7240_MAC_CFG2, (AG7240_MAC_CFG2_PAD_CRC_EN | AG7240_MAC_CFG2_LEN_CHECK | AG7240_MAC_CFG2_IF_10_100));
+ }
+
+ ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_0, 0x1f00);
+ ag7240_mii_setup(mac);
+
+ ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_1, 0x10ffff);
+ ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_2, 0xAAA0555);
+
+ ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_4, 0x3ffff);
+
+ // TODO: check this register
+ /*
+ * When enable the web failsafe mode in uboot,you can't drop the broadcast
+ * frames now,the PC first will tx a ARP request packet, it's a broadcast packet.
+ */
+ ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0x66b82);
+ /*
+ * Setting Drop CRC Errors, Pause Frames, Length Error frames
+ * and Multi/Broad cast frames.
+ */
+ //ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0x7eccf);
+
+ ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_3, 0x1f00140);
+ //printf(": cfg1 %#x cfg2 %#x\n", ag7240_reg_rd(mac, AG7240_MAC_CFG1), ag7240_reg_rd(mac, AG7240_MAC_CFG2));
+}
+
+static int ag7240_check_link(ag7240_mac_t *mac)
+{
+ int link = 0, duplex = 0, speed = 0;
+ char *s;
+
+ s = getenv("stdin");
+
+ ag7240_phy_link(mac->mac_unit, &link);
+ ag7240_phy_duplex(mac->mac_unit, &duplex);
+ ag7240_phy_speed(mac->mac_unit, &speed);
+
+ mac->link = link;
+
+ if (!mac->link) {
+ if ((s != NULL) && (strcmp(s, "nc") != 0)){
+ printf("Link down: %s\n", mac->dev->name);
+ }
+ return 0;
+ }
+
+ switch (speed) {
+ case _1000BASET:
+ ag7240_set_mac_if(mac, 1);
+ ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
+
+ if(is_ar7242() && (mac->mac_unit == 0)){
+ ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x1c000000);
+ }
+#ifdef CONFIG_F1E_PHY
+ if(is_wasp() && (mac->mac_unit == 0)){
+ ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0e000000);
+ }
+#elif CONFIG_VIR_PHY
+ if(is_wasp() && (mac->mac_unit == 0)){
+ ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x82000000);
+ ar7240_reg_wr(AG7240_ETH_CFG, 0x000c0001);
+ }
+#else
+ if (is_wasp() && (mac->mac_unit == 0) && !is_f2e()){
+ ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x06000000);
+ }
+#endif
+ if(is_wasp() && mac->mac_unit == 0 && is_f1e() ){
+ ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RXD_DELAY);
+ ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RDV_DELAY);
+ }
+ break;
+
+ case _100BASET:
+ ag7240_set_mac_if(mac, 0);
+ ag7240_set_mac_speed(mac, 1);
+ ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
+
+ if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e()) {
+ ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0101);
+ }
+
+ if (is_wasp() && mac->mac_unit == 0 && is_f1e()) {
+ ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RXD_DELAY);
+ ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RDV_DELAY);
+ }
+ break;
+
+ case _10BASET:
+ ag7240_set_mac_if(mac, 0);
+ ag7240_set_mac_speed(mac, 0);
+ ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
+
+ if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e()) {
+ ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1616);
+ }
+
+ if (is_wasp() && mac->mac_unit == 0 && is_f1e()){
+ ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);
+ ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);
+ }
+
+ if (is_f2e()) {
+ ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RMII_HISPD_GE0);
+ }
+ break;
+
+ default:
+ if ((s != NULL) && (strcmp(s, "nc") != 0)) {
+ printf("## Error: invalid speed detected\n");
+ }
+ return 0;
+ }
+
+ if (mac->link && (duplex == mac->duplex) && (speed == mac->speed)) {
+ return 1;
+ }
+
+ mac->duplex = duplex;
+ mac->speed = speed;
+
+ if((s != NULL) && (strcmp(s, "nc") != 0)){
+ printf("Ethernet mode (duplex/speed): %d/%d Mbps\n", duplex, speed);
+ }
+
+ ag7240_set_mac_duplex(mac, duplex);
+
+ return 1;
+}
+
+/*
+ * For every command we re-setup the ring and start with clean h/w rx state
+ */
+static int ag7240_clean_rx(struct eth_device *dev, bd_t * bd)
+{
+ int i;
+ ag7240_desc_t *fr;
+ ag7240_mac_t *mac = (ag7240_mac_t*)dev->priv;
+
+ if (!ag7240_check_link(mac)) {
+ return 0;
+ }
+
+ mac->next_rx = 0;
+
+ for (i = 0; i < NO_OF_RX_FIFOS; i++) {
+ fr = mac->fifo_rx[i];
+ fr->pkt_start_addr = virt_to_phys(NetRxPackets[i]);
+ flush_cache((u32)NetRxPackets[i], PKTSIZE_ALIGN);
+ ag7240_rx_give_to_dma(fr);
+ }
+
+ ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(mac->fifo_rx[0]));
+ ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, AG7240_RXE); /* rx start */
+
+ udelay(1000 * 1000);
+ return 1;
+}
+
+static int ag7240_alloc_fifo(int ndesc, ag7240_desc_t ** fifo)
+{
+ int i;
+ u32 size;
+ uchar *p = NULL;
+
+ size = sizeof(ag7240_desc_t) * ndesc;
+ size += CFG_CACHELINE_SIZE - 1;
+
+ if ((p = malloc(size)) == NULL) {
+ printf("## Error: cant allocate fifos\n");
+ return -1;
+ }
+
+ p = (uchar *)(((u32)p + CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1));
+ p = UNCACHED_SDRAM(p);
+
+ for (i = 0; i < ndesc; i++) {
+ fifo[i] = (ag7240_desc_t *)p + i;
+ }
+
+ return 0;
+}
+
+static int ag7240_setup_fifos(ag7240_mac_t *mac)
+{
+ int i;
+
+ if (ag7240_alloc_fifo(NO_OF_TX_FIFOS, mac->fifo_tx)) {
+ return 1;
+ }
+
+ for (i = 0; i < NO_OF_TX_FIFOS; i++) {
+ mac->fifo_tx[i]->next_desc = (i == NO_OF_TX_FIFOS - 1) ? virt_to_phys(mac->fifo_tx[0]) : virt_to_phys(mac->fifo_tx[i + 1]);
+ ag7240_tx_own(mac->fifo_tx[i]);
+ }
+
+ if (ag7240_alloc_fifo(NO_OF_RX_FIFOS, mac->fifo_rx)) {
+ return 1;
+ }
+
+ for (i = 0; i < NO_OF_RX_FIFOS; i++) {
+ mac->fifo_rx[i]->next_desc = (i == NO_OF_RX_FIFOS - 1) ? virt_to_phys(mac->fifo_rx[0]) : virt_to_phys(mac->fifo_rx[i + 1]);
+ }
+
+ return 1;
+}
+
+static void ag7240_halt(struct eth_device *dev)
+{
+ ag7240_mac_t *mac = (ag7240_mac_t *)dev->priv;
+ ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 0);
+ while (ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL))
+ ;
+}
+
+/*
+ * Get MAC address stored in flash
+ */
+static void ag7240_get_ethaddr(struct eth_device *dev)
+{
+ unsigned char *mac = dev->enetaddr;
+ bd_t *bd = gd->bd;
+
+ memcpy(mac, (void *)bd->bi_enetaddr, 6);
+}
+
+int ag7240_enet_initialize(bd_t * bis)
+{
+ struct eth_device *dev[CFG_AG7240_NMACS];
+ u32 mask, mac_h, mac_l;
+ int i;
+
+ //printf("ag934x_enet_initialize...\n");
+
+ /*
+ if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0)){
+ ar7240_reg_wr(AR7240_RESET,0);
+ }
+
+ if(is_ar933x()) //Turn on LED
+ ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28) | (0xF8));
+ */
+
+ for (i = 0;i < CFG_AG7240_NMACS;i++) {
+ if ((dev[i] = (struct eth_device *)malloc(sizeof(struct eth_device))) == NULL) {
+ //puts("malloc failed\n");
+ return 0;
+ }
+
+ if ((ag7240_macs[i] = (ag7240_mac_t *)malloc(sizeof(ag7240_mac_t))) == NULL) {
+ //puts("malloc failed\n");
+ return 0;
+ }
+
+ memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
+ memset(dev[i], 0, sizeof(dev[i]));
+
+ sprintf(dev[i]->name, "eth%d", i);
+ ag7240_get_ethaddr(dev[i]);
+
+ ag7240_macs[i]->mac_unit = i;
+ ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE;
+ ag7240_macs[i]->dev = dev[i];
+
+ dev[i]->iobase = 0;
+ dev[i]->init = ag7240_clean_rx;
+ dev[i]->halt = ag7240_halt;
+ dev[i]->send = ag7240_send;
+ dev[i]->recv = ag7240_recv;
+ dev[i]->priv = (void *)ag7240_macs[i];
+ }
+
+ for (i = 0; i < CFG_AG7240_NMACS; i++) {
+
+ eth_register(dev[i]);
+
+#if(CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
+#endif
+
+ ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);
+
+ if (!i) {
+ mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY);
+
+ if (is_ar7241() || is_ar7242() || is_wasp()) {
+ mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
+ }
+
+ //printf(" wasp reset mask:%x \n",mask);
+
+ ar7240_reg_rmw_set(AR7240_RESET, mask);
+ udelay(1000 * 100);
+
+ ar7240_reg_rmw_clear(AR7240_RESET, mask);
+ udelay(1000 * 100);
+
+ udelay(10 * 1000);
+ }
+
+ ag7240_hw_start(ag7240_macs[i]);
+
+ ag7240_setup_fifos(ag7240_macs[i]);
+
+ udelay(100 * 1000);
+
+ //unsigned char *mac = dev[i]->enetaddr;
+ //printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
+
+ mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
+ mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
+
+ ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
+ ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);
+
+ /* if using header for register configuration, we have to */
+ /* configure s26 register after frame transmission is enabled */
+ if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */
+#ifdef CONFIG_AR7242_S16_PHY
+ if (is_ar7242() || is_wasp()) {
+ athrs16_reg_init();
+ } else
+#endif
+ {
+#ifdef CFG_ATHRS17_PHY
+ athrs17_reg_init();
+#endif
+
+#ifdef CFG_ATHRS26_PHY
+ athrs26_reg_init();
+#endif
+
+#ifdef CFG_ATHRS27_PHY
+ //printf("s27 reg init \n");
+ athrs27_reg_init();
+#endif
+
+#ifdef CONFIG_F1E_PHY
+ //printf("F1Phy reg init \n");
+ athr_reg_init();
+#endif
+
+#ifdef CONFIG_VIR_PHY
+ //printf("VIRPhy reg init \n");
+ athr_vir_reg_init();
+#endif
+
+#ifdef CONFIG_F2E_PHY
+ //printf("F2Phy reg init \n");
+ athr_reg_init();
+#endif
+
+ }
+ } else {
+#ifdef CFG_ATHRS26_PHY
+ athrs26_reg_init_lan();
+#endif
+
+#ifdef CFG_ATHRS27_PHY
+ //printf("s27 reg init lan \n");
+ athrs27_reg_init_lan();
+#endif
+ }
+
+ ag7240_phy_setup(ag7240_macs[i]->mac_unit);
+ //printf("%s up\n",dev[i]->name);
+ }
+
+ return 1;
+}
+
+uint16_t ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg)
+{
+ ag7240_mac_t *mac = ag7240_name2mac(devname);
+ uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg, val;
+ volatile int rddata;
+ uint16_t ii = 0xFFFF;
+
+ /*
+ * Check for previous transactions are complete. Added to avoid
+ * race condition while running at higher frequencies.
+ */
+ do {
+ udelay(5);
+ rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
+ } while (rddata && --ii);
+
+ //if(ii == 0)
+ //printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
+
+ ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);
+ ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr);
+ ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, AG7240_MGMT_CMD_READ);
+
+ do {
+ udelay(5);
+ rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
+ } while (rddata && --ii);
+
+ //if(ii==0)
+ //printf("Error!!! Leave ag7240_miiphy_read without polling correct status!\n");
+
+ val = ag7240_reg_rd(mac, AG7240_MII_MGMT_STATUS);
+ ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);
+
+ return val;
+}
+
+void ag7240_miiphy_write(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t data)
+{
+ ag7240_mac_t *mac = ag7240_name2mac(devname);
+ uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg;
+ volatile int rddata;
+ uint16_t ii = 0xFFFF;
+
+ /*
+ * Check for previous transactions are complete. Added to avoid
+ * race condition while running at higher frequencies.
+ */
+ do {
+ udelay(5);
+ rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
+ } while (rddata && --ii);
+
+ //if(ii == 0)
+ //printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
+
+ ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr);
+ ag7240_reg_wr(mac, AG7240_MII_MGMT_CTRL, data);
+
+ do {
+ rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
+ } while (rddata && --ii);
+
+}
+++ /dev/null
-#include <asm/addrspace.h>\r
-#include <asm/types.h>\r
-#include <config.h>\r
-#include <ar7240_soc.h>\r
-\r
-#define REG_OFFSET 4\r
-\r
-/* === END OF CONFIG === */\r
-\r
-/* register offset */\r
-#define OFS_RCV_BUFFER (0*REG_OFFSET)\r
-#define OFS_TRANS_HOLD (0*REG_OFFSET)\r
-#define OFS_SEND_BUFFER (0*REG_OFFSET)\r
-#define OFS_INTR_ENABLE (1*REG_OFFSET)\r
-#define OFS_INTR_ID (2*REG_OFFSET)\r
-#define OFS_DATA_FORMAT (3*REG_OFFSET)\r
-#define OFS_LINE_CONTROL (3*REG_OFFSET)\r
-#define OFS_MODEM_CONTROL (4*REG_OFFSET)\r
-#define OFS_RS232_OUTPUT (4*REG_OFFSET)\r
-#define OFS_LINE_STATUS (5*REG_OFFSET)\r
-#define OFS_MODEM_STATUS (6*REG_OFFSET)\r
-#define OFS_RS232_INPUT (6*REG_OFFSET)\r
-#define OFS_SCRATCH_PAD (7*REG_OFFSET)\r
-\r
-#define OFS_DIVISOR_LSB (0*REG_OFFSET)\r
-#define OFS_DIVISOR_MSB (1*REG_OFFSET)\r
-\r
-#define MY_WRITE(y, z) ((*((volatile u32*)(y))) = z)\r
-#define UART16550_READ(y) ar7240_reg_rd((AR7240_UART_BASE+y))\r
-#define UART16550_WRITE(x, z) ar7240_reg_wr((AR7240_UART_BASE+x), z)\r
-\r
-/*\r
- * This is taken from [Linux]/include/linux/kernel.h\r
- * Keep the name unchanged here\r
- * When this project decides to include that kernel.h some time,\r
- * this would be found "automatically" and be removed hopefully\r
- */\r
-#define DIV_ROUND_CLOSEST(x, divisor)( \\r
-{ \\r
- typeof(divisor) __divisor = divisor; \\r
- (((x) + ((__divisor) / 2)) / (__divisor)); \\r
-} \\r
-)\r
-\r
-/*\r
- * Get CPU, RAM and AHB clocks\r
- * Based on: Linux/arch/mips/ath79/clock.c\r
- */\r
-void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq){\r
-#ifdef CONFIG_WASP\r
- u32 ref_rate, pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv, cpu_pll, ddr_pll;\r
-\r
- // determine reference clock (25 or 40 MHz)\r
- pll = ar7240_reg_rd(RST_BOOTSTRAP_ADDRESS);\r
-\r
- if(pll & 0x10){ // bit 4 == 1 -> REF_CLK == 40 MHz\r
- ref_rate = 40000000;\r
- } else {\r
- ref_rate = 25000000;\r
- }\r
-\r
- pll = ar7240_reg_rd(DPLL2_ADDRESS_c4);\r
-\r
- // CPU PLL from SRIF?\r
- if(pll & (1 << 30)){\r
-\r
- out_div = (pll >> 13) & 0x7;\r
- pll = ar7240_reg_rd(0x181161c0);\r
- nint = (pll >> 18) & 0x1ff;\r
- //nfrac = pll & 0x0003ffff;\r
- ref_div = (pll >> 27) & 0x1f;\r
- //frac = 1 << 18;\r
-\r
- } else {\r
- // only for tests\r
- // TODO: fix me\r
- *cpu_freq = 560000000;\r
- *ddr_freq = 400000000;\r
- *ahb_freq = 200000000;\r
- return;\r
- }\r
-\r
- cpu_pll = (ref_rate / ref_div) * nint;\r
- cpu_pll /= (1 << out_div);\r
-\r
- // DDR PLL from SRIF?\r
- pll = ar7240_reg_rd(DPLL2_ADDRESS_44);\r
-\r
- if (pll & (1 << 30)) {\r
-\r
- out_div = (pll >> 13) & 0x7;\r
- pll = ar7240_reg_rd(0x18116240);\r
- nint = (pll >> 18) & 0x1ff;\r
- //nfrac = pll & 0x0003ffff;\r
- ref_div = (pll >> 27) & 0x1f;\r
- //frac = 1 << 18;\r
-\r
- } else {\r
- // only for tests\r
- // TODO: fix me\r
- *cpu_freq = 560000000;\r
- *ddr_freq = 400000000;\r
- *ahb_freq = 200000000;\r
- return;\r
- }\r
-\r
- ddr_pll = (ref_rate / ref_div) * nint;\r
- ddr_pll /= (1 << out_div);\r
-\r
- clk_ctrl = ar7240_reg_rd(AR934X_CPU_DDR_CLOCK_CONTROL);\r
-\r
- postdiv = (clk_ctrl >> 5) & 0x1f;\r
-\r
- // CPU CLK\r
- if(clk_ctrl & (1 << 2)){ // CPU_PLL_BYPASS\r
- *cpu_freq = ref_rate;\r
- } else if(clk_ctrl & (1 << 20)){ // CPU CLK is derived from CPU_PLL\r
- *cpu_freq = cpu_pll / (postdiv + 1);\r
- } else { // CPU CLK is derived from DDR_PLL\r
- *cpu_freq = ddr_pll / (postdiv + 1);\r
- }\r
-\r
- postdiv = (clk_ctrl >> 10) & 0x1f;\r
-\r
- // DDR CLK\r
- if(clk_ctrl & (1 << 3)){ // DDR_PLL_BYPASS\r
- *ddr_freq = ref_rate;\r
- } else if(clk_ctrl & (1 << 21)){ // DDR CLK is derived from DDR_PLL\r
- *ddr_freq = ddr_pll / (postdiv + 1);\r
- } else { // DDR CLK is derived from CPU_PLL\r
- *ddr_freq = cpu_pll / (postdiv + 1);\r
- }\r
-\r
- postdiv = (clk_ctrl >> 15) & 0x1f;\r
-\r
- // AHB CLK\r
- if(clk_ctrl & (1 << 4)){ // AHB_PLL_BYPASS\r
- *ahb_freq = ref_rate;\r
- } else if(clk_ctrl & (1 << 24)){ // AHB CLK is derived from DDR_PLL\r
- *ahb_freq = ddr_pll / (postdiv + 1);\r
- } else { // AHB CLK is derived from CPU_PLL\r
- *ahb_freq = cpu_pll / (postdiv + 1);\r
- }\r
-\r
-#else\r
- u32 pll, pll_div, ref_div, ahb_div, ddr_div, freq;\r
-\r
- pll = ar7240_reg_rd(AR7240_CPU_PLL_CONFIG);\r
-\r
- pll_div = ((pll & PLL_CONFIG_PLL_DIV_MASK) >> PLL_CONFIG_PLL_DIV_SHIFT);\r
- ref_div = ((pll & PLL_CONFIG_PLL_REF_DIV_MASK) >> PLL_CONFIG_PLL_REF_DIV_SHIFT);\r
- ddr_div = ((pll & PLL_CONFIG_DDR_DIV_MASK) >> PLL_CONFIG_DDR_DIV_SHIFT) + 1;\r
- ahb_div = (((pll & PLL_CONFIG_AHB_DIV_MASK) >> PLL_CONFIG_AHB_DIV_SHIFT) + 1) * 2;\r
-\r
- freq = pll_div * ref_div * 5000000;\r
-\r
- if(cpu_freq){\r
- *cpu_freq = freq;\r
- }\r
-\r
- if(ddr_freq){\r
- *ddr_freq = freq/ddr_div;\r
- }\r
-\r
- if(ahb_freq){\r
- *ahb_freq = freq/ahb_div;\r
- }\r
-#endif\r
-}\r
-\r
-int serial_init(void){\r
- u32 div, val;\r
-#ifdef CONFIG_WASP\r
- val = ar7240_reg_rd(WASP_BOOTSTRAP_REG);\r
-\r
- if((val & WASP_REF_CLK_25) == 0){\r
- div = DIV_ROUND_CLOSEST((25 * 1000000), (16 * CONFIG_BAUDRATE));\r
- } else {\r
- div = DIV_ROUND_CLOSEST((40 * 1000000), (16 * CONFIG_BAUDRATE));\r
- }\r
-#else\r
- u32 ahb_freq, ddr_freq, cpu_freq;\r
-\r
- ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);\r
-\r
- div = DIV_ROUND_CLOSEST(ahb_freq, (16 * CONFIG_BAUDRATE));\r
-\r
- MY_WRITE(0xb8040000, 0xcff);\r
- MY_WRITE(0xb8040008, 0x3b);\r
-\r
- val = ar7240_reg_rd(0xb8040028);\r
- MY_WRITE(0xb8040028,(val | 0x8002));\r
-\r
- MY_WRITE(0xb8040008, 0x2f);\r
-#endif\r
-\r
- /*\r
- * set DIAB bit\r
- */\r
- UART16550_WRITE(OFS_LINE_CONTROL, 0x80);\r
-\r
- /* set divisor */\r
- UART16550_WRITE(OFS_DIVISOR_LSB, (div & 0xff));\r
- UART16550_WRITE(OFS_DIVISOR_MSB, ((div >> 8) & 0xff));\r
-\r
- /* clear DIAB bit*/\r
- UART16550_WRITE(OFS_LINE_CONTROL, 0x00);\r
-\r
- /* set data format */\r
- UART16550_WRITE(OFS_DATA_FORMAT, 0x3);\r
-\r
- UART16550_WRITE(OFS_INTR_ENABLE, 0);\r
-\r
- return(0);\r
-}\r
-\r
-int serial_tstc(void){\r
- return(UART16550_READ(OFS_LINE_STATUS) & 0x1);\r
-}\r
-\r
-u8 serial_getc(void){\r
- while(!serial_tstc());\r
- return(UART16550_READ(OFS_RCV_BUFFER));\r
-}\r
-\r
-void serial_putc(u8 byte){\r
- if(byte == '\n'){\r
- serial_putc('\r');\r
- }\r
-\r
- while(((UART16550_READ(OFS_LINE_STATUS)) & 0x20) == 0x0);\r
-\r
- UART16550_WRITE(OFS_SEND_BUFFER, byte);\r
-}\r
-\r
-void serial_puts(const char *s){\r
- while(*s){\r
- serial_putc(*s++);\r
- }\r
-}\r
+++ /dev/null
-/*
- * Atheros AR933x clocks helper functions
- *
- * Copyright (C) 2014 Piotr Dymacz <piotr@dymacz.pl>
- * Copyright (C) 2014 Mantas Pucka <mantas@8devices.com>
- *
- * SPDX-License-Identifier:GPL-2.0
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/addrspace.h>
-#include <asm/ar933x.h>
-
-inline int ar933x_40MHz_xtal(void)
-{
- return (ar933x_reg_read(BOOTSTRAP_STATUS_REG) & BOOTSTRAP_SEL_25_40M_MASK);
-}
-
-/*
- * Get CPU, RAM and AHB clocks
- * Based on: Linux/arch/mips/ath79/clock.c
- */
-void ar933x_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq)
-{
- u32 ref_rate, clock_ctrl, cpu_config, pll, temp;
-
- if(ar933x_40MHz_xtal() == 1){
- ref_rate = 40000000;
- } else {
- ref_rate = 25000000;
- }
-
- /*
- * Read CPU CLock Control Register (CLOCK_CONTROL) value
- */
- clock_ctrl = ar933x_reg_read(CPU_CLOCK_CONTROL_REG);
-
- if(clock_ctrl & CPU_CLOCK_CONTROL_BYPASS_MASK){
- /* PLL is bypassed, so all clocks are == reference clock */
- *cpu_freq = ref_rate;
- *ddr_freq = ref_rate;
- *ahb_freq = ref_rate;
- } else {
- /* read CPU PLL Configuration register (CPU_PLL_CONFIG) value */
- cpu_config = ar933x_reg_read(CPU_PLL_CONFIG_REG);
-
- /* REFDIV */
- temp = (cpu_config & CPU_PLL_CONFIG_REFDIV_MASK)
- >> CPU_PLL_CONFIG_REFDIV_SHIFT;
- pll = ref_rate / temp;
-
- /* DIV_INT (multiplier) */
- temp = (cpu_config & CPU_PLL_CONFIG_DIV_INT_MASK)
- >> CPU_PLL_CONFIG_DIV_INT_SHIFT;
- pll *= temp;
-
- /* OUTDIV */
- temp = (cpu_config & CPU_PLL_CONFIG_OUTDIV_MASK)
- >> CPU_PLL_CONFIG_OUTDIV_SHIFT;
-
- /* Value 0 is not allowed */
- if(temp == 0){
- temp = 1;
- }
-
- pll >>= temp;
-
- /* CPU clock divider */
- temp = ((clock_ctrl & CPU_CLOCK_CONTROL_CPU_POST_DIV_MASK)
- >> CPU_CLOCK_CONTROL_CPU_POST_DIV_SHIFT) + 1;
- *cpu_freq = pll / temp;
-
- /* DDR clock divider */
- temp = ((clock_ctrl & CPU_CLOCK_CONTROL_DDR_POST_DIV_MASK)
- >> CPU_CLOCK_CONTROL_DDR_POST_DIV_SHIFT) + 1;
- *ddr_freq = pll / temp;
-
- /* AHB clock divider */
- temp = ((clock_ctrl & CPU_CLOCK_CONTROL_AHB_POST_DIV_MASK)
- >> CPU_CLOCK_CONTROL_AHB_POST_DIV_SHIFT) + 1;
- *ahb_freq = pll / temp;
- }
-}
--- /dev/null
+/*
+ * PLL and clocks configurations for
+ * Qualcomm/Atheros AR933x WiSoC
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2008-2010 Atheros Communications Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <soc/qca_pll_list.h>
+#include <config.h>
+#include <soc/qca_soc_common.h>
+#include <soc/ar933x_pll_init.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+
+#define reg_oc_recovery t0
+#define reg_spi_ctrl_cfg t1
+#define reg_ref_clk_val t2
+#define reg_cpu_pll_cfg t3
+#define reg_cpu_clk_ctrl t4
+#define reg_cpu_pll_dit t5
+#define reg_loop_counter t6
+
+/* Sanity check for O/C recovery button number */
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+ #if (CONFIG_QCA_GPIO_OC_RECOVERY_BTN >= QCA_GPIO_COUNT)
+ #error "O/C recovery button number is not correct!"
+ #endif
+
+ #define CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN \
+ (1 << CONFIG_QCA_GPIO_OC_RECOVERY_BTN)
+#endif
+
+.globl lowlevel_init
+.type lowlevel_init, @function
+.align 4
+.text
+.ent lowlevel_init
+
+lowlevel_init:
+
+/*
+ * Get reference clock (XTAL) type, based on BOOTSTRAP register
+ * and save its value in one register for later use
+ */
+ li reg_ref_clk_val, 25
+ li t8, QCA_RST_BOOTSTRAP_REG
+ lw t9, 0(t8)
+ li t8, QCA_RST_BOOTSTRAP_REF_CLK_MASK
+ and t9, t9, t8
+ bgtz t9, set_xtal_40mhz
+ nop
+
+ b wlan_rst_init
+ nop
+
+set_xtal_40mhz:
+ li reg_ref_clk_val, 40
+
+/*
+ * Several WLAN module resets as in Atheros (Q)SDK
+ */
+wlan_rst_init:
+ li t8, QCA_RST_RESET_REG
+
+ /* 2x WLAN resets */
+ lw t9, 0(t8)
+ or t9, t9, QCA_RST_RESET_WLAN_RST_MASK
+ sw t9, 0(t8)
+ nop
+ nop
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_RST_RESET_WLAN_RST_MASK
+ sw t9, 0(t8)
+ nop
+ nop
+
+ lw t9, 0(t8)
+ or t9, t9, QCA_RST_RESET_WLAN_RST_MASK
+ sw t9, 0(t8)
+ nop
+ nop
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_RST_RESET_WLAN_RST_MASK
+ sw t9, 0(t8)
+ nop
+ nop
+
+wlan_rst:
+ li t8, QCA_RST_RESET_REG
+
+ lw t9, 0(t8)
+ or t9, t9, QCA_RST_RESET_WLAN_RST_MASK
+ sw t9, 0(t8)
+ nop
+ nop
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_RST_RESET_WLAN_RST_MASK
+ sw t9, 0(t8)
+ nop
+ nop
+
+ li reg_loop_counter, 30
+
+eep_busy:
+ beq zero, reg_loop_counter, wlan_rst
+ nop
+ addi reg_loop_counter, reg_loop_counter, -1
+ li t8, QCA_RST_BOOTSTRAP_REG
+ lw t9, 0(t8)
+ and t9, t9, QCA_RST_BOOTSTRAP_EEPBUSY_MASK
+ bnez t9, eep_busy
+ nop
+
+/*
+ * From datasheet:
+ * For normal operation mode, SW should select
+ * the APB interface before register access
+ *
+ * Register: BOOTSTRAP, bit: 17 (JTAG=1, APB=0)
+ * Should be set by default, but it's not...
+ */
+sel_apb_for_mac:
+ li t8, QCA_RST_BOOTSTRAP_REG
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK
+ sw t9, 0(t8)
+
+/* AHB max master timeout */
+ahb_max_timeout:
+ li t8, QCA_AHB_MASTER_TOUT_MAX_REG
+ lw t9, 0(t8)
+ or t9, t9, 0xFFFFF
+ sw t9, 0(t8)
+
+/*
+ * Reset RTC
+ * TODO: do we need to reset RTC at all?
+ */
+rtc_reset:
+ li t8, QCA_RTC_SYNC_FORCE_WAKE_REG
+ li t9, (QCA_RTC_SYNC_FORCE_WAKE_EN_MASK |\
+ QCA_RTC_SYNC_FORCE_WAKE_MACINTR_MASK)
+ sw t9, 0(t8)
+ nop
+ nop
+
+ li t8, QCA_RTC_SYNC_RST_REG
+ li t9, 0x0
+ sw t9, 0(t8)
+ nop
+ nop
+
+ li t9, QCA_RTC_SYNC_RST_RESET_MASK
+ sw t9, 0(t8)
+ nop
+
+ li t8, QCA_RTC_SYNC_STATUS_REG
+
+rtc_wait_on:
+ lw t9, 0(t8)
+ and t9, t9, QCA_RTC_SYNC_STATUS_ON_MASK
+ beqz t9, rtc_wait_on
+ nop
+
+/*
+ * O/C recovery mode (start with safe PLL/clocks configuration):
+ * 1. Check if defined recovery button is pressed
+ * 2. Indicate recovery mode in predefined register
+ * 3. If in recovery mode, do not use PLL configuration from FLASH,
+ * because it is probably the reason why user is using recovery mode
+ */
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+is_oc_recovery_btn_pressed:
+ li reg_oc_recovery, 0
+ li t8, QCA_GPIO_IN_REG
+ lw t9, 0(t8)
+ and t9, t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN
+
+ #ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW
+ bne t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN, in_oc_recovery_mode
+ nop
+ #else
+ beq t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN, in_oc_recovery_mode
+ nop
+ #endif
+
+ #ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET
+ b is_pll_cfg_in_flash
+ #else
+ b xtal_type_check
+ #endif
+ nop
+
+in_oc_recovery_mode:
+ li reg_oc_recovery, 1
+ b xtal_type_check
+ nop
+#endif /* CONFIG_QCA_GPIO_OC_RECOVERY_BTN */
+
+/*
+ * Check if PLL configuration is stored in FLASH:
+ * 1. Get 32-bit value from defined offset in FLASH
+ * 2. Compare it with predefined magic value
+ * 3. If values are not equal, continue default PLL/clocks configuration
+ * 4. If values are equal it means we should have target PLL/clocks register
+ * values stored in FLASH, just after magic value, in the following order:
+ * - SPI_CONTROL (offset 4)
+ * - CPU_PLL_CONFIG (offset 8)
+ * - CPU_CLOCK_CONTROL (offset 12)
+ * - CPU_PLL_DITHER_FRAC (offset 16)
+ * 5. After loading target values from FLASH,
+ * jump directly to PLL/clocks configuration
+ */
+#ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET
+is_pll_cfg_in_flash:
+ li t8, CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET
+ lw t9, 0(t8)
+ bne t9, QCA_PLL_IN_FLASH_MAGIC, xtal_type_check
+ nop
+
+pll_cfg_in_flash:
+ lw reg_spi_ctrl_cfg, 4(t8)
+ lw reg_cpu_pll_cfg, 8(t8)
+ lw reg_cpu_clk_ctrl, 12(t8)
+ lw reg_cpu_pll_dit, 16(t8)
+ b cpu_clock_control
+ nop
+#endif /* CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET */
+
+/*
+ * Check XTAL type, configure PLL settle time and include dedicated
+ * PLL/clocks values, predefined in header file, based on selected
+ * preset configuration
+ */
+xtal_type_check:
+ beq reg_ref_clk_val, 40, xtal_is_40mhz
+ nop
+
+xtal_is_25mhz:
+ li t8, QCA_PLL_CPU_PLL_CFG2_REG
+ li t9, QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL25
+ sw t9, 0(t8)
+
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+ beq reg_oc_recovery, 1, xtal_is_25mhz_recovery
+ nop
+#endif
+
+ li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL
+ li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25
+ li reg_cpu_clk_ctrl, QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25
+ li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25
+ b cpu_clock_control
+ nop
+
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+xtal_is_25mhz_recovery:
+ li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL_SAFE
+ li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25
+ li reg_cpu_clk_ctrl, QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL25
+ li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL25
+ b cpu_clock_control
+ nop
+#endif
+
+xtal_is_40mhz:
+ li t8, QCA_PLL_CPU_PLL_CFG2_REG
+ li t9, QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL40
+ sw t9, 0(t8)
+
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+ beq reg_oc_recovery, 1, xtal_is_40mhz_recovery
+ nop
+#endif
+
+ li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL
+ li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40
+ li reg_cpu_clk_ctrl, QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40
+ li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40
+
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+ b cpu_clock_control
+ nop
+
+xtal_is_40mhz_recovery:
+ li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL_SAFE
+ li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40
+ li reg_cpu_clk_ctrl, QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL40
+ li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL40
+#endif
+
+/*
+ * Load target value into CPU_CLOCK_CONTROL register, but for now keep bypass
+ * enabled (by default, after reset, it should be bypassed, do it just in case)
+ */
+cpu_clock_control:
+ li t8, QCA_PLL_CPU_CLK_CTRL_REG
+ move t9, reg_cpu_clk_ctrl
+ or t9, t9, QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK
+ sw t9, 0(t8)
+
+/*
+ * Load target value into CPU_PLL_CONFIG register, but for now keep PLL down
+ * (by default, after reset, it should be powered down, do it just in case)
+ */
+cpu_pll_config:
+ li t8, QCA_PLL_CPU_PLL_CFG_REG
+ move t9, reg_cpu_pll_cfg
+ or t9, t9, QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK
+ sw t9, 0(t8)
+
+/* Load target NFRAC_MIN value into PLL_DITHER_FRAC register */
+cpu_pll_dither:
+ li t8, QCA_PLL_CPU_PLL_DITHER_FRAC_REG
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK
+ or t9, t9, reg_cpu_pll_dit
+ sw t9, 0(t8)
+
+/* Enable CPU PLL and wait for update complete */
+cpu_pll_enable:
+ li t8, QCA_PLL_CPU_PLL_CFG_REG
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK
+ sw t9, 0(t8)
+ nop
+
+/* Wait for CPU PLL update complete */
+cpu_pll_wait:
+ lw t9, 0(t8)
+ and t9, t9, QCA_PLL_CPU_PLL_CFG_UPDATING_MASK
+ bgtz t9, cpu_pll_wait
+ nop
+
+/* Disable bypassing all clocks, use target AHB_POST_DIV value */
+pll_bypass_disable:
+ li t8, QCA_PLL_CPU_CLK_CTRL_REG
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK
+ sw t9, 0(t8)
+
+/* Setup SPI (clock and other settings) */
+spi_setup:
+ li t8, QCA_SPI_CTRL_REG
+ sw reg_spi_ctrl_cfg, 0(t8)
+ and reg_spi_ctrl_cfg, reg_spi_ctrl_cfg, QCA_SPI_CTRL_REMAP_DIS_MASK
+ beqz reg_spi_ctrl_cfg, end
+ nop
+
+/*
+ * This is a small hack, needed after setting REMAP_DISABLE bit
+ * in SPI_CONTROL_ADDR register.
+ *
+ * Before that, SPI FLASH is mapped to 0x1FC00000, but just after
+ * setting REMAP_DISABLE bit, aliasing is disabled and SPI FLASH
+ * is mapped to 0x1F00000, so that the whole 16 MB address space
+ * could be used.
+ *
+ * That means, we need to "fix" return address, stored previously
+ * in $ra register, subtracting a value 0x00C00000 from it.
+ *
+ * Without that, jump would end up somewhere far away on FLASH...
+ */
+ li t8, 0x00C00000
+ subu ra, ra, t8
+
+end:
+ jr ra
+ nop
+
+.end lowlevel_init
+++ /dev/null
-/*
- * Atheros AR933x UART driver
- *
- * Copyright (C) 2014 Piotr Dymacz <piotr@dymacz.pl>
- * Copyright (C) 2008-2010 Atheros Communications Inc.
- *
- * Values for UART_SCALE and UART_STEP:
- * https://www.mail-archive.com/openwrt-devel@lists.openwrt.org/msg22371.html
- *
- * SPDX-License-Identifier:GPL-2.0
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/addrspace.h>
-#include <asm/ar933x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void ar933x_serial_get_scale_step(u32 *uart_scale, u32 *uart_step)
-{
- if(ar933x_40MHz_xtal() == 1){
- switch(gd->baudrate){
- case 600:
- *uart_scale = 255;
- *uart_step = 503;
- break;
- case 1200:
- *uart_scale = 249;
- *uart_step = 983;
- break;
- case 2400:
- *uart_scale = 167;
- *uart_step = 1321;
- break;
- case 4800:
- *uart_scale = 87;
- *uart_step = 1384;
- break;
- case 9600:
- *uart_scale = 45;
- *uart_step = 1447;
- break;
- case 14400:
- *uart_scale = 53;
- *uart_step = 2548;
- break;
- case 19200:
- *uart_scale = 22;
- *uart_step = 1447;
- break;
- case 28800:
- *uart_scale = 26;
- *uart_step = 2548;
- break;
- case 38400:
- *uart_scale = 28;
- *uart_step = 3649;
- break;
- case 56000:
- *uart_scale = 7;
- *uart_step = 1468;
- break;
- case 57600:
- *uart_scale = 34;
- *uart_step = 6606;
- break;
- case 115200:
- *uart_scale = 28;
- *uart_step = 10947;
- break;
- case 128000:
- *uart_scale = 6;
- *uart_step = 2936;
- break;
- case 153600:
- *uart_scale = 18;
- *uart_step = 9563;
- break;
- case 230400:
- *uart_scale = 16;
- *uart_step = 12834;
- break;
- case 250000:
- *uart_scale = 4;
- *uart_step = 4096;
- break;
- case 256000:
- *uart_scale = 6;
- *uart_step = 5872;
- break;
- case 460800:
- *uart_scale = 7;
- *uart_step = 12079;
- break;
- case 576000:
- *uart_scale = 4;
- *uart_step = 9437;
- break;
- case 921600:
- *uart_scale = 3;
- *uart_step = 12079;
- break;
- case 1000000:
- *uart_scale = 2;
- *uart_step = 9830;
- break;
- case 1152000:
- *uart_scale = 2;
- *uart_step = 11324;
- break;
- case 1500000:
- *uart_scale = 0;
- *uart_step = 4915;
- break;
- case 2000000:
- *uart_scale = 0;
- *uart_step = 6553;
- break;
- default:
- *uart_scale = (40000000 / (16 * gd->baudrate)) - 1;
- *uart_step = 8192;
- }
- } else {
- switch(gd->baudrate){
- case 600:
- *uart_scale = 255;
- *uart_step = 805;
- break;
- case 1200:
- *uart_scale = 209;
- *uart_step = 1321;
- break;
- case 2400:
- *uart_scale = 104;
- *uart_step = 1321;
- break;
- case 4800:
- *uart_scale = 54;
- *uart_step = 1384;
- break;
- case 9600:
- *uart_scale = 78;
- *uart_step = 3976;
- break;
- case 14400:
- *uart_scale = 98;
- *uart_step = 7474;
- break;
- case 19200:
- *uart_scale = 55;
- *uart_step = 5637;
- break;
- case 28800:
- *uart_scale = 77;
- *uart_step = 11777;
- break;
- case 38400:
- *uart_scale = 36;
- *uart_step = 7449;
- break;
- case 56000:
- *uart_scale = 4;
- *uart_step = 1468;
- break;
- case 57600:
- *uart_scale = 35;
- *uart_step = 10871;
- break;
- case 115200:
- *uart_scale = 20;
- *uart_step = 12683;
- break;
- case 128000:
- *uart_scale = 11;
- *uart_step = 8053;
- break;
- case 153600:
- *uart_scale = 9;
- *uart_step = 8053;
- break;
- case 230400:
- *uart_scale = 9;
- *uart_step = 12079;
- break;
- case 250000:
- *uart_scale = 6;
- *uart_step = 9175;
- break;
- case 256000:
- *uart_scale = 5;
- *uart_step = 8053;
- break;
- case 460800:
- *uart_scale = 4;
- *uart_step = 12079;
- break;
- case 576000:
- *uart_scale = 3;
- *uart_step = 12079;
- break;
- case 921600:
- *uart_scale = 1;
- *uart_step = 9663;
- break;
- case 1000000:
- *uart_scale = 1;
- *uart_step = 10485;
- break;
- case 1152000:
- *uart_scale = 1;
- *uart_step = 12079;
- break;
- case 1500000:
- *uart_scale = 0;
- *uart_step = 7864;
- break;
- case 2000000:
- *uart_scale = 0;
- *uart_step = 10485;
- break;
- default:
- *uart_scale = (25000000 / (16 * gd->baudrate)) - 1;
- *uart_step = 8192;
- }
- }
-}
-
-void serial_setbrg(void)
-{
- /* TODO: better clock calculation, baudrate, etc. */
- u32 uart_clock;
- u32 uart_scale;
- u32 uart_step;
-
- ar933x_serial_get_scale_step(&uart_scale, &uart_step);
-
- uart_clock = (uart_scale << UART_CLOCK_SCALE_SHIFT);
- uart_clock |= (uart_step << UART_CLOCK_STEP_SHIFT);
-
- ar933x_reg_write(UART_CLOCK_REG, uart_clock);
-}
-
-int serial_init(void)
-{
- u32 uart_cs;
-
- /*
- * Set GPIO10 (UART_SO) as output and enable UART,
- * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
- */
- ar933x_reg_read_set(GPIO_OE_REG, GPIO10);
-
- ar933x_reg_read_set(GPIO_FUNCTION_1_REG,
- (1 << GPIO_FUNCTION_1_UART_EN_SHIFT) |
- (1 << 15));
-
- /*
- * UART controller configuration:
- * - no DMA
- * - no interrupt
- * - DCE mode
- * - no flow control
- * - set RX ready oride
- * - set TX ready oride
- */
- uart_cs = (0 << UART_CS_DMA_EN_SHIFT) |
- (0 << UART_CS_HOST_INT_EN_SHIFT) |
- (1 << UART_CS_RX_READY_ORIDE_SHIFT) |
- (1 << UART_CS_TX_READY_ORIDE_SHIFT) |
- (UART_CS_IFACE_MODE_DCE_VAL << UART_CS_IFACE_MODE_SHIFT) |
- (UART_CS_FLOW_MODE_NO_VAL << UART_CS_FLOW_MODE_SHIFT);
-
- ar933x_reg_write(UART_CS_REG, uart_cs);
-
- serial_setbrg();
-
- return 0;
-}
-
-void serial_putc(const char c)
-{
- u32 uart_data;
-
- if(c == '\n')
- serial_putc('\r');
-
- /* Wait for FIFO */
- do{
- uart_data = ar933x_reg_read(UART_DATA_REG);
- } while(((uart_data & UART_TX_CSR_MASK) >> UART_TX_CSR_SHIFT) == 0);
-
- /* Put data in buffer and set CSR bit */
- uart_data = (u32)c | (1 << UART_TX_CSR_SHIFT);
-
- ar933x_reg_write(UART_DATA_REG, uart_data);
-}
-
-int serial_getc(void)
-{
- u32 uart_data;
-
- while(!serial_tstc())
- ;
-
- uart_data = ar933x_reg_read(UART_DATA_REG);
-
- ar933x_reg_write(UART_DATA_REG, (1 << UART_RX_CSR_SHIFT));
-
- return (uart_data & UART_TX_RX_DATA_MASK);
-}
-
-int serial_tstc(void)
-{
- u32 uart_data = ar933x_reg_read(UART_DATA_REG);
-
- if((uart_data & UART_RX_CSR_MASK) >> UART_RX_CSR_SHIFT){
- return 1;
- }
-
- return 0;
-}
-
-void serial_puts(const char *s)
-{
- while(*s){
- serial_putc(*s++);
- }
-}
+++ /dev/null
-/*
- * Startup Code for MIPS32 CPU-core
- *
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <ar7240_soc.h>
-
- .globl hornet_ddr_init
- .text
- .align 4
-
-#define set_mem(_mem, _val) \
- li t9, _mem; \
- sw _val, 0(t9);
-
-//============================================
-// init DDR1 parameter before rel_start
-//===========================================
-hornet_ddr_init:
- // 0x18000000 (DDR_CONFIG, p. 54)
- // CFG_DDR_CONFIG_VAL = 0x7fbc8cd0 (ap121.h)
- li t8, CFG_DDR_CONFIG_VAL;
- set_mem(0xB8000000, t8);
-
- // 0x18000004 (DDR_CONFIG2, p. 55)
- // CFG_DDR_CONFIG2_VAL = 0x99d0e6a8 (ap121.h)
- li t8, CFG_DDR_CONFIG2_VAL;
- set_mem(0xB8000004, t8);
-
-/*
- * WR720N v3 (CH version) has wrong bootstrap configuration,
- * so the memory type cannot be recognized automatically
- */
-#if !defined(CONFIG_FOR_TPLINK_WR720N_V3)
-mem_type:
- // TODO: what about SDRAM?
- // 0x180600AC (BOOT_STRAP, p. 81)
- li t8, 0xB80600AC // load BOOT_STRAP reg address
- lw t9, 0(t8) // and its value
- li t8, 0x2000 // 0x2000 -> BIT13 is set
- and t9, t9, t8
- beq t9, zero, ddr1_config // jump if we have DDR1
-
-ddr2_config:
- // Enable DDR2
- // 0x1800008C (DDR_DDR2_CONFIG, p. 58)
- li t8, 0xA59;
- set_mem(0xB800008C, t8);
-
- // Precharge All
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x8;
- set_mem(0xB8000010, t8);
-
- // Disable High Temperature Self-Refresh Rate
- // 0x18000090 (DDR_EMR2, p. 58)
- li t8, 0x0;
- set_mem(0xB8000090, t8);
-
- // Extended Mode Register 2 Set (EMR2S)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x10;
- set_mem(0xB8000010, t8);
-
- // 0x18000094 (DDR_EMR3, p. 58)
- li t8, 0x0;
- set_mem(0xB8000094, t8);
-
- // Extended Mode Register 3 Set (EMR3S)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x20;
- set_mem(0xB8000010, t8);
-
- // Enable DLL
- // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
- li t8, 0x0;
- set_mem(0xB800000C, t8);
-
- // Extended Mode Register Set (EMRS)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x2;
- set_mem(0xB8000010, t8);
-
- // Reset DLL
- // 0x18000008 (DDR_MODE_REGISTER, p. 55)
- li t8, 0x100;
- set_mem(0xB8000008, t8);
-
- // Mode Register Set (MRS)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x1;
- set_mem(0xB8000010, t8);
-
- // Precharge All
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x8;
- set_mem(0xB8000010, t8);
-
- // Auto Refresh
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x4;
- set_mem(0xB8000010, t8);
-
- // Auto Refresh
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x4;
- set_mem(0xB8000010, t8);
-
- // Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8
- // 0x18000008 (DDR_MODE_REGISTER, p. 55)
- li t8, 0xa33;
- set_mem(0xB8000008, t8);
-
- // Mode Register Set (MRS)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x1;
- set_mem(0xB8000010, t8);
-
- // E7,E8,E9 equal to 1(Enable OCD defaults), Enable DLL, Reduced Drive Strength
- // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
- li t8, 0x382;
- set_mem(0xB800000C, t8);
-
- // Extended Mode Register Set (EMRS)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x2;
- set_mem(0xB8000010, t8);
-
- // E7,E8,E9 equal to 0(OCD exit), Enable DLL, Reduced Drive Strength
- // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
- li t8, 0x402;
- set_mem(0xB800000C, t8);
-
- // Extended Mode Register Set (EMRS)
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x2;
- set_mem(0xB8000010, t8);
-
- // Refresh control. Bit 14 is enable. Bits<13:0> Refresh time
- // 0x18000014 (DDR_REFRESH, p. 56)
- li t8, CFG_DDR_REFRESH_VAL;
- set_mem(0xB8000014, t8);
-
- // DQS 0 Tap Control (needs tuning)
- // 0x1800001C (TAP_CONTROL_0, p. 56)
- li t8, CFG_DDR_TAP0_VAL;
- set_mem(0xB800001C, t8);
-
- // DQS 1 Tap Control (needs tuning)
- // 0x18000020 (TAP_CONTROL_1, p. 57)
- li t8, CFG_DDR_TAP1_VAL;
- set_mem(0xB8000020, t8);
-
- // For 16-bit DDR
- // 0x18000018 (DDR_RD_DATA_THIS_CYCLE, p. 56)
- li t8, 0x00ff;
- set_mem(0xB8000018, t8);
-
- nop
- jr ra
-#endif /* !defined(CONFIG_FOR_TPLINK_WR720N_V3) */
-
-ddr1_config:
- // Precharge All
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x8;
- set_mem(0xB8000010, t8);
-
- // 0x18000008 (DDR_MODE_REGISTER, p. 55)
- li t8, CFG_DDR_MODE_VAL_INIT;
- set_mem(0xB8000008, t8);
-
- // Write Mode Word in DDR
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x1;
- set_mem(0xB8000010, t8);
-
- // Enable DLL, High drive strength from DDR
- // 0x1800000C (DDR_EXTENDED_MODE_REGISTER, p. 55)
- li t8, 0x2;
- set_mem(0xB800000C, t8);
-
- // Write Extended Mode Word of DDR
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x2;
- set_mem(0xB8000010, t8);
-
- // Precharge All
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x8;
- set_mem(0xB8000010, t8);
-
- // DLL out of reset, CAS Latency 3
- // 0x18000008 (DDR_MODE_REGISTER, p. 55)
- li t8, CFG_DDR_MODE_VAL;
- set_mem(0xB8000008, t8);
-
- // Write mode word
- // 0x18000010 (DDR_CONTROL, p. 56)
- li t8, 0x1;
- set_mem(0xB8000010, t8);
-
- // Refresh control. Bit 14 is enable. Bits<13:0> Refresh time
- // 0x18000014 (DDR_REFRESH, p. 56)
- li t8, CFG_DDR_REFRESH_VAL;
- set_mem(0xB8000014, t8);
-
- // DQS 0 Tap Control (needs tuning)
- // 0x1800001C (TAP_CONTROL_0, p. 56)
- li t8, CFG_DDR_TAP0_VAL;
- set_mem(0xB800001C, t8);
-
- // DQS 1 Tap Control (needs tuning)
- // 0x18000020 (TAP_CONTROL_1, p. 57)
- li t8, CFG_DDR_TAP1_VAL;
- set_mem(0xB8000020, t8);
-
- // For 16-bit DDR
- // 0x18000018 (DDR_RD_DATA_THIS_CYCLE, p. 56)
- li t8, 0x00ff;
- set_mem(0xB8000018, t8);
-
- nop
- jr ra
-
-/*
- * void hornet_ddr_tap_init(void)
- *
- * This "function" is used to find the tap settings for the DDR
- */
- .globl hornet_ddr_tap_init
- .ent hornet_ddr_tap_init
-hornet_ddr_tap_init: /* { */
-
- li t1,0x80500000
- li t0,0xffffffff
-
- sw t0,0x0(t1)
- sw t0,0x4(t1)
- sw t0,0x8(t1)
- sw t0,0xc(t1)
-
- nop
- nop
-
-ddr_pat_init:
- li t8, 0xa0002000
- li t0, 0x00
- li t1, 0x100
-
-write_loop_start:
- andi t2, t0, 0x03
-
-pat_000:
- li t3, 0x00
- bne t2, t3,pat_001
- li t9, 0x00000000
- sw t9, 0x0 (t8)
- b pat_004
-
-pat_001:
- li t3, 0x01
- bne t2, t3,pat_002
- li t9, 0x0000ffff
- sw t9, 0x0 (t8)
- b pat_004
-
-pat_002:
- li t3, 0x02
- bne t2, t3,pat_003
- li t9, 0xffff0000
- sw t9, 0x0 (t8)
- b pat_004
-
-pat_003:
- li t3, 0x03
- bne t2, t3,pat_004
- li t9, 0xffffffff
- sw t9, 0x0 (t8)
-
-pat_004:
- andi t2, t0, 0x0c
- li t3, 0x00
- bne t2, t3,pat_005
- li t9, 0x00000000
- sw t9, 0x4 (t8)
- b pat_008
-
-pat_005:
- li t3, 0x04
- bne t2, t3,pat_006
- li t9, 0x0000ffff
- sw t9, 0x4 (t8)
- b pat_008
-
-pat_006:
- li t3, 0x08
- bne t2, t3,pat_007
- li t9, 0xffff0000
- sw t9, 0x4 (t8)
- b pat_008
-
-pat_007:
- li t3, 0x0c
- bne t2, t3,pat_008
- li t9, 0xffffffff
- sw t9, 0x4 (t8)
-
-pat_008:
- andi t2, t0, 0x30
- li t3, 0x00
- bne t2, t3,pat_009
- li t9, 0x00000000
- sw t9, 0x8 (t8)
- b pat_00c
-
-pat_009:
- li t3, 0x10
- bne t2, t3,pat_00a
- li t9, 0x0000ffff
- sw t9, 0x8 (t8)
- b pat_00c
-
-pat_00a:
- li t3, 0x20
- bne t2, t3,pat_00b
- li t9, 0xffff0000
- sw t9, 0x8 (t8)
- b pat_00c
-
-pat_00b:
- li t3, 0x30
- bne t2, t3,pat_00c
- li t9, 0xffffffff
- sw t9, 0x8 (t8)
-
-pat_00c:
- andi t2, t0, 0xc0
- li t3, 0x00
- bne t2, t3,pat_00d
- li t9, 0x00000000
- sw t9, 0xc (t8)
- b pat_done
-
-pat_00d:
- li t3, 0x40
- bne t2, t3,pat_00e
- li t9, 0x0000ffff
- sw t9, 0xc (t8)
- b pat_done
-
-pat_00e:
- li t3, 0x80
- bne t2, t3,pat_00f
- li t9, 0xffff0000
- sw t9, 0xc (t8)
- b pat_done
-
-pat_00f:
- li t3, 0xc0
- bne t2, t3,pat_done
- li t9, 0xffffffff
- sw t9, 0xc (t8)
-
-pat_done:
- addiu t0, t0, 0x1
- addiu t8, t8, 0x10
- bne t0, t1, write_loop_start
-
-###### ddr init over #########
-
- li a0, 0xa0002000
- li a1, 0x80002000 ### Start address of the pattern 200
- li a2, 0x80003000 ### End Address of the pattern 220
- li t0, 0xb800001c ## Tap settings addr
- lw a3, 0x0(t0) ## loading default tap value
- nop
- ori t0, a3, 0x0
- nop
- li t1, 0x1 ## $t1=1 indicates increasing tap value, 0 = decreasing
-
-load_tap:
- li t7, 0x2
- #li t7, 0x200 ## No. of times read has to happen for 1 tap setting
- li t8, 0xb8000000 #### Loading Tap Setting
- sw t0, 0x1c(t8)
- nop
- sw t0, 0x20(t8)
- nop
- #if 0 /* Hornet doesn't have DQS2, DQS3*/
- sw t0, 0x24(t8)
- nop
- sw t0, 0x28(t8)
- nop
- #endif
-
-###### t0 stores current tap setting under test
-###### t1 indicates increment or decrement of tap
-
-pat_read:
- ori t2, a0, 0x0
- nop
- ori t3, a1, 0x0
- nop
- ori t4, a2, 0x0
- nop
-
-tap_addr_loop:
- lw t5, 0x0(t2)
- nop
- lw t6, 0x0(t3)
- nop
- nop
-
- bne t5, t6, tap_fail # jump to fail if not equal
- nop
- nop
- nop
-
- addiu t2, t2, 0x4 #incrementing addr
- addiu t3, t3, 0x4
- nop
- nop
-
- bne t3, t4, tap_addr_loop # compare new addr if end addr not reached
- nop
-
- addiu t7, t7, -1 # read passed for all locations once hence decrement t7
- nop
- bnez t7, pat_read # t7 = 0 represents passing of all locations for given tap
- nop
- nop
-
- bnez t1, tap_incr # increment tap if t1 = 1
- nop
- nop
-
- bnez t0, tap_decr ## $t0=0 implies tap=0 works
- nop ## so low limit=0, else decrement tap value
- nop
- li t8, 0x80500000 ## assigning lower limit = 0
- sw t0, 0x0(t8)
- add t9, t9, t0 ##adding lower limit to upper limit (used to calc mid value)
- nop
- nop
-
- b tap_calc
- nop
- nop
-
-tap_decr: # decrement t0 by 1 and move to loading this new tap
- addiu t0, t0 , -1
- nop
- b load_tap
- nop
- nop
-
-tap_incr:
- addiu t0, t0 , 0x1
- nop
- xori v1, t0, 0x20 # limiting upper limit to 0x20
- nop
- bnez v1, load_tap
- nop
- nop
- b up_limit
- nop
- nop
-
-tap_fail:
- bnez t1, up_limit # t1=0 means lower limit detected @ fail else upper limit
- nop
- nop
- nop
- addiu t0, t0, 0x1
- nop
- li t8, 0x80500000 # storing lower limit
- nop
- sw t0, 0x0(t8)
- add t9, t9, t0 # storing lower limit# adding lower limit and upper limit
- nop
- nop
- nop
-
- b tap_calc
- nop
- nop
-
-up_limit:
- addiu t0, t0, -1
- li t1, 0x0 ## changing to decreasing tap mode
- li t8, 0x80500000 ## storing upper limit
- sw t0, 0x4(t8)
- ori t9, t0, 0x0
- nop
- nop
- nop
-
- ori t0, a3, 0x0 # loading default tap value
- nop
- b load_tap
- nop
- nop
-
-tap_calc: ## calculating mid value of the tap, storing DQS0, DQS1 in 0x80500008, 0x8050000c resp.
- li t7, 0x2
- nop
- div t9, t7
- nop
- mfhi t6
- mflo t5
- nop
- nop
- add t6, t6, t5
- li t8, 0x80500000
- nop
- sw t5, 0x8(t8)
- nop
- sw t6, 0xc(t8)
- nop
- nop
- li t8, 0xb8000000 #### Loading Tap Setting
- nop
- sw t5, 0x1c(t8)
- nop
- sw t6, 0x20(t8)
- nop
- nop
- nop
-
-end:
- nop
- nop
- nop
- jr ra
-
- .end hornet_ddr_tap_init
-/* } */
+++ /dev/null
-/*
- * Memory controller config:
- * Assumes that the caches are initialized.
- *
- * 0) Figah out the Tap controller settings.
- * 1) Figure out whether the interface is 16bit or 32bit.
- * 2) Size the DRAM
- *
- * 0) Tap controller settings
- * --------------------------
- * The Table below provides all possible values of TAP controllers. We need to
- * find the extreme left and extreme right of the spectrum (of max_udelay and
- * min_udelay). We then program the TAP to be in the middle.
- * Note for this we would need to be able to read and write memory. So,
- * initially we assume that a 16bit interface, which will always work unless
- * there is exactly _1_ 32 bit part...for now we assume this is not the case.
- *
- * The algo:
- * 0) Program the controller in 16bit mode.
- * 1) Start with the extreme left of the table
- * 2) Write 0xa4, 0xb5, 0xc6, 0xd7 to 0, 2, 4, 6
- * 3) Read 0 - this will fetch the entire cacheline.
- * 4) If the value at address 4 is good, record this table entry, goto 6
- * 5) Increment to get the next table entry. Goto 2.
- * 6) Start with extreme right. Do the same as above.
- *
- * 1) 16bit or 32bit
- * -----------------
- * 31st bit of reg 0x1800_0000 will determine the mode. By default,
- * controller is set to 32-bit mode. In 32 bit mode, full data bus DQ [31:0]
- * will be used to write 32 bit data. Suppose you have 16bit DDR memory
- * (it will have 16bit wide data bus). If you try to write 16 bit DDR in 32
- * bit mode, you are going to miss upper 16 bits of data. Reading to that
- * location will give you only lower 16 bits correctly, upper 16 bits will
- * have some junk value. E.g.,
- *
- * write to 0x0000_0000 0x12345678
- * write to 0x0000_1000 0x00000000 (just to discharge DQ[31:16] )
- * read from 0x0000_0000
- * if u see something like 0x0000_5678 (or XXXX_5678 but not equal to
- * 0x12345678) - its a 16 bit interface
- *
- * 2) Size the DRAM
- * -------------------
- * DDR wraps around. Write a pattern to 0x0000_0000. Write an address
- * pattern at 4M, 8M, 16M etc. and check when 0x0000_0000 gets overwritten.
- *
- *
- * We can use #define's for all these addresses and patterns but its easier
- * to see what's going on without :)
- */
-#include <common.h>
-#include <asm/addrspace.h>
-#include "ar7240_soc.h"
-
-// We check for size in 16M increments
-#define AR7240_DDR_SIZE_INCR (16*1024*1024)
-int ar7240_ddr_find_size(void){
- uint8_t *p = (uint8_t *)KSEG1, pat = 0x77;
- int i;
-
- *p = pat;
-
- for(i = 1;; i++){
- *(p + i * AR7240_DDR_SIZE_INCR) = (uint8_t)(i);
-
- if(*p != pat){
- break;
- }
- }
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- return(i * AR7240_DDR_SIZE_INCR);
-#else
- // TODO: something is wrong with relocation,
- // need to fix it for boards with > 32M of RAM
- return((i * AR7240_DDR_SIZE_INCR) - 1024*1024);
-#endif
-}
-
-#if defined(CONFIG_WASP)
-int wasp_ddr_initial_config(uint32_t refresh){
- int ddr_config, ddr_config2, ext_mod, mod_val, mod_val_init, cycle_val, tap_val, type;
-
- switch(WASP_RAM_TYPE(ar7240_reg_rd(WASP_BOOTSTRAP_REG))){
- case 0:
- case 1: // SDRAM
-
- // XXX XXX XXX XXX XXX XXX XXX XXX XXX
- // Boot strap select is not working. In some boards,
- // ddr2 shows up as sdram. Hence ignoring the foll.
- // break statement.
- // XXX XXX XXX XXX XXX XXX XXX XXX XXX
- // break;
-
- ddr_config = CFG_934X_SDRAM_CONFIG_VAL;
- ddr_config2 = CFG_934X_SDRAM_CONFIG2_VAL;
- mod_val_init = CFG_934X_SDRAM_MODE_VAL_INIT;
- mod_val = CFG_934X_SDRAM_MODE_VAL;
- cycle_val = CFG_SDRAM_RD_DATA_THIS_CYCLE_VAL;
- tap_val = CFG_934X_SDRAM_TAP_VAL;
-
- ar7240_reg_wr_nf(AR7240_DDR_CTL_CONFIG, 0x13b);
- udelay(100);
-
- ar7240_reg_wr_nf(AR7240_DDR_DEBUG_RD_CNTL, 0x3000001f);
- udelay(100);
-
- type = 0;
-
- break;
-
- case 2: // ddr2
-
- ddr_config = CFG_934X_DDR2_CONFIG_VAL;
- ddr_config2 = CFG_934X_DDR2_CONFIG2_VAL;
- ext_mod = CFG_934X_DDR2_EXT_MODE_VAL;
- mod_val_init = CFG_934X_DDR2_MODE_VAL_INIT;
- mod_val = CFG_934X_DDR2_MODE_VAL;
- cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL;
- tap_val = CFG_934X_DDR2_TAP_VAL;
-
- ar7240_reg_wr_nf(AR7240_DDR_DDR2_CONFIG, CFG_934X_DDR2_EN_TWL_VAL);
- udelay(100);
-
- ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x10);
- udelay(10);
-
- ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x20);
- udelay(10);
-
- if(ar7240_reg_rd(AR7240_REV_ID) & 0xf){
- // NAND Clear
- if(ar7240_reg_rd(WASP_BOOTSTRAP_REG) & (1 << 3)){
- ar7240_reg_wr_nf(AR7240_DDR_CTL_CONFIG, (1 << 6));
- cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32;
- } else {
- ar7240_reg_rmw_set(AR7240_DDR_CTL_CONFIG, (1 << 6));
- cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16;
- }
- } else {
-#if DDR2_32BIT_SUPPORT
- ar7240_reg_wr_nf(AR7240_DDR_CTL_CONFIG, 0);
-#endif
- }
- udelay(10);
-
- type = 1;
-
- break;
-
- case 3: // ddr1
-
- ddr_config = CFG_934X_DDR1_CONFIG_VAL;
- ddr_config2 = CFG_934X_DDR1_CONFIG2_VAL;
- ext_mod = CFG_934X_DDR1_EXT_MODE_VAL;
- mod_val_init = CFG_934X_DDR1_MODE_VAL_INIT;
- mod_val = CFG_934X_DDR1_MODE_VAL;
- cycle_val = CFG_DDR1_RD_DATA_THIS_CYCLE_VAL;
- tap_val = CFG_934X_DDR1_TAP_VAL;
-
- type = 2;
-
- break;
- }
-
- ar7240_reg_wr_nf(AR7240_DDR_CONFIG, ddr_config);
- udelay(100);
-
- ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, ddr_config2 | 0x80);
- udelay(100);
-
- ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
- udelay(10);
-
- ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val_init);
- udelay(1000);
-
- ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1);
- udelay(10);
-
- if(type == 1){
- //ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, CFG_934X_DDR2_EXT_MODE_VAL_INIT);
- ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, CFG_934X_DDR2_MODE_VAL_INIT);
- udelay(100);
-
- ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2);
- udelay(10);
- }
-
- if(type != 0){
- ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, ext_mod);
- }
- udelay(100);
-
- ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2);
- udelay(10);
-
- ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
- udelay(10);
-
- ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val);
- udelay(100);
-
- ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1);
- udelay(10);
-
- ar7240_reg_wr_nf(AR7240_DDR_REFRESH, refresh);
- udelay(100);
-
- ar7240_reg_wr(AR7240_DDR_TAP_CONTROL0, tap_val);
- ar7240_reg_wr(AR7240_DDR_TAP_CONTROL1, tap_val);
-
- if(ar7240_reg_rd(AR7240_REV_ID) & 0xf){
- /* NAND Clear */
- if((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & (1 << 3)) && type){
- ar7240_reg_wr(AR7240_DDR_TAP_CONTROL2, tap_val);
- ar7240_reg_wr(AR7240_DDR_TAP_CONTROL3, tap_val);
- }
- } else {
-#if DDR2_32BIT_SUPPORT
- if(type != 0){
- ar7240_reg_wr(AR7240_DDR_TAP_CONTROL2, tap_val);
- ar7240_reg_wr(AR7240_DDR_TAP_CONTROL3, tap_val);
- }
-#endif
- }
-
- ar7240_reg_wr_nf(AR7240_DDR_RD_DATA_THIS_CYCLE, cycle_val);
- udelay(100);
-
- ar7240_reg_wr_nf(AR7240_DDR_BURST, 0x74444444);
- udelay(100);
-
- ar7240_reg_wr_nf(AR7240_DDR_BURST2, 0x222);
- udelay(100);
-
- ar7240_reg_wr_nf(AR7240_AHB_MASTER_TIMEOUT, 0xfffff);
- udelay(100);
-
-#if (CFG_PLL_FREQ == CFG_PLL_600_500_250) || \
- (CFG_PLL_FREQ == CFG_PLL_500_500_250)
- // PMU2 ddr ldo tune
- ar7240_reg_rmw_set(0xb8116c44, (0x3 << 19));
- udelay(100);
-#endif
-
- return(type);
-}
-#endif
--- /dev/null
+/*
+ * PLL and clocks configurations for
+ * Qualcomm/Atheros AR934x and QCA95xx WiSoCs
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <soc/qca_pll_list.h>
+#include <config.h>
+#include <soc/qca_soc_common.h>
+#include <soc/qca95xx_pll_init.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+
+#define reg_oc_recovery t0
+#define reg_spi_ctrl_cfg t1
+#define reg_ref_clk_val t2
+#define reg_cpu_pll_cfg t3
+#define reg_ddr_pll_cfg t4
+#define reg_cpu_ddr_clk t5
+#define reg_cpu_pll_dit t6
+#define reg_ddr_pll_dit t7
+
+/* Sanity check for O/C recovery button number */
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+ #if (CONFIG_QCA_GPIO_OC_RECOVERY_BTN >= QCA_GPIO_COUNT)
+ #error "O/C recovery button number is not correct!"
+ #endif
+
+ #define CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN \
+ (1 << CONFIG_QCA_GPIO_OC_RECOVERY_BTN)
+#endif
+
+.globl lowlevel_init
+.type lowlevel_init, @function
+.align 4
+.text
+.ent lowlevel_init
+
+lowlevel_init:
+
+/*
+ * Get reference clock (XTAL) type, based on BOOTSTRAP register
+ * and save its value in one register for later use
+ */
+ li reg_ref_clk_val, 25
+ li t8, QCA_RST_BOOTSTRAP_REG
+ lw t9, 0(t8)
+ li t8, QCA_RST_BOOTSTRAP_REF_CLK_MASK
+ and t9, t9, t8
+ bgtz t9, set_xtal_40mhz
+ nop
+
+ b ahb_max_timeout
+ nop
+
+set_xtal_40mhz:
+ li reg_ref_clk_val, 40
+
+/* AHB max master timeout */
+ahb_max_timeout:
+ li t8, QCA_AHB_MASTER_TOUT_MAX_REG
+ lw t9, 0(t8)
+ or t9, t9, 0xFFFFF
+ sw t9, 0(t8)
+
+/*
+ * Reset RTC:
+ * 1. First reset RTC submodule using RST_RESET register
+ * 2. Then use RTC_SYNC_RESET register
+ * 3. And at the end, wait for ON_STATE bit set in RTC_SYNC_STATUS register
+ *
+ * TODO: do we need to reset RTC at all?
+ */
+rtc_reset:
+ li t8, QCA_RST_RESET_REG
+ lw t9, 0(t8)
+ or t9, t9, QCA_RST_RESET_RTC_RST_MASK
+ sw t9, 0(t8)
+ nop
+ nop
+
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_RST_RESET_RTC_RST_MASK
+ sw t9, 0(t8)
+ nop
+
+ li t8, QCA_RTC_SYNC_RST_REG
+ li t9, 0x0
+ sw t9, 0(t8)
+ nop
+ nop
+
+ li t9, QCA_RTC_SYNC_RST_RESET_MASK
+ sw t9, 0(t8)
+ nop
+
+ li t8, QCA_RTC_SYNC_STATUS_REG
+
+rtc_wait_on:
+ lw t9, 0(t8)
+ and t9, t9, QCA_RTC_SYNC_STATUS_ON_MASK
+ beqz t9, rtc_wait_on
+ nop
+
+/*
+ * O/C recovery mode (start with safe PLL/clocks configuration):
+ * 1. Check if defined recovery button is pressed
+ * 2. Indicate recovery mode in predefined register
+ * 3. If in recovery mode, do not use PLL configuration from FLASH,
+ * because it is probably the reason why user is using recovery mode
+ */
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+is_oc_recovery_btn_pressed:
+ li reg_oc_recovery, 0
+ li t8, QCA_GPIO_IN_REG
+ lw t9, 0(t8)
+ and t9, t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN
+
+ #ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW
+ bne t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN, in_oc_recovery_mode
+ nop
+ #else
+ beq t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN, in_oc_recovery_mode
+ nop
+ #endif
+
+ #ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET
+ b is_pll_cfg_in_flash
+ #else
+ b xtal_type_check
+ #endif
+ nop
+
+in_oc_recovery_mode:
+ li reg_oc_recovery, 1
+ b xtal_type_check
+ nop
+#endif /* CONFIG_QCA_GPIO_OC_RECOVERY_BTN */
+
+/*
+ * Check if PLL configuration is stored in FLASH:
+ * 1. Get 32-bit value from defined offset in FLASH
+ * 2. Compare it with predefined magic value
+ * 3. If values are not equal, continue default PLL/clocks configuration
+ * 4. If values are equal it means we should have target PLL/clocks register
+ * values stored in FLASH, just after magic value, in the following order:
+ * - SPI_CONTROL (offset 4)
+ * - CPU_PLL_CONFIG (offset 8)
+ * - DDR_PLL_CONFIG (offset 12)
+ * - CPU_DDR_CLOCK_CONTROL (offset 16)
+ * - CPU_PLL_DITHER (offset 20)
+ * - DDR_PLL_DITHER (offset 24)
+ * 5. After loading target values from FLASH,
+ * jump directly to PLL/clocks configuration
+ */
+#ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET
+is_pll_cfg_in_flash:
+ li t8, CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET
+ lw t9, 0(t8)
+ bne t9, QCA_PLL_IN_FLASH_MAGIC, xtal_type_check
+ nop
+
+pll_cfg_in_flash:
+ lw reg_spi_ctrl_cfg, 4(t8)
+ lw reg_cpu_pll_cfg, 8(t8)
+ lw reg_ddr_pll_cfg, 12(t8)
+ lw reg_cpu_ddr_clk, 16(t8)
+ lw reg_cpu_pll_dit, 20(t8)
+ lw reg_ddr_pll_dit, 24(t8)
+ b cpu_ddr_clock_control
+ nop
+#endif /* CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET */
+
+/*
+ * Check XTAL type and include dedicated PLL/clocks values,
+ * predefined in header file, based on selected preset configuration
+ */
+xtal_type_check:
+ beq reg_ref_clk_val, 40, xtal_is_40mhz
+ nop
+
+xtal_is_25mhz:
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+ beq reg_oc_recovery, 1, xtal_is_25mhz_recovery
+ nop
+#endif
+
+ li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL
+ li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25
+ li reg_ddr_pll_cfg, QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25
+ li reg_cpu_ddr_clk, QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25
+ li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25
+ li reg_ddr_pll_dit, QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25
+ b cpu_ddr_clock_control
+ nop
+
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+xtal_is_25mhz_recovery:
+ li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL_SAFE
+ li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25
+ li reg_ddr_pll_cfg, QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL25
+ li reg_cpu_ddr_clk, QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_SAFE_XTAL25
+ li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL25
+ li reg_ddr_pll_dit, QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL25
+ b cpu_ddr_clock_control
+ nop
+#endif
+
+xtal_is_40mhz:
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+ beq reg_oc_recovery, 1, xtal_is_40mhz_recovery
+ nop
+#endif
+
+ li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL
+ li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40
+ li reg_ddr_pll_cfg, QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40
+ li reg_cpu_ddr_clk, QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40
+ li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40
+ li reg_ddr_pll_dit, QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL40
+
+#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN
+ b cpu_ddr_clock_control
+ nop
+
+xtal_is_40mhz_recovery:
+ li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL_SAFE
+ li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40
+ li reg_ddr_pll_cfg, QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL40
+ li reg_cpu_ddr_clk, QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_SAFE_XTAL40
+ li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL40
+ li reg_ddr_pll_dit, QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL40
+#endif
+
+/*
+ * Load target value into CPU_DDR_CLOCK_CONTROL register,
+ * but for now keep bypass enabled for all clocks (CPU, DDR, AHB)
+ * (by default, after reset, they should be bypassed, do it just in case)
+ */
+cpu_ddr_clock_control:
+ li t8, QCA_PLL_CPU_DDR_CLK_CTRL_REG
+ move t9, reg_cpu_ddr_clk
+ or t9, t9, (QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK |\
+ QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK |\
+ QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK)
+ sw t9, 0(t8)
+
+/*
+ * Load target values into CPU/DDR_PLL_CONFIG registers, but for now keep PLLs down
+ * (by default, after reset, it should be powered down, do it just in case)
+ */
+cpu_pll_config:
+ li t8, QCA_PLL_CPU_PLL_CFG_REG
+ move t9, reg_cpu_pll_cfg
+ or t9, t9, QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK
+ sw t9, 0(t8)
+
+ddr_pll_config:
+ li t8, QCA_PLL_DDR_PLL_CFG_REG
+ move t9, reg_ddr_pll_cfg
+ or t9, t9, QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK
+ sw t9, 0(t8)
+
+/* Load target NFRAC_MIN values into CPU/DDR_PLL_DITHER registers */
+cpu_pll_dither:
+ li t8, QCA_PLL_CPU_PLL_DITHER_REG
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK
+ or t9, t9, reg_cpu_pll_dit
+ sw t9, 0(t8)
+
+ddr_pll_dither:
+ li t8, QCA_PLL_DDR_PLL_DITHER_REG
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK
+ or t9, t9, reg_ddr_pll_dit
+ sw t9, 0(t8)
+
+/* Disable PLL configuration over SRIF registers (just for sure) */
+cpu_pll_srif_disable:
+ li t8, QCA_PLL_SRIF_CPU_DPLL2_REG
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK
+ sw t9, 0(t8)
+
+ddr_pll_srif_disable:
+ li t8, QCA_PLL_SRIF_DDR_DPLL2_REG
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK
+ sw t9, 0(t8)
+
+/* Enable CPU PLL (only if we need it) and wait for update complete */
+cpu_pll_enable:
+ move t8, reg_cpu_pll_cfg
+ and t8, t8, QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK
+ bgtz t8, ddr_pll_enable
+ nop
+ li t8, QCA_PLL_CPU_PLL_CFG_REG
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK
+ sw t9, 0(t8)
+ nop
+
+/* Wait for CPU PLL update complete */
+cpu_pll_wait:
+ lw t9, 0(t8)
+ and t9, t9, QCA_PLL_CPU_PLL_CFG_UPDATING_MASK
+ bgtz t9, cpu_pll_wait
+ nop
+
+/* Enable DDR PLL (only if we need it) and wait for update complete */
+ddr_pll_enable:
+ move t8, reg_ddr_pll_cfg
+ and t8, t8, QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK
+ bgtz t8, pll_bypass_disable
+ nop
+ li t8, QCA_PLL_DDR_PLL_CFG_REG
+ lw t9, 0(t8)
+ and t9, t9, ~QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK
+ sw t9, 0(t8)
+ nop
+
+/* Wait for DDR PLL update complete */
+ddr_pll_wait:
+ lw t9, 0(t8)
+ and t9, t9, QCA_PLL_DDR_PLL_CFG_UPDATING_MASK
+ bgtz t9, ddr_pll_wait
+ nop
+
+/* Disable bypassing all clocks */
+pll_bypass_disable:
+ li t8, QCA_PLL_CPU_DDR_CLK_CTRL_REG
+ lw t9, 0(t8)
+ and t9, t9, ~(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK |\
+ QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK |\
+ QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK)
+ sw t9, 0(t8)
+
+/* Setup SPI (clock and other settings) */
+spi_setup:
+
+#ifdef CONFIG_QCA_PLL_SPI_FLASH_CLK_AUTO
+ /*
+ * Configure SPI FLASH and clock:
+ * 1. Check which PLL is used to drive AHB clock
+ * 2. Calculate selected PLL output value
+ * 3. Calculate target AHB clock value
+ * 4. Find minimum divider for SPI clock
+ * 5. Setup SPI FLASH clock and other related options (REMAP, etc.)
+ */
+ li t8, QCA_PLL_CPU_DDR_CLK_CTRL_REG
+ lw t9, 0(t8)
+
+ and t3, t9, QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK
+ srl t3, t3, QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT
+ /* t3 = AHB_POST_DIV + 1 */
+ addi t3, t3, 1
+
+ /* Find out where AHB clock come from (CPU or DDR PLL) */
+ and t9, t9, QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK
+ bgtz t9, ahb_clk_from_ddr_pll
+ nop
+
+ahb_clk_from_cpu_pll:
+ li t8, QCA_PLL_CPU_PLL_CFG_REG
+ lw t9, 0(t8)
+
+ /* Calculate NINT */
+ and t8, t9, QCA_PLL_CPU_PLL_CFG_NINT_MASK
+ srl t8, t8, QCA_PLL_CPU_PLL_CFG_NINT_SHIFT
+ mul t4, t8, reg_ref_clk_val /* t4 = REFCLK * NINT */
+
+ /* Calculate OUTDIV */
+ and t8, t9, QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK
+ srl t8, t8, QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT
+ li t5, 1
+ sllv t5, t5, t8 /* t5 = 2 ^ OUTDIV */
+
+ /* Calculate REFDIV */
+ and t8, t9, QCA_PLL_CPU_PLL_CFG_REFDIV_MASK
+ srl t8, t8, QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT
+ mul t5, t8, t5 /* t5 = REDIV * (2 ^ OUTDIV) */
+ nop
+
+ b ahb_clk_calculation
+ nop
+
+ahb_clk_from_ddr_pll:
+ li t8, QCA_PLL_DDR_PLL_CFG_REG
+ lw t9, 0(t8)
+
+ /* Calculate NINT */
+ and t8, t9, QCA_PLL_DDR_PLL_CFG_NINT_MASK
+ srl t8, t8, QCA_PLL_DDR_PLL_CFG_NINT_SHIFT
+ mul t4, t8, reg_ref_clk_val /* t4 = REFCLK * NINT */
+
+ /* Calculate OUTDIV */
+ and t8, t9, QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK
+ srl t8, t8, QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT
+ li t5, 1
+ sllv t5, t5, t8 /* t5 = 2 ^ OUTDIV */
+
+ /* Calculate REFDIV */
+ and t8, t9, QCA_PLL_DDR_PLL_CFG_REFDIV_MASK
+ srl t8, t8, QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT
+ mul t5, t8, t5 /* t5 = REDIV * (2 ^ OUTDIV) */
+ nop
+ nop
+
+ahb_clk_calculation:
+ mul t5, t5, t3 /* t5 = REDIV * (2 ^ OUTDIV) * (AHB_POST_DIV + 1) */
+ nop
+ nop
+
+ /* Store AHB CLK in t3 */
+ div t3, t4, t5
+
+ li t9, CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ
+ li t6, 0 /* t6 = CLOCK_DIVIDER for SPI FLASH clock */
+
+/* Maximum SPI clock divider loop */
+spi_clk_calculation:
+ move t7, t6
+ addi t7, t7, 1
+ sll t7, t7, 1 /* t7 = 2 * (CLOCK_DIVIDER + 1) */
+ div t4, t3, t7 /* t4 = SPI FLASH clock */
+ sltu t5, t4, t9 /* t4 < t9 ? t5 = 1 : t5 = 0 */
+
+ /* SPI clock == target maximum clock? */
+ beq t4, t9, spi_clk_setup
+ nop
+
+ /* SPI clock < target maximum clock? */
+ bgtz t5, spi_clk_setup
+ nop
+
+ addi t6, t6, 1
+ b spi_clk_calculation
+ nop
+
+spi_clk_setup:
+ sll t6, t6, QCA_SPI_CTRL_CLK_DIV_SHIFT
+ and reg_spi_ctrl_cfg, reg_spi_ctrl_cfg, ~QCA_SPI_CTRL_CLK_DIV_MASK
+ or reg_spi_ctrl_cfg, reg_spi_ctrl_cfg, t6
+#endif /* CONFIG_QCA_PLL_SPI_FLASH_CLK_AUTO */
+
+ li t8, QCA_SPI_CTRL_REG
+ sw reg_spi_ctrl_cfg, 0(t8)
+ and reg_spi_ctrl_cfg, reg_spi_ctrl_cfg, QCA_SPI_CTRL_REMAP_DIS_MASK
+ beqz reg_spi_ctrl_cfg, end
+ nop
+
+/*
+ * This is a small hack, needed after setting REMAP_DISABLE bit
+ * in SPI_CONTROL_ADDR register.
+ *
+ * Before that, SPI FLASH is mapped to 0x1FC00000, but just after
+ * setting REMAP_DISABLE bit, aliasing is disabled and SPI FLASH
+ * is mapped to 0x1F00000, so that the whole 16 MB address space
+ * could be used.
+ *
+ * That means, we need to "fix" return address, stored previously
+ * in $ra register, subtracting a value 0x00C00000 from it.
+ *
+ * Without that, jump would end up somewhere far away on FLASH...
+ */
+ li t8, 0x00C00000
+ subu ra, ra, t8
+
+end:
+ jr ra
+ nop
+
+.end lowlevel_init
--- /dev/null
+/*
+ * Qualcomm/Atheros WiSoCs system clocks related functions
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * Partially based on:
+ * Linux/arch/mips/ath79/clock.c
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <soc/qca_soc_common.h>
+
+/*
+ * Calculates and returns PLL value
+ * TODO: check for overflow!
+ */
+static u32 qca_get_pll(u32 ref_clk,
+ u32 refdiv,
+ u32 nfrac,
+ u32 nfracdiv,
+ u32 nint,
+ u32 outdiv)
+{
+ u64 pll_mul, pll_div;
+
+ pll_mul = ref_clk;
+ pll_div = refdiv;
+
+ if (pll_div == 0)
+ pll_div = 1;
+
+ if (nfrac > 0) {
+ pll_mul = pll_mul * ((nint * nfracdiv) + nfrac);
+ pll_div = pll_div * nfracdiv;
+ } else {
+ pll_mul = pll_mul * nint;
+ }
+
+ pll_div = pll_div << outdiv;
+
+ return (u32)(pll_mul / pll_div);
+}
+
+/*
+ * Get CPU, RAM, AHB and SPI clocks
+ * TODO: confirm nfracdiv values
+ */
+void qca_sys_clocks(u32 *cpu_clk,
+ u32 *ddr_clk,
+ u32 *ahb_clk,
+ u32 *spi_clk,
+ u32 *ref_clk)
+{
+ u32 qca_ahb_clk, qca_cpu_clk, qca_ddr_clk, qca_ref_clk, qca_spi_clk;
+ u32 nint, outdiv, refdiv;
+ u32 nfrac, nfracdiv;
+ u32 reg_val, temp;
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ u32 cpu_pll;
+#else
+ u32 cpu_pll, ddr_pll;
+#endif
+
+ if (qca_xtal_is_40mhz() == 1) {
+ qca_ref_clk = VAL_40MHz;
+ } else {
+ qca_ref_clk = VAL_25MHz;
+ }
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ /*
+ * Main AR933x CPU PLL clock calculation:
+ *
+ * 1. If CPU PLL DITHER is disabled:
+ * VCO_OUT = (REF_CLK / REF_DIV) * (NINT + (NFRAC_MIN / 1024))
+ * CPU_PLL_OUT = VCO_OUT / (2^OUT_DIV)
+ *
+ * 2. If CPU PLL DITHER is enabled:
+ * VCO_OUT = (REF_CLK / REF_DIV) * (NINT + (NFRAC / 1024))
+ * CPU_PLL_OUT = VCO_OUT / (2^OUT_DIV)
+ *
+ * TODO: NFRAC does not exist in AR9331 datasheet,
+ * but exist in many other QC/A WiSOC datasheets,
+ * we should somehow (scope?) check and confirm it
+ */
+
+ /* Read CPU CLock Control Register (CLOCK_CONTROL) value */
+ reg_val = qca_soc_reg_read(QCA_PLL_CPU_CLK_CTRL_REG);
+
+ if (reg_val & QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK) {
+ /* PLL is bypassed, so all clocks are == reference clock */
+ qca_cpu_clk = qca_ref_clk;
+ qca_ddr_clk = qca_ref_clk;
+ qca_ahb_clk = qca_ref_clk;
+ } else {
+ reg_val = qca_soc_reg_read(QCA_PLL_CPU_PLL_DITHER_REG);
+
+ if (reg_val & QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK) {
+ reg_val = qca_soc_reg_read(QCA_PLL_CPU_PLL_CFG_REG);
+ nfrac = (reg_val & QCA_PLL_CPU_PLL_CFG_NFRAC_MASK)
+ >> QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT;
+ } else {
+ /* NFRAC = NFRAC_MIN if DITHER_EN is 0 */
+ reg_val = qca_soc_reg_read(QCA_PLL_CPU_PLL_DITHER_FRAC_REG);
+ nfrac = (reg_val & QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK)
+ >> QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT;
+ }
+
+ nfracdiv = 1 << 10;
+
+ reg_val = qca_soc_reg_read(QCA_PLL_CPU_PLL_CFG_REG);
+
+ nint = (reg_val & QCA_PLL_CPU_PLL_CFG_NINT_MASK)
+ >> QCA_PLL_CPU_PLL_CFG_NINT_SHIFT;
+
+ refdiv = (reg_val & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK)
+ >> QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT;
+
+ outdiv = (reg_val & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK)
+ >> QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT;
+
+ /* TODO: need confirmation that OUTDIV == 0 is not supported for AR933x */
+ if (outdiv == 0)
+ outdiv = 1;
+
+ /* Final CPU PLL value */
+ cpu_pll = qca_get_pll(qca_ref_clk, refdiv,
+ nfrac, nfracdiv, nint, outdiv);
+
+ /* CPU, DDR and AHB clock dividers */
+ reg_val = qca_soc_reg_read(QCA_PLL_CPU_CLK_CTRL_REG);
+
+ temp = ((reg_val & QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK)
+ >> QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT) + 1;
+ qca_cpu_clk = cpu_pll / temp;
+
+ temp = ((reg_val & QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK)
+ >> QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT) + 1;
+ qca_ddr_clk = cpu_pll / temp;
+
+ temp = ((reg_val & QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK)
+ >> QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT) + 1;
+ qca_ahb_clk = cpu_pll / temp;
+ }
+#else
+ /*
+ * Main AR934x/QCA95xx CPU/DDR PLL clock calculation
+ */
+
+ /* CPU PLL */
+ reg_val = qca_soc_reg_read(QCA_PLL_SRIF_CPU_DPLL2_REG);
+
+ /* CPU PLL settings from SRIF CPU DPLL2? */
+ if (reg_val & QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK) {
+ outdiv = (reg_val & QCA_PLL_SRIF_DPLL2_OUTDIV_MASK)
+ >> QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT;
+
+ reg_val = qca_soc_reg_read(QCA_PLL_SRIF_CPU_DPLL1_REG);
+
+ nfrac = (reg_val & QCA_PLL_SRIF_DPLL1_NFRAC_MASK)
+ >> QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT;
+
+ nfracdiv = 1 << 18;
+
+ nint = (reg_val & QCA_PLL_SRIF_DPLL1_NINT_MASK)
+ >> QCA_PLL_SRIF_DPLL1_NINT_SHIFT;
+
+ refdiv = (reg_val & QCA_PLL_SRIF_DPLL1_REFDIV_MASK)
+ >> QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT;
+ } else {
+ reg_val = qca_soc_reg_read(QCA_PLL_CPU_PLL_DITHER_REG);
+
+ if (reg_val & QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK) {
+ reg_val = qca_soc_reg_read(QCA_PLL_CPU_PLL_CFG_REG);
+ nfrac = (reg_val & QCA_PLL_CPU_PLL_CFG_NFRAC_MASK)
+ >> QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT;
+ } else {
+ /* NFRAC = NFRAC_MIN if DITHER_EN is 0 */
+ nfrac = (reg_val & QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK)
+ >> QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT;
+ }
+
+ nfracdiv = 1 << 6;
+
+ reg_val = qca_soc_reg_read(QCA_PLL_CPU_PLL_CFG_REG);
+
+ nint = (reg_val & QCA_PLL_CPU_PLL_CFG_NINT_MASK)
+ >> QCA_PLL_CPU_PLL_CFG_NINT_SHIFT;
+
+ refdiv = (reg_val & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK)
+ >> QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT;
+
+ outdiv = (reg_val & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK)
+ >> QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT;
+ }
+
+ /* Final CPU PLL value */
+ cpu_pll = qca_get_pll(qca_ref_clk, refdiv,
+ nfrac, nfracdiv, nint, outdiv);
+
+ /* DDR PLL */
+ reg_val = qca_soc_reg_read(QCA_PLL_SRIF_DDR_DPLL2_REG);
+
+ /* DDR PLL settings from SRIF DDR DPLL2? */
+ if (reg_val & QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK) {
+ outdiv = (reg_val & QCA_PLL_SRIF_DPLL2_OUTDIV_MASK)
+ >> QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT;
+
+ reg_val = qca_soc_reg_read(QCA_PLL_SRIF_DDR_DPLL1_REG);
+
+ nfrac = (reg_val & QCA_PLL_SRIF_DPLL1_NFRAC_MASK)
+ >> QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT;
+
+ nfracdiv = 1 << 18;
+
+ nint = (reg_val & QCA_PLL_SRIF_DPLL1_NINT_MASK)
+ >> QCA_PLL_SRIF_DPLL1_NINT_SHIFT;
+
+ refdiv = (reg_val & QCA_PLL_SRIF_DPLL1_REFDIV_MASK)
+ >> QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT;
+ } else {
+ reg_val = qca_soc_reg_read(QCA_PLL_DDR_PLL_DITHER_REG);
+
+ if (reg_val & QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK) {
+ reg_val = qca_soc_reg_read(QCA_PLL_DDR_PLL_CFG_REG);
+ nfrac = (reg_val & QCA_PLL_DDR_PLL_CFG_NFRAC_MASK)
+ >> QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT;
+ } else {
+ /* NFRAC = NFRAC_MIN if DITHER_EN is 0 */
+ nfrac = (reg_val & QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK)
+ >> QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT;
+ }
+
+ nfracdiv = 1 << 10;
+
+ reg_val = qca_soc_reg_read(QCA_PLL_DDR_PLL_CFG_REG);
+
+ nint = (reg_val & QCA_PLL_DDR_PLL_CFG_NINT_MASK)
+ >> QCA_PLL_DDR_PLL_CFG_NINT_SHIFT;
+
+ refdiv = (reg_val & QCA_PLL_DDR_PLL_CFG_REFDIV_MASK)
+ >> QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT;
+
+ outdiv = (reg_val & QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK)
+ >> QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT;
+ }
+
+ /* Final DDR PLL value */
+ ddr_pll = qca_get_pll(qca_ref_clk, refdiv,
+ nfrac, nfracdiv, nint, outdiv);
+
+ /* CPU clock divider */
+ reg_val = qca_soc_reg_read(QCA_PLL_CPU_DDR_CLK_CTRL_REG);
+
+ temp = ((reg_val & QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK)
+ >> QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) + 1;
+
+ if (reg_val & QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK) {
+ qca_cpu_clk = qca_ref_clk;
+ } else if (reg_val & QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK) {
+ qca_cpu_clk = cpu_pll / temp;
+ } else {
+ qca_cpu_clk = ddr_pll / temp;
+ }
+
+ /* DDR clock divider */
+ temp = ((reg_val & QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK)
+ >> QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) + 1;
+
+ if (reg_val & QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK) {
+ qca_ddr_clk = qca_ref_clk;
+ } else if (reg_val & QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK) {
+ qca_ddr_clk = ddr_pll / temp;
+ } else {
+ qca_ddr_clk = cpu_pll / temp;
+ }
+
+ /* AHB clock divider */
+ temp = ((reg_val & QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK)
+ >> QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) + 1;
+
+ if (reg_val & QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK) {
+ qca_ahb_clk = qca_ref_clk;
+ } else if (reg_val & QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) {
+ qca_ahb_clk = ddr_pll / temp;
+ } else {
+ qca_ahb_clk = cpu_pll / temp;
+ }
+#endif
+ /* Calculate SPI FLASH clock if needed */
+ if (spi_clk != NULL) {
+ /* First disable SPI */
+ qca_soc_reg_read_set(QCA_SPI_FUNC_SEL_REG,
+ QCA_SPI_FUNC_SEL_FUNC_SEL_MASK);
+
+ /* SPI clock = AHB clock / ((SPI clock divider + 1) * 2) */
+ reg_val = (qca_soc_reg_read(QCA_SPI_CTRL_REG) & QCA_SPI_CTRL_CLK_DIV_MASK)
+ >> QCA_SPI_CTRL_CLK_DIV_SHIFT;
+
+ qca_spi_clk = qca_ahb_clk / ((reg_val + 1) * 2);
+
+ /* Re-enable SPI */
+ qca_soc_reg_read_clear(QCA_SPI_FUNC_SEL_REG,
+ QCA_SPI_FUNC_SEL_FUNC_SEL_MASK);
+ }
+
+ /* Return values */
+ if (cpu_clk != NULL)
+ *cpu_clk = qca_cpu_clk;
+
+ if (ddr_clk != NULL)
+ *ddr_clk = qca_ddr_clk;
+
+ if (ahb_clk != NULL)
+ *ahb_clk = qca_ahb_clk;
+
+ if (spi_clk != NULL)
+ *spi_clk = qca_spi_clk;
+
+ if (ref_clk != NULL)
+ *ref_clk = qca_ref_clk;
+}
--- /dev/null
+/*
+ * Qualcomm/Atheros WiSoCs common/helper functions
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/addrspace.h>
+#include <soc/qca_soc_common.h>
+
+/*
+ * Returns 1 if reference clock is 40 MHz
+ */
+inline u32 qca_xtal_is_40mhz(void)
+{
+ return ((qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG) &
+ QCA_RST_BOOTSTRAP_REF_CLK_MASK) >> QCA_RST_BOOTSTRAP_REF_CLK_SHIFT);
+}
+
+/*
+ * Performs full chip reset
+ */
+void qca_full_chip_reset(void)
+{
+ volatile u32 i = 1;
+
+ do {
+ qca_soc_reg_write(QCA_RST_RESET_REG,
+ QCA_RST_RESET_FULL_CHIP_RST_MASK
+ | QCA_RST_RESET_DDR_RST_MASK);
+ } while (i);
+}
--- /dev/null
+/*
+ * Qualcomm/Atheros WiSoCs DRAM related
+ * functions for WiSoC families:
+ * - Atheros AR933x
+ * - Atheros AR934x
+ * - Qualcomm/Atheros QCA953x
+ * - Qualcomm/Atheros QCA955x
+ * - Qualcomm/Atheros QCA956x
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Copyright (C) 2014 Qualcomm Atheros, Inc.
+ * Copyright (C) 2008-2010 Atheros Communications Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/addrspace.h>
+#include <soc/qca_soc_common.h>
+#include <soc/qca_dram.h>
+
+#define QCA_DDR_SIZE_INCREMENT (8 * 1024 * 1024)
+
+/*
+ * Returns size (in bytes) of the DRAM memory
+ *
+ * DDR wraps around, write a pattern to 0x00000000
+ * at 8M, 16M, 32M etc. and check when it gets overwritten
+ */
+u32 qca_dram_size(void)
+{
+ u8 *p = (u8 *)KSEG1;
+ u8 pattern = 0x77;
+ u32 i;
+
+ *p = pattern;
+
+ #define max_i (QCA_DRAM_MAX_SIZE_VAL / QCA_DDR_SIZE_INCREMENT)
+
+ for (i = 1; (i < max_i); i++) {
+ *(p + i * QCA_DDR_SIZE_INCREMENT) = (u8)i;
+
+ if (*p != pattern) {
+ break;
+ }
+ }
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ return ((i < max_i) ?
+ (i * QCA_DDR_SIZE_INCREMENT) : QCA_DRAM_MAX_SIZE_VAL);
+#else
+ /*
+ * TODO:
+ * something is wrong with relocation,
+ * need to fix it for boards with > 32M of RAM
+ *
+ * For now just return 1 MB smaller size
+ */
+ return ((i < max_i) ?
+ (i * QCA_DDR_SIZE_INCREMENT) : QCA_DRAM_MAX_SIZE_VAL) - 1024 * 1024;
+#endif
+}
+
+/*
+ * Return memory type value from BOOT_STRAP register
+ */
+u32 qca_dram_type(void)
+{
+#if defined(CONFIG_BOARD_DRAM_TYPE_SDR)
+ #error "SDRAM is not supported!"
+ return RAM_MEMORY_TYPE_SDR;
+#elif defined(CONFIG_BOARD_DRAM_TYPE_DDR1)
+ return RAM_MEMORY_TYPE_DDR1;
+#elif defined(CONFIG_BOARD_DRAM_TYPE_DDR2)
+ return RAM_MEMORY_TYPE_DDR2;
+#else
+ u32 dram_type;
+
+ dram_type = ((qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG)
+ & QCA_RST_BOOTSTRAP_MEM_TYPE_MASK) >> QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT);
+
+ switch (dram_type) {
+ case QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL:
+ dram_type = RAM_MEMORY_TYPE_SDR;
+ break;
+ case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL:
+ dram_type = RAM_MEMORY_TYPE_DDR1;
+ break;
+ case QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL:
+ dram_type = RAM_MEMORY_TYPE_DDR2;
+ break;
+ default:
+ dram_type = RAM_MEMORY_TYPE_UNKNOWN;
+ break;
+ }
+
+ return dram_type;
+#endif
+}
+
+/*
+ * Returns DDR width (16 or 32)
+ */
+u32 qca_dram_ddr_width(void)
+{
+#ifndef CONFIG_BOARD_DRAM_DDR_WIDTH
+ #if (SOC_TYPE & QCA_AR933X_SOC)
+ return 16;
+ #else
+ if (qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG)
+ & QCA_RST_BOOTSTRAP_DDR_WIDTH_32_MASK)
+ return 32;
+
+ return 16;
+ #endif
+#else
+ return CONFIG_BOARD_DRAM_DDR_WIDTH;
+#endif
+}
+
+/*
+ * Returns CAS latency, based on setting in DDR_CONFIG register
+ */
+inline u32 qca_dram_cas_lat(void)
+{
+#ifndef CONFIG_BOARD_DRAM_CAS_LATENCY
+ u32 reg;
+
+ reg = (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_CAS_3LSB_MASK)
+ >> QCA_DDR_CFG_CAS_3LSB_SHIFT;
+
+ if (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_CAS_MSB_MASK)
+ reg = reg + 8;
+
+ /* CAS_LATENCY value in DDR_CONFIG register == 2 * MEM_CAS */
+ return reg / 2;
+#else
+ return CONFIG_BOARD_DRAM_CAS_LATENCY
+#endif
+}
+
+/*
+ * Returns tRCD latency
+ */
+inline u32 qca_dram_trcd_lat(void)
+{
+ u32 reg;
+
+ reg = (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_TRCD_MASK)
+ >> QCA_DDR_CFG_TRCD_SHIFT;
+
+ return reg / 2;
+}
+
+/*
+ * Returns tRP latency
+ */
+inline u32 qca_dram_trp_lat(void)
+{
+ u32 reg;
+
+ reg = (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_TRP_MASK)
+ >> QCA_DDR_CFG_TRP_SHIFT;
+
+ return reg / 2;
+}
+
+/*
+ * Returns tRAS latency
+ */
+inline u32 qca_dram_tras_lat(void)
+{
+ u32 reg;
+
+ reg = (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_TRAS_MASK)
+ >> QCA_DDR_CFG_TRAS_SHIFT;
+
+ return reg / 2;
+}
+
+/*
+ * ===============================================
+ * DQS delay tap controller tune related functions
+ * ===============================================
+ */
+#define DQS_DELAY_TAP_DEFAULT_VAL 8
+
+#if (SOC_TYPE & QCA_AR933X_SOC) |\
+ (SOC_TYPE & QCA_AR934X_SOC)
+ #define DQS_DELAY_TAP_MAX_VAL 62
+#else
+ #define DQS_DELAY_TAP_MAX_VAL 63
+#endif
+
+/*
+ * Setup DQS_{0,1,2,3} delay tap control register/s
+ */
+static void qca_ddr_tap_save(u32 tap, u32 ddr_width)
+{
+#if (SOC_TYPE & QCA_AR933X_SOC) |\
+ (SOC_TYPE & QCA_AR934X_SOC)
+ u32 tap_h;
+
+ /* It seems that AR93xx SoCs have two delay chains */
+ if (tap > (DQS_DELAY_TAP_MAX_VAL / 2)) {
+ tap_h = tap - (DQS_DELAY_TAP_MAX_VAL / 2);
+ tap = tap & QCA_DDR_TAP_CTRL_TAP_L_MASK;
+ tap = tap | (tap_h << QCA_DDR_TAP_CTRL_TAP_H_SHIFT);
+ }
+#endif
+
+ qca_soc_reg_write(QCA_DDR_TAP_CTRL_0_REG, tap);
+ qca_soc_reg_write(QCA_DDR_TAP_CTRL_1_REG, tap);
+
+ /* Setup DQS2 and DQS3 only for 32-bit DDR interface width */
+ if (ddr_width == 32) {
+ qca_soc_reg_write(QCA_DDR_TAP_CTRL_2_REG, tap);
+ qca_soc_reg_write(QCA_DDR_TAP_CTRL_3_REG, tap);
+ }
+}
+
+/*
+ * Only for AR933x we will use different code
+ * for delay tap controller tune as it seems
+ * that this SoC doesn't have DDR BIST.
+ *
+ * Below function is universal, so it should
+ * work also for other QC/A WiSoCs and give
+ * same (or very similar) results. The only
+ * difference is that the DDR BIST based
+ * version seems to be much faster.
+ */
+#if (SOC_TYPE & QCA_AR933X_SOC)
+
+ #define DQS_DELAY_TAP_PATTERN_OFFSET 0x2000
+ #define DQS_DELAY_TAP_PATTERN_SIZE 0x1000
+ #define DQS_DELAY_TAP_TEST_LOOPS 2
+
+/*
+ * Prepare pattern for further tests
+ */
+static inline void qca_ddr_tap_patt(void)
+{
+ u32 i, j, pat;
+ u32 *addr;
+
+ /* Prepare 4M (256 x 4 x 4 bytes) pattern */
+ addr = (void *)KSEG1ADDR(DQS_DELAY_TAP_PATTERN_OFFSET);
+
+ for (i = 0; i < 256; i++) {
+ pat = 0;
+
+ for (j = 0; j < 8; j++) {
+ if (i & (1 << j)) {
+ if (j % 2)
+ pat |= 0xFFFF0000;
+ else
+ pat |= 0x0000FFFF;
+ }
+
+ if (j % 2) {
+ *addr++ = pat;
+ pat = 0;
+ }
+ }
+ }
+}
+
+/*
+ * This function is a modified C version of the original
+ * ar933x_ddr_tap_init() function, written in asm,
+ * included in Atheros (Q)SDK code.
+ *
+ * Below is a modified version, partially based on:
+ * https://patchwork.ozlabs.org/patch/569046/
+ */
+static void qca_ddr_tap_tune(u32 ddr_width)
+{
+ u32 *addr, *addr_k0, *addr_k1;
+ u32 tap, tap_hi, tap_lo;
+ u32 err, got_lo, i;
+
+ /* Pattern */
+ qca_ddr_tap_patt();
+
+ got_lo = 0;
+ tap_hi = 0;
+ tap_lo = 0;
+
+ addr = (void *)KSEG1ADDR(DQS_DELAY_TAP_PATTERN_OFFSET
+ + DQS_DELAY_TAP_PATTERN_SIZE);
+
+ /*
+ * Idea here is to test all possible tap values, one by one,
+ * starting from the lowest. We are looking for a range within
+ * the written and read back data is the same. We assume here
+ * that the valid tap range is continuous.
+ *
+ * From hardware POV, delay tap controller is used to adjust
+ * the data window.
+ */
+ for (tap = 0; tap <= DQS_DELAY_TAP_MAX_VAL; tap++) {
+ qca_ddr_tap_save(tap, ddr_width);
+
+ err = 0;
+
+ for (i = 0; i < DQS_DELAY_TAP_TEST_LOOPS; i++) {
+ addr_k1 = (void *)KSEG1ADDR(DQS_DELAY_TAP_PATTERN_OFFSET);
+ addr_k0 = (void *)KSEG0ADDR(DQS_DELAY_TAP_PATTERN_OFFSET);
+
+ while (addr_k1 < addr) {
+ if (*addr_k1++ != *addr_k0++) {
+ err = 1;
+ break;
+ }
+ }
+
+ if (err)
+ break;
+ }
+
+ if (err) {
+ if (got_lo) {
+ if (tap > 0)
+ tap_hi = tap - 1;
+
+ break;
+ }
+ } else {
+ if (!got_lo) {
+ tap_lo = tap;
+ got_lo = 1;
+ } else {
+ tap_hi = tap;
+ }
+ }
+ }
+
+ /* Calculate final tap value (rounded up average) */
+ if (got_lo) {
+ tap = (tap_hi + tap_lo + 1) / 2;
+ } else {
+ tap = DQS_DELAY_TAP_DEFAULT_VAL;
+ }
+
+ qca_ddr_tap_save(tap, ddr_width);
+}
+
+#else /* SOC_TYPE & QCA_AR933X_SOC */
+
+ #define DQS_DELAY_TAP_TEST_LOOPS 8
+
+/*
+ * Unknown magic values and registers from Atheros (Q)SDK.
+ *
+ * It looks like some test patterns and masks setup,
+ * but it's not confirmed. Used here values are
+ * different, but were tested on real hardware.
+ */
+static inline void qca_ddr_tap_bist_init(void)
+{
+ qca_soc_reg_write(QCA_DDR_PERF_COMP_AHB_GE0_0_REG, 0xAAAAAAAA);
+ qca_soc_reg_write(QCA_DDR_PERF_MASK_AHB_GE0_0_REG, 0xAAAAAAAA);
+
+ qca_soc_reg_write(QCA_DDR_PERF_COMP_AHB_GE0_1_REG, 0x55555555);
+ qca_soc_reg_write(QCA_DDR_PERF_MASK_AHB_GE0_1_REG, 0x55555555);
+
+ qca_soc_reg_write(QCA_DDR_PERF_COMP_AHB_GE1_0_REG, 0xAAAAAAAA);
+ qca_soc_reg_write(QCA_DDR_PERF_MASK_AHB_GE1_0_REG, 0xAAAAAAAA);
+
+ qca_soc_reg_write(QCA_DDR_PERF_COMP_AHB_GE1_1_REG, 0x55555555);
+ qca_soc_reg_write(QCA_DDR_PERF_MASK_AHB_GE1_1_REG, 0x55555555);
+}
+
+/*
+ * This function is a modified C version of the original
+ * ath_ddr_tap_cal() function, written in asm,
+ * included in Atheros (Q)SDK code.
+ *
+ * It seems that newer QC/A WiSoCs have some kind of
+ * built-in self-test (BIST) for DDR controller, but
+ * none of the used registers or their values are
+ * described in datasheets, so for now, we will just
+ * use them as in original code.
+ *
+ * Below is a modified version, partially based on:
+ * https://patchwork.ozlabs.org/patch/569047/
+ */
+static void qca_ddr_tap_tune(u32 ddr_width)
+{
+ u32 tap, tap_hi, tap_lo;
+ u32 fail, got_lo, reg;
+
+ got_lo = 0;
+ tap_hi = 0;
+ tap_lo = 0;
+
+ /* How many test loops per tested tap value */
+ qca_soc_reg_write(QCA_DDR_PERF_COMP_ADDR_1_REG,
+ (DQS_DELAY_TAP_TEST_LOOPS
+ << QCA_DDR_PERF_COMP_ADDR_1_TEST_CNT_SHIFT));
+
+ /*
+ * Unknown magic value, original comment:
+ * "4 Row Address Bits, 4 Column Address Bits, 2 BA bits"
+ */
+ qca_soc_reg_write(QCA_DDR_PERF_MASK_ADDR_0_REG, 0xFA5DE83F);
+
+ /*
+ * Test all possible tap values, try to find working range
+ * (minimum and maximum delays) and use average value
+ */
+ for (tap = 0; tap <= DQS_DELAY_TAP_MAX_VAL; tap++) {
+ qca_ddr_tap_save(tap, ddr_width);
+
+ qca_ddr_tap_bist_init();
+
+ /* Enable BIST test and wait for finish */
+ qca_soc_reg_write(QCA_DDR_BIST_REG, QCA_DDR_BIST_TEST_EN_MASK);
+
+ do {
+ reg = qca_soc_reg_read(QCA_DDR_BIST_STATUS_REG);
+ } while (!(reg & QCA_DDR_BIST_STATUS_DONE_MASK));
+
+ /* Disable BIST test */
+ qca_soc_reg_write(QCA_DDR_BIST_REG, 0);
+
+ /* Check how many tests failed */
+ fail = (reg & QCA_DDR_BIST_STATUS_FAIL_CNT_MASK)
+ >> QCA_DDR_BIST_STATUS_FAIL_CNT_SHIFT;
+
+ if (fail == 0) {
+ if (!got_lo) {
+ tap_lo = tap;
+ got_lo = 1;
+ } else {
+ tap_hi = tap;
+ }
+ } else {
+ if (got_lo) {
+ if (tap > 0)
+ tap_hi = tap - 1;
+
+ break;
+ }
+ }
+ }
+
+ /* Calculate final tap value (rounded up average) */
+ if (got_lo) {
+ tap = (tap_hi + tap_lo + 1) / 2;
+ } else {
+ tap = DQS_DELAY_TAP_DEFAULT_VAL;
+ }
+
+ qca_ddr_tap_save(tap, ddr_width);
+}
+
+#endif /* SOC_TYPE & QCA_AR933X_SOC */
+
+/*
+ * ===============================================
+ * DDR controller initialization related functions
+ * ===============================================
+ */
+
+/*
+ * Below defines are "safe" DDR1/DDR2 timing parameters.
+ * They should work for most chips, but not for all.
+ *
+ * For different values, user can define target value
+ * of all memory controller related registers.
+ *
+ */
+#define DDRx_tMRD_ns 10
+#define DDRx_tRAS_ns 40
+#define DDRx_tRCD_ns 15
+#define DDRx_tRP_ns 15
+#define DDRx_tRRD_ns 10
+#define DDRx_tWR_ns 15
+#define DDRx_tWTR_ns 10
+
+#define DDR1_tRFC_ns 75
+#define DDR2_tRFC_ns 120
+
+#define DDR2_tFAW_ns 50
+#define DDR2_tWL_ns 5
+
+#define DDR_addit_lat 0
+#define DDR_burst_len 8
+
+/* All above values are safe for clocks not lower than below values */
+#define DDR1_timing_clk_max 400
+#define DDR2_timing_clk_max 533
+
+/* Maximum timing values, based on register fields sizes */
+#define MAX_tFAW BITS(0, 6)
+#define MAX_tMRD BITS(0, 4)
+#define MAX_tRAS BITS(0, 5)
+#define MAX_tRCD BITS(0, 4)
+#define MAX_tRFC BITS(0, 6)
+#define MAX_tRP BITS(0, 4)
+#define MAX_tRRD BITS(0, 4)
+#define MAX_tRTP BITS(0, 4)
+#define MAX_tRTW BITS(0, 5)
+#define MAX_tWL BITS(0, 4)
+#define MAX_tWR BITS(0, 4)
+#define MAX_tWTR BITS(0, 5)
+
+/*
+ * Setup DDR_CONFIG register
+ */
+static inline void qca_dram_set_ddr_cfg(u32 mem_cas,
+ u32 ddr_clk,
+ u32 mem_type)
+{
+#ifndef CONFIG_QCA_DDR_CFG_REG_VAL
+ u32 reg = 0;
+ u32 tmp = 0;
+
+ reg = qca_soc_reg_read(QCA_DDR_CFG_REG);
+
+ /* Always use page close policy */
+ reg = reg | QCA_DDR_CFG_PAGE_CLOSE_MASK;
+
+ /* CAS should be (2 * MEM_CAS) or (2 * MEM_CAS) + 1/2/3 */
+ tmp = 2 * mem_cas;
+ tmp = (tmp << QCA_DDR_CFG_CAS_3LSB_SHIFT) & QCA_DDR_CFG_CAS_3LSB_MASK;
+ if (mem_cas > 3) {
+ tmp = tmp | QCA_DDR_CFG_CAS_MSB_MASK;
+ }
+
+ reg = reg & ~QCA_DDR_CFG_CAS_3LSB_MASK;
+ reg = reg | tmp;
+
+ /*
+ * Calculate rest of timing related values,
+ * always round up to closest integer
+ */
+
+ /* tMRD */
+ tmp = ((DDRx_tMRD_ns * ddr_clk) + 500) / 1000;
+ if (tmp > MAX_tMRD)
+ tmp = MAX_tMRD;
+
+ tmp = (tmp << QCA_DDR_CFG_TMRD_SHIFT) & QCA_DDR_CFG_TMRD_MASK;
+ reg = reg & ~QCA_DDR_CFG_TMRD_MASK;
+ reg = reg | tmp;
+
+ /* tRFC */
+ if (mem_type == RAM_MEMORY_TYPE_DDR2) {
+ tmp = ((DDR2_tRFC_ns * ddr_clk) + 500) / 1000;
+ } else {
+ tmp = ((DDR1_tRFC_ns * ddr_clk) + 500) / 1000;
+ }
+
+ if (tmp > MAX_tRFC)
+ tmp = MAX_tRFC;
+
+ tmp = (tmp << QCA_DDR_CFG_TRFC_SHIFT) & QCA_DDR_CFG_TRFC_MASK;
+ reg = reg & ~QCA_DDR_CFG_TRFC_MASK;
+ reg = reg | tmp;
+
+ /* tRRD */
+ tmp = ((DDRx_tRRD_ns * ddr_clk) + 500) / 1000;
+ if (tmp > MAX_tRRD)
+ tmp = MAX_tRRD;
+
+ tmp = (tmp << QCA_DDR_CFG_TRRD_SHIFT) & QCA_DDR_CFG_TRRD_MASK;
+ reg = reg & ~QCA_DDR_CFG_TRRD_MASK;
+ reg = reg | tmp;
+
+ /* tRP */
+ tmp = ((DDRx_tRP_ns * ddr_clk) + 500) / 1000;
+ if (tmp > MAX_tRP)
+ tmp = MAX_tRP;
+
+ tmp = (tmp << QCA_DDR_CFG_TRP_SHIFT) & QCA_DDR_CFG_TRP_MASK;
+ reg = reg & ~QCA_DDR_CFG_TRP_MASK;
+ reg = reg | tmp;
+
+ /* tRCD */
+ tmp = ((DDRx_tRCD_ns * ddr_clk) + 500) / 1000;
+ if (tmp > MAX_tRCD)
+ tmp = MAX_tRCD;
+
+ tmp = (tmp << QCA_DDR_CFG_TRCD_SHIFT) & QCA_DDR_CFG_TRCD_MASK;
+ reg = reg & ~QCA_DDR_CFG_TRCD_MASK;
+ reg = reg | tmp;
+
+ /* tRAS */
+ tmp = ((DDRx_tRAS_ns * ddr_clk) + 500) / 1000;
+ if (tmp > MAX_tRAS)
+ tmp = MAX_tRAS;
+
+ tmp = (tmp << QCA_DDR_CFG_TRAS_SHIFT) & QCA_DDR_CFG_TRAS_MASK;
+ reg = reg & ~QCA_DDR_CFG_TRAS_MASK;
+ reg = reg | tmp;
+
+ qca_soc_reg_write(QCA_DDR_CFG_REG, reg);
+#else
+ qca_soc_reg_write(QCA_DDR_CFG_REG, CONFIG_QCA_DDR_CFG_REG_VAL);
+#endif
+}
+
+/*
+ * Setup DDR_CONFIG2 register
+ */
+static inline void qca_dram_set_ddr_cfg2(u32 mem_cas,
+ u32 ddr_clk,
+ u32 mem_type,
+ u32 ddr_width)
+{
+#ifndef CONFIG_QCA_DDR_CFG2_REG_VAL
+ u32 reg = 0;
+ u32 tmp = 0;
+
+ reg = qca_soc_reg_read(QCA_DDR_CFG2_REG);
+
+ /* Enable CKE */
+ reg = reg | QCA_DDR_CFG2_CKE_MASK;
+
+ /* Gate open latency = 2 * MEM_CAS */
+ tmp = 2 * mem_cas;
+ tmp = (tmp << QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT)
+ & QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK;
+ reg = reg & ~QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK;
+ reg = reg | tmp;
+
+ /* tWTR */
+ if (mem_type == RAM_MEMORY_TYPE_DDR2) {
+ /* tWTR = 2 * WL + BL + 2 * max(tWTR/tCK, 2) */
+ tmp = 2 * (mem_cas + DDR_addit_lat - 1) + DDR_burst_len + 4;
+
+ if (ddr_clk >= 600)
+ tmp = tmp + 2;
+ } else {
+ /* tWTR = 2 + BL + (2 * tWTR/tCK) */
+ tmp = 2 + DDR_burst_len + (((DDRx_tWTR_ns * ddr_clk) + 500) / 1000);
+ }
+
+ if (tmp > MAX_tWTR)
+ tmp = MAX_tWTR;
+
+ tmp = (tmp << QCA_DDR_CFG2_TWTR_SHIFT) & QCA_DDR_CFG2_TWTR_MASK;
+ reg = reg & ~QCA_DDR_CFG2_TWTR_MASK;
+ reg = reg | tmp;
+
+ /* tRTP */
+ if (ddr_width == 32) {
+ tmp = DDR_burst_len;
+ } else {
+ tmp = MAX_tRTP;
+ }
+
+ tmp = (tmp << QCA_DDR_CFG2_TRTP_SHIFT) & QCA_DDR_CFG2_TRTP_MASK;
+ reg = reg & ~QCA_DDR_CFG2_TRTP_MASK;
+ reg = reg | tmp;
+
+ /* tRTW */
+ if (mem_type == RAM_MEMORY_TYPE_DDR2) {
+ /* tRTW = 2 * (RL + BL/2 + 1 -WL), RL = CL + AL, WL = RL - 1 */
+ tmp = DDR_burst_len + 4;
+ } else {
+ /* tRTW = 2 * (CL + BL/2) */
+ tmp = DDR_burst_len + (2 * mem_cas);
+ }
+
+ if (tmp > MAX_tRTW)
+ tmp = MAX_tRTW;
+
+ tmp = (tmp << QCA_DDR_CFG2_TRTW_SHIFT) & QCA_DDR_CFG2_TRTW_MASK;
+ reg = reg & ~QCA_DDR_CFG2_TRTW_MASK;
+ reg = reg | tmp;
+
+ /* tWR */
+ tmp = ((DDRx_tWR_ns * ddr_clk) + 500) / 1000;
+ if (tmp > MAX_tWR)
+ tmp = MAX_tWR;
+
+ tmp = (tmp << QCA_DDR_CFG2_TWR_SHIFT) & QCA_DDR_CFG2_TWR_MASK;
+ reg = reg & ~QCA_DDR_CFG2_TWR_MASK;
+ reg = reg | tmp;
+
+ /* Always use burst length = 8 and type: sequential */
+ tmp = (DDR_burst_len << QCA_DDR_CFG2_BURST_LEN_SHIFT)
+ & QCA_DDR_CFG2_BURST_LEN_MASK;
+ reg = reg & ~(QCA_DDR_CFG2_BURST_LEN_MASK
+ | QCA_DDR_CFG2_BURST_TYPE_MASK);
+ reg = reg | tmp;
+
+ qca_soc_reg_write(QCA_DDR_CFG2_REG, reg);
+#else
+ qca_soc_reg_write(QCA_DDR_CFG2_REG, CONFIG_QCA_DDR_CFG2_REG_VAL);
+#endif
+}
+
+/*
+ * Setup DDR2_CONFIG register (only for DDR2)
+ */
+static inline void qca_dram_set_ddr2_cfg(u32 mem_cas,
+ u32 ddr_clk)
+{
+#ifndef CONFIG_QCA_DDR_DDR2_CFG_REG_VAL
+ u32 reg = 0;
+ u32 tmp = 0;
+
+ reg = qca_soc_reg_read(QCA_DDR_DDR2_CFG_REG);
+
+ /* Enable DDR2 */
+ reg = reg | QCA_DDR_DDR2_CFG_DDR2_EN_MASK;
+
+ /* tFAW */
+ tmp = ((DDR2_tFAW_ns * ddr_clk) + 500) / 1000;
+ if (tmp > MAX_tFAW)
+ tmp = MAX_tFAW;
+
+ tmp = (tmp << QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT)
+ & QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK;
+ reg = reg & ~QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK;
+ reg = reg | tmp;
+
+ /* tWL */
+ tmp = (2 * mem_cas) - 3;
+
+ /* For some reason, odd value doesn't work on AR933x (FIXME) */
+ #if (SOC_TYPE & QCA_AR933X_SOC)
+ if (tmp % 2)
+ tmp = tmp - 1;
+ #endif
+
+ tmp = (tmp << QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT)
+ & QCA_DDR_DDR2_CFG_DDR2_TWL_MASK;
+ reg = reg & ~QCA_DDR_DDR2_CFG_DDR2_TWL_MASK;
+ reg = reg | tmp;
+
+ qca_soc_reg_write(QCA_DDR_DDR2_CFG_REG, reg);
+#else
+ qca_soc_reg_write(QCA_DDR_DDR2_CFG_REG, CONFIG_QCA_DDR_DDR2_CFG_REG_VAL);
+#endif
+}
+
+/*
+ * Enables DDR refresh and sets
+ * refresh period based on XTAL
+ */
+static inline void qca_dram_set_en_refresh(void)
+{
+ /*
+ * Enable DDR refresh and setup refresh period:
+ * 1. We assume 7.8 us maximum average period refresh interval
+ * 2. 7.8 us ~= 0.1282 MHz
+ * 3. For 25 MHz XTAL: (25 / 0.1282) ~= 195
+ * 4. For 40 MHz XTAL: (40 / 0.1282) ~= 312
+ */
+ if (qca_xtal_is_40mhz()) {
+ qca_soc_reg_write(QCA_DDR_REFRESH_REG,
+ QCA_DDR_REFRESH_EN_MASK
+ | (312 << QCA_DDR_REFRESH_PERIOD_SHIFT));
+ } else {
+ qca_soc_reg_write(QCA_DDR_REFRESH_REG,
+ QCA_DDR_REFRESH_EN_MASK
+ | (195 << QCA_DDR_REFRESH_PERIOD_SHIFT));
+ }
+}
+
+/*
+ * Initial DRAM configuration
+ */
+void qca_dram_init(void)
+{
+ u32 ahb_clk, cpu_clk, ddr_clk, mem_type, tmp_clk;
+ u32 cas_lat, ddr_width, reg, tmp, wr_recovery;
+
+ mem_type = qca_dram_type();
+
+ qca_sys_clocks(&cpu_clk, &ddr_clk, &ahb_clk, NULL, NULL);
+ cpu_clk = cpu_clk / 1000000;
+ ddr_clk = ddr_clk / 1000000;
+ ahb_clk = ahb_clk / 1000000;
+
+ /* Set CAS based on clock, but allow to set static value */
+#ifndef CONFIG_BOARD_DRAM_CAS_LATENCY
+ if (mem_type == RAM_MEMORY_TYPE_DDR1) {
+ if (ddr_clk <= 266) {
+ cas_lat = 2;
+ } else {
+ cas_lat = 3;
+ }
+ } else {
+ if (ddr_clk <= 400) {
+ cas_lat = 3;
+ } else if (ddr_clk <= 533) {
+ cas_lat = 4;
+ } else if (ddr_clk <= 666) {
+ cas_lat = 5;
+ } else if (ddr_clk <= 800) {
+ cas_lat = 6;
+ } else {
+ cas_lat = 7;
+ }
+ }
+#else
+ cas_lat = CONFIG_BOARD_DRAM_CAS_LATENCY;
+#endif
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ /* AR933x supports only 16-bit memory */
+ ddr_width = 16;
+ qca_soc_reg_write(QCA_DDR_RD_DATA_THIS_CYCLE_REG, 0xFF);
+#else
+ /* For other WiSoCs we can determine DDR width, based on bootstrap */
+ ddr_width = qca_dram_ddr_width();
+
+ if (ddr_width == 32) {
+ /* For 32-bit clear HALF_WIDTH and set VEC = 0xFF */
+ qca_soc_reg_read_clear(QCA_DDR_CTRL_CFG_REG,
+ QCA_DDR_CTRL_CFG_HALF_WIDTH_MASK);
+
+ qca_soc_reg_write(QCA_DDR_RD_DATA_THIS_CYCLE_REG, 0xFF);
+ } else {
+ qca_soc_reg_read_set(QCA_DDR_CTRL_CFG_REG,
+ QCA_DDR_CTRL_CFG_HALF_WIDTH_MASK);
+
+ qca_soc_reg_write(QCA_DDR_RD_DATA_THIS_CYCLE_REG, 0xFFFF);
+ }
+
+ /* If DDR_CLK < 2 * AHB_CLK, set DDR FSM wait control to 0xA24 */
+ if (ddr_clk < (2 * ahb_clk))
+ qca_soc_reg_write(QCA_DDR_FSM_WAIT_CTRL_REG, 0xA24);
+#endif
+
+ /*
+ * CPU/DDR sync mode only when we don't use
+ * fractional multipliers in PLL/clocks config
+ */
+ tmp = 0;
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ reg = qca_soc_reg_read(QCA_PLL_CPU_PLL_DITHER_FRAC_REG);
+ reg = (reg & QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK)
+ >> QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT;
+
+ if (reg)
+ tmp = 1;
+#else
+ reg = qca_soc_reg_read(QCA_PLL_CPU_PLL_DITHER_REG);
+ reg = (reg & QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK)
+ >> QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT;
+
+ if (reg)
+ tmp = 1;
+
+ reg = qca_soc_reg_read(QCA_PLL_DDR_PLL_DITHER_REG);
+ reg = (reg & QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK)
+ >> QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT;
+
+ if (reg)
+ tmp = 1;
+#endif
+
+ if (!tmp && (cpu_clk == ddr_clk)) {
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ qca_soc_reg_read_set(QCA_DDR_TAP_CTRL_3_REG, (1 << 8));
+#else
+ qca_soc_reg_read_set(QCA_DDR_CTRL_CFG_REG,
+ QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_MASK);
+#endif
+ } else {
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ qca_soc_reg_read_clear(QCA_DDR_TAP_CTRL_3_REG, (1 << 8));
+#else
+ qca_soc_reg_read_clear(QCA_DDR_CTRL_CFG_REG,
+ QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_MASK);
+#endif
+ }
+
+ /* Check if clock is not too low for our "safe" timing values */
+ tmp_clk = ddr_clk;
+ if (mem_type == RAM_MEMORY_TYPE_DDR1) {
+ if (tmp_clk < DDR1_timing_clk_max)
+ tmp_clk = DDR1_timing_clk_max;
+ } else {
+ if (tmp_clk < DDR2_timing_clk_max)
+ tmp_clk = DDR2_timing_clk_max;
+ }
+
+ /* Enable DDR2 */
+ if (mem_type == RAM_MEMORY_TYPE_DDR2) {
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ qca_dram_set_ddr2_cfg(cas_lat, tmp_clk);
+#else
+ qca_soc_reg_write(QCA_DDR_CTRL_CFG_REG,
+ QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_MASK);
+
+ qca_dram_set_ddr2_cfg(cas_lat, tmp_clk);
+#endif
+
+ }
+
+ /* Setup DDR timing related registers */
+ qca_dram_set_ddr_cfg(cas_lat, tmp_clk, mem_type);
+ qca_dram_set_ddr_cfg2(cas_lat, tmp_clk, mem_type, ddr_width);
+
+ /* Precharge all */
+ qca_dram_force_preall();
+
+ if (mem_type == RAM_MEMORY_TYPE_DDR2) {
+ /* Setup target EMR2 and EMR3 */
+ qca_dram_set_emr2(_ddr_sdram_emr2_val(0, 0, 0));
+ qca_dram_set_emr3(0);
+ }
+
+ /* Enable and reset DLL */
+ qca_dram_set_emr(_ddr_sdram_emr_val(0, 1, 0, 0, 0, 0));
+ qca_dram_set_mr(_ddr_sdram_mr_val(0, 0, 1, 0));
+
+ /* Precharge all, 2x auto refresh */
+ qca_dram_force_preall();
+
+ qca_dram_force_aref();
+ qca_dram_force_aref();
+
+ if (mem_type == RAM_MEMORY_TYPE_DDR2) {
+ /* Setup target MR */
+ wr_recovery = ((DDRx_tWR_ns * tmp_clk) + 1000) / 2000;
+ qca_dram_set_mr(_ddr_sdram_mr_val(0, cas_lat, 0, wr_recovery));
+
+ /* OCD calibration, target EMR (nDQS disable, weak strength) */
+ qca_dram_set_emr(
+ _ddr_sdram_emr_val(0, 1, DDR_SDRAM_EMR_OCD_DEFAULT_VAL, 1, 0, 0));
+
+ qca_dram_set_emr(
+ _ddr_sdram_emr_val(0, 1, DDR_SDRAM_EMR_OCD_EXIT_VAL, 1, 0, 0));
+ } else {
+ /* Setup target MR */
+ qca_dram_set_mr(_ddr_sdram_mr_val(0, cas_lat, 0, 0));
+ }
+
+ /* Enable DDR refresh and setup refresh period */
+ qca_dram_set_en_refresh();
+
+ /*
+ * At this point memory should be fully configured,
+ * so we can perform delay tap controller tune.
+ */
+ qca_ddr_tap_tune(ddr_width);
+}
--- /dev/null
+/*
+ * This file contains code used for lowlevel initialization
+ * of GPIO, on supported Qualcomm/Atheros platforms
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <soc/qca_soc_common.h>
+
+/*
+ * Low level GPIO initialization:
+ * 1. Setup JTAG (disable by default, but allow to keep it up)
+ * 2. Disable all clock observation on platforms which support this
+ * 3. Setup UART lines
+ * 4. Setup all configured GPIO inputs/outputs
+ * 5. Set desired init values on configured GPIOs
+ *
+ * The user may use several config definitions here:
+ * 1. CONFIG_QCA_KEEP_JTAG_ENABLED
+ * - if defined, JTAG will not be disabled
+ * 2. CONFIG_QCA_GPIO_MASK_OUTPUTS,
+ * CONFIG_QCA_GPIO_MASK_INPUTS
+ * - bitmask for GPIOs to be set as outputs and inputs
+ * 3. CONFIG_QCA_GPIO_LSUART_TX,
+ * CONFIG_QCA_GPIO_LSUART_RX
+ * - GPIO number for LSUART TX (10 if empty) and RX line (9 if empty)
+ * 4. CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI,
+ * CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO
+ * - bitmask for outputs initialized to high and low state at start
+ * 5. CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI,
+ * CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ * - bitmask for GPIO driven LEDs, used only in leds_on/leds_off functions,
+ * GPIO numbers for LEDs MUST be defined also in CONFIG_QCA_GPIO_MASK_OUTPUTS!
+ *
+ * TODO:
+ * 1. Allow to select LS, HS, both or none UART type
+ * on platforms which support both
+ * 2. Allow to select clocks observation on chosen pins
+ * 3. Ethernet/WLAN LEDs configuration
+ * 4. Enable JTAG on request (button?)
+ */
+
+/* Sanity check for GPIO driven LEDs */
+#if (defined(CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI) || \
+ defined(CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO)) && \
+ !defined(CONFIG_QCA_GPIO_MASK_OUTPUTS)
+ #error "GPIO numbers for LEDs must be included in CONFIG_QCA_GPIO_MASK_OUTPUTS!"
+#endif
+
+#if (defined(CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI) && \
+ !(CONFIG_QCA_GPIO_MASK_OUTPUTS & CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI)) || \
+ (defined(CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO) && \
+ !(CONFIG_QCA_GPIO_MASK_OUTPUTS & CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO))
+ #error "GPIO numbers for LEDs must be included in CONFIG_QCA_GPIO_MASK_OUTPUTS!"
+#endif
+
+.globl lowlevel_gpio_init
+.type lowlevel_gpio_init, @function
+.align 4
+.text
+.ent lowlevel_gpio_init
+
+lowlevel_gpio_init:
+/*
+ * =========================
+ * Low level GPIO setup for:
+ * 1. AR934x
+ * 2. QCA953x
+ * 3. QCA955x
+ * =========================
+ */
+#if (SOC_TYPE & QCA_AR934X_SOC) || \
+ (SOC_TYPE & QCA_QCA953X_SOC) || \
+ (SOC_TYPE & QCA_QCA955X_SOC)
+
+ /* Sanity check for JTAG pins (GPIO 0~3) */
+ #if defined(CONFIG_SKIP_LOWLEVEL_INIT) || \
+ defined(CONFIG_QCA_KEEP_JTAG_ENABLED)
+ #if (defined(CONFIG_QCA_GPIO_MASK_INPUTS) && (CONFIG_QCA_GPIO_MASK_INPUTS & 0xF)) || \
+ (defined(CONFIG_QCA_GPIO_MASK_OUTPUTS) && (CONFIG_QCA_GPIO_MASK_OUTPUTS & 0xF))
+ #error "Cannot use JTAG and GPIO0~3 at the same time!"
+ #endif
+ #endif
+
+ /*
+ * Disable:
+ * 1. By default JTAG (bit 1 set)
+ * 2. All clock observation (bits 2~9 reset)
+ */
+ li t8, QCA_GPIO_FUNC_REG
+ #if defined(CONFIG_SKIP_LOWLEVEL_INIT) || \
+ defined(CONFIG_QCA_KEEP_JTAG_ENABLED)
+ li t9, 0x0
+ #else
+ li t9, QCA_GPIO_FUNC_JTAG_DIS_MASK
+ #endif
+ sw t9, 0(t8)
+
+ /* By default use GPIO10 for TX and GPIO9 for RX */
+ #ifndef CONFIG_QCA_GPIO_LSUART_TX
+ #define CONFIG_QCA_GPIO_LSUART_TX 10
+ #endif
+
+ #ifndef CONFIG_QCA_GPIO_LSUART_RX
+ #define CONFIG_QCA_GPIO_LSUART_RX 9
+ #endif
+
+ #define CONFIG_QCA_GPIO_MASK_LSUART_TX (1 << CONFIG_QCA_GPIO_LSUART_TX)
+ #define CONFIG_QCA_GPIO_MASK_LSUART_RX (1 << CONFIG_QCA_GPIO_LSUART_RX)
+
+ #define CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT \
+ (8 * (CONFIG_QCA_GPIO_LSUART_TX - \
+ ((CONFIG_QCA_GPIO_LSUART_TX / 4) * 4)))
+
+ /* Some sanity checks for LS UART GPIO lines */
+ #if (CONFIG_QCA_GPIO_LSUART_TX >= QCA_GPIO_COUNT) || \
+ (CONFIG_QCA_GPIO_LSUART_RX >= QCA_GPIO_COUNT)
+ #error "LSUART GPIO numbers for TX and/or RX lines are not correct!"
+ #endif
+
+ #if (CONFIG_QCA_GPIO_LSUART_TX == CONFIG_QCA_GPIO_LSUART_RX)
+ #error "LSUART TX and RX GPIO numbers cannot be the same!"
+ #endif
+
+ /*
+ * Do not allow to use LSUART TX/RX lines
+ * as regular GPIO inputs/outputs at the same time
+ */
+ #if defined(CONFIG_QCA_GPIO_MASK_INPUTS) || defined(CONFIG_QCA_GPIO_MASK_OUTPUTS)
+ #if (CONFIG_QCA_GPIO_MASK_INPUTS & CONFIG_QCA_GPIO_MASK_LSUART_TX) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & CONFIG_QCA_GPIO_MASK_LSUART_RX) || \
+ (CONFIG_QCA_GPIO_MASK_OUTPUTS & CONFIG_QCA_GPIO_MASK_LSUART_TX) || \
+ (CONFIG_QCA_GPIO_MASK_OUTPUTS & CONFIG_QCA_GPIO_MASK_LSUART_RX)
+ #error "Cannot use LSUART lines as regular GPIOs at the same time!"
+ #endif
+ #endif
+
+ /* Setup GPIO number for LSUART RX in GPIO IN MUX */
+ li t8, QCA_GPIO_IN_EN0_REG
+ lw t9, 0(t8)
+ and t9, t9, ~(QCA_GPIO_IN_EN0_LSUART_RXD_MASK)
+ or t9, t9, (CONFIG_QCA_GPIO_LSUART_RX << QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT)
+ sw t9, 0(t8)
+
+ /*
+ * Target regular GPIO and LSUART TX line configuration
+ *
+ * After selecting GPIO as output in GPIO_OE register,
+ * the line will be set to low, which causes signal
+ * toggle on pulled-up lines
+ *
+ * To prevent this, we need to first setup desired
+ * init state for all GPIOs configured as outputs
+ * and then setup them as outputs
+ */
+ li t8, QCA_GPIO_OUT_REG
+ lw t9, 0(t8)
+ #ifdef CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI
+ or t9, t9, (CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI | \
+ CONFIG_QCA_GPIO_MASK_LSUART_TX)
+ #else
+ or t9, t9, CONFIG_QCA_GPIO_MASK_LSUART_TX
+ #endif
+ #ifdef CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO
+ and t9, t9, ~(CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO)
+ #endif
+ sw t9, 0(t8)
+
+ /*
+ * TODO: what with default LSUART TX line?
+ *
+ * Some of QCA WiSoCs have GPIOs for LSUART TX/RX lines
+ * set by default (10 and 9 respectively) on reset and
+ * others do not (ex. QCA953x?).
+ *
+ * Because of that we can use more than one line
+ * for TX signal if we setup other than default
+ * GPIO for it, without change default GPIO
+ * function.
+ *
+ * Confirmed on AR9344 with LSUART TX set on
+ * GPIO1 and GPIO10 at the same time
+ */
+
+ /*
+ * Set GPIO mode on desired lines and GPIO number
+ * for LSUART TX using GPIO_OUT_FUNCTIONX registers:
+ * - 0 ~ 3 -> GPIO_OUT_FUNCTION0 (mask: 0x00000F)
+ * - 4 ~ 7 -> GPIO_OUT_FUNCTION1 (mask: 0x0000F0)
+ * - 8 ~ 11 -> GPIO_OUT_FUNCTION2 (mask: 0x000F00)
+ * - 12 ~ 15 -> GPIO_OUT_FUNCTION3 (mask: 0x00F000)
+ * - 16 ~ 19 -> GPIO_OUT_FUNCTION4 (mask: 0x0F0000)
+ * - 20 ~ 23 -> GPIO_OUT_FUNCTION5 (mask: 0xF00000)
+ */
+ #if defined(CONFIG_QCA_GPIO_MASK_OUTPUTS) || \
+ defined(CONFIG_QCA_GPIO_MASK_INPUTS) || \
+ defined(CONFIG_QCA_GPIO_MASK_LSUART_TX)
+
+ /* GPIO_OUT_FUNCTION0 (GPIO 0~3) */
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & 0x00000F) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & 0x00000F) || \
+ (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0x00000F)
+ li t8, QCA_GPIO_OUT_FUNC0_REG
+ lw t9, 0(t8)
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO0) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO0)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO0_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO1) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO1)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO1_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO2) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO2)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO2_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO3) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO3)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO3_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0x00000F)
+ and t9, t9, ~(0xFF << CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ or t9, t9, (QCA_GPIO_OUT_MUX_LSUART_TXD_VAL << \
+ CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ #endif
+ sw t9, 0(t8)
+ #endif
+
+ /* GPIO_OUT_FUNCTION1 (GPIO 4~7) */
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & 0x0000F0) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & 0x0000F0) || \
+ (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0x0000F0)
+ li t8, QCA_GPIO_OUT_FUNC1_REG
+ lw t9, 0(t8)
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO4) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO4)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO4_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO5) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO5)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO5_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO6) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO6)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO6_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO7) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO7)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO7_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0x0000F0)
+ and t9, t9, ~(0xFF << CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ or t9, t9, (QCA_GPIO_OUT_MUX_LSUART_TXD_VAL << \
+ CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ #endif
+ sw t9, 0(t8)
+ #endif
+
+ /* GPIO_OUT_FUNCTION2 (GPIO 8~11) */
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & 0x000F00) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & 0x000F00) || \
+ (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0x000F00)
+ li t8, QCA_GPIO_OUT_FUNC2_REG
+ lw t9, 0(t8)
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO8) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO8)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO8_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO9) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO9)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO9_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO10) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO10)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO10_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO11) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO11)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO11_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0x000F00)
+ and t9, t9, ~(0xFF << CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ or t9, t9, (QCA_GPIO_OUT_MUX_LSUART_TXD_VAL << \
+ CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ #endif
+ sw t9, 0(t8)
+ #endif
+
+ /* GPIO_OUT_FUNCTION3 (GPIO 12~15) */
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & 0x00F000) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & 0x00F000) || \
+ (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0x00F000)
+ li t8, QCA_GPIO_OUT_FUNC3_REG
+ lw t9, 0(t8)
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO12) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO12)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO12_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO13) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO13)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO13_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO14) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO14)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO14_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO15) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO15)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO15_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0x00F000)
+ and t9, t9, ~(0xFF << CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ or t9, t9, (QCA_GPIO_OUT_MUX_LSUART_TXD_VAL << \
+ CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ #endif
+ sw t9, 0(t8)
+ #endif
+
+ /* GPIO_OUT_FUNCTION4 (GPIO 16~19) */
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & 0x0F0000) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & 0x0F0000) || \
+ (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0x0F0000)
+ li t8, QCA_GPIO_OUT_FUNC4_REG
+ lw t9, 0(t8)
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO16) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO16)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO16_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO17) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO17)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO17_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO18) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO18)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO18_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO19) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO19)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO19_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0x0F0000)
+ and t9, t9, ~(0xFF << CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ or t9, t9, (QCA_GPIO_OUT_MUX_LSUART_TXD_VAL << \
+ CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ #endif
+ sw t9, 0(t8)
+ #endif
+
+ /* GPIO_OUT_FUNCTION5 (GPIO 20~23) */
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & 0xF00000) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & 0xF00000) || \
+ (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0xF00000)
+ li t8, QCA_GPIO_OUT_FUNC5_REG
+ lw t9, 0(t8)
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO20) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO20)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO20_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO21) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO21)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO21_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO22) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO22)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO22_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO23) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO23)
+ and t9, t9, ~(QCA_GPIO_OUT_FUNCX_GPIO23_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_LSUART_TX & 0xF00000)
+ and t9, t9, ~(0xFF << CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ or t9, t9, (QCA_GPIO_OUT_MUX_LSUART_TXD_VAL << \
+ CONFIG_QCA_GPIO_LSUART_TX_FUNCX_SHIFT)
+ #endif
+ sw t9, 0(t8)
+ #endif
+
+ /*
+ * And finally, setup GPIO type (out/in)
+ * in GPIO_OE register for all configured
+ * regular GPIOs and LSUART TX/RX lines
+ */
+ li t8, QCA_GPIO_OE_REG
+ lw t9, 0(t8)
+ #ifdef CONFIG_QCA_GPIO_MASK_OUTPUTS
+ and t9, t9, ~(CONFIG_QCA_GPIO_MASK_OUTPUTS | \
+ CONFIG_QCA_GPIO_MASK_LSUART_TX)
+ #else
+ and t9, t9, ~(CONFIG_QCA_GPIO_MASK_LSUART_TX)
+ #endif
+ #ifdef CONFIG_QCA_GPIO_MASK_INPUTS
+ or t9, t9, (CONFIG_QCA_GPIO_MASK_INPUTS | CONFIG_QCA_GPIO_MASK_LSUART_RX)
+ #else
+ or t9, t9, CONFIG_QCA_GPIO_MASK_LSUART_RX
+ #endif
+ sw t9, 0(t8)
+
+ #endif /* CONFIG_QCA_GPIO_MASK_OUTPUTS || CONFIG_QCA_GPIO_MASK_INPUTS || CONFIG_QCA_GPIO_MASK_LSUART_TX */
+
+#endif /* (SOC_TYPE & QCA_AR934X_SOC) || (SOC_TYPE & QCA_QCA953X_SOC) || (SOC_TYPE & QCA_QCA955X_SOC) */
+
+/*
+ * ===============================
+ * Low level GPIO setup for AR933x
+ * ===============================
+ */
+#if (SOC_TYPE & QCA_AR933X_SOC)
+
+ /* Sanity check for JTAG pins (GPIO 6~8) */
+ #if defined(CONFIG_SKIP_LOWLEVEL_INIT) || \
+ defined(CONFIG_QCA_KEEP_JTAG_ENABLED)
+ #if (defined(CONFIG_QCA_GPIO_MASK_INPUTS) && (CONFIG_QCA_GPIO_MASK_INPUTS & 0x1C0)) || \
+ (defined(CONFIG_QCA_GPIO_MASK_OUTPUTS) && (CONFIG_QCA_GPIO_MASK_OUTPUTS & 0x1C0))
+ #error "Cannot use JTAG and GPIO6~8 at the same time!"
+ #endif
+ #endif
+
+ /*
+ * On AR933x HSUART TX/RX lines are connected to
+ * GPIO10 and GPIO9 respectively, so do not allow
+ * to use those GPIOs as regular at the same time
+ */
+ #if defined(CONFIG_QCA_GPIO_MASK_INPUTS) || defined(CONFIG_QCA_GPIO_MASK_OUTPUTS)
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & (GPIO9 | GPIO10)) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & (GPIO9 | GPIO10))
+ #error "Cannot use HSUART lines as regular GPIOs at the same time!"
+ #endif
+ #endif
+
+ /*
+ * Workaround for hang issue,
+ * from original Atheros (Q)SDK:
+ *
+ * "Hornet 1.1 currently need a reset
+ * once we boot to let the resetb has
+ * enough time to stable, so that
+ * trigger reset at 1st boot".
+ *
+ * Read one 4 byte value from SRAM base address and compare it with
+ * known magic number (0x12345678 here), if it's the same, it means
+ * that this is not first boot and we can continue. Otherwise, make
+ * full chip reset (it's not power reset, SRAM data will survive).
+ *
+ * We need it here as it's first custom asm code executed in start{_bootstrap).S
+ *
+ * TODO: FIXME!
+ */
+first_boot:
+ li t8, 0xBD000000
+ lw t9, 0(t8)
+ li t7, 0x12345678
+ sw t7, 0(t8)
+ bne t9, t7, full_reset
+ nop
+
+ b gpio_setup
+ nop
+
+full_reset:
+ li t8, QCA_RST_RESET_REG
+ lw t9, 0(t8)
+ or t9, t9, (QCA_RST_RESET_FULL_CHIP_RST_MASK | \
+ QCA_RST_RESET_DDR_RST_MASK)
+ sw t9, 0(t8)
+ nop
+ nop
+ nop
+ nop
+
+ /*
+ * GPIO configuration, using GPIO_FUNCTION_1 register:
+ * 1. Disable JTAG by default
+ * 2. Enable HSUART on GPIO9 and GPIO10 by default
+ * 3. Disable HSUART RTS/CTS on GPIO11/12 if needed
+ * 4. Disable selected Ethernet switch LEDs if needed
+ */
+gpio_setup:
+ li t8, QCA_GPIO_FUNC_1_REG
+ lw t9, 0(t8)
+ #if defined(CONFIG_SKIP_LOWLEVEL_INIT) || \
+ defined(CONFIG_QCA_KEEP_JTAG_ENABLED)
+ and t9, t9, ~(QCA_GPIO_FUNC_1_JTAG_DIS_MASK)
+ or t9, t9, QCA_GPIO_FUNC_1_UART_EN_MASK
+ #else
+ or t9, t9, (QCA_GPIO_FUNC_1_JTAG_DIS_MASK | \
+ QCA_GPIO_FUNC_1_UART_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & (GPIO11 | GPIO12)) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & (GPIO11 | GPIO12))
+ and t9, t9, ~(QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO13) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO13)
+ and t9, t9, ~(QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO14) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO14)
+ and t9, t9, ~(QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO15) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO15)
+ and t9, t9, ~(QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO16) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO16)
+ and t9, t9, ~(QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO17) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO17)
+ and t9, t9, ~(QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO9)
+ and t9, t9, ~(QCA_GPIO_FUNC_1_SPI_CS_EN1_MASK)
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO10)
+ and t9, t9, ~(QCA_GPIO_FUNC_1_SPI_CS_EN2_MASK)
+ #endif
+ /* From datasheet: bit 15 should be written with 1 */
+ or t9, t9, ((1 << 15) | \
+ QCA_GPIO_FUNC_1_SPI_EN_MASK)
+ sw t9, 0(t8)
+
+ /* Enable regular GPIO function on GPIO26 and/or GPIO27 if needed */
+ #if defined(CONFIG_QCA_GPIO_MASK_OUTPUTS) || \
+ defined(CONFIG_QCA_GPIO_MASK_INPUTS)
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & (GPIO26 | GPIO27)) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & (GPIO26 | GPIO27))
+ li t8, QCA_RST_BOOTSTRAP_REG
+ lw t9, 0(t8)
+ or t9, t9, QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_MASK
+ sw t9, 0(t8)
+ #endif
+ #endif
+
+ /* Enable regular GPIO function on GPIO11 and/or GPIO12 if needed */
+ #if defined(CONFIG_QCA_GPIO_MASK_OUTPUTS) || \
+ defined(CONFIG_QCA_GPIO_MASK_INPUTS)
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & (GPIO11 | GPIO12)) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & (GPIO11 | GPIO12))
+ li t8, QCA_GPIO_FUNC_2_REG
+ lw t9, 0(t8)
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO11) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO11)
+ or t9, t9, QCA_GPIO_FUNC_2_JUMPSTART_DIS_MASK
+ #endif
+ #if (CONFIG_QCA_GPIO_MASK_OUTPUTS & GPIO12) || \
+ (CONFIG_QCA_GPIO_MASK_INPUTS & GPIO12)
+ or t9, t9, QCA_GPIO_FUNC_2_WPS_DIS_MASK
+ #endif
+ sw t9, 0(t8)
+ #endif
+ #endif
+
+ /* Setup init states on requested GPIO lines */
+ li t8, QCA_GPIO_OUT_REG
+ lw t9, 0(t8)
+ #ifdef CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI
+ or t9, t9, CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI
+ #endif
+ #ifdef CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO
+ and t9, t9, ~(CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO)
+ #endif
+ sw t9, 0(t8)
+
+ /* Setup GPIOs in OE register */
+ #if defined(CONFIG_QCA_GPIO_MASK_OUTPUTS) || \
+ defined(CONFIG_QCA_GPIO_MASK_INPUTS)
+ li t8, QCA_GPIO_OE_REG
+ lw t9, 0(t8)
+ #ifdef CONFIG_QCA_GPIO_MASK_OUTPUTS
+ or t9, t9, CONFIG_QCA_GPIO_MASK_OUTPUTS
+ #endif
+ #ifdef CONFIG_QCA_GPIO_MASK_INPUTS
+ and t9, t9, ~(CONFIG_QCA_GPIO_MASK_INPUTS)
+ #endif
+ sw t9, 0(t8)
+ #endif
+
+#endif /* (SOC_TYPE & QCA_AR933X_SOC) */
+
+/*
+ * Custom, GPIO related code for boards should go here,
+ * after initial/basic GPIO configuration
+ */
+
+ jr ra
+ nop
+
+.end lowlevel_gpio_init
+
+/*
+ * Set all predefined GPIO driven LEDs ON
+ */
+
+.globl all_led_on
+.type all_led_on, @function
+.align 4
+.text
+.ent all_led_on
+
+all_led_on:
+#if defined(CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI) || \
+ defined(CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO)
+ li t8, QCA_GPIO_OUT_REG
+ lw t9, 0(t8)
+ #ifdef CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
+ or t9, t9, CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
+ #endif
+ #ifdef CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ and t9, t9, ~(CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO)
+ #endif
+ sw t9, 0(t8)
+#else
+ nop
+#endif
+
+ jr ra
+ nop
+
+.end all_led_on
+
+/*
+ * Set all predefined GPIO driven LEDs OFF
+ */
+
+.globl all_led_off
+.type all_led_off, @function
+.align 4
+.text
+.ent all_led_off
+
+all_led_off:
+#if defined(CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI) || \
+ defined(CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO)
+ li t8, QCA_GPIO_OUT_REG
+ lw t9, 0(t8)
+ #ifdef CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
+ and t9, t9, ~(CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI)
+ #endif
+ #ifdef CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ or t9, t9, CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ #endif
+ sw t9, 0(t8)
+#else
+ nop
+#endif
+
+ jr ra
+ nop
+
+.end all_led_off
--- /dev/null
+/*
+ * Qualcomm/Atheros High-Speed UART driver
+ *
+ * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2014 Mantas Pucka <mantas@8devices.com>
+ * Copyright (C) 2008-2010 Atheros Communications Inc.
+ *
+ * Values for UART_SCALE and UART_STEP:
+ * https://www.mail-archive.com/openwrt-devel@lists.openwrt.org/msg22371.html
+ *
+ * Partially based on:
+ * Linux/drivers/tty/serial/ar933x_uart.c
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/addrspace.h>
+#include <soc/qca_soc_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* HS UART baudrate = (REF_CLK / (CLOCK_SCALE + 1)) * (CLOCK_STEP * (1 / 2^17)) */
+static u32 qca_hsuart_get_baud(u32 ref_clk, u32 uart_scale, u32 uart_step)
+{
+ u64 baudrate;
+ u32 div;
+
+ div = (uart_scale + 1) * (2 << 16);
+
+ baudrate = (ref_clk * uart_step) + (div / 2);
+ baudrate = baudrate / div;
+
+ return (u32)baudrate;
+}
+
+static void qca_hsuart_get_scale_step(u32 baudrate,
+ u32 *uart_scale,
+ u32 *uart_step)
+{
+ s32 diff;
+ u32 ref_clk;
+ u32 tscale;
+ u64 tstep;
+ s32 min_diff;
+
+ *uart_scale = 0;
+ *uart_step = 0;
+
+ min_diff = baudrate;
+
+ if (qca_xtal_is_40mhz() == 1) {
+ ref_clk = VAL_40MHz;
+ } else {
+ ref_clk = VAL_25MHz;
+ }
+
+ for (tscale = 0; tscale < QCA_HSUART_CLK_SCALE_MAX_VAL; tscale++) {
+ tstep = baudrate * (tscale + 1);
+ tstep = tstep * (2 << 16);
+ tstep = tstep / ref_clk;
+
+ if (tstep > QCA_HSUART_CLK_STEP_MAX_VAL)
+ break;
+
+ diff = qca_hsuart_get_baud(ref_clk, tscale, tstep) - baudrate;
+
+ if (diff < 0)
+ diff = -1 * diff;
+
+ if (diff < min_diff) {
+ min_diff = diff;
+ *uart_scale = tscale;
+ *uart_step = tstep;
+ }
+ }
+}
+
+void serial_setbrg(void)
+{
+ u32 uart_clock;
+ u32 uart_scale;
+ u32 uart_step;
+
+ qca_hsuart_get_scale_step(gd->baudrate, &uart_scale, &uart_step);
+
+ uart_clock = (uart_scale << QCA_HSUART_CLK_SCALE_SHIFT);
+ uart_clock |= (uart_step << QCA_HSUART_CLK_STEP_SHIFT);
+
+ qca_soc_reg_write(QCA_HSUART_CLK_REG, uart_clock);
+}
+
+int serial_init(void)
+{
+ u32 uart_cs;
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ /*
+ * Set GPIO10 (UART_SO) as output and enable UART,
+ * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+ */
+ qca_soc_reg_read_set(QCA_GPIO_OE_REG, GPIO10);
+
+ qca_soc_reg_read_set(QCA_GPIO_FUNC_1_REG,
+ QCA_GPIO_FUNC_1_UART_EN_MASK | BIT(15));
+#else
+ #error "Missing GPIO configuration for HS UART"
+#endif
+
+ /*
+ * High-Speed UART controller configuration:
+ * - no DMA
+ * - no interrupt
+ * - no parity
+ * - DCE mode
+ * - no flow control
+ * - set RX ready oride
+ * - set TX ready oride
+ */
+ uart_cs = (0 << QCA_HSUART_CS_DMA_EN_SHIFT) |
+ (0 << QCA_HSUART_CS_HOST_INT_EN_SHIFT) |
+ (1 << QCA_HSUART_CS_RX_READY_ORIDE_SHIFT) |
+ (1 << QCA_HSUART_CS_TX_READY_ORIDE_SHIFT) |
+ (QCA_HSUART_CS_PAR_MODE_NO_VAL << QCA_HSUART_CS_PAR_MODE_SHIFT) |
+ (QCA_HSUART_CS_IFACE_MODE_DCE_VAL << QCA_HSUART_CS_IFACE_MODE_SHIFT) |
+ (QCA_HSUART_CS_FLOW_MODE_NO_VAL << QCA_HSUART_CS_FLOW_MODE_SHIFT);
+
+ qca_soc_reg_write(QCA_HSUART_CS_REG, uart_cs);
+
+ serial_setbrg();
+
+ return 0;
+}
+
+void serial_putc(const char c)
+{
+ u32 uart_data;
+
+ if (c == '\n')
+ serial_putc('\r');
+
+ /* Wait for FIFO */
+ do {
+ uart_data = qca_soc_reg_read(QCA_HSUART_DATA_REG);
+ } while (((uart_data & QCA_HSUART_DATA_TX_CSR_MASK)
+ >> QCA_HSUART_DATA_TX_CSR_SHIFT) == 0);
+
+ /* Put data in buffer and set CSR bit */
+ uart_data = (u32)c | (1 << QCA_HSUART_DATA_TX_CSR_SHIFT);
+
+ qca_soc_reg_write(QCA_HSUART_DATA_REG, uart_data);
+}
+
+int serial_getc(void)
+{
+ u32 uart_data;
+
+ while (!serial_tstc())
+ ;
+
+ uart_data = qca_soc_reg_read(QCA_HSUART_DATA_REG);
+
+ qca_soc_reg_write(QCA_HSUART_DATA_REG,
+ (1 << QCA_HSUART_DATA_RX_CSR_SHIFT));
+
+ return (uart_data & QCA_HSUART_DATA_TX_RX_DATA_MASK);
+}
+
+int serial_tstc(void)
+{
+ u32 uart_data = qca_soc_reg_read(QCA_HSUART_DATA_REG);
+
+ return ((uart_data & QCA_HSUART_DATA_RX_CSR_MASK)
+ >> QCA_HSUART_DATA_RX_CSR_SHIFT);
+}
+
+void serial_puts(const char *s)
+{
+ while (*s)
+ serial_putc(*s++);
+}
--- /dev/null
+/*
+ * Qualcomm/Atheros Low-Speed UART driver
+ *
+ * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2008-2010 Atheros Communications Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/addrspace.h>
+#include <soc/qca_soc_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void serial_setbrg(void)
+{
+ u32 div;
+
+ /*
+ * TODO: prepare list of supported range of baudrate values
+ * For 40 MHz ref_clk, successfully tested up to 1152000 on AR9344
+ *
+ * TODO: support 100 MHz reference clocks on AR934x and QCA955x
+ */
+
+ /* Round to closest, final baudrate = ref_clk / (16 * div) */
+ if (qca_xtal_is_40mhz() == 1) {
+ div = (VAL_40MHz + (8 * gd->baudrate)) / (16 * gd->baudrate);
+ } else {
+ div = (VAL_25MHz + (8 * gd->baudrate)) / (16 * gd->baudrate);
+ }
+
+ /* Set DLAB bit in LCR register unlocks DLL/DLH registers */
+ qca_soc_reg_read_set(QCA_LSUART_LCR_REG, QCA_LSUART_LCR_DLAB_MASK);
+
+ /* Write div into DLL and DLH registers */
+ qca_soc_reg_write(QCA_LSUART_DLL_REG, (div & 0xFF));
+ qca_soc_reg_write(QCA_LSUART_DLH_REG, ((div >> 8) & 0xFF));
+
+ /* Clear DLAB bit in LCR register */
+ qca_soc_reg_read_clear(QCA_LSUART_LCR_REG, QCA_LSUART_LCR_DLAB_MASK);
+}
+
+int serial_init(void)
+{
+ u32 uart_lcr;
+
+ serial_setbrg();
+
+ /* No interrupt */
+ qca_soc_reg_write(QCA_LSUART_IER_REG, 0x0);
+
+ /* No FIFO/DMA */
+ qca_soc_reg_write(QCA_LSUART_FCR_REG, 0x0);
+
+ /*
+ * Low-Speed UART controller configuration:
+ * - data: 8bits
+ * - stop: 1bit
+ * - parity: no
+ */
+ uart_lcr = (QCA_LSUART_LCR_CLS_8BIT_VAL << QCA_LSUART_LCR_CLS_SHIFT)
+ | (0 << QCA_LSUART_LCR_STOP_SHIFT)
+ | (0 << QCA_LSUART_LCR_PEN_SHIFT);
+
+ qca_soc_reg_write(QCA_LSUART_LCR_REG, uart_lcr);
+
+ return 0;
+}
+
+void serial_putc(const char c)
+{
+ u32 line_status;
+
+ if (c == '\n')
+ serial_putc('\r');
+
+ /* Wait for empty THR */
+ do {
+ line_status = qca_soc_reg_read(QCA_LSUART_LSR_REG);
+ } while (((line_status & QCA_LSUART_LSR_THRE_MASK)
+ >> QCA_LSUART_LSR_THRE_SHIFT) == 0);
+
+ /* Put data in THR */
+ qca_soc_reg_write(QCA_LSUART_THR_REG, (u32)c);
+}
+
+int serial_getc(void)
+{
+ while (!serial_tstc())
+ ;
+
+ /* Get data from RBR */
+ return (qca_soc_reg_read(QCA_LSUART_RBR_REG)
+ & QCA_LSUART_RBR_RBR_MASK);
+}
+
+int serial_tstc(void)
+{
+ u32 uart_data = qca_soc_reg_read(QCA_LSUART_LSR_REG);
+
+ /* Check data ready bit */
+ return ((uart_data & QCA_LSUART_LSR_DR_MASK)
+ >> QCA_LSUART_LSR_DR_SHIFT);
+}
+
+void serial_puts(const char *s)
+{
+ while (*s)
+ serial_putc(*s++);
+}
--- /dev/null
+/*
+ * Qualcomm/Atheros Serial SPI FLASH driver utilizing SHIFT registers
+ *
+ * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include <config.h>
+#include <common.h>
+#include <flash.h>
+#include <asm/addrspace.h>
+#include <soc/qca_soc_common.h>
+
+/* Use CS0 by default */
+static u32 qca_sf_cs_mask = QCA_SPI_SHIFT_CNT_CHNL_CS0_MASK;
+
+static inline void qca_sf_spi_en(void)
+{
+ qca_soc_reg_write(QCA_SPI_FUNC_SEL_REG, 1);
+}
+
+static inline void qca_sf_spi_di(void)
+{
+ qca_soc_reg_write(QCA_SPI_SHIFT_CNT_REG, 0);
+ qca_soc_reg_write(QCA_SPI_FUNC_SEL_REG, 0);
+}
+
+static inline u32 qca_sf_shift_in(void)
+{
+ return qca_soc_reg_read(QCA_SPI_SHIFT_DATAIN_REG);
+}
+
+/*
+ * Shifts out 'bits_cnt' bits from 'data_out' value
+ * If 'terminate' is zero, then CS is not driven high at end of transaction
+ */
+static void qca_sf_shift_out(u32 data_out, u32 bits_cnt, u32 terminate)
+{
+ u32 reg_val = 0;
+
+ qca_soc_reg_write(QCA_SPI_SHIFT_CNT_REG, 0);
+
+ /* Data to shift out */
+ qca_soc_reg_write(QCA_SPI_SHIFT_DATAOUT_REG, data_out);
+
+ reg_val = reg_val | bits_cnt
+ | qca_sf_cs_mask
+ | QCA_SPI_SHIFT_CNT_SHIFT_EN_MASK;
+
+ if (terminate)
+ reg_val = reg_val | QCA_SPI_SHIFT_CNT_TERMINATE_MASK;
+
+ /* Enable shifting in/out */
+ qca_soc_reg_write(QCA_SPI_SHIFT_CNT_REG, reg_val);
+}
+
+static u32 qca_sf_sfdp_bfpt_dword(u32 ptp_offset, u32 dword_num)
+{
+ u32 data_out;
+
+ data_out = (SPI_FLASH_CMD_SFDP << 24);
+ data_out = data_out | (ptp_offset + ((dword_num - 1) * 4));
+
+ qca_sf_shift_out(data_out, 32, 0);
+ qca_sf_shift_out(0x0, 40, 1);
+
+ return cpu_to_le32(qca_sf_shift_in());
+}
+
+static inline void qca_sf_write_en(void)
+{
+ qca_sf_shift_out(SPI_FLASH_CMD_WREN, 8, 1);
+}
+
+static inline void qca_sf_write_di(void)
+{
+ qca_sf_shift_out(SPI_FLASH_CMD_WRDI, 8, 1);
+}
+
+static void qca_sf_bank_to_cs_mask(u32 bank)
+{
+ switch (bank) {
+ case 0:
+ qca_sf_cs_mask = QCA_SPI_SHIFT_CNT_CHNL_CS0_MASK;
+ break;
+ case 1:
+ qca_sf_cs_mask = QCA_SPI_SHIFT_CNT_CHNL_CS1_MASK;
+ break;
+ case 2:
+ qca_sf_cs_mask = QCA_SPI_SHIFT_CNT_CHNL_CS2_MASK;
+ break;
+ default:
+ qca_sf_cs_mask = QCA_SPI_SHIFT_CNT_CHNL_CS0_MASK;
+ break;
+ }
+}
+
+/* Poll status register and wait till busy bit is cleared */
+static void qca_sf_busy_wait(void)
+{
+ volatile u32 data_in;
+
+ /* Poll status register continuously (keep CS low during whole loop) */
+ qca_sf_shift_out(SPI_FLASH_CMD_RDSR, 8, 0);
+
+ do {
+ qca_sf_shift_out(0x0, 8, 0);
+ data_in = qca_sf_shift_in() & 0x1;
+ } while (data_in);
+
+ /* Disable CS chip */
+ qca_sf_shift_out(0x0, 0, 1);
+}
+
+/* Bulk (whole) FLASH erase */
+void qca_sf_bulk_erase(u32 bank)
+{
+ qca_sf_bank_to_cs_mask(bank);
+ qca_sf_spi_en();
+ qca_sf_write_en();
+ qca_sf_shift_out(SPI_FLASH_CMD_ES_ALL, 8, 1);
+ qca_sf_busy_wait();
+ qca_sf_spi_di();
+}
+
+/* Erase one sector at provided address */
+u32 qca_sf_sect_erase(u32 bank, u32 address, u32 sect_size, u8 erase_cmd)
+{
+ u32 data_out;
+
+ qca_sf_bank_to_cs_mask(bank);
+
+ /* TODO: 4-byte addressing support */
+ data_out = (erase_cmd << 24) | (address & 0x00FFFFFF);
+
+ qca_sf_spi_en();
+ qca_sf_write_en();
+ qca_sf_shift_out(data_out, 32, 1);
+ qca_sf_busy_wait();
+ qca_sf_spi_di();
+
+ return 0;
+}
+
+/* Writes 'length' bytes at 'address' using page program command */
+void qca_sf_write_page(u32 bank, u32 address, u32 length, u8 *data)
+{
+ u32 data_out, i;
+
+ qca_sf_bank_to_cs_mask(bank);
+
+ data_out = SPI_FLASH_CMD_PP << 24;
+ data_out = data_out | (address & 0x00FFFFFF);
+
+ qca_sf_spi_en();
+ qca_sf_write_en();
+ qca_sf_shift_out(data_out, 32, 0);
+
+ length--;
+ for (i = 0; i < length; i++) {
+ qca_sf_shift_out(*(data + i), 8, 0);
+ }
+
+ /* Last byte and terminate */
+ qca_sf_shift_out(*(data + i), 8, 1);
+
+ qca_sf_busy_wait();
+ qca_sf_spi_di();
+}
+
+/*
+ * Checks if FLASH supports SFDP and if yes, tries to get following data:
+ * - chip size
+ * - erase sector size
+ * - erase command
+ */
+u32 qca_sf_sfdp_info(u32 bank,
+ u32 *flash_size,
+ u32 *sect_size,
+ u8 *erase_cmd)
+{
+ u8 buffer[12];
+ u8 ss = 0, ec = 0;
+ u32 data_in, i;
+ u32 ptp_length, ptp_offset;
+
+ qca_sf_bank_to_cs_mask(bank);
+
+ qca_sf_spi_en();
+
+ /* Shift out SFDP command with 0x0 address */
+ qca_sf_shift_out(SPI_FLASH_CMD_SFDP << 24, 32, 0);
+
+ /* 1 dummy byte and 4 bytes for SFDP signature */
+ qca_sf_shift_out(0x0, 40, 0);
+ data_in = qca_sf_shift_in();
+
+ if (cpu_to_le32(data_in) != SPI_FLASH_SFDP_SIGN) {
+ qca_sf_shift_out(0x0, 0, 1);
+ qca_sf_spi_di();
+ return 1;
+ }
+
+ /*
+ * We need to check SFDP and first parameter header major versions,
+ * because we support now only v1, exit also if ptp_length is < 9
+ */
+ for (i = 0; i < 3; i++) {
+ qca_sf_shift_out(0x0, 32, 0);
+ data_in = qca_sf_shift_in();
+
+ memcpy(&buffer[i * 4], &data_in, 4);
+ }
+
+ ptp_length = buffer[7];
+ ptp_offset = buffer[8] | (buffer[10] << 16) | (buffer[9] << 8);
+
+ if (buffer[1] != 1 || buffer[6] != 1 || ptp_length < 9) {
+ qca_sf_shift_out(0x0, 0, 1);
+ qca_sf_spi_di();
+ return 1;
+ }
+
+ qca_sf_shift_out(0x0, 0, 1);
+
+ /* FLASH density (2nd DWORD in JEDEC basic FLASH parameter table) */
+ data_in = qca_sf_sfdp_bfpt_dword(ptp_offset, 2);
+
+ /* We do not support >= 4 Gbits chips */
+ if ((data_in & (1 << 31)) || data_in == 0)
+ return 1;
+
+ /* TODO: it seems that density is 0-based, like max. available address? */
+ if (flash_size != NULL)
+ *flash_size = ((data_in & 0x7FFFFFFF) + 1) / 8;
+
+ /* Sector/block erase size and command: 8th and 9th DWORD */
+ data_in = qca_sf_sfdp_bfpt_dword(ptp_offset, 8);
+ memcpy(&buffer[0], &data_in, 4);
+
+ data_in = qca_sf_sfdp_bfpt_dword(ptp_offset, 9);
+ memcpy(&buffer[4], &data_in, 4);
+
+ /* We prefer bigger erase sectors */
+ for (i = 0; i < 7; i += 2) {
+ if ((buffer[i + 1] != 0) && buffer[i + 1] > ss) {
+ ss = buffer[i + 1];
+ ec = buffer[i];
+ }
+ }
+
+ if (ss == 0)
+ return 1;
+
+ if (sect_size != NULL)
+ *sect_size = 1 << ss;
+
+ if (erase_cmd != NULL)
+ *erase_cmd = ec;
+
+ qca_sf_spi_di();
+
+ return 0;
+}
+
+/* Returns JEDEC ID for selected FLASH chip */
+u32 qca_sf_jedec_id(u32 bank)
+{
+ u32 data_in;
+
+ qca_sf_bank_to_cs_mask(bank);
+
+ qca_sf_spi_en();
+ qca_sf_shift_out(SPI_FLASH_CMD_JEDEC << 24, 32, 1);
+ data_in = qca_sf_shift_in();
+ qca_sf_spi_di();
+
+ return (data_in & 0x00FFFFFF);
+}
/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:GPL-2.0
*/
#include <common.h>
#include <command.h>
#include <asm/mipsregs.h>
-#if defined(CONFIG_AR7100)
-#include <asm/addrspace.h>
-#include <ar7100_soc.h>
-#endif
-
-#if defined(CONFIG_AR7240)
-#include <asm/addrspace.h>
-#include <ar7240_soc.h>
-#endif
+extern void dcache_flush_range(u32 a, u32 end);
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
-#if defined(CONFIG_AR7100)
- for(;;){
- ar7100_reg_wr(AR7100_RESET, (AR7100_RESET_FULL_CHIP | AR7100_RESET_DDR));
- }
-#elif defined(CONFIG_AR7240)
-#ifndef COMPRESSED_UBOOT
- fprintf(stdout, "\nResetting the board...\n");
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ printf("Resetting the board...");
milisecdelay(500);
-#endif /* #ifndef COMPRESSED_UBOOT */
- for(;;){
- #ifdef CONFIG_WASP
- if(ar7240_reg_rd(AR7240_REV_ID) & 0xf){
- ar7240_reg_wr(AR7240_RESET, (AR7240_RESET_FULL_CHIP | AR7240_RESET_DDR));
- } else {
- /*
- * WAR for full chip reset spi vs. boot-rom selection
- * bug in wasp 1.0
- */
- ar7240_reg_wr(AR7240_GPIO_OE, ar7240_reg_rd(AR7240_GPIO_OE) & (~(1 << 17)));
- }
- #else
- ar7240_reg_wr(AR7240_RESET, (AR7240_RESET_FULL_CHIP | AR7240_RESET_DDR));
- #endif
- }
-#endif
-#ifndef COMPRESSED_UBOOT
- fprintf(stderr, "\n*** ERROR: RESET FAILED! ***\n");
-#endif /* #ifndef COMPRESSED_UBOOT */
- return(0);
-}
-extern void dcache_flush_range(u32 a, u32 end);
+ full_reset();
-void flush_cache(ulong start_addr, ulong size){
+ /* After full chip reset we should not reach next step... */
+ printf("\n## Error: RESET FAILED!\n");
+
+ return 0;
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
u32 end, a;
a = start_addr & ~(CFG_CACHELINE_SIZE - 1);
dcache_flush_range(a, end);
}
+
+/*
+ * Read CPU type and put its name into buffer
+ * For now only 24/74Kc are supported as all
+ * supported SOCs are based on one of them
+ */
+void cpu_name(char *name)
+{
+ u32 cpu_id = read_c0_prid();
+
+ if (name == NULL)
+ return;
+
+ switch (cpu_id & PRID_IMP_MASK) {
+ case PRID_IMP_24K:
+ sprintf(name, "MIPS 24Kc");
+ break;
+ case PRID_IMP_74K:
+ sprintf(name, "MIPS 74Kc");
+ break;
+ default:
+ sprintf(name, "MIPS Unknown");
+ break;
+ }
+}
/*
- * Startup Code for MIPS32 CPU-core
+ * Startup Code for MIPS32 CPU-core
*
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2013 Qualcomm Atheros, Inc.
+ * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:GPL-2.0
*/
-
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
-#include <ar7240_soc.h>
-
-#define ATH_SPI_CLOCK 0x1F000004
+#include <soc/qca_soc_common.h>
-#define RVECENT(f,n) \
- b f; nop
+#define RVECENT(f,n) \
+ b f; nop
-#define XVECENT(f,bev) \
- b f ; \
- li k0,bev
+#define XVECENT(f,bev) \
+ b f; \
+ li k0, bev
.set noreorder
#ifdef COMPRESSED_UBOOT
#endif
.globl _start
.text
-_start:
+_start:
#ifndef COMPRESSED_UBOOT
RVECENT(reset,0) /* U-boot entry point */
- RVECENT(reset,1) /* software reboot */
+ RVECENT(reset,1) /* Software reboot */
RVECENT(romReserved,2)
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
- /* We hope there are no more reserved vectors!
+ /*
+ * We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
.align 4
reset:
-
-#if defined(CONFIG_WASP_SUPPORT)
-
- // Disable JTAG (bit 1 set) and ALL clock observation (bit 2~9 reset)
- // Do not do this in RAM version!
- li a1, AR934X_GPIO_FUNCTION
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- li v1, 0x2
-#else
- li v1, 0x0
-#endif
- sw v1, 0(a1)
-
-#if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1)
- /*
- * LEDs and buttons GPIOs on WDR3600/WDR43x0 v1:
- *
- * 11 => USB1 LED
- * 12 => USB2 LED
- * 13 => WLAN2G
- * 14 => SYS
- * 15 => QSS
- * 21 => USB2 POWER (active high)
- * 22 => USB1 POWER (active high)
- *
- * 16 => Reset button
- * 17 => Wi-Fi ON/OFF switch
- *
- * All OUT GPIOs are active LOW if not stated otherwise
- */
-
- // GPIO Init
- li a1, AR934X_GPIO_OE
- lw v1, 0(a1)
- // Set GPIOs 11~15 and 21~22 as outputs
- and v1, v1, 0xFF9F07FF
- // Set GPIOs 16~17 as inputs
- or v1, v1, 0x30000
- sw v1, 0(a1)
-
- // Set GPIO function for GPIO 11
- li a1, AR934X_GPIO_OUT_FUNCTION2
- lw v1, 0(a1)
- and v1, v1, 0x00FFFFFF
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 12~15
- li a1, AR934X_GPIO_OUT_FUNCTION3
- li v1, 0x0
- sw v1, 0(a1)
-
- // Turn on power on both USB
- li a1, AR934X_GPIO_SET
- li v1, 0x600000
- sw v1, 0(a1)
-
- // Turn off all LEDs
- li a1, AR934X_GPIO_SET
- li v1, 0xF800
- sw v1, 0(a1)
-
-#elif defined(CONFIG_FOR_TPLINK_WDR3500_V1)
- /*
- * LEDs and buttons GPIOs on WDR3500 v1:
- *
- * 11 => USB LED
- * 12 => USB POWER (active high)
- * 13 => WLAN2G
- * 14 => SYS
- * 15 => QSS
- * 18 => WAN
- * 19 => LAN1
- * 20 => LAN2
- * 21 => LAN3
- * 22 => LAN4
- *
- * 16 => Reset button
- * 17 => Wi-Fi ON/OFF switch
- *
- * All OUT GPIOs are active LOW if not stated otherwise
- */
-
- // GPIO Init
- li a1, AR934X_GPIO_OE
- lw v1, 0(a1)
- // Set GPIOs 11~15 and 18~22 as outputs
- and v1, v1, 0xFF8307FF
- // Set GPIOs 16~17 as inputs
- or v1, v1, 0x30000
- sw v1, 0(a1)
-
- // Set GPIO function for GPIO 11
- li a1, AR934X_GPIO_OUT_FUNCTION2
- lw v1, 0(a1)
- and v1, v1, 0x00FFFFFF
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 12~15
- li a1, AR934X_GPIO_OUT_FUNCTION3
- li v1, 0x0
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 18~19
- li a1, AR934X_GPIO_OUT_FUNCTION4
- lw v1, 0(a1)
- and v1, v1, 0xFFFF
- sw v1, 0(a1)
-
- // Turn on power on USB
- li a1, AR934X_GPIO_SET
- li v1, 0x1000
- sw v1, 0(a1)
-
- // Turn off all LEDs
- li a1, AR934X_GPIO_SET
- li v1, 0x7CF800
- sw v1, 0(a1)
-
-#elif defined(CONFIG_FOR_TPLINK_WR841N_V8)
- /*
- * LEDs and buttons GPIOs on WR841N/D v8:
- *
- * 12 => LAN4
- * 13 => WLAN
- * 14 => SYS
- * 15 => QSS
- * 18 => WAN
- * 19 => LAN1
- * 20 => LAN2
- * 21 => LAN3
- *
- * 16 => Wi-Fi ON/OFF switch
- * 17 => Reset button
- *
- * All OUT GPIOs are active LOW if not stated otherwise
- */
-
- // GPIOs init
- li a1, AR934X_GPIO_OE
- lw v1, 0(a1)
- // Set GPIOs 12~15 and 18~21 as outputs
- and v1, v1, 0xFFC30FFF
- // Set GPIOs 16~17 as inputs
- or v1, v1, 0x30000
- sw v1, 0(a1)
-
- // Set gpio function for GPIOs 12~15
- li a1, AR934X_GPIO_OUT_FUNCTION3
- li v1, 0x0
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 18~19
- li a1, AR934X_GPIO_OUT_FUNCTION4
- lw v1, 0(a1)
- and v1, v1, 0xFFFF
- sw v1, 0(a1)
-
- // Turn off all LEDs
- li a1, AR934X_GPIO_SET
- li v1, 0x3CF000
- sw v1, 0(a1)
-
-#elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
- /*
- * LEDs and buttons GPIOs on MR3420 v2:
- *
- * 4 => USB Power (active high)
- * 11 => USB/3G LED
- * 12 => LAN4
- * 13 => WLAN
- * 14 => SYS
- * 15 => QSS
- * 18 => WAN
- * 19 => LAN1
- * 20 => LAN2
- * 21 => LAN3
- *
- * 16 => WPS button
- * 17 => Reset button
- *
- * All OUT GPIOs are active LOW if not stated otherwise
- */
-
- // GPIOs init
- li a1, AR934X_GPIO_OE
- lw v1, 0(a1)
- // Set GPIOs 4, 11~15 and 18~21 as outputs
- and v1, v1, 0xFFC307EF
- // Set GPIOs 16~17 as inputs
- or v1, v1, 0x30000
- sw v1, 0(a1)
-
- // Set GPIO function for GPIO 4
- li a1, AR934X_GPIO_OUT_FUNCTION1
- lw v1, 0(a1)
- and v1, v1, 0xFFFFFF00
- sw v1, 0(a1)
-
- // Set GPIO function for GPIO 11
- li a1, AR934X_GPIO_OUT_FUNCTION2
- lw v1, 0(a1)
- and v1, v1, 0x00FFFFFF
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 12~15
- li a1, AR934X_GPIO_OUT_FUNCTION3
- li v1, 0x0
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 18~19
- li a1, AR934X_GPIO_OUT_FUNCTION4
- lw v1, 0(a1)
- and v1, v1, 0xFFFF
- sw v1, 0(a1)
-
- // Turn on power on USB
- li a1, AR934X_GPIO_SET
- li v1, 0x10
- sw v1, 0(a1)
-
- // Turn off all LEDs
- li a1, AR934X_GPIO_SET
- li v1, 0x3CF800
- sw v1, 0(a1)
-
-#elif defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
- /*
- * LEDs and buttons GPIOs on WA830REv2 and WA801ND v2:
- *
- * 13 => WLAN
- * 14 => SYS
- * 15 => QSS
- * 18 => LAN
- *
- * 16 => Range Extender
- * 17 => Reset button
- *
- * All OUT GPIOs are active LOW if not stated otherwise
- */
-
- // GPIOs init
- li a1, AR934X_GPIO_OE
- lw v1, 0(a1)
- // Set GPIOs 13~15 and 18 as outputs
- and v1, v1, 0xFFFB1FFF
- // Set GPIOs 16~17 as inputs
- or v1, v1, 0x30000
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 13~15
- li a1, AR934X_GPIO_OUT_FUNCTION3
- lw v1, 0(a1)
- and v1, v1, 0xFF
- sw v1, 0(a1)
-
- // Set GPIO function for GPIO 18
- li a1, AR934X_GPIO_OUT_FUNCTION4
- lw v1, 0(a1)
- and v1, v1, 0xFF00FFFF
- sw v1, 0(a1)
-
- // Turn off all LEDs
- li a1, AR934X_GPIO_SET
- li v1, 0x4E000
- sw v1, 0(a1)
-
-#endif
-
-#endif /* #if defined(CONFIG_WASP_SUPPORT) */
-
/*
* Clearing CP0 registers - This is generally required for the MIPS-24k
* core used by Atheros.
*/
- mtc0 zero, $0
- mtc0 zero, $1
- mtc0 zero, $2
- mtc0 zero, $3
- mtc0 zero, $4
- mtc0 zero, $5
- mtc0 zero, $6
- mtc0 zero, $7
- mtc0 zero, $8
- mtc0 zero, $9
- mtc0 zero, $10
- mtc0 zero, $11
- li t0, 0x10000004
- mtc0 t0, $12
- mtc0 zero, $13
- mtc0 zero, $14
- mtc0 zero, $15
- mtc0 zero, $16
- mtc0 zero, $17
- mtc0 zero, $18
- mtc0 zero, $19
- mtc0 zero, $20
- mtc0 zero, $21
- mtc0 zero, $22
- mtc0 zero, $23
- mtc0 zero, $24
- mtc0 zero, $25
- mtc0 zero, $26
- mtc0 zero, $27
- mtc0 zero, $28
-
-#ifdef CONFIG_WASP_SUPPORT
- mtc0 zero, $29 # C0_TagHi
- mtc0 zero, $28, 2 # C0_DTagLo
- mtc0 zero, $29, 2 # C0_DTagHi
+ mtc0 zero, $0
+ mtc0 zero, $1
+ mtc0 zero, $2
+ mtc0 zero, $3
+ mtc0 zero, $4
+ mtc0 zero, $5
+ mtc0 zero, $6
+ mtc0 zero, $7
+ mtc0 zero, $8
+ mtc0 zero, $9
+ mtc0 zero, $10
+ mtc0 zero, $11
+ li t0, 0x10000004
+ mtc0 t0, $12
+ mtc0 zero, $13
+ mtc0 zero, $14
+ mtc0 zero, $15
+ mtc0 zero, $16
+ mtc0 zero, $17
+ mtc0 zero, $18
+ mtc0 zero, $19
+ mtc0 zero, $20
+ mtc0 zero, $21
+ mtc0 zero, $22
+ mtc0 zero, $23
+ mtc0 zero, $24
+ mtc0 zero, $25
+ mtc0 zero, $26
+ mtc0 zero, $27
+ mtc0 zero, $28
+
+#if (SOC_TYPE & QCA_AR934X_SOC) | \
+ (SOC_TYPE & QCA_QCA953X_SOC) | \
+ (SOC_TYPE & QCA_QCA955X_SOC) | \
+ (SOC_TYPE & QCA_QCA956X_SOC)
+ mtc0 zero, $29 # C0_TagHi
+ mtc0 zero, $28, 2 # C0_DTagLo
+ mtc0 zero, $29, 2 # C0_DTagHi
#endif
- /*
- * Clear watch registers.
- */
-
- mtc0 zero, CP0_WATCHLO
- mtc0 zero, CP0_WATCHHI
+ /* Clear watch registers */
+ mtc0 zero, CP0_WATCHLO
+ mtc0 zero, CP0_WATCHHI
/* STATUS register */
- mfc0 k0, CP0_STATUS
- li k1, ~ST0_IE
- and k0, k1
- mtc0 zero, CP0_CAUSE
- mtc0 k0, CP0_STATUS
+ mfc0 k0, CP0_STATUS
+ li k1, ~ST0_IE
+ and k0, k1
+ mtc0 zero, CP0_CAUSE
+ mtc0 k0, CP0_STATUS
/* CAUSE register */
- mtc0 zero, CP0_CAUSE
+ mtc0 zero, CP0_CAUSE
/* Init Timer */
- mtc0 zero, CP0_COUNT
- mtc0 zero, CP0_COMPARE
+ mtc0 zero, CP0_COUNT
+ mtc0 zero, CP0_COMPARE
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/* CONFIG0 register */
- li t0, CONF_CM_UNCACHED
- mtc0 t0, CP0_CONFIG
-#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
+ li t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+#endif
#endif /* #ifndef COMPRESSED_UBOOT */
- /* Initialize GOT pointer.*/
- bal 1f
+ /* Initialize GOT pointer.*/
+ bal 1f
nop
- .word _GLOBAL_OFFSET_TABLE_
- 1:
- move gp, ra
- lw t1, 0(ra)
- move gp, t1
+ .word _GLOBAL_OFFSET_TABLE_
+1:
+ move gp, ra
+ lw t1, 0(ra)
+ move gp, t1
#ifndef COMPRESSED_UBOOT
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#if defined(CONFIG_MACH_HORNET) && defined(CONFIG_HORNET_1_1_WAR)
-/**************************************************************************/
-/*
- * WAR: Hornet 1.1 currently need a reset once we boot to let the resetb has
- * enough time to stable, so that trigger reset at 1st boot, system team
- * is investigaing the issue, will remove in short
- */
-
-do_reset_normal:
-
- li t7, 0xbd000000
- lw t8, 0(t7) // t8 : value of 0xb8050024
- li t9, 0x12345678
- sw t9, 0(t7)
- bne t8, t9, do_reset // if 0xb8050024 == 0x19 , go to do_cpld
- nop
- b normal_path
-
-do_reset:
- li t7, 0xb806001c // load reset register 0x1806001c
- lw t8, 0(t7)
- li t9, 0x1000000 // bit24, fullchip reset
- or t8, t8, t9 // t8: set bit 18
- sw t8, 0(t7)
-
-normal_path:
-#endif /* CONFIG_MACH_HORNET */
-#endif
-
-/**************************************************************************/
-
- /* Initialize any external memory.
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) || defined(CONFIG_ATHEROS)
- la t9, lowlevel_init
- jalr t9
- nop
+ /* Lowlevel initialization of GPIO */
+ la t7, lowlevel_gpio_init
+ jalr t7
nop
-#if defined(CONFIG_MACH_HORNET)
- la t9, hornet_ddr_init
- jalr t9
- nop
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* Initialize any external memory */
+ la t9, lowlevel_init
+ jalr t9
nop
-#endif
- la t0, rel_start
- j t0
+ la t0, rel_start
+ j t0
nop
-#endif
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
rel_start:
-
-#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) || defined(CONFIG_ATHEROS)
- /* REMAP_DISABLE */
- li a0, KSEG1ADDR(ATH_SPI_CLOCK)
-#if defined(CONFIG_MACH_QCA955x)
- li t0, 0x246
-#elif defined(CONFIG_WASP_SUPPORT)
- li t0, 0x243
-#else
- // TODO: SPI clock from FLASH?
- // for now we will use divider = 10 ( (4+1)*2 )
- li t0, 0x44
-#endif
- sw t0, 0(a0)
-#endif
-
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- /* Initialize caches...
- */
- la t9, simple_mips_cache_reset
- jalr t9
+ /* Initialize caches... */
+ la t9, simple_mips_cache_reset
+ jalr t9
nop
- /* ... and enable them.
- */
-#if defined(CONFIG_WASP_SUPPORT) && !defined(CONFIG_ATH_NAND_BR)
- li t7, KSEG1ADDR(AR7240_REV_ID)
- lw t7, 0(t7)
- andi t9, t7, 0xf
- bne zero, t9, 1f
+ /* ... and enable them */
+#if (SOC_TYPE & QCA_AR934X_SOC)
+ li t7, KSEG1ADDR(QCA_RST_REVISION_ID_REG)
+ lw t7, 0(t7)
+ andi t9, t7, 0xf
+ bne zero, t9, 1f
nop
- li t0, CONF_CM_UNCACHED
- j 2f
+ li t0, CONF_CM_UNCACHED
+ j 2f
nop
#endif
-1: li t0, CONF_CM_CACHABLE_NONCOHERENT
-2: mtc0 t0, CP0_CONFIG
+1:
+ li t0, CONF_CM_CACHABLE_NONCOHERENT
+2:
+ mtc0 t0, CP0_CONFIG
-#if !defined(CONFIG_AR7100) && !defined(CONFIG_AR7240)
- /* Set up temporary stack.
- */
- li a0, CFG_INIT_SP_OFFSET
- la t9, mips_cache_lock
- jalr t9
+#if (SOC_TYPE & QCA_AR933X_SOC) || \
+ (SOC_TYPE & QCA_AR934X_SOC)
+ la t9, mips_cache_lock_24k
+ jalr t9
nop
#endif
-#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240)
- la t9, mips_cache_lock_24k
- jalr t9
- nop
-#endif
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* #ifndef COMPRESSED_UBOOT */
-#ifdef CONFIG_WASP_SUPPORT
- li t0, 0xbd007000 /* Setup stack in SRAM */
+#if (SOC_TYPE & QCA_AR934X_SOC) | \
+ (SOC_TYPE & QCA_QCA953X_SOC)
+ /* Setup stack in SRAM */
+ li t0, CONFIG_INIT_SRAM_SP_OFFSET
#else
- li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
+ li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
#endif
- la sp, 0(t0)
+ la sp, 0(t0)
- la t9, board_init_f
- j t9
+ la t9, board_init_f
+ j t9
nop
/*
* a1 = gd
* a2 = destination address
*/
- .globl relocate_code
- .ent relocate_code
+ .globl relocate_code
+ .ent relocate_code
+
relocate_code:
- move sp, a0 /* Set new stack pointer */
+ /* Set new stack pointer */
+ move sp, a0
- li t0, CFG_MONITOR_BASE
- la t3, in_ram
- lw t2, -12(t3) /* t2 <-- uboot_end_data */
- move t1, a2
+ li t0, CFG_MONITOR_BASE
+ la t3, in_ram
+ lw t2, -12(t3) /* t2 - uboot_end_data */
+ move t1, a2
/*
* Fix GOT pointer:
- *
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*/
- move t6, gp
- sub gp, CFG_MONITOR_BASE
- add gp, a2 /* gp now adjusted */
- sub t6, gp, t6 /* t6 <-- relocation offset */
+ move t6, gp
+ sub gp, CFG_MONITOR_BASE
+ add gp, a2 /* gp now adjusted */
+ sub t6, gp, t6 /* t6 - relocation offset */
/*
* t0 = source address
* t2 = source end address
*/
1:
- lw t3, 0(t0)
- sw t3, 0(t1)
- addu t0, 4
- ble t0, t2, 1b
- addu t1, 4 /* delay slot */
+ lw t3, 0(t0)
+ sw t3, 0(t1)
+ addu t0, 4
+ ble t0, t2, 1b
+ addu t1, 4 /* Delay slot */
- /* If caches were enabled, we would have to flush them here.
- */
+ /* If caches were enabled, we would have to flush them here */
- /* Jump to where we've relocated ourselves.
- */
- addi t0, a2, in_ram - _start
- j t0
+ /* Jump to where we've relocated ourselves */
+ addi t0, a2, in_ram - _start
+ j t0
nop
- .word uboot_end_data
- .word uboot_end
- .word num_got_entries
+ .word uboot_end_data
+ .word uboot_end
+ .word num_got_entries
in_ram:
- /* Now we want to update GOT.
- */
- lw t3, -4(t0) /* t3 <-- num_got_entries */
- addi t4, gp, 8 /* Skipping first two entries. */
- li t2, 2
+ /* Now we want to update GOT */
+ lw t3, -4(t0) /* t3 - num_got_entries */
+ addi t4, gp, 8 /* Skipping first two entries */
+ li t2, 2
1:
- lw t1, 0(t4)
- beqz t1, 2f
- add t1, t6
- sw t1, 0(t4)
+ lw t1, 0(t4)
+ beqz t1, 2f
+ add t1, t6
+ sw t1, 0(t4)
2:
- addi t2, 1
- blt t2, t3, 1b
- addi t4, 4 /* delay slot */
+ addi t2, 1
+ blt t2, t3, 1b
+ addi t4, 4 /* Delay slot */
- /* Clear BSS.
- */
- lw t1, -12(t0) /* t1 <-- uboot_end_data */
- lw t2, -8(t0) /* t2 <-- uboot_end */
- add t1, t6 /* adjust pointers */
- add t2, t6
-
- sub t1, 4
-1: addi t1, 4
- bltl t1, t2, 1b
- sw zero, 0(t1) /* delay slot */
-
- move a0, a1
- la t9, board_init_r
- j t9
- move a1, a2 /* delay slot */
-
- .end relocate_code
+ /* Clear BSS */
+ lw t1, -12(t0) /* t1 - uboot_end_data */
+ lw t2, -8(t0) /* t2 - uboot_end */
+ add t1, t6 /* Adjust pointers */
+ add t2, t6
+
+ sub t1, 4
+1:
+ addi t1, 4
+ bltl t1, t2, 1b
+ sw zero, 0(t1) /* Delay slot */
+
+ move a0, a1
+ la t9, board_init_r
+ j t9
+ move a1, a2 /* Delay slot */
+
+ .end relocate_code
#ifndef COMPRESSED_UBOOT
/* Exception handlers */
/*
- * Startup Code for MIPS32 CPU-core
+ * Startup Code for MIPS32 CPU-core
*
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2013 Qualcomm Atheros, Inc.
+ * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:GPL-2.0
*/
-
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
-#include <ar7240_soc.h>
-
-#define AR7100_SPI_CLOCK 0x1F000004
+#include <soc/qca_soc_common.h>
-#define RVECENT(f,n) \
- b f; nop
+#define RVECENT(f,n) \
+ b f; nop
-#define XVECENT(f,bev) \
- b f ; \
- li k0,bev
+#define XVECENT(f,bev) \
+ b f; \
+ li k0, bev
.set noreorder
.globl _start_bootstrap
.text
+
_start_bootstrap:
- RVECENT(reset,0) /* U-boot entry point */
- RVECENT(reset,1) /* software reboot */
+ RVECENT(reset,0) /* U-boot entry point */
+ RVECENT(reset,1) /* Software reboot */
RVECENT(romReserved,2)
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
- /* We hope there are no more reserved vectors!
+ /*
+ * We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
+
.align 4
reset:
-
-#if defined(CONFIG_WASP_SUPPORT)
-
- // Disable JTAG (bit 1 set) and ALL clock observation (bit 2~9 reset)
- li a1, AR934X_GPIO_FUNCTION
- li v1, 0x2
- sw v1, 0(a1)
-
-#if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1)
- /*
- * LEDs and buttons GPIOs on WDR3600/WDR43x0 v1:
- *
- * 11 => USB1 LED
- * 12 => USB2 LED
- * 13 => WLAN2G
- * 14 => SYS
- * 15 => QSS
- * 21 => USB2 POWER (active high)
- * 22 => USB1 POWER (active high)
- *
- * 16 => Reset button
- * 17 => Wi-Fi ON/OFF switch
- *
- * All OUT GPIOs are active LOW if not stated otherwise
- */
-
- // GPIO Init
- li a1, AR934X_GPIO_OE
- lw v1, 0(a1)
- // Set GPIOs 11~15 and 21~22 as outputs
- and v1, v1, 0xFF9F07FF
- // Set GPIOs 16~17 as inputs
- or v1, v1, 0x30000
- sw v1, 0(a1)
-
- // Set GPIO function for GPIO 11
- li a1, AR934X_GPIO_OUT_FUNCTION2
- lw v1, 0(a1)
- and v1, v1, 0x00FFFFFF
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 12~15
- li a1, AR934X_GPIO_OUT_FUNCTION3
- li v1, 0x0
- sw v1, 0(a1)
-
- // Turn on power on both USB
- li a1, AR934X_GPIO_SET
- li v1, 0x600000
- sw v1, 0(a1)
-
- // Turn on all LEDs
- li a1, AR934X_GPIO_CLEAR
- li v1, 0xF800
- sw v1, 0(a1)
-
- // Wait for a while, for leds bootup blink
- li a1, 0
- li v1, 0x70000
-
-1:
- addi a1, a1, 1
- bne a1, v1, 1b
- nop
-
- // Turn off all LEDs
- li a1, AR934X_GPIO_SET
- li v1, 0xF800
- sw v1, 0(a1)
-
-#elif defined(CONFIG_FOR_TPLINK_WDR3500_V1)
- /*
- * LEDs and buttons GPIOs on WDR3500 v1:
- *
- * 11 => USB LED
- * 12 => USB POWER (active high)
- * 13 => WLAN2G
- * 14 => SYS
- * 15 => QSS
- * 18 => WAN
- * 19 => LAN1
- * 20 => LAN2
- * 21 => LAN3
- * 22 => LAN4
- *
- * 16 => Reset button
- * 17 => Wi-Fi ON/OFF switch
- *
- * All OUT GPIOs are active LOW if not stated otherwise
- */
-
- // GPIO Init
- li a1, AR934X_GPIO_OE
- lw v1, 0(a1)
- // Set GPIOs 11~15 and 18~22 as outputs
- and v1, v1, 0xFF8307FF
- // Set GPIOs 16~17 as inputs
- or v1, v1, 0x30000
- sw v1, 0(a1)
-
- // Set GPIO function for GPIO 11
- li a1, AR934X_GPIO_OUT_FUNCTION2
- lw v1, 0(a1)
- and v1, v1, 0x00FFFFFF
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 12~15
- li a1, AR934X_GPIO_OUT_FUNCTION3
- li v1, 0x0
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 18~19
- li a1, AR934X_GPIO_OUT_FUNCTION4
- lw v1, 0(a1)
- and v1, v1, 0xFFFF
- sw v1, 0(a1)
-
- // Turn on power on USB
- li a1, AR934X_GPIO_SET
- li v1, 0x1000
- sw v1, 0(a1)
-
- // Turn off all LEDs
- li a1, AR934X_GPIO_SET
- li v1, 0x7CF800
- sw v1, 0(a1)
-
-#elif defined(CONFIG_FOR_TPLINK_WR841N_V8)
- /*
- * LEDs and buttons GPIOs on WR841N/D v8:
- *
- * 12 => LAN4
- * 13 => WLAN
- * 14 => SYS
- * 15 => QSS
- * 18 => WAN
- * 19 => LAN1
- * 20 => LAN2
- * 21 => LAN3
- *
- * 16 => Wi-Fi ON/OFF switch
- * 17 => Reset button
- *
- * All OUT GPIOs are active LOW if not stated otherwise
- */
-
- // GPIOs init
- li a1, AR934X_GPIO_OE
- lw v1, 0(a1)
- // Set GPIOs 12~15 and 18~21 as outputs
- and v1, v1, 0xFFC30FFF
- // Set GPIOs 16~17 as inputs
- or v1, v1, 0x30000
- sw v1, 0(a1)
-
- // Set gpio function for GPIOs 12~15
- li a1, AR934X_GPIO_OUT_FUNCTION3
- li v1, 0x0
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 18~19
- li a1, AR934X_GPIO_OUT_FUNCTION4
- lw v1, 0(a1)
- and v1, v1, 0xFFFF
- sw v1, 0(a1)
-
- // Turn off all LEDs
- li a1, AR934X_GPIO_SET
- li v1, 0x3CF000
- sw v1, 0(a1)
-
-#elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
- /*
- * LEDs and buttons GPIOs on MR3420 v2:
- *
- * 4 => USB Power (active high)
- * 11 => USB/3G LED
- * 12 => LAN4
- * 13 => WLAN
- * 14 => SYS
- * 15 => QSS
- * 18 => WAN
- * 19 => LAN1
- * 20 => LAN2
- * 21 => LAN3
- *
- * 16 => WPS button
- * 17 => Reset button
- *
- * All OUT GPIOs are active LOW if not stated otherwise
- */
-
- // GPIOs init
- li a1, AR934X_GPIO_OE
- lw v1, 0(a1)
- // Set GPIOs 4, 11~15 and 18~21 as outputs
- and v1, v1, 0xFFC307EF
- // Set GPIOs 16~17 as inputs
- or v1, v1, 0x30000
- sw v1, 0(a1)
-
- // Set GPIO function for GPIO 4
- li a1, AR934X_GPIO_OUT_FUNCTION1
- lw v1, 0(a1)
- and v1, v1, 0xFFFFFF00
- sw v1, 0(a1)
-
- // Set GPIO function for GPIO 11
- li a1, AR934X_GPIO_OUT_FUNCTION2
- lw v1, 0(a1)
- and v1, v1, 0x00FFFFFF
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 12~15
- li a1, AR934X_GPIO_OUT_FUNCTION3
- li v1, 0x0
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 18~19
- li a1, AR934X_GPIO_OUT_FUNCTION4
- lw v1, 0(a1)
- and v1, v1, 0xFFFF
- sw v1, 0(a1)
-
- // Turn on power on USB
- li a1, AR934X_GPIO_SET
- li v1, 0x10
- sw v1, 0(a1)
-
- // Turn off all LEDs
- li a1, AR934X_GPIO_SET
- li v1, 0x3CF800
- sw v1, 0(a1)
-
-#elif defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
- /*
- * LEDs and buttons GPIOs on WA830REv2 and WA801ND v2:
- *
- * 13 => WLAN
- * 14 => SYS
- * 15 => QSS
- * 18 => LAN
- *
- * 16 => Range Extender
- * 17 => Reset button
- *
- * All OUT GPIOs are active LOW if not stated otherwise
- */
-
- // GPIOs init
- li a1, AR934X_GPIO_OE
- lw v1, 0(a1)
- // Set GPIOs 13~15 and 18 as outputs
- and v1, v1, 0xFFFB1FFF
- // Set GPIOs 16~17 as inputs
- or v1, v1, 0x30000
- sw v1, 0(a1)
-
- // Set GPIO function for GPIOs 13~15
- li a1, AR934X_GPIO_OUT_FUNCTION3
- lw v1, 0(a1)
- and v1, v1, 0xFF
- sw v1, 0(a1)
-
- // Set GPIO function for GPIO 18
- li a1, AR934X_GPIO_OUT_FUNCTION4
- lw v1, 0(a1)
- and v1, v1, 0xFF00FFFF
- sw v1, 0(a1)
-
- // Turn off all LEDs
- li a1, AR934X_GPIO_SET
- li v1, 0x4E000
- sw v1, 0(a1)
-
-#endif
-
-#endif /* #if defined(CONFIG_WASP_SUPPORT) */
-
/*
* Clearing CP0 registers - This is generally required for the MIPS-24k
- * core used by Atheros.
+ * core used by Atheros.
*/
- mtc0 zero, $0
- mtc0 zero, $1
- mtc0 zero, $2
- mtc0 zero, $3
- mtc0 zero, $4
- mtc0 zero, $5
- mtc0 zero, $6
- mtc0 zero, $7
- mtc0 zero, $8
- mtc0 zero, $9
- mtc0 zero, $10
- mtc0 zero, $11
- li t0, 0x10000004
- mtc0 t0, $12
- mtc0 zero, $13
- mtc0 zero, $14
- mtc0 zero, $15
- mtc0 zero, $16
- mtc0 zero, $17
- mtc0 zero, $18
- mtc0 zero, $19
- mtc0 zero, $20
- mtc0 zero, $21
- mtc0 zero, $22
- mtc0 zero, $23
- mtc0 zero, $24
- mtc0 zero, $25
- mtc0 zero, $26
- mtc0 zero, $27
- mtc0 zero, $28
-
-#ifdef CONFIG_WASP_SUPPORT
+ mtc0 zero, $0
+ mtc0 zero, $1
+ mtc0 zero, $2
+ mtc0 zero, $3
+ mtc0 zero, $4
+ mtc0 zero, $5
+ mtc0 zero, $6
+ mtc0 zero, $7
+ mtc0 zero, $8
+ mtc0 zero, $9
+ mtc0 zero, $10
+ mtc0 zero, $11
+ li t0, 0x10000004
+ mtc0 t0, $12
+ mtc0 zero, $13
+ mtc0 zero, $14
+ mtc0 zero, $15
+ mtc0 zero, $16
+ mtc0 zero, $17
+ mtc0 zero, $18
+ mtc0 zero, $19
+ mtc0 zero, $20
+ mtc0 zero, $21
+ mtc0 zero, $22
+ mtc0 zero, $23
+ mtc0 zero, $24
+ mtc0 zero, $25
+ mtc0 zero, $26
+ mtc0 zero, $27
+ mtc0 zero, $28
+
+#if (SOC_TYPE & QCA_AR934X_SOC) | \
+ (SOC_TYPE & QCA_QCA953X_SOC) | \
+ (SOC_TYPE & QCA_QCA955X_SOC) | \
+ (SOC_TYPE & QCA_QCA956X_SOC)
mtc0 zero, $29 # C0_TagHi
mtc0 zero, $28, 2 # C0_DTagLo
mtc0 zero, $29, 2 # C0_DTagHi
#endif
- /*
- * Clear watch registers.
- */
-
- mtc0 zero, CP0_WATCHLO
- mtc0 zero, CP0_WATCHHI
+ /* Clear watch registers */
+ mtc0 zero, CP0_WATCHLO
+ mtc0 zero, CP0_WATCHHI
/* STATUS register */
- mfc0 k0, CP0_STATUS
- li k1, ~ST0_IE
- and k0, k1
- mtc0 zero, CP0_CAUSE
- mtc0 k0, CP0_STATUS
+ mfc0 k0, CP0_STATUS
+ li k1, ~ST0_IE
+ and k0, k1
+ mtc0 zero, CP0_CAUSE
+ mtc0 k0, CP0_STATUS
/* CAUSE register */
- mtc0 zero, CP0_CAUSE
+ mtc0 zero, CP0_CAUSE
/* Init Timer */
- mtc0 zero, CP0_COUNT
- mtc0 zero, CP0_COMPARE
+ mtc0 zero, CP0_COUNT
+ mtc0 zero, CP0_COMPARE
/* CONFIG0 register */
- li t0, CONF_CM_UNCACHED
- mtc0 t0, CP0_CONFIG
-
+ li t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
- /* Initialize GOT pointer.*/
- bal 1f
+ /* Initialize GOT pointer.*/
+ bal 1f
nop
- .word _GLOBAL_OFFSET_TABLE_
+ .word _GLOBAL_OFFSET_TABLE_
1:
- move gp, ra
- lw t1, 0(ra)
- move gp, t1
+ move gp, ra
+ lw t1, 0(ra)
+ move gp, t1
-#if defined(CONFIG_MACH_HORNET) && defined(CONFIG_HORNET_1_1_WAR)
-/**************************************************************************/
-/*
- * WAR: Hornet 1.1 currently need a reset once we boot to let the resetb has
- * enough time to stable, so that trigger reset at 1st boot, system team
- * is investigaing the issue, will remove in short
- */
-
-do_reset_normal:
-
- li t7, 0xbd000000
- lw t8, 0(t7) // t8 : value of 0xbd000000
- li t9, 0x12345678
- bne t8, t9, do_reset // if value of 0xbd000000 != 0x12345678 , go to do_reset
- nop
- li t9, 0xffffffff
- sw t9, 0(t7)
- b normal_path
- nop
-
-do_reset:
- sw t9, 0(t7)
- li t7, 0xb806001c // load reset register 0x1806001c
- lw t8, 0(t7)
- li t9, 0x1000000 // bit24, fullchip reset
- or t8, t8, t9
- sw t8, 0(t7)
-do_reset_loop:
- b do_reset_loop
- nop
-
-normal_path:
-#endif /* CONFIG_MACH_HORNET */
-
-/**************************************************************************/
-
- /* Initialize any external memory.
- */
-#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240)
- la t9, lowlevel_init
- jalr t9
- nop
+ /* Lowlevel initialization of GPIO */
+ la t7, lowlevel_gpio_init
+ jalr t7
nop
-#if defined(CONFIG_MACH_HORNET)
- la t9, hornet_ddr_init
- jalr t9
+ /* Initialize any external memory */
+ la t9, lowlevel_init
+ jalr t9
nop
- nop
-#endif
- la t0, rel_start
- j t0
+ la t0, rel_start
+ j t0
nop
-#endif
rel_start:
+ /* Initialize caches... */
+ la t9, simple_mips_cache_reset
+ jalr t9
+ nop
-#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240)
- /* REMAP_DISABLE */
- // TODO: SPI clock from FLASH?
- // for now we will use divider = 10 ( (4+1)*2 )
- li a0, KSEG1ADDR(AR7100_SPI_CLOCK)
- li t0, 0x44
- sw t0, 0(a0)
-#endif
-
-#if defined(CONFIG_AR9100) && defined(CFG_HOWL_1_2)
- /* Disable remap for parallel flash */
- li t7, AR9100_FLASH_CONFIG;
- lw t8, 0(t7);
- li t9, 0xffbf0000;
- and t8, t8, t9;
- li t9, 0x22fc;
- or t8, t8, t9;
- li t9, 0xffcfffff; /* scale = 0 */
- and t8, t8, t9;
- sw t8, 0(t7);
-
-#endif
+ /* ... and enable them */
+#if (SOC_TYPE & QCA_AR934X_SOC)
+ li t7, KSEG1ADDR(QCA_RST_REVISION_ID_REG)
+ lw t7, 0(t7)
+ andi t9, t7, 0xf
+ bne zero, t9, 1f
+ nop
- /* Initialize caches...
- */
- la t9, simple_mips_cache_reset
- jalr t9
+ li t0, CONF_CM_UNCACHED
+ j 2f
nop
+#endif
- /* ... and enable them.
- */
- li t0, CONF_CM_CACHABLE_NONCOHERENT
- mtc0 t0, CP0_CONFIG
+1:
+ li t0, CONF_CM_CACHABLE_NONCOHERENT
+2:
+ mtc0 t0, CP0_CONFIG
-#if !defined(CONFIG_AR7100) && !defined(CONFIG_AR7240)
- /* Set up temporary stack.
- */
- li a0, CFG_INIT_SP_OFFSET
- la t9, mips_cache_lock
- jalr t9
+#if (SOC_TYPE & QCA_AR933X_SOC) || \
+ (SOC_TYPE & QCA_AR934X_SOC)
+ la t9, mips_cache_lock_24k
+ jalr t9
nop
#endif
-#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240)
- la t9, mips_cache_lock_24k
- jalr t9
- nop
+#if (SOC_TYPE & QCA_AR934X_SOC) || \
+ (SOC_TYPE & QCA_QCA953X_SOC)
+ /* Setup stack in SRAM */
+ li t0, CONFIG_INIT_SRAM_SP_OFFSET
+#else
+ li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
#endif
+ la sp, 0(t0)
- li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
- la sp, 0(t0)
-
- la t9, bootstrap_board_init_f
- j t9
+ la t9, bootstrap_board_init_f
+ j t9
nop
-
/*
* void bootstrap_relocate_code (addr_sp, gd, addr_moni)
*
* a1 = gd
* a2 = destination address
*/
- .globl bootstrap_relocate_code
- .ent bootstrap_relocate_code
+ .globl bootstrap_relocate_code
+ .ent bootstrap_relocate_code
+
bootstrap_relocate_code:
- move sp, a0 /* Set new stack pointer */
+ /* Set new stack pointer */
+ move sp, a0
+
+ li t0, BOOTSTRAP_CFG_MONITOR_BASE
+ la t3, in_ram
+ lw t2, -12(t3) /* t2 <-- uboot_end_data_bootsrap */
- li t0, BOOTSTRAP_CFG_MONITOR_BASE
- la t3, in_ram
- lw t2, -12(t3) /* t2 <-- uboot_end_data_bootsrap */
/*
* Ideally, following line is not needed. However,
* Adding 256k to what needs to be read in actually.
* This introduces some delay that seems to help boot.
*/
- li t3, (256 << 10)
+ li t3, (256 << 10)
- add t2, t3
- move t1, a2
+ add t2, t3
+ move t1, a2
/*
* Fix GOT pointer:
- *
- * New GOT-PTR = (old GOT-PTR - BOOTSTRAP_CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*/
- move t6, gp
- sub gp, BOOTSTRAP_CFG_MONITOR_BASE
- add gp, a2 /* gp now adjusted */
- sub t6, gp, t6 /* t6 <-- relocation offset */
+ move t6, gp
+ sub gp, BOOTSTRAP_CFG_MONITOR_BASE
+ add gp, a2 /* gp now adjusted */
+ sub t6, gp, t6 /* t6 - relocation offset */
/*
* t0 = source address
* t2 = source end address
*/
1:
- lw t3, 0(t0)
- sw t3, 0(t1)
- addu t0, 4
- ble t0, t2, 1b
- addu t1, 4 /* delay slot */
+ lw t3, 0(t0)
+ sw t3, 0(t1)
+ addu t0, 4
+ ble t0, t2, 1b
+ addu t1, 4 /* Delay slot */
- /* If caches were enabled, we would have to flush them here.
- */
+ /* If caches were enabled, we would have to flush them here */
- /* Jump to where we've relocated ourselves.
- */
- addi t0, a2, in_ram - _start_bootstrap
- j t0
+ /* Jump to where we've relocated ourselves */
+ addi t0, a2, in_ram - _start_bootstrap
+ j t0
nop
- .word uboot_end_data_bootstrap
- .word uboot_end_bootstrap
- .word num_got_entries
+ .word uboot_end_data_bootstrap
+ .word uboot_end_bootstrap
+ .word num_got_entries
in_ram:
- /* Now we want to update GOT.
- */
- lw t3, -4(t0) /* t3 <-- num_got_entries */
- addi t4, gp, 8 /* Skipping first two entries. */
- li t2, 2
+ /* Now we want to update GOT */
+ lw t3, -4(t0) /* t3 - num_got_entries */
+ addi t4, gp, 8 /* Skipping first two entries */
+ li t2, 2
1:
- lw t1, 0(t4)
- beqz t1, 2f
- add t1, t6
- sw t1, 0(t4)
+ lw t1, 0(t4)
+ beqz t1, 2f
+ add t1, t6
+ sw t1, 0(t4)
2:
- addi t2, 1
- blt t2, t3, 1b
- addi t4, 4 /* delay slot */
+ addi t2, 1
+ blt t2, t3, 1b
+ addi t4, 4 /* Delay slot */
- /* Clear BSS.
- */
- lw t1, -12(t0) /* t1 <-- uboot_end_data_bootstrap */
- lw t2, -8(t0) /* t2 <-- uboot_end_bootstrap */
- add t1, t6 /* adjust pointers */
- add t2, t6
+ /* Clear BSS */
+ lw t1, -12(t0) /* t1 - uboot_end_data */
+ lw t2, -8(t0) /* t2 - uboot_end */
+ add t1, t6 /* Adjust pointers */
+ add t2, t6
sub t1, 4
-1: addi t1, 4
- bltl t1, t2, 1b
- sw zero, 0(t1) /* delay slot */
+1:
+ addi t1, 4
+ bltl t1, t2, 1b
+ sw zero, 0(t1) /* Delay slot */
- move a0, a1
- la t9, bootstrap_board_init_r
- j t9
- move a1, a2 /* delay slot */
+ move a0, a1
+ la t9, bootstrap_board_init_r
+ j t9
+ move a1, a2 /* Delay slot */
- .end bootstrap_relocate_code
+ .end bootstrap_relocate_code
- /* Exception handlers.
- */
+ /* Exception handlers */
romReserved:
b romReserved
--- /dev/null
+<!DOCTYPE HTML>
+<html>
+ <head>
+ <meta charset="utf-8">
+ <title>Page not found</title>
+ <link rel="stylesheet" href="style.css">
+ </head>
+ <body>
+ <div id="m">
+ <h1 class="red">Page not found</h1>
+ <p>The page you were looking for doesn't exist!<br>Go back to <a href="index.html">firmware update</a> page.</p>
+ </div>
+ <div id="f">This code is based on <a href="https://github.com/pepe2k/u-boot_mod" target="_blank">GitHub</a></div>
+ </body>
+</html>
\ No newline at end of file
--- /dev/null
+<!DOCTYPE HTML>
+<html>
+ <head>
+ <meta charset="utf-8">
+ <title>ART update</title>
+ <link rel="stylesheet" href="style.css">
+ </head>
+ <body>
+ <div id="m">
+ <h1>ART UPDATE</h1>
+ <p>You are going to update <strong>ART (Atheros Radio Test)</strong> on the device.<br>Please, choose file from your local hard drive and click <strong>Update ART</strong> button.</p>
+ <form method="post" enctype="multipart/form-data"><input type="file" name="art"><input type="submit" value="Update ART"></form>
+ <div class="i w">
+ <strong>WARNINGS</strong>
+ <ul>
+ <li>do not power off the device during update</li>
+ <li>if everything goes well, the device will restart</li>
+ <li>you can upload whatever you want, so be sure that you choose proper ART image for your device</li>
+ </ul>
+ </div>
+ </div>
+ <div id="f">This code is based on <a href="https://github.com/pepe2k/u-boot_mod" target="_blank">GitHub</a></div>
+ </body>
+</html>
\ No newline at end of file
--- /dev/null
+<!DOCTYPE HTML>
+<html>
+ <head>
+ <meta charset="utf-8">
+ <title>Update failed</title>
+ <link rel="stylesheet" href="style.css">
+ </head>
+ <body>
+ <div id="m">
+ <h1 class="red">Update failed!</h1>
+ <p>Please, try again or contact with the author of this modification.<br>You can also get more information during update in U-Boot console.</p>
+ </div>
+ <div id="f">This code is based on <a href="https://github.com/pepe2k/u-boot_mod" target="_blank">GitHub</a></div>
+ </body>
+</html>
\ No newline at end of file
--- /dev/null
+<!DOCTYPE HTML>
+<html>
+ <head>
+ <meta charset="utf-8">
+ <title>Update in progress</title>
+ <style>
+ h1,p,body{margin:0;padding:0}html,body{font:13px/20px Tahoma,sans-serif;background:#135B72;color:#FFF;text-align:center;height:100%}#m{padding:30px 0}#m>*{padding:20px}#f{font-size:11px;position:absolute;bottom:0;width:100%;padding:15px 0}a{color:#FEDD12;text-decoration:none}h1{font:bold 40px/40px Arial}#l{height:30px;width:30px;margin:30px auto;-webkit-animation:r 1s infinite linear;-moz-animation:r 1s infinite linear;-o-animation:r 1s infinite linear;animation:r 1s infinite linear;border-left:5px solid #FEDD12;border-right:5px solid #FEDD12;border-bottom:5px solid #135B72;border-top:5px solid #135B72;border-radius:100%}@-webkit-keyframes r{from{-webkit-transform:rotate(0deg)}to{-webkit-transform:rotate(359deg)}}@-moz-keyframes r{from{-moz-transform:rotate(0deg)}to{-moz-transform:rotate(359deg)}}@-o-keyframes r{from{-o-transform:rotate(0deg)}to{-o-transform:rotate(359deg)}}@keyframes r{from{transform:rotate(0deg)}to{transform:rotate(359deg)}}
+ </style>
+ </head>
+ <body>
+ <div id="m">
+ <h1>Update in progress</h1>
+ <p>Your file was successfully uploaded! Update is in progress and you should wait for automatic reset of the device.<br>Update time depends on image size and may take up to a few minutes. You can close this page.</p>
+ <div id="l"></div>
+ </div>
+ <div id="f">This code is based on <a href="https://github.com/pepe2k/u-boot_mod" target="_blank">GitHub</a></div>
+ </body>
+</html>
\ No newline at end of file
--- /dev/null
+<!DOCTYPE HTML>
+<html>
+ <head>
+ <meta charset="utf-8">
+ <title>Firmware update for Black Swift board</title>
+ <link rel="stylesheet" href="style.css">
+ </head>
+ <body>
+ <div id="h">Black Swift board</div>
+ <div id="m">
+ <h1>Firmware update</h1>
+ <p>You are going to upload new firmware to the device.<br>Choose a proper file from your local hard drive and click <strong>"Update firmware"</strong> button.<br>Please, do not power off the device during update, if everything goes well, the device will restart.</p>
+ <form method="post" enctype="multipart/form-data"><input type="file" name="firmware"><input type="submit" value="Update firmware"></form>
+ </div>
+ <div id="m">Please, go <a href="uboot.html">here</a> to update U-Boot or <a href="art.html">here</a> to update ART.</div>
+ <div id="f">This code is based on <a href="https://github.com/pepe2k/u-boot_mod" target="_blank">GitHub</a></div>
+ </body>
+</html>
\ No newline at end of file
--- /dev/null
+h1,
+p,
+form,
+body {
+ margin: 0;
+ padding: 0;
+}
+
+html,
+body {
+ font: 13px/20px Tahoma, sans-serif;
+ background: #135B72;
+ color: #FFF;
+ text-align: center;
+ height: 100%;
+}
+
+#m, #h {
+ padding: 30px 0;
+}
+
+#h {
+ font: bold 40px/40px Arial;
+ background: #ffffff;
+ color: #000000;
+ text-align: center;
+}
+
+#m > * {
+ padding: 20px;
+}
+
+#f {
+ font-size: 11px;
+ position: absolute;
+ bottom: 0;
+ width: 100%;
+ padding: 15px 0;
+}
+
+a {
+ color: #FEDD12;
+ text-decoration: none;
+}
+
+h1 {
+ font: bold 40px/40px Arial;
+}
+
+.red {
+ color: #ED0000;
+}
\ No newline at end of file
--- /dev/null
+<!DOCTYPE HTML>
+<html>
+ <head>
+ <meta charset="utf-8">
+ <title>U-Boot update</title>
+ <link rel="stylesheet" href="style.css">
+ </head>
+ <body>
+ <div id="m">
+ <h1>U-BOOT UPDATE</h1>
+ <p>You are going to update <strong>U-Boot bootloader</strong> on the device.<br>Please, choose file from your local hard drive and click <strong>Update U-Boot</strong> button.</p>
+ <form method="post" enctype="multipart/form-data"><input type="file" name="uboot"><input type="submit" value="Update U-Boot"></form>
+ <div class="i w">
+ <strong>WARNINGS</strong>
+ <ul>
+ <li>do not power off the device during update</li>
+ <li>if everything goes well, the device will restart</li>
+ <li>you can upload whatever you want, so be sure that you choose proper U-Boot image for your device</li>
+ <li>updating U-Boot is a very dangerous operation and may damage your device!</li>
+ </ul>
+ </div>
+ </div>
+ <div id="f">This code is based on <a href="https://github.com/pepe2k/u-boot_mod" target="_blank">GitHub</a></div>
+ </body>
+</html>
\ No newline at end of file
--- /dev/null
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _QCA953X_H
+#define _QCA953X_H
+
+#ifndef __ASSEMBLY__
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <linux/types.h>
+#endif /* __ASSEMBLY__ */
+
+#undef is_qca953x
+#undef is_hb
+
+#define is_qca953x() (1)
+#define is_hb() (1)
+
+
+#define CPU_PLL_CONFIG_UPDATING_MSB 31
+#define CPU_PLL_CONFIG_UPDATING_LSB 31
+#define CPU_PLL_CONFIG_UPDATING_MASK 0x80000000
+#define CPU_PLL_CONFIG_UPDATING_GET(x) (((x) & CPU_PLL_CONFIG_UPDATING_MASK) >> CPU_PLL_CONFIG_UPDATING_LSB)
+#define CPU_PLL_CONFIG_UPDATING_SET(x) (((x) << CPU_PLL_CONFIG_UPDATING_LSB) & CPU_PLL_CONFIG_UPDATING_MASK)
+#define CPU_PLL_CONFIG_UPDATING_RESET 0x1 // 1
+#define CPU_PLL_CONFIG_PLLPWD_MSB 30
+#define CPU_PLL_CONFIG_PLLPWD_LSB 30
+#define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000
+#define CPU_PLL_CONFIG_PLLPWD_GET(x) (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB)
+#define CPU_PLL_CONFIG_PLLPWD_SET(x) (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
+#define CPU_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
+#define CPU_PLL_CONFIG_SPARE_MSB 29
+#define CPU_PLL_CONFIG_SPARE_LSB 22
+#define CPU_PLL_CONFIG_SPARE_MASK 0x3fc00000
+#define CPU_PLL_CONFIG_SPARE_GET(x) (((x) & CPU_PLL_CONFIG_SPARE_MASK) >> CPU_PLL_CONFIG_SPARE_LSB)
+#define CPU_PLL_CONFIG_SPARE_SET(x) (((x) << CPU_PLL_CONFIG_SPARE_LSB) & CPU_PLL_CONFIG_SPARE_MASK)
+#define CPU_PLL_CONFIG_SPARE_RESET 0x0 // 0
+#define CPU_PLL_CONFIG_OUTDIV_MSB 21
+#define CPU_PLL_CONFIG_OUTDIV_LSB 19
+#define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000
+#define CPU_PLL_CONFIG_OUTDIV_GET(x) (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB)
+#define CPU_PLL_CONFIG_OUTDIV_SET(x) (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
+#define CPU_PLL_CONFIG_OUTDIV_RESET 0x0 // 0
+#define CPU_PLL_CONFIG_RANGE_MSB 18
+#define CPU_PLL_CONFIG_RANGE_LSB 17
+#define CPU_PLL_CONFIG_RANGE_MASK 0x00060000
+#define CPU_PLL_CONFIG_RANGE_GET(x) (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB)
+#define CPU_PLL_CONFIG_RANGE_SET(x) (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
+#define CPU_PLL_CONFIG_RANGE_RESET 0x3 // 3
+#define CPU_PLL_CONFIG_REFDIV_MSB 16
+#define CPU_PLL_CONFIG_REFDIV_LSB 12
+#define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000
+#define CPU_PLL_CONFIG_REFDIV_GET(x) (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB)
+#define CPU_PLL_CONFIG_REFDIV_SET(x) (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
+#define CPU_PLL_CONFIG_REFDIV_RESET 0x2 // 2
+#define CPU_PLL_CONFIG_NINT_MSB 11
+#define CPU_PLL_CONFIG_NINT_LSB 6
+#define CPU_PLL_CONFIG_NINT_MASK 0x00000fc0
+#define CPU_PLL_CONFIG_NINT_GET(x) (((x) & CPU_PLL_CONFIG_NINT_MASK) >> CPU_PLL_CONFIG_NINT_LSB)
+#define CPU_PLL_CONFIG_NINT_SET(x) (((x) << CPU_PLL_CONFIG_NINT_LSB) & CPU_PLL_CONFIG_NINT_MASK)
+#define CPU_PLL_CONFIG_NINT_RESET 0x14 // 20
+#define CPU_PLL_CONFIG_NFRAC_MSB 5
+#define CPU_PLL_CONFIG_NFRAC_LSB 0
+#define CPU_PLL_CONFIG_NFRAC_MASK 0x0000003f
+#define CPU_PLL_CONFIG_NFRAC_GET(x) (((x) & CPU_PLL_CONFIG_NFRAC_MASK) >> CPU_PLL_CONFIG_NFRAC_LSB)
+#define CPU_PLL_CONFIG_NFRAC_SET(x) (((x) << CPU_PLL_CONFIG_NFRAC_LSB) & CPU_PLL_CONFIG_NFRAC_MASK)
+#define CPU_PLL_CONFIG_NFRAC_RESET 0x10 // 16
+#define CPU_PLL_CONFIG_ADDRESS 0x18050000
+#define DDR_PLL_CONFIG_UPDATING_MSB 31
+#define DDR_PLL_CONFIG_UPDATING_LSB 31
+#define DDR_PLL_CONFIG_UPDATING_MASK 0x80000000
+#define DDR_PLL_CONFIG_UPDATING_GET(x) (((x) & DDR_PLL_CONFIG_UPDATING_MASK) >> DDR_PLL_CONFIG_UPDATING_LSB)
+#define DDR_PLL_CONFIG_UPDATING_SET(x) (((x) << DDR_PLL_CONFIG_UPDATING_LSB) & DDR_PLL_CONFIG_UPDATING_MASK)
+#define DDR_PLL_CONFIG_UPDATING_RESET 0x1 // 1
+#define DDR_PLL_CONFIG_PLLPWD_MSB 30
+#define DDR_PLL_CONFIG_PLLPWD_LSB 30
+#define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000
+#define DDR_PLL_CONFIG_PLLPWD_GET(x) (((x) & DDR_PLL_CONFIG_PLLPWD_MASK) >> DDR_PLL_CONFIG_PLLPWD_LSB)
+#define DDR_PLL_CONFIG_PLLPWD_SET(x) (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
+#define DDR_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
+#define DDR_PLL_CONFIG_SPARE_MSB 29
+#define DDR_PLL_CONFIG_SPARE_LSB 26
+#define DDR_PLL_CONFIG_SPARE_MASK 0x3c000000
+#define DDR_PLL_CONFIG_SPARE_GET(x) (((x) & DDR_PLL_CONFIG_SPARE_MASK) >> DDR_PLL_CONFIG_SPARE_LSB)
+#define DDR_PLL_CONFIG_SPARE_SET(x) (((x) << DDR_PLL_CONFIG_SPARE_LSB) & DDR_PLL_CONFIG_SPARE_MASK)
+#define DDR_PLL_CONFIG_SPARE_RESET 0x0 // 0
+#define DDR_PLL_CONFIG_OUTDIV_MSB 25
+#define DDR_PLL_CONFIG_OUTDIV_LSB 23
+#define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000
+#define DDR_PLL_CONFIG_OUTDIV_GET(x) (((x) & DDR_PLL_CONFIG_OUTDIV_MASK) >> DDR_PLL_CONFIG_OUTDIV_LSB)
+#define DDR_PLL_CONFIG_OUTDIV_SET(x) (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK)
+#define DDR_PLL_CONFIG_OUTDIV_RESET 0x0 // 0
+#define DDR_PLL_CONFIG_RANGE_MSB 22
+#define DDR_PLL_CONFIG_RANGE_LSB 21
+#define DDR_PLL_CONFIG_RANGE_MASK 0x00600000
+#define DDR_PLL_CONFIG_RANGE_GET(x) (((x) & DDR_PLL_CONFIG_RANGE_MASK) >> DDR_PLL_CONFIG_RANGE_LSB)
+#define DDR_PLL_CONFIG_RANGE_SET(x) (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK)
+#define DDR_PLL_CONFIG_RANGE_RESET 0x3 // 3
+#define DDR_PLL_CONFIG_REFDIV_MSB 20
+#define DDR_PLL_CONFIG_REFDIV_LSB 16
+#define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000
+#define DDR_PLL_CONFIG_REFDIV_GET(x) (((x) & DDR_PLL_CONFIG_REFDIV_MASK) >> DDR_PLL_CONFIG_REFDIV_LSB)
+#define DDR_PLL_CONFIG_REFDIV_SET(x) (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK)
+#define DDR_PLL_CONFIG_REFDIV_RESET 0x2 // 2
+#define DDR_PLL_CONFIG_NINT_MSB 15
+#define DDR_PLL_CONFIG_NINT_LSB 10
+#define DDR_PLL_CONFIG_NINT_MASK 0x0000fc00
+#define DDR_PLL_CONFIG_NINT_GET(x) (((x) & DDR_PLL_CONFIG_NINT_MASK) >> DDR_PLL_CONFIG_NINT_LSB)
+#define DDR_PLL_CONFIG_NINT_SET(x) (((x) << DDR_PLL_CONFIG_NINT_LSB) & DDR_PLL_CONFIG_NINT_MASK)
+#define DDR_PLL_CONFIG_NINT_RESET 0x14 // 20
+#define DDR_PLL_CONFIG_NFRAC_MSB 9
+#define DDR_PLL_CONFIG_NFRAC_LSB 0
+#define DDR_PLL_CONFIG_NFRAC_MASK 0x000003ff
+#define DDR_PLL_CONFIG_NFRAC_GET(x) (((x) & DDR_PLL_CONFIG_NFRAC_MASK) >> DDR_PLL_CONFIG_NFRAC_LSB)
+#define DDR_PLL_CONFIG_NFRAC_SET(x) (((x) << DDR_PLL_CONFIG_NFRAC_LSB) & DDR_PLL_CONFIG_NFRAC_MASK)
+#define DDR_PLL_CONFIG_NFRAC_RESET 0x200 // 512
+#define DDR_PLL_CONFIG_ADDRESS 0x18050004
+
+#define DDR_CTL_CONFIG_SRAM_TSEL_MSB 31
+#define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30
+#define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000
+#define DDR_CTL_CONFIG_SRAM_TSEL_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) >> DDR_CTL_CONFIG_SRAM_TSEL_LSB)
+#define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK)
+#define DDR_CTL_CONFIG_SRAM_TSEL_RESET 0x1 // 1
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MSB 29
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB 21
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK 0x3fe00000
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(x) (((x) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) >> DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB)
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x) (((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK)
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_RESET 0x0 // 0
+#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MSB 20
+#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB 20
+#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK 0x00100000
+#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB)
+#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK)
+#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_RESET 0x1 // 1
+#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MSB 19
+#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB 19
+#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK 0x00080000
+#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB)
+#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK)
+#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_RESET 0x1 // 1
+#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MSB 18
+#define DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB 18
+#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK 0x00040000
+#define DDR_CTL_CONFIG_USB_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB)
+#define DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK)
+#define DDR_CTL_CONFIG_USB_SRAM_SYNC_RESET 0x1 // 1
+#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MSB 17
+#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB 17
+#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK 0x00020000
+#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB)
+#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK)
+#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_RESET 0x1 // 1
+#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MSB 16
+#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB 16
+#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK 0x00010000
+#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB)
+#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK)
+#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_RESET 0x1 // 1
+#define DDR_CTL_CONFIG_SPARE_MSB 13
+#define DDR_CTL_CONFIG_SPARE_LSB 7
+#define DDR_CTL_CONFIG_SPARE_MASK 0x00003f80
+#define DDR_CTL_CONFIG_SPARE_GET(x) (((x) & DDR_CTL_CONFIG_SPARE_MASK) >> DDR_CTL_CONFIG_SPARE_LSB)
+#define DDR_CTL_CONFIG_SPARE_SET(x) (((x) << DDR_CTL_CONFIG_SPARE_LSB) & DDR_CTL_CONFIG_SPARE_MASK)
+#define DDR_CTL_CONFIG_SPARE_RESET 0x0 // 0
+#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MSB 6
+#define DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB 6
+#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK 0x00000040
+#define DDR_CTL_CONFIG_PAD_DDR2_SEL_GET(x) (((x) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK) >> DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB)
+#define DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(x) (((x) << DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK)
+#define DDR_CTL_CONFIG_PAD_DDR2_SEL_RESET 0x0 // 0
+#define DDR_CTL_CONFIG_GATE_SRAM_CLK_MSB 4
+#define DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB 4
+#define DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK 0x00000010
+#define DDR_CTL_CONFIG_GATE_SRAM_CLK_GET(x) (((x) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK) >> DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB)
+#define DDR_CTL_CONFIG_GATE_SRAM_CLK_SET(x) (((x) << DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK)
+#define DDR_CTL_CONFIG_GATE_SRAM_CLK_RESET 0x0 // 0
+#define DDR_CTL_CONFIG_SRAM_REQ_ACK_MSB 3
+#define DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB 3
+#define DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK 0x00000008
+#define DDR_CTL_CONFIG_SRAM_REQ_ACK_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK) >> DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB)
+#define DDR_CTL_CONFIG_SRAM_REQ_ACK_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK)
+#define DDR_CTL_CONFIG_SRAM_REQ_ACK_RESET 0x0 // 0
+#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MSB 2
+#define DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB 2
+#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK 0x00000004
+#define DDR_CTL_CONFIG_CPU_DDR_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK) >> DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB)
+#define DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK)
+#define DDR_CTL_CONFIG_CPU_DDR_SYNC_RESET 0x0 // 0
+#define DDR_CTL_CONFIG_HALF_WIDTH_MSB 1
+#define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1
+#define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002
+#define DDR_CTL_CONFIG_HALF_WIDTH_GET(x) (((x) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) >> DDR_CTL_CONFIG_HALF_WIDTH_LSB)
+#define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) (((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK)
+#define DDR_CTL_CONFIG_HALF_WIDTH_RESET 0x1 // 1
+#define DDR_CTL_CONFIG_SDRAM_MODE_EN_MSB 0
+#define DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB 0
+#define DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK 0x00000001
+#define DDR_CTL_CONFIG_SDRAM_MODE_EN_GET(x) (((x) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK) >> DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB)
+#define DDR_CTL_CONFIG_SDRAM_MODE_EN_SET(x) (((x) << DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK)
+#define DDR_CTL_CONFIG_SDRAM_MODE_EN_RESET 0x0 // 0
+#define DDR_CTL_CONFIG_ADDRESS 0x18000108
+
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MSB 31
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB 31
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK 0x80000000
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB)
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK)
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_RESET 0x0 // 0
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MSB 30
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB 30
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK 0x40000000
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB)
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK)
+#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_RESET 0x0 // 0
+#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MSB 29
+#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB 29
+#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK 0x20000000
+#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_GET(x) (((x) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK) >> DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB)
+#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_SET(x) (((x) << DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK)
+#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_RESET 0x0 // 0
+#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MSB 28
+#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB 28
+#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK 0x10000000
+#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_GET(x) (((x) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK) >> DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB)
+#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_SET(x) (((x) << DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK)
+#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_RESET 0x1 // 1
+#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MSB 27
+#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB 27
+#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK 0x08000000
+#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_GET(x) (((x) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK) >> DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB)
+#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_SET(x) (((x) << DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK)
+#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_RESET 0x0 // 0
+#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MSB 16
+#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB 16
+#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK 0x00010000
+#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB)
+#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB) & DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK)
+#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_RESET 0x0 // 0
+#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MSB 15
+#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB 15
+#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK 0x00008000
+#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK) >> DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB)
+#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB) & DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK)
+#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_RESET 0x0 // 0
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MSB 14
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB 13
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK 0x00006000
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB)
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK)
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_RESET 0x0 // 0
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_MSB 12
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_LSB 8
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_MASK 0x00001f00
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_LSB)
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK)
+#define DDR_DEBUG_RD_CNTL_GATE_TAP_RESET 0x1 // 1
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MSB 6
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB 5
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK 0x00000060
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB)
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK)
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_RESET 0x0 // 0
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_MSB 4
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB 0
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK 0x0000001f
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB)
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK)
+#define DDR_DEBUG_RD_CNTL_CK_P_TAP_RESET 0x1 // 1
+#define DDR_DEBUG_RD_CNTL_ADDRESS 0x18000118
+
+#define DDR2_CONFIG_DDR2_TWL_MSB 13
+#define DDR2_CONFIG_DDR2_TWL_LSB 10
+#define DDR2_CONFIG_DDR2_TWL_MASK 0x00003c00
+#define DDR2_CONFIG_DDR2_TWL_GET(x) (((x) & DDR2_CONFIG_DDR2_TWL_MASK) >> DDR2_CONFIG_DDR2_TWL_LSB)
+#define DDR2_CONFIG_DDR2_TWL_SET(x) (((x) << DDR2_CONFIG_DDR2_TWL_LSB) & DDR2_CONFIG_DDR2_TWL_MASK)
+#define DDR2_CONFIG_DDR2_TWL_RESET 0x1 // 1
+#define DDR2_CONFIG_DDR2_ODT_MSB 9
+#define DDR2_CONFIG_DDR2_ODT_LSB 9
+#define DDR2_CONFIG_DDR2_ODT_MASK 0x00000200
+#define DDR2_CONFIG_DDR2_ODT_GET(x) (((x) & DDR2_CONFIG_DDR2_ODT_MASK) >> DDR2_CONFIG_DDR2_ODT_LSB)
+#define DDR2_CONFIG_DDR2_ODT_SET(x) (((x) << DDR2_CONFIG_DDR2_ODT_LSB) & DDR2_CONFIG_DDR2_ODT_MASK)
+#define DDR2_CONFIG_DDR2_ODT_RESET 0x1 // 1
+#define DDR2_CONFIG_TFAW_MSB 7
+#define DDR2_CONFIG_TFAW_LSB 2
+#define DDR2_CONFIG_TFAW_MASK 0x000000fc
+#define DDR2_CONFIG_TFAW_GET(x) (((x) & DDR2_CONFIG_TFAW_MASK) >> DDR2_CONFIG_TFAW_LSB)
+#define DDR2_CONFIG_TFAW_SET(x) (((x) << DDR2_CONFIG_TFAW_LSB) & DDR2_CONFIG_TFAW_MASK)
+#define DDR2_CONFIG_TFAW_RESET 0x16 // 22
+#define DDR2_CONFIG_ENABLE_DDR2_MSB 0
+#define DDR2_CONFIG_ENABLE_DDR2_LSB 0
+#define DDR2_CONFIG_ENABLE_DDR2_MASK 0x00000001
+#define DDR2_CONFIG_ENABLE_DDR2_GET(x) (((x) & DDR2_CONFIG_ENABLE_DDR2_MASK) >> DDR2_CONFIG_ENABLE_DDR2_LSB)
+#define DDR2_CONFIG_ENABLE_DDR2_SET(x) (((x) << DDR2_CONFIG_ENABLE_DDR2_LSB) & DDR2_CONFIG_ENABLE_DDR2_MASK)
+#define DDR2_CONFIG_ENABLE_DDR2_RESET 0x0 // 0
+#define DDR2_CONFIG_ADDRESS 0x180000b8
+
+#define DDR_CONTROL_EMR3S_MSB 5
+#define DDR_CONTROL_EMR3S_LSB 5
+#define DDR_CONTROL_EMR3S_MASK 0x00000020
+#define DDR_CONTROL_EMR3S_GET(x) (((x) & DDR_CONTROL_EMR3S_MASK) >> DDR_CONTROL_EMR3S_LSB)
+#define DDR_CONTROL_EMR3S_SET(x) (((x) << DDR_CONTROL_EMR3S_LSB) & DDR_CONTROL_EMR3S_MASK)
+#define DDR_CONTROL_EMR3S_RESET 0x0 // 0
+#define DDR_CONTROL_EMR2S_MSB 4
+#define DDR_CONTROL_EMR2S_LSB 4
+#define DDR_CONTROL_EMR2S_MASK 0x00000010
+#define DDR_CONTROL_EMR2S_GET(x) (((x) & DDR_CONTROL_EMR2S_MASK) >> DDR_CONTROL_EMR2S_LSB)
+#define DDR_CONTROL_EMR2S_SET(x) (((x) << DDR_CONTROL_EMR2S_LSB) & DDR_CONTROL_EMR2S_MASK)
+#define DDR_CONTROL_EMR2S_RESET 0x0 // 0
+#define DDR_CONTROL_PREA_MSB 3
+#define DDR_CONTROL_PREA_LSB 3
+#define DDR_CONTROL_PREA_MASK 0x00000008
+#define DDR_CONTROL_PREA_GET(x) (((x) & DDR_CONTROL_PREA_MASK) >> DDR_CONTROL_PREA_LSB)
+#define DDR_CONTROL_PREA_SET(x) (((x) << DDR_CONTROL_PREA_LSB) & DDR_CONTROL_PREA_MASK)
+#define DDR_CONTROL_PREA_RESET 0x0 // 0
+#define DDR_CONTROL_REF_MSB 2
+#define DDR_CONTROL_REF_LSB 2
+#define DDR_CONTROL_REF_MASK 0x00000004
+#define DDR_CONTROL_REF_GET(x) (((x) & DDR_CONTROL_REF_MASK) >> DDR_CONTROL_REF_LSB)
+#define DDR_CONTROL_REF_SET(x) (((x) << DDR_CONTROL_REF_LSB) & DDR_CONTROL_REF_MASK)
+#define DDR_CONTROL_REF_RESET 0x0 // 0
+#define DDR_CONTROL_EMRS_MSB 1
+#define DDR_CONTROL_EMRS_LSB 1
+#define DDR_CONTROL_EMRS_MASK 0x00000002
+#define DDR_CONTROL_EMRS_GET(x) (((x) & DDR_CONTROL_EMRS_MASK) >> DDR_CONTROL_EMRS_LSB)
+#define DDR_CONTROL_EMRS_SET(x) (((x) << DDR_CONTROL_EMRS_LSB) & DDR_CONTROL_EMRS_MASK)
+#define DDR_CONTROL_EMRS_RESET 0x0 // 0
+#define DDR_CONTROL_MRS_MSB 0
+#define DDR_CONTROL_MRS_LSB 0
+#define DDR_CONTROL_MRS_MASK 0x00000001
+#define DDR_CONTROL_MRS_GET(x) (((x) & DDR_CONTROL_MRS_MASK) >> DDR_CONTROL_MRS_LSB)
+#define DDR_CONTROL_MRS_SET(x) (((x) << DDR_CONTROL_MRS_LSB) & DDR_CONTROL_MRS_MASK)
+#define DDR_CONTROL_MRS_RESET 0x0 // 0
+#define DDR_CONTROL_ADDRESS 0x18000010
+
+#define DDR_CONFIG_CAS_LATENCY_MSB_MSB 31
+#define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31
+#define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000
+#define DDR_CONFIG_CAS_LATENCY_MSB_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) >> DDR_CONFIG_CAS_LATENCY_MSB_LSB)
+#define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK)
+#define DDR_CONFIG_CAS_LATENCY_MSB_RESET 0x0 // 0
+#define DDR_CONFIG_OPEN_PAGE_MSB 30
+#define DDR_CONFIG_OPEN_PAGE_LSB 30
+#define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000
+#define DDR_CONFIG_OPEN_PAGE_GET(x) (((x) & DDR_CONFIG_OPEN_PAGE_MASK) >> DDR_CONFIG_OPEN_PAGE_LSB)
+#define DDR_CONFIG_OPEN_PAGE_SET(x) (((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK)
+#define DDR_CONFIG_OPEN_PAGE_RESET 0x1 // 1
+#define DDR_CONFIG_CAS_LATENCY_MSB 29
+#define DDR_CONFIG_CAS_LATENCY_LSB 27
+#define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000
+#define DDR_CONFIG_CAS_LATENCY_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MASK) >> DDR_CONFIG_CAS_LATENCY_LSB)
+#define DDR_CONFIG_CAS_LATENCY_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK)
+#define DDR_CONFIG_CAS_LATENCY_RESET 0x6 // 6
+#define DDR_CONFIG_TMRD_MSB 26
+#define DDR_CONFIG_TMRD_LSB 23
+#define DDR_CONFIG_TMRD_MASK 0x07800000
+#define DDR_CONFIG_TMRD_GET(x) (((x) & DDR_CONFIG_TMRD_MASK) >> DDR_CONFIG_TMRD_LSB)
+#define DDR_CONFIG_TMRD_SET(x) (((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK)
+#define DDR_CONFIG_TMRD_RESET 0xf // 15
+#define DDR_CONFIG_TRFC_MSB 22
+#define DDR_CONFIG_TRFC_LSB 17
+#define DDR_CONFIG_TRFC_MASK 0x007e0000
+#define DDR_CONFIG_TRFC_GET(x) (((x) & DDR_CONFIG_TRFC_MASK) >> DDR_CONFIG_TRFC_LSB)
+#define DDR_CONFIG_TRFC_SET(x) (((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK)
+#define DDR_CONFIG_TRFC_RESET 0x24 // 36
+#define DDR_CONFIG_TRRD_MSB 16
+#define DDR_CONFIG_TRRD_LSB 13
+#define DDR_CONFIG_TRRD_MASK 0x0001e000
+#define DDR_CONFIG_TRRD_GET(x) (((x) & DDR_CONFIG_TRRD_MASK) >> DDR_CONFIG_TRRD_LSB)
+#define DDR_CONFIG_TRRD_SET(x) (((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK)
+#define DDR_CONFIG_TRRD_RESET 0x4 // 4
+#define DDR_CONFIG_TRP_MSB 12
+#define DDR_CONFIG_TRP_LSB 9
+#define DDR_CONFIG_TRP_MASK 0x00001e00
+#define DDR_CONFIG_TRP_GET(x) (((x) & DDR_CONFIG_TRP_MASK) >> DDR_CONFIG_TRP_LSB)
+#define DDR_CONFIG_TRP_SET(x) (((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK)
+#define DDR_CONFIG_TRP_RESET 0x6 // 6
+#define DDR_CONFIG_TRCD_MSB 8
+#define DDR_CONFIG_TRCD_LSB 5
+#define DDR_CONFIG_TRCD_MASK 0x000001e0
+#define DDR_CONFIG_TRCD_GET(x) (((x) & DDR_CONFIG_TRCD_MASK) >> DDR_CONFIG_TRCD_LSB)
+#define DDR_CONFIG_TRCD_SET(x) (((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK)
+#define DDR_CONFIG_TRCD_RESET 0x6 // 6
+#define DDR_CONFIG_TRAS_MSB 4
+#define DDR_CONFIG_TRAS_LSB 0
+#define DDR_CONFIG_TRAS_MASK 0x0000001f
+#define DDR_CONFIG_TRAS_GET(x) (((x) & DDR_CONFIG_TRAS_MASK) >> DDR_CONFIG_TRAS_LSB)
+#define DDR_CONFIG_TRAS_SET(x) (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
+#define DDR_CONFIG_TRAS_RESET 0x10 // 16
+#define DDR_CONFIG_ADDRESS 0x18000000
+
+#define DDR_CONFIG2_HALF_WIDTH_LOW_MSB 31
+#define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31
+#define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000
+#define DDR_CONFIG2_HALF_WIDTH_LOW_GET(x) (((x) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) >> DDR_CONFIG2_HALF_WIDTH_LOW_LSB)
+#define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) (((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK)
+#define DDR_CONFIG2_HALF_WIDTH_LOW_RESET 0x1 // 1
+#define DDR_CONFIG2_SWAP_A26_A27_MSB 30
+#define DDR_CONFIG2_SWAP_A26_A27_LSB 30
+#define DDR_CONFIG2_SWAP_A26_A27_MASK 0x40000000
+#define DDR_CONFIG2_SWAP_A26_A27_GET(x) (((x) & DDR_CONFIG2_SWAP_A26_A27_MASK) >> DDR_CONFIG2_SWAP_A26_A27_LSB)
+#define DDR_CONFIG2_SWAP_A26_A27_SET(x) (((x) << DDR_CONFIG2_SWAP_A26_A27_LSB) & DDR_CONFIG2_SWAP_A26_A27_MASK)
+#define DDR_CONFIG2_SWAP_A26_A27_RESET 0x0 // 0
+#define DDR_CONFIG2_GATE_OPEN_LATENCY_MSB 29
+#define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26
+#define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000
+#define DDR_CONFIG2_GATE_OPEN_LATENCY_GET(x) (((x) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) >> DDR_CONFIG2_GATE_OPEN_LATENCY_LSB)
+#define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) (((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK)
+#define DDR_CONFIG2_GATE_OPEN_LATENCY_RESET 0x6 // 6
+#define DDR_CONFIG2_TWTR_MSB 25
+#define DDR_CONFIG2_TWTR_LSB 21
+#define DDR_CONFIG2_TWTR_MASK 0x03e00000
+#define DDR_CONFIG2_TWTR_GET(x) (((x) & DDR_CONFIG2_TWTR_MASK) >> DDR_CONFIG2_TWTR_LSB)
+#define DDR_CONFIG2_TWTR_SET(x) (((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK)
+#define DDR_CONFIG2_TWTR_RESET 0xe // 14
+#define DDR_CONFIG2_TRTP_MSB 20
+#define DDR_CONFIG2_TRTP_LSB 17
+#define DDR_CONFIG2_TRTP_MASK 0x001e0000
+#define DDR_CONFIG2_TRTP_GET(x) (((x) & DDR_CONFIG2_TRTP_MASK) >> DDR_CONFIG2_TRTP_LSB)
+#define DDR_CONFIG2_TRTP_SET(x) (((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK)
+#define DDR_CONFIG2_TRTP_RESET 0x8 // 8
+#define DDR_CONFIG2_TRTW_MSB 16
+#define DDR_CONFIG2_TRTW_LSB 12
+#define DDR_CONFIG2_TRTW_MASK 0x0001f000
+#define DDR_CONFIG2_TRTW_GET(x) (((x) & DDR_CONFIG2_TRTW_MASK) >> DDR_CONFIG2_TRTW_LSB)
+#define DDR_CONFIG2_TRTW_SET(x) (((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK)
+#define DDR_CONFIG2_TRTW_RESET 0x10 // 16
+#define DDR_CONFIG2_TWR_MSB 11
+#define DDR_CONFIG2_TWR_LSB 8
+#define DDR_CONFIG2_TWR_MASK 0x00000f00
+#define DDR_CONFIG2_TWR_GET(x) (((x) & DDR_CONFIG2_TWR_MASK) >> DDR_CONFIG2_TWR_LSB)
+#define DDR_CONFIG2_TWR_SET(x) (((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK)
+#define DDR_CONFIG2_TWR_RESET 0x6 // 6
+#define DDR_CONFIG2_CKE_MSB 7
+#define DDR_CONFIG2_CKE_LSB 7
+#define DDR_CONFIG2_CKE_MASK 0x00000080
+#define DDR_CONFIG2_CKE_GET(x) (((x) & DDR_CONFIG2_CKE_MASK) >> DDR_CONFIG2_CKE_LSB)
+#define DDR_CONFIG2_CKE_SET(x) (((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK)
+#define DDR_CONFIG2_CKE_RESET 0x0 // 0
+#define DDR_CONFIG2_PHASE_SELECT_MSB 6
+#define DDR_CONFIG2_PHASE_SELECT_LSB 6
+#define DDR_CONFIG2_PHASE_SELECT_MASK 0x00000040
+#define DDR_CONFIG2_PHASE_SELECT_GET(x) (((x) & DDR_CONFIG2_PHASE_SELECT_MASK) >> DDR_CONFIG2_PHASE_SELECT_LSB)
+#define DDR_CONFIG2_PHASE_SELECT_SET(x) (((x) << DDR_CONFIG2_PHASE_SELECT_LSB) & DDR_CONFIG2_PHASE_SELECT_MASK)
+#define DDR_CONFIG2_PHASE_SELECT_RESET 0x0 // 0
+#define DDR_CONFIG2_CNTL_OE_EN_MSB 5
+#define DDR_CONFIG2_CNTL_OE_EN_LSB 5
+#define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020
+#define DDR_CONFIG2_CNTL_OE_EN_GET(x) (((x) & DDR_CONFIG2_CNTL_OE_EN_MASK) >> DDR_CONFIG2_CNTL_OE_EN_LSB)
+#define DDR_CONFIG2_CNTL_OE_EN_SET(x) (((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK)
+#define DDR_CONFIG2_CNTL_OE_EN_RESET 0x1 // 1
+#define DDR_CONFIG2_BURST_TYPE_MSB 4
+#define DDR_CONFIG2_BURST_TYPE_LSB 4
+#define DDR_CONFIG2_BURST_TYPE_MASK 0x00000010
+#define DDR_CONFIG2_BURST_TYPE_GET(x) (((x) & DDR_CONFIG2_BURST_TYPE_MASK) >> DDR_CONFIG2_BURST_TYPE_LSB)
+#define DDR_CONFIG2_BURST_TYPE_SET(x) (((x) << DDR_CONFIG2_BURST_TYPE_LSB) & DDR_CONFIG2_BURST_TYPE_MASK)
+#define DDR_CONFIG2_BURST_TYPE_RESET 0x0 // 0
+#define DDR_CONFIG2_BURST_LENGTH_MSB 3
+#define DDR_CONFIG2_BURST_LENGTH_LSB 0
+#define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f
+#define DDR_CONFIG2_BURST_LENGTH_GET(x) (((x) & DDR_CONFIG2_BURST_LENGTH_MASK) >> DDR_CONFIG2_BURST_LENGTH_LSB)
+#define DDR_CONFIG2_BURST_LENGTH_SET(x) (((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK)
+#define DDR_CONFIG2_BURST_LENGTH_RESET 0x8 // 8
+#define DDR_CONFIG2_ADDRESS 0x18000004
+
+#define DDR_CONFIG_3_SPARE_MSB 31
+#define DDR_CONFIG_3_SPARE_LSB 4
+#define DDR_CONFIG_3_SPARE_MASK 0xfffffff0
+#define DDR_CONFIG_3_SPARE_GET(x) (((x) & DDR_CONFIG_3_SPARE_MASK) >> DDR_CONFIG_3_SPARE_LSB)
+#define DDR_CONFIG_3_SPARE_SET(x) (((x) << DDR_CONFIG_3_SPARE_LSB) & DDR_CONFIG_3_SPARE_MASK)
+#define DDR_CONFIG_3_SPARE_RESET 0x0 // 0
+#define DDR_CONFIG_3_TWR_MSB_MSB 3
+#define DDR_CONFIG_3_TWR_MSB_LSB 3
+#define DDR_CONFIG_3_TWR_MSB_MASK 0x00000008
+#define DDR_CONFIG_3_TWR_MSB_GET(x) (((x) & DDR_CONFIG_3_TWR_MSB_MASK) >> DDR_CONFIG_3_TWR_MSB_LSB)
+#define DDR_CONFIG_3_TWR_MSB_SET(x) (((x) << DDR_CONFIG_3_TWR_MSB_LSB) & DDR_CONFIG_3_TWR_MSB_MASK)
+#define DDR_CONFIG_3_TWR_MSB_RESET 0x0 // 0
+#define DDR_CONFIG_3_TRAS_MSB_MSB 2
+#define DDR_CONFIG_3_TRAS_MSB_LSB 2
+#define DDR_CONFIG_3_TRAS_MSB_MASK 0x00000004
+#define DDR_CONFIG_3_TRAS_MSB_GET(x) (((x) & DDR_CONFIG_3_TRAS_MSB_MASK) >> DDR_CONFIG_3_TRAS_MSB_LSB)
+#define DDR_CONFIG_3_TRAS_MSB_SET(x) (((x) << DDR_CONFIG_3_TRAS_MSB_LSB) & DDR_CONFIG_3_TRAS_MSB_MASK)
+#define DDR_CONFIG_3_TRAS_MSB_RESET 0x0 // 0
+#define DDR_CONFIG_3_TRFC_LSB_MSB 1
+#define DDR_CONFIG_3_TRFC_LSB_LSB 0
+#define DDR_CONFIG_3_TRFC_LSB_MASK 0x00000003
+#define DDR_CONFIG_3_TRFC_LSB_GET(x) (((x) & DDR_CONFIG_3_TRFC_LSB_MASK) >> DDR_CONFIG_3_TRFC_LSB_LSB)
+#define DDR_CONFIG_3_TRFC_LSB_SET(x) (((x) << DDR_CONFIG_3_TRFC_LSB_LSB) & DDR_CONFIG_3_TRFC_LSB_MASK)
+#define DDR_CONFIG_3_TRFC_LSB_RESET 0x0 // 0
+#define DDR_CONFIG_3_ADDRESS 0x1800015c
+
+#define DDR_MODE_REGISTER_VALUE_MSB 13
+#define DDR_MODE_REGISTER_VALUE_LSB 0
+#define DDR_MODE_REGISTER_VALUE_MASK 0x00003fff
+#define DDR_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_MODE_REGISTER_VALUE_MASK) >> DDR_MODE_REGISTER_VALUE_LSB)
+#define DDR_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_MODE_REGISTER_VALUE_LSB) & DDR_MODE_REGISTER_VALUE_MASK)
+#define DDR_MODE_REGISTER_VALUE_RESET 0x133 // 307
+#define DDR_MODE_REGISTER_ADDRESS 0x18000008
+
+#define DDR_EXTENDED_MODE_REGISTER_VALUE_MSB 13
+#define DDR_EXTENDED_MODE_REGISTER_VALUE_LSB 0
+#define DDR_EXTENDED_MODE_REGISTER_VALUE_MASK 0x00003fff
+#define DDR_EXTENDED_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK) >> DDR_EXTENDED_MODE_REGISTER_VALUE_LSB)
+#define DDR_EXTENDED_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_EXTENDED_MODE_REGISTER_VALUE_LSB) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK)
+#define DDR_EXTENDED_MODE_REGISTER_VALUE_RESET 0x2 // 2
+#define DDR_EXTENDED_MODE_REGISTER_ADDRESS 0x1800000c
+
+#define DDR_REFRESH_ENABLE_MSB 14
+#define DDR_REFRESH_ENABLE_LSB 14
+#define DDR_REFRESH_ENABLE_MASK 0x00004000
+#define DDR_REFRESH_ENABLE_GET(x) (((x) & DDR_REFRESH_ENABLE_MASK) >> DDR_REFRESH_ENABLE_LSB)
+#define DDR_REFRESH_ENABLE_SET(x) (((x) << DDR_REFRESH_ENABLE_LSB) & DDR_REFRESH_ENABLE_MASK)
+#define DDR_REFRESH_ENABLE_RESET 0x0 // 0
+#define DDR_REFRESH_PERIOD_MSB 13
+#define DDR_REFRESH_PERIOD_LSB 0
+#define DDR_REFRESH_PERIOD_MASK 0x00003fff
+#define DDR_REFRESH_PERIOD_GET(x) (((x) & DDR_REFRESH_PERIOD_MASK) >> DDR_REFRESH_PERIOD_LSB)
+#define DDR_REFRESH_PERIOD_SET(x) (((x) << DDR_REFRESH_PERIOD_LSB) & DDR_REFRESH_PERIOD_MASK)
+#define DDR_REFRESH_PERIOD_RESET 0x12c // 300
+#define DDR_REFRESH_ADDRESS 0x18000014
+
+#define BB_DPLL2_LOCAL_PLL_MSB 31
+#define BB_DPLL2_LOCAL_PLL_LSB 31
+#define BB_DPLL2_LOCAL_PLL_MASK 0x80000000
+#define BB_DPLL2_LOCAL_PLL_GET(x) (((x) & BB_DPLL2_LOCAL_PLL_MASK) >> BB_DPLL2_LOCAL_PLL_LSB)
+#define BB_DPLL2_LOCAL_PLL_SET(x) (((x) << BB_DPLL2_LOCAL_PLL_LSB) & BB_DPLL2_LOCAL_PLL_MASK)
+#define BB_DPLL2_LOCAL_PLL_RESET 0x0 // 0
+#define BB_DPLL2_KI_MSB 30
+#define BB_DPLL2_KI_LSB 29
+#define BB_DPLL2_KI_MASK 0x60000000
+#define BB_DPLL2_KI_GET(x) (((x) & BB_DPLL2_KI_MASK) >> BB_DPLL2_KI_LSB)
+#define BB_DPLL2_KI_SET(x) (((x) << BB_DPLL2_KI_LSB) & BB_DPLL2_KI_MASK)
+#define BB_DPLL2_KI_RESET 0x2 // 2
+#define BB_DPLL2_KD_MSB 28
+#define BB_DPLL2_KD_LSB 25
+#define BB_DPLL2_KD_MASK 0x1e000000
+#define BB_DPLL2_KD_GET(x) (((x) & BB_DPLL2_KD_MASK) >> BB_DPLL2_KD_LSB)
+#define BB_DPLL2_KD_SET(x) (((x) << BB_DPLL2_KD_LSB) & BB_DPLL2_KD_MASK)
+#define BB_DPLL2_KD_RESET 0xa // 10
+#define BB_DPLL2_EN_NEGTRIG_MSB 24
+#define BB_DPLL2_EN_NEGTRIG_LSB 24
+#define BB_DPLL2_EN_NEGTRIG_MASK 0x01000000
+#define BB_DPLL2_EN_NEGTRIG_GET(x) (((x) & BB_DPLL2_EN_NEGTRIG_MASK) >> BB_DPLL2_EN_NEGTRIG_LSB)
+#define BB_DPLL2_EN_NEGTRIG_SET(x) (((x) << BB_DPLL2_EN_NEGTRIG_LSB) & BB_DPLL2_EN_NEGTRIG_MASK)
+#define BB_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
+#define BB_DPLL2_SEL_1SDM_MSB 23
+#define BB_DPLL2_SEL_1SDM_LSB 23
+#define BB_DPLL2_SEL_1SDM_MASK 0x00800000
+#define BB_DPLL2_SEL_1SDM_GET(x) (((x) & BB_DPLL2_SEL_1SDM_MASK) >> BB_DPLL2_SEL_1SDM_LSB)
+#define BB_DPLL2_SEL_1SDM_SET(x) (((x) << BB_DPLL2_SEL_1SDM_LSB) & BB_DPLL2_SEL_1SDM_MASK)
+#define BB_DPLL2_SEL_1SDM_RESET 0x0 // 0
+#define BB_DPLL2_PLL_PWD_MSB 22
+#define BB_DPLL2_PLL_PWD_LSB 22
+#define BB_DPLL2_PLL_PWD_MASK 0x00400000
+#define BB_DPLL2_PLL_PWD_GET(x) (((x) & BB_DPLL2_PLL_PWD_MASK) >> BB_DPLL2_PLL_PWD_LSB)
+#define BB_DPLL2_PLL_PWD_SET(x) (((x) << BB_DPLL2_PLL_PWD_LSB) & BB_DPLL2_PLL_PWD_MASK)
+#define BB_DPLL2_PLL_PWD_RESET 0x1 // 1
+#define BB_DPLL2_OUTDIV_MSB 21
+#define BB_DPLL2_OUTDIV_LSB 19
+#define BB_DPLL2_OUTDIV_MASK 0x00380000
+#define BB_DPLL2_OUTDIV_GET(x) (((x) & BB_DPLL2_OUTDIV_MASK) >> BB_DPLL2_OUTDIV_LSB)
+#define BB_DPLL2_OUTDIV_SET(x) (((x) << BB_DPLL2_OUTDIV_LSB) & BB_DPLL2_OUTDIV_MASK)
+#define BB_DPLL2_OUTDIV_RESET 0x1 // 1
+#define BB_DPLL2_PHASE_SHIFT_MSB 18
+#define BB_DPLL2_PHASE_SHIFT_LSB 12
+#define BB_DPLL2_PHASE_SHIFT_MASK 0x0007f000
+#define BB_DPLL2_PHASE_SHIFT_GET(x) (((x) & BB_DPLL2_PHASE_SHIFT_MASK) >> BB_DPLL2_PHASE_SHIFT_LSB)
+#define BB_DPLL2_PHASE_SHIFT_SET(x) (((x) << BB_DPLL2_PHASE_SHIFT_LSB) & BB_DPLL2_PHASE_SHIFT_MASK)
+#define BB_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
+#define BB_DPLL2_TESTIN_MSB 11
+#define BB_DPLL2_TESTIN_LSB 2
+#define BB_DPLL2_TESTIN_MASK 0x00000ffc
+#define BB_DPLL2_TESTIN_GET(x) (((x) & BB_DPLL2_TESTIN_MASK) >> BB_DPLL2_TESTIN_LSB)
+#define BB_DPLL2_TESTIN_SET(x) (((x) << BB_DPLL2_TESTIN_LSB) & BB_DPLL2_TESTIN_MASK)
+#define BB_DPLL2_TESTIN_RESET 0x0 // 0
+#define BB_DPLL2_SEL_COUNT_MSB 1
+#define BB_DPLL2_SEL_COUNT_LSB 1
+#define BB_DPLL2_SEL_COUNT_MASK 0x00000002
+#define BB_DPLL2_SEL_COUNT_GET(x) (((x) & BB_DPLL2_SEL_COUNT_MASK) >> BB_DPLL2_SEL_COUNT_LSB)
+#define BB_DPLL2_SEL_COUNT_SET(x) (((x) << BB_DPLL2_SEL_COUNT_LSB) & BB_DPLL2_SEL_COUNT_MASK)
+#define BB_DPLL2_SEL_COUNT_RESET 0x0 // 0
+#define BB_DPLL2_RESET_TEST_MSB 0
+#define BB_DPLL2_RESET_TEST_LSB 0
+#define BB_DPLL2_RESET_TEST_MASK 0x00000001
+#define BB_DPLL2_RESET_TEST_GET(x) (((x) & BB_DPLL2_RESET_TEST_MASK) >> BB_DPLL2_RESET_TEST_LSB)
+#define BB_DPLL2_RESET_TEST_SET(x) (((x) << BB_DPLL2_RESET_TEST_LSB) & BB_DPLL2_RESET_TEST_MASK)
+#define BB_DPLL2_RESET_TEST_RESET 0x0 // 0
+#define BB_DPLL2_ADDRESS 0x18116184
+
+#define PCIe_DPLL2_LOCAL_PLL_MSB 31
+#define PCIe_DPLL2_LOCAL_PLL_LSB 31
+#define PCIe_DPLL2_LOCAL_PLL_MASK 0x80000000
+#define PCIe_DPLL2_LOCAL_PLL_GET(x) (((x) & PCIe_DPLL2_LOCAL_PLL_MASK) >> PCIe_DPLL2_LOCAL_PLL_LSB)
+#define PCIe_DPLL2_LOCAL_PLL_SET(x) (((x) << PCIe_DPLL2_LOCAL_PLL_LSB) & PCIe_DPLL2_LOCAL_PLL_MASK)
+#define PCIe_DPLL2_LOCAL_PLL_RESET 0x0 // 0
+#define PCIe_DPLL2_KI_MSB 30
+#define PCIe_DPLL2_KI_LSB 29
+#define PCIe_DPLL2_KI_MASK 0x60000000
+#define PCIe_DPLL2_KI_GET(x) (((x) & PCIe_DPLL2_KI_MASK) >> PCIe_DPLL2_KI_LSB)
+#define PCIe_DPLL2_KI_SET(x) (((x) << PCIe_DPLL2_KI_LSB) & PCIe_DPLL2_KI_MASK)
+#define PCIe_DPLL2_KI_RESET 0x2 // 2
+#define PCIe_DPLL2_KD_MSB 28
+#define PCIe_DPLL2_KD_LSB 25
+#define PCIe_DPLL2_KD_MASK 0x1e000000
+#define PCIe_DPLL2_KD_GET(x) (((x) & PCIe_DPLL2_KD_MASK) >> PCIe_DPLL2_KD_LSB)
+#define PCIe_DPLL2_KD_SET(x) (((x) << PCIe_DPLL2_KD_LSB) & PCIe_DPLL2_KD_MASK)
+#define PCIe_DPLL2_KD_RESET 0xa // 10
+#define PCIe_DPLL2_EN_NEGTRIG_MSB 24
+#define PCIe_DPLL2_EN_NEGTRIG_LSB 24
+#define PCIe_DPLL2_EN_NEGTRIG_MASK 0x01000000
+#define PCIe_DPLL2_EN_NEGTRIG_GET(x) (((x) & PCIe_DPLL2_EN_NEGTRIG_MASK) >> PCIe_DPLL2_EN_NEGTRIG_LSB)
+#define PCIe_DPLL2_EN_NEGTRIG_SET(x) (((x) << PCIe_DPLL2_EN_NEGTRIG_LSB) & PCIe_DPLL2_EN_NEGTRIG_MASK)
+#define PCIe_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
+#define PCIe_DPLL2_SEL_1SDM_MSB 23
+#define PCIe_DPLL2_SEL_1SDM_LSB 23
+#define PCIe_DPLL2_SEL_1SDM_MASK 0x00800000
+#define PCIe_DPLL2_SEL_1SDM_GET(x) (((x) & PCIe_DPLL2_SEL_1SDM_MASK) >> PCIe_DPLL2_SEL_1SDM_LSB)
+#define PCIe_DPLL2_SEL_1SDM_SET(x) (((x) << PCIe_DPLL2_SEL_1SDM_LSB) & PCIe_DPLL2_SEL_1SDM_MASK)
+#define PCIe_DPLL2_SEL_1SDM_RESET 0x0 // 0
+#define PCIe_DPLL2_PLL_PWD_MSB 22
+#define PCIe_DPLL2_PLL_PWD_LSB 22
+#define PCIe_DPLL2_PLL_PWD_MASK 0x00400000
+#define PCIe_DPLL2_PLL_PWD_GET(x) (((x) & PCIe_DPLL2_PLL_PWD_MASK) >> PCIe_DPLL2_PLL_PWD_LSB)
+#define PCIe_DPLL2_PLL_PWD_SET(x) (((x) << PCIe_DPLL2_PLL_PWD_LSB) & PCIe_DPLL2_PLL_PWD_MASK)
+#define PCIe_DPLL2_PLL_PWD_RESET 0x1 // 1
+#define PCIe_DPLL2_OUTDIV_MSB 21
+#define PCIe_DPLL2_OUTDIV_LSB 19
+#define PCIe_DPLL2_OUTDIV_MASK 0x00380000
+#define PCIe_DPLL2_OUTDIV_GET(x) (((x) & PCIe_DPLL2_OUTDIV_MASK) >> PCIe_DPLL2_OUTDIV_LSB)
+#define PCIe_DPLL2_OUTDIV_SET(x) (((x) << PCIe_DPLL2_OUTDIV_LSB) & PCIe_DPLL2_OUTDIV_MASK)
+#define PCIe_DPLL2_OUTDIV_RESET 0x1 // 1
+#define PCIe_DPLL2_PHASE_SHIFT_MSB 18
+#define PCIe_DPLL2_PHASE_SHIFT_LSB 12
+#define PCIe_DPLL2_PHASE_SHIFT_MASK 0x0007f000
+#define PCIe_DPLL2_PHASE_SHIFT_GET(x) (((x) & PCIe_DPLL2_PHASE_SHIFT_MASK) >> PCIe_DPLL2_PHASE_SHIFT_LSB)
+#define PCIe_DPLL2_PHASE_SHIFT_SET(x) (((x) << PCIe_DPLL2_PHASE_SHIFT_LSB) & PCIe_DPLL2_PHASE_SHIFT_MASK)
+#define PCIe_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
+#define PCIe_DPLL2_TESTIN_MSB 11
+#define PCIe_DPLL2_TESTIN_LSB 2
+#define PCIe_DPLL2_TESTIN_MASK 0x00000ffc
+#define PCIe_DPLL2_TESTIN_GET(x) (((x) & PCIe_DPLL2_TESTIN_MASK) >> PCIe_DPLL2_TESTIN_LSB)
+#define PCIe_DPLL2_TESTIN_SET(x) (((x) << PCIe_DPLL2_TESTIN_LSB) & PCIe_DPLL2_TESTIN_MASK)
+#define PCIe_DPLL2_TESTIN_RESET 0x0 // 0
+#define PCIe_DPLL2_SEL_COUNT_MSB 1
+#define PCIe_DPLL2_SEL_COUNT_LSB 1
+#define PCIe_DPLL2_SEL_COUNT_MASK 0x00000002
+#define PCIe_DPLL2_SEL_COUNT_GET(x) (((x) & PCIe_DPLL2_SEL_COUNT_MASK) >> PCIe_DPLL2_SEL_COUNT_LSB)
+#define PCIe_DPLL2_SEL_COUNT_SET(x) (((x) << PCIe_DPLL2_SEL_COUNT_LSB) & PCIe_DPLL2_SEL_COUNT_MASK)
+#define PCIe_DPLL2_SEL_COUNT_RESET 0x0 // 0
+#define PCIe_DPLL2_RESET_TEST_MSB 0
+#define PCIe_DPLL2_RESET_TEST_LSB 0
+#define PCIe_DPLL2_RESET_TEST_MASK 0x00000001
+#define PCIe_DPLL2_RESET_TEST_GET(x) (((x) & PCIe_DPLL2_RESET_TEST_MASK) >> PCIe_DPLL2_RESET_TEST_LSB)
+#define PCIe_DPLL2_RESET_TEST_SET(x) (((x) << PCIe_DPLL2_RESET_TEST_LSB) & PCIe_DPLL2_RESET_TEST_MASK)
+#define PCIe_DPLL2_RESET_TEST_RESET 0x0 // 0
+#define PCIe_DPLL2_ADDRESS 0x18116c04
+
+#define DDR_DPLL2_LOCAL_PLL_MSB 31
+#define DDR_DPLL2_LOCAL_PLL_LSB 31
+#define DDR_DPLL2_LOCAL_PLL_MASK 0x80000000
+#define DDR_DPLL2_LOCAL_PLL_GET(x) (((x) & DDR_DPLL2_LOCAL_PLL_MASK) >> DDR_DPLL2_LOCAL_PLL_LSB)
+#define DDR_DPLL2_LOCAL_PLL_SET(x) (((x) << DDR_DPLL2_LOCAL_PLL_LSB) & DDR_DPLL2_LOCAL_PLL_MASK)
+#define DDR_DPLL2_LOCAL_PLL_RESET 0x0 // 0
+#define DDR_DPLL2_KI_MSB 30
+#define DDR_DPLL2_KI_LSB 29
+#define DDR_DPLL2_KI_MASK 0x60000000
+#define DDR_DPLL2_KI_GET(x) (((x) & DDR_DPLL2_KI_MASK) >> DDR_DPLL2_KI_LSB)
+#define DDR_DPLL2_KI_SET(x) (((x) << DDR_DPLL2_KI_LSB) & DDR_DPLL2_KI_MASK)
+#define DDR_DPLL2_KI_RESET 0x2 // 2
+#define DDR_DPLL2_KD_MSB 28
+#define DDR_DPLL2_KD_LSB 25
+#define DDR_DPLL2_KD_MASK 0x1e000000
+#define DDR_DPLL2_KD_GET(x) (((x) & DDR_DPLL2_KD_MASK) >> DDR_DPLL2_KD_LSB)
+#define DDR_DPLL2_KD_SET(x) (((x) << DDR_DPLL2_KD_LSB) & DDR_DPLL2_KD_MASK)
+#define DDR_DPLL2_KD_RESET 0xa // 10
+#define DDR_DPLL2_EN_NEGTRIG_MSB 24
+#define DDR_DPLL2_EN_NEGTRIG_LSB 24
+#define DDR_DPLL2_EN_NEGTRIG_MASK 0x01000000
+#define DDR_DPLL2_EN_NEGTRIG_GET(x) (((x) & DDR_DPLL2_EN_NEGTRIG_MASK) >> DDR_DPLL2_EN_NEGTRIG_LSB)
+#define DDR_DPLL2_EN_NEGTRIG_SET(x) (((x) << DDR_DPLL2_EN_NEGTRIG_LSB) & DDR_DPLL2_EN_NEGTRIG_MASK)
+#define DDR_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
+#define DDR_DPLL2_SEL_1SDM_MSB 23
+#define DDR_DPLL2_SEL_1SDM_LSB 23
+#define DDR_DPLL2_SEL_1SDM_MASK 0x00800000
+#define DDR_DPLL2_SEL_1SDM_GET(x) (((x) & DDR_DPLL2_SEL_1SDM_MASK) >> DDR_DPLL2_SEL_1SDM_LSB)
+#define DDR_DPLL2_SEL_1SDM_SET(x) (((x) << DDR_DPLL2_SEL_1SDM_LSB) & DDR_DPLL2_SEL_1SDM_MASK)
+#define DDR_DPLL2_SEL_1SDM_RESET 0x0 // 0
+#define DDR_DPLL2_PLL_PWD_MSB 22
+#define DDR_DPLL2_PLL_PWD_LSB 22
+#define DDR_DPLL2_PLL_PWD_MASK 0x00400000
+#define DDR_DPLL2_PLL_PWD_GET(x) (((x) & DDR_DPLL2_PLL_PWD_MASK) >> DDR_DPLL2_PLL_PWD_LSB)
+#define DDR_DPLL2_PLL_PWD_SET(x) (((x) << DDR_DPLL2_PLL_PWD_LSB) & DDR_DPLL2_PLL_PWD_MASK)
+#define DDR_DPLL2_PLL_PWD_RESET 0x1 // 1
+#define DDR_DPLL2_OUTDIV_MSB 21
+#define DDR_DPLL2_OUTDIV_LSB 19
+#define DDR_DPLL2_OUTDIV_MASK 0x00380000
+#define DDR_DPLL2_OUTDIV_GET(x) (((x) & DDR_DPLL2_OUTDIV_MASK) >> DDR_DPLL2_OUTDIV_LSB)
+#define DDR_DPLL2_OUTDIV_SET(x) (((x) << DDR_DPLL2_OUTDIV_LSB) & DDR_DPLL2_OUTDIV_MASK)
+#define DDR_DPLL2_OUTDIV_RESET 0x1 // 1
+#define DDR_DPLL2_PHASE_SHIFT_MSB 18
+#define DDR_DPLL2_PHASE_SHIFT_LSB 12
+#define DDR_DPLL2_PHASE_SHIFT_MASK 0x0007f000
+#define DDR_DPLL2_PHASE_SHIFT_GET(x) (((x) & DDR_DPLL2_PHASE_SHIFT_MASK) >> DDR_DPLL2_PHASE_SHIFT_LSB)
+#define DDR_DPLL2_PHASE_SHIFT_SET(x) (((x) << DDR_DPLL2_PHASE_SHIFT_LSB) & DDR_DPLL2_PHASE_SHIFT_MASK)
+#define DDR_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
+#define DDR_DPLL2_TESTIN_MSB 11
+#define DDR_DPLL2_TESTIN_LSB 2
+#define DDR_DPLL2_TESTIN_MASK 0x00000ffc
+#define DDR_DPLL2_TESTIN_GET(x) (((x) & DDR_DPLL2_TESTIN_MASK) >> DDR_DPLL2_TESTIN_LSB)
+#define DDR_DPLL2_TESTIN_SET(x) (((x) << DDR_DPLL2_TESTIN_LSB) & DDR_DPLL2_TESTIN_MASK)
+#define DDR_DPLL2_TESTIN_RESET 0x0 // 0
+#define DDR_DPLL2_SEL_COUNT_MSB 1
+#define DDR_DPLL2_SEL_COUNT_LSB 1
+#define DDR_DPLL2_SEL_COUNT_MASK 0x00000002
+#define DDR_DPLL2_SEL_COUNT_GET(x) (((x) & DDR_DPLL2_SEL_COUNT_MASK) >> DDR_DPLL2_SEL_COUNT_LSB)
+#define DDR_DPLL2_SEL_COUNT_SET(x) (((x) << DDR_DPLL2_SEL_COUNT_LSB) & DDR_DPLL2_SEL_COUNT_MASK)
+#define DDR_DPLL2_SEL_COUNT_RESET 0x0 // 0
+#define DDR_DPLL2_RESET_TEST_MSB 0
+#define DDR_DPLL2_RESET_TEST_LSB 0
+#define DDR_DPLL2_RESET_TEST_MASK 0x00000001
+#define DDR_DPLL2_RESET_TEST_GET(x) (((x) & DDR_DPLL2_RESET_TEST_MASK) >> DDR_DPLL2_RESET_TEST_LSB)
+#define DDR_DPLL2_RESET_TEST_SET(x) (((x) << DDR_DPLL2_RESET_TEST_LSB) & DDR_DPLL2_RESET_TEST_MASK)
+#define DDR_DPLL2_RESET_TEST_RESET 0x0 // 0
+#define DDR_DPLL2_ADDRESS 0x18116244
+
+#define CPU_DPLL2_LOCAL_PLL_MSB 31
+#define CPU_DPLL2_LOCAL_PLL_LSB 31
+#define CPU_DPLL2_LOCAL_PLL_MASK 0x80000000
+#define CPU_DPLL2_LOCAL_PLL_GET(x) (((x) & CPU_DPLL2_LOCAL_PLL_MASK) >> CPU_DPLL2_LOCAL_PLL_LSB)
+#define CPU_DPLL2_LOCAL_PLL_SET(x) (((x) << CPU_DPLL2_LOCAL_PLL_LSB) & CPU_DPLL2_LOCAL_PLL_MASK)
+#define CPU_DPLL2_LOCAL_PLL_RESET 0x0 // 0
+#define CPU_DPLL2_KI_MSB 30
+#define CPU_DPLL2_KI_LSB 29
+#define CPU_DPLL2_KI_MASK 0x60000000
+#define CPU_DPLL2_KI_GET(x) (((x) & CPU_DPLL2_KI_MASK) >> CPU_DPLL2_KI_LSB)
+#define CPU_DPLL2_KI_SET(x) (((x) << CPU_DPLL2_KI_LSB) & CPU_DPLL2_KI_MASK)
+#define CPU_DPLL2_KI_RESET 0x2 // 2
+#define CPU_DPLL2_KD_MSB 28
+#define CPU_DPLL2_KD_LSB 25
+#define CPU_DPLL2_KD_MASK 0x1e000000
+#define CPU_DPLL2_KD_GET(x) (((x) & CPU_DPLL2_KD_MASK) >> CPU_DPLL2_KD_LSB)
+#define CPU_DPLL2_KD_SET(x) (((x) << CPU_DPLL2_KD_LSB) & CPU_DPLL2_KD_MASK)
+#define CPU_DPLL2_KD_RESET 0xa // 10
+#define CPU_DPLL2_EN_NEGTRIG_MSB 24
+#define CPU_DPLL2_EN_NEGTRIG_LSB 24
+#define CPU_DPLL2_EN_NEGTRIG_MASK 0x01000000
+#define CPU_DPLL2_EN_NEGTRIG_GET(x) (((x) & CPU_DPLL2_EN_NEGTRIG_MASK) >> CPU_DPLL2_EN_NEGTRIG_LSB)
+#define CPU_DPLL2_EN_NEGTRIG_SET(x) (((x) << CPU_DPLL2_EN_NEGTRIG_LSB) & CPU_DPLL2_EN_NEGTRIG_MASK)
+#define CPU_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
+#define CPU_DPLL2_SEL_1SDM_MSB 23
+#define CPU_DPLL2_SEL_1SDM_LSB 23
+#define CPU_DPLL2_SEL_1SDM_MASK 0x00800000
+#define CPU_DPLL2_SEL_1SDM_GET(x) (((x) & CPU_DPLL2_SEL_1SDM_MASK) >> CPU_DPLL2_SEL_1SDM_LSB)
+#define CPU_DPLL2_SEL_1SDM_SET(x) (((x) << CPU_DPLL2_SEL_1SDM_LSB) & CPU_DPLL2_SEL_1SDM_MASK)
+#define CPU_DPLL2_SEL_1SDM_RESET 0x0 // 0
+#define CPU_DPLL2_PLL_PWD_MSB 22
+#define CPU_DPLL2_PLL_PWD_LSB 22
+#define CPU_DPLL2_PLL_PWD_MASK 0x00400000
+#define CPU_DPLL2_PLL_PWD_GET(x) (((x) & CPU_DPLL2_PLL_PWD_MASK) >> CPU_DPLL2_PLL_PWD_LSB)
+#define CPU_DPLL2_PLL_PWD_SET(x) (((x) << CPU_DPLL2_PLL_PWD_LSB) & CPU_DPLL2_PLL_PWD_MASK)
+#define CPU_DPLL2_PLL_PWD_RESET 0x1 // 1
+#define CPU_DPLL2_OUTDIV_MSB 21
+#define CPU_DPLL2_OUTDIV_LSB 19
+#define CPU_DPLL2_OUTDIV_MASK 0x00380000
+#define CPU_DPLL2_OUTDIV_GET(x) (((x) & CPU_DPLL2_OUTDIV_MASK) >> CPU_DPLL2_OUTDIV_LSB)
+#define CPU_DPLL2_OUTDIV_SET(x) (((x) << CPU_DPLL2_OUTDIV_LSB) & CPU_DPLL2_OUTDIV_MASK)
+#define CPU_DPLL2_OUTDIV_RESET 0x1 // 1
+#define CPU_DPLL2_PHASE_SHIFT_MSB 18
+#define CPU_DPLL2_PHASE_SHIFT_LSB 12
+#define CPU_DPLL2_PHASE_SHIFT_MASK 0x0007f000
+#define CPU_DPLL2_PHASE_SHIFT_GET(x) (((x) & CPU_DPLL2_PHASE_SHIFT_MASK) >> CPU_DPLL2_PHASE_SHIFT_LSB)
+#define CPU_DPLL2_PHASE_SHIFT_SET(x) (((x) << CPU_DPLL2_PHASE_SHIFT_LSB) & CPU_DPLL2_PHASE_SHIFT_MASK)
+#define CPU_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
+#define CPU_DPLL2_TESTIN_MSB 11
+#define CPU_DPLL2_TESTIN_LSB 2
+#define CPU_DPLL2_TESTIN_MASK 0x00000ffc
+#define CPU_DPLL2_TESTIN_GET(x) (((x) & CPU_DPLL2_TESTIN_MASK) >> CPU_DPLL2_TESTIN_LSB)
+#define CPU_DPLL2_TESTIN_SET(x) (((x) << CPU_DPLL2_TESTIN_LSB) & CPU_DPLL2_TESTIN_MASK)
+#define CPU_DPLL2_TESTIN_RESET 0x0 // 0
+#define CPU_DPLL2_SEL_COUNT_MSB 1
+#define CPU_DPLL2_SEL_COUNT_LSB 1
+#define CPU_DPLL2_SEL_COUNT_MASK 0x00000002
+#define CPU_DPLL2_SEL_COUNT_GET(x) (((x) & CPU_DPLL2_SEL_COUNT_MASK) >> CPU_DPLL2_SEL_COUNT_LSB)
+#define CPU_DPLL2_SEL_COUNT_SET(x) (((x) << CPU_DPLL2_SEL_COUNT_LSB) & CPU_DPLL2_SEL_COUNT_MASK)
+#define CPU_DPLL2_SEL_COUNT_RESET 0x0 // 0
+#define CPU_DPLL2_RESET_TEST_MSB 0
+#define CPU_DPLL2_RESET_TEST_LSB 0
+#define CPU_DPLL2_RESET_TEST_MASK 0x00000001
+#define CPU_DPLL2_RESET_TEST_GET(x) (((x) & CPU_DPLL2_RESET_TEST_MASK) >> CPU_DPLL2_RESET_TEST_LSB)
+#define CPU_DPLL2_RESET_TEST_SET(x) (((x) << CPU_DPLL2_RESET_TEST_LSB) & CPU_DPLL2_RESET_TEST_MASK)
+#define CPU_DPLL2_RESET_TEST_RESET 0x0 // 0
+#define CPU_DPLL2_ADDRESS 0x181161c4
+
+#define DDR_RD_DATA_THIS_CYCLE_ADDRESS 0x18000018
+
+#define TAP_CONTROL_0_ADDRESS 0x1800001c
+#define TAP_CONTROL_1_ADDRESS 0x18000020
+#define TAP_CONTROL_2_ADDRESS 0x18000024
+#define TAP_CONTROL_3_ADDRESS 0x18000028
+
+#define DDR_BURST_CPU_PRIORITY_MSB 31
+#define DDR_BURST_CPU_PRIORITY_LSB 31
+#define DDR_BURST_CPU_PRIORITY_MASK 0x80000000
+#define DDR_BURST_CPU_PRIORITY_GET(x) (((x) & DDR_BURST_CPU_PRIORITY_MASK) >> DDR_BURST_CPU_PRIORITY_LSB)
+#define DDR_BURST_CPU_PRIORITY_SET(x) (((x) << DDR_BURST_CPU_PRIORITY_LSB) & DDR_BURST_CPU_PRIORITY_MASK)
+#define DDR_BURST_CPU_PRIORITY_RESET 0x0 // 0
+#define DDR_BURST_CPU_PRIORITY_BE_MSB 30
+#define DDR_BURST_CPU_PRIORITY_BE_LSB 30
+#define DDR_BURST_CPU_PRIORITY_BE_MASK 0x40000000
+#define DDR_BURST_CPU_PRIORITY_BE_GET(x) (((x) & DDR_BURST_CPU_PRIORITY_BE_MASK) >> DDR_BURST_CPU_PRIORITY_BE_LSB)
+#define DDR_BURST_CPU_PRIORITY_BE_SET(x) (((x) << DDR_BURST_CPU_PRIORITY_BE_LSB) & DDR_BURST_CPU_PRIORITY_BE_MASK)
+#define DDR_BURST_CPU_PRIORITY_BE_RESET 0x1 // 1
+#define DDR_BURST_ENABLE_RWP_MASK_MSB 29
+#define DDR_BURST_ENABLE_RWP_MASK_LSB 28
+#define DDR_BURST_ENABLE_RWP_MASK_MASK 0x30000000
+#define DDR_BURST_ENABLE_RWP_MASK_GET(x) (((x) & DDR_BURST_ENABLE_RWP_MASK_MASK) >> DDR_BURST_ENABLE_RWP_MASK_LSB)
+#define DDR_BURST_ENABLE_RWP_MASK_SET(x) (((x) << DDR_BURST_ENABLE_RWP_MASK_LSB) & DDR_BURST_ENABLE_RWP_MASK_MASK)
+#define DDR_BURST_ENABLE_RWP_MASK_RESET 0x3 // 3
+#define DDR_BURST_MAX_WRITE_BURST_MSB 27
+#define DDR_BURST_MAX_WRITE_BURST_LSB 24
+#define DDR_BURST_MAX_WRITE_BURST_MASK 0x0f000000
+#define DDR_BURST_MAX_WRITE_BURST_GET(x) (((x) & DDR_BURST_MAX_WRITE_BURST_MASK) >> DDR_BURST_MAX_WRITE_BURST_LSB)
+#define DDR_BURST_MAX_WRITE_BURST_SET(x) (((x) << DDR_BURST_MAX_WRITE_BURST_LSB) & DDR_BURST_MAX_WRITE_BURST_MASK)
+#define DDR_BURST_MAX_WRITE_BURST_RESET 0x4 // 4
+#define DDR_BURST_MAX_READ_BURST_MSB 23
+#define DDR_BURST_MAX_READ_BURST_LSB 20
+#define DDR_BURST_MAX_READ_BURST_MASK 0x00f00000
+#define DDR_BURST_MAX_READ_BURST_GET(x) (((x) & DDR_BURST_MAX_READ_BURST_MASK) >> DDR_BURST_MAX_READ_BURST_LSB)
+#define DDR_BURST_MAX_READ_BURST_SET(x) (((x) << DDR_BURST_MAX_READ_BURST_LSB) & DDR_BURST_MAX_READ_BURST_MASK)
+#define DDR_BURST_MAX_READ_BURST_RESET 0x4 // 4
+#define DDR_BURST_CPU_MAX_BL_MSB 19
+#define DDR_BURST_CPU_MAX_BL_LSB 16
+#define DDR_BURST_CPU_MAX_BL_MASK 0x000f0000
+#define DDR_BURST_CPU_MAX_BL_GET(x) (((x) & DDR_BURST_CPU_MAX_BL_MASK) >> DDR_BURST_CPU_MAX_BL_LSB)
+#define DDR_BURST_CPU_MAX_BL_SET(x) (((x) << DDR_BURST_CPU_MAX_BL_LSB) & DDR_BURST_CPU_MAX_BL_MASK)
+#define DDR_BURST_CPU_MAX_BL_RESET 0x3 // 3
+#define DDR_BURST_USB_MAX_BL_MSB 15
+#define DDR_BURST_USB_MAX_BL_LSB 12
+#define DDR_BURST_USB_MAX_BL_MASK 0x0000f000
+#define DDR_BURST_USB_MAX_BL_GET(x) (((x) & DDR_BURST_USB_MAX_BL_MASK) >> DDR_BURST_USB_MAX_BL_LSB)
+#define DDR_BURST_USB_MAX_BL_SET(x) (((x) << DDR_BURST_USB_MAX_BL_LSB) & DDR_BURST_USB_MAX_BL_MASK)
+#define DDR_BURST_USB_MAX_BL_RESET 0x4 // 4
+#define DDR_BURST_PCIE_MAX_BL_MSB 11
+#define DDR_BURST_PCIE_MAX_BL_LSB 8
+#define DDR_BURST_PCIE_MAX_BL_MASK 0x00000f00
+#define DDR_BURST_PCIE_MAX_BL_GET(x) (((x) & DDR_BURST_PCIE_MAX_BL_MASK) >> DDR_BURST_PCIE_MAX_BL_LSB)
+#define DDR_BURST_PCIE_MAX_BL_SET(x) (((x) << DDR_BURST_PCIE_MAX_BL_LSB) & DDR_BURST_PCIE_MAX_BL_MASK)
+#define DDR_BURST_PCIE_MAX_BL_RESET 0x3 // 3
+#define DDR_BURST_GE1_MAX_BL_MSB 7
+#define DDR_BURST_GE1_MAX_BL_LSB 4
+#define DDR_BURST_GE1_MAX_BL_MASK 0x000000f0
+#define DDR_BURST_GE1_MAX_BL_GET(x) (((x) & DDR_BURST_GE1_MAX_BL_MASK) >> DDR_BURST_GE1_MAX_BL_LSB)
+#define DDR_BURST_GE1_MAX_BL_SET(x) (((x) << DDR_BURST_GE1_MAX_BL_LSB) & DDR_BURST_GE1_MAX_BL_MASK)
+#define DDR_BURST_GE1_MAX_BL_RESET 0x3 // 3
+#define DDR_BURST_GE0_MAX_BL_MSB 3
+#define DDR_BURST_GE0_MAX_BL_LSB 0
+#define DDR_BURST_GE0_MAX_BL_MASK 0x0000000f
+#define DDR_BURST_GE0_MAX_BL_GET(x) (((x) & DDR_BURST_GE0_MAX_BL_MASK) >> DDR_BURST_GE0_MAX_BL_LSB)
+#define DDR_BURST_GE0_MAX_BL_SET(x) (((x) << DDR_BURST_GE0_MAX_BL_LSB) & DDR_BURST_GE0_MAX_BL_MASK)
+#define DDR_BURST_GE0_MAX_BL_RESET 0x3 // 3
+#define DDR_BURST_ADDRESS 0x180000c4
+
+#define DDR_BURST2_WMAC_MAX_BL_MSB 3
+#define DDR_BURST2_WMAC_MAX_BL_LSB 0
+#define DDR_BURST2_WMAC_MAX_BL_MASK 0x0000000f
+#define DDR_BURST2_WMAC_MAX_BL_GET(x) (((x) & DDR_BURST2_WMAC_MAX_BL_MASK) >> DDR_BURST2_WMAC_MAX_BL_LSB)
+#define DDR_BURST2_WMAC_MAX_BL_SET(x) (((x) << DDR_BURST2_WMAC_MAX_BL_LSB) & DDR_BURST2_WMAC_MAX_BL_MASK)
+#define DDR_BURST2_WMAC_MAX_BL_RESET 0x3 // 3
+#define DDR_BURST2_ADDRESS 0x180000c8
+
+#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MSB 19
+#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB 0
+#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK 0x000fffff
+#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_GET(x) (((x) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK) >> DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB)
+#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_SET(x) (((x) << DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK)
+#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_RESET 0x8000 // 32768
+#define DDR_AHB_MASTER_TIMEOUT_MAX_ADDRESS 0x180000cc
+
+#define PMU1_ADDRESS 0x18116c40
+
+#define PMU2_SWREGMSB_MSB 31
+#define PMU2_SWREGMSB_LSB 22
+#define PMU2_SWREGMSB_MASK 0xffc00000
+#define PMU2_SWREGMSB_GET(x) (((x) & PMU2_SWREGMSB_MASK) >> PMU2_SWREGMSB_LSB)
+#define PMU2_SWREGMSB_SET(x) (((x) << PMU2_SWREGMSB_LSB) & PMU2_SWREGMSB_MASK)
+#define PMU2_SWREGMSB_RESET 0x0 // 0
+#define PMU2_PGM_MSB 21
+#define PMU2_PGM_LSB 21
+#define PMU2_PGM_MASK 0x00200000
+#define PMU2_PGM_GET(x) (((x) & PMU2_PGM_MASK) >> PMU2_PGM_LSB)
+#define PMU2_PGM_SET(x) (((x) << PMU2_PGM_LSB) & PMU2_PGM_MASK)
+#define PMU2_PGM_RESET 0x0 // 0
+#define PMU2_LDO_TUNE_MSB 20
+#define PMU2_LDO_TUNE_LSB 19
+#define PMU2_LDO_TUNE_MASK 0x00180000
+#define PMU2_LDO_TUNE_GET(x) (((x) & PMU2_LDO_TUNE_MASK) >> PMU2_LDO_TUNE_LSB)
+#define PMU2_LDO_TUNE_SET(x) (((x) << PMU2_LDO_TUNE_LSB) & PMU2_LDO_TUNE_MASK)
+#define PMU2_LDO_TUNE_RESET 0x0 // 0
+#define PMU2_PWDLDO_DDR_MSB 18
+#define PMU2_PWDLDO_DDR_LSB 18
+#define PMU2_PWDLDO_DDR_MASK 0x00040000
+#define PMU2_PWDLDO_DDR_GET(x) (((x) & PMU2_PWDLDO_DDR_MASK) >> PMU2_PWDLDO_DDR_LSB)
+#define PMU2_PWDLDO_DDR_SET(x) (((x) << PMU2_PWDLDO_DDR_LSB) & PMU2_PWDLDO_DDR_MASK)
+#define PMU2_PWDLDO_DDR_RESET 0x0 // 0
+#define PMU2_LPOPWD_MSB 17
+#define PMU2_LPOPWD_LSB 17
+#define PMU2_LPOPWD_MASK 0x00020000
+#define PMU2_LPOPWD_GET(x) (((x) & PMU2_LPOPWD_MASK) >> PMU2_LPOPWD_LSB)
+#define PMU2_LPOPWD_SET(x) (((x) << PMU2_LPOPWD_LSB) & PMU2_LPOPWD_MASK)
+#define PMU2_LPOPWD_RESET 0x0 // 0
+#define PMU2_SPARE_MSB 16
+#define PMU2_SPARE_LSB 0
+#define PMU2_SPARE_MASK 0x0001ffff
+#define PMU2_SPARE_GET(x) (((x) & PMU2_SPARE_MASK) >> PMU2_SPARE_LSB)
+#define PMU2_SPARE_SET(x) (((x) << PMU2_SPARE_LSB) & PMU2_SPARE_MASK)
+#define PMU2_SPARE_RESET 0x0 // 0
+#define PMU2_ADDRESS 0x18116c44
+
+#define PHY_CTRL0_LOOPBACK_ERR_CNT_MSB 31
+#define PHY_CTRL0_LOOPBACK_ERR_CNT_LSB 24
+#define PHY_CTRL0_LOOPBACK_ERR_CNT_MASK 0xff000000
+#define PHY_CTRL0_LOOPBACK_ERR_CNT_GET(x) (((x) & PHY_CTRL0_LOOPBACK_ERR_CNT_MASK) >> PHY_CTRL0_LOOPBACK_ERR_CNT_LSB)
+#define PHY_CTRL0_LOOPBACK_ERR_CNT_SET(x) (((x) << PHY_CTRL0_LOOPBACK_ERR_CNT_LSB) & PHY_CTRL0_LOOPBACK_ERR_CNT_MASK)
+#define PHY_CTRL0_LOOPBACK_ERR_CNT_RESET 0x0 // 0
+#define PHY_CTRL0_DIG_LOOPBACK_EN_MSB 23
+#define PHY_CTRL0_DIG_LOOPBACK_EN_LSB 23
+#define PHY_CTRL0_DIG_LOOPBACK_EN_MASK 0x00800000
+#define PHY_CTRL0_DIG_LOOPBACK_EN_GET(x) (((x) & PHY_CTRL0_DIG_LOOPBACK_EN_MASK) >> PHY_CTRL0_DIG_LOOPBACK_EN_LSB)
+#define PHY_CTRL0_DIG_LOOPBACK_EN_SET(x) (((x) << PHY_CTRL0_DIG_LOOPBACK_EN_LSB) & PHY_CTRL0_DIG_LOOPBACK_EN_MASK)
+#define PHY_CTRL0_DIG_LOOPBACK_EN_RESET 0x0 // 0
+#define PHY_CTRL0_ANA_LOOPBACK_EN_MSB 22
+#define PHY_CTRL0_ANA_LOOPBACK_EN_LSB 22
+#define PHY_CTRL0_ANA_LOOPBACK_EN_MASK 0x00400000
+#define PHY_CTRL0_ANA_LOOPBACK_EN_GET(x) (((x) & PHY_CTRL0_ANA_LOOPBACK_EN_MASK) >> PHY_CTRL0_ANA_LOOPBACK_EN_LSB)
+#define PHY_CTRL0_ANA_LOOPBACK_EN_SET(x) (((x) << PHY_CTRL0_ANA_LOOPBACK_EN_LSB) & PHY_CTRL0_ANA_LOOPBACK_EN_MASK)
+#define PHY_CTRL0_ANA_LOOPBACK_EN_RESET 0x0 // 0
+#define PHY_CTRL0_TX_PATTERN_EN_MSB 21
+#define PHY_CTRL0_TX_PATTERN_EN_LSB 21
+#define PHY_CTRL0_TX_PATTERN_EN_MASK 0x00200000
+#define PHY_CTRL0_TX_PATTERN_EN_GET(x) (((x) & PHY_CTRL0_TX_PATTERN_EN_MASK) >> PHY_CTRL0_TX_PATTERN_EN_LSB)
+#define PHY_CTRL0_TX_PATTERN_EN_SET(x) (((x) << PHY_CTRL0_TX_PATTERN_EN_LSB) & PHY_CTRL0_TX_PATTERN_EN_MASK)
+#define PHY_CTRL0_TX_PATTERN_EN_RESET 0x0 // 0
+#define PHY_CTRL0_RX_PATTERN_EN_MSB 20
+#define PHY_CTRL0_RX_PATTERN_EN_LSB 20
+#define PHY_CTRL0_RX_PATTERN_EN_MASK 0x00100000
+#define PHY_CTRL0_RX_PATTERN_EN_GET(x) (((x) & PHY_CTRL0_RX_PATTERN_EN_MASK) >> PHY_CTRL0_RX_PATTERN_EN_LSB)
+#define PHY_CTRL0_RX_PATTERN_EN_SET(x) (((x) << PHY_CTRL0_RX_PATTERN_EN_LSB) & PHY_CTRL0_RX_PATTERN_EN_MASK)
+#define PHY_CTRL0_RX_PATTERN_EN_RESET 0x0 // 0
+#define PHY_CTRL0_TEST_SPEED_SELECT_MSB 19
+#define PHY_CTRL0_TEST_SPEED_SELECT_LSB 19
+#define PHY_CTRL0_TEST_SPEED_SELECT_MASK 0x00080000
+#define PHY_CTRL0_TEST_SPEED_SELECT_GET(x) (((x) & PHY_CTRL0_TEST_SPEED_SELECT_MASK) >> PHY_CTRL0_TEST_SPEED_SELECT_LSB)
+#define PHY_CTRL0_TEST_SPEED_SELECT_SET(x) (((x) << PHY_CTRL0_TEST_SPEED_SELECT_LSB) & PHY_CTRL0_TEST_SPEED_SELECT_MASK)
+#define PHY_CTRL0_TEST_SPEED_SELECT_RESET 0x0 // 0
+#define PHY_CTRL0_PLL_OVERIDE_MSB 18
+#define PHY_CTRL0_PLL_OVERIDE_LSB 18
+#define PHY_CTRL0_PLL_OVERIDE_MASK 0x00040000
+#define PHY_CTRL0_PLL_OVERIDE_GET(x) (((x) & PHY_CTRL0_PLL_OVERIDE_MASK) >> PHY_CTRL0_PLL_OVERIDE_LSB)
+#define PHY_CTRL0_PLL_OVERIDE_SET(x) (((x) << PHY_CTRL0_PLL_OVERIDE_LSB) & PHY_CTRL0_PLL_OVERIDE_MASK)
+#define PHY_CTRL0_PLL_OVERIDE_RESET 0x0 // 0
+#define PHY_CTRL0_PLL_MOD_MSB 17
+#define PHY_CTRL0_PLL_MOD_LSB 15
+#define PHY_CTRL0_PLL_MOD_MASK 0x00038000
+#define PHY_CTRL0_PLL_MOD_GET(x) (((x) & PHY_CTRL0_PLL_MOD_MASK) >> PHY_CTRL0_PLL_MOD_LSB)
+#define PHY_CTRL0_PLL_MOD_SET(x) (((x) << PHY_CTRL0_PLL_MOD_LSB) & PHY_CTRL0_PLL_MOD_MASK)
+#define PHY_CTRL0_PLL_MOD_RESET 0x0 // 0
+#define PHY_CTRL0_PLL_DIV_MSB 14
+#define PHY_CTRL0_PLL_DIV_LSB 6
+#define PHY_CTRL0_PLL_DIV_MASK 0x00007fc0
+#define PHY_CTRL0_PLL_DIV_GET(x) (((x) & PHY_CTRL0_PLL_DIV_MASK) >> PHY_CTRL0_PLL_DIV_LSB)
+#define PHY_CTRL0_PLL_DIV_SET(x) (((x) << PHY_CTRL0_PLL_DIV_LSB) & PHY_CTRL0_PLL_DIV_MASK)
+#define PHY_CTRL0_PLL_DIV_RESET 0x0 // 0
+#define PHY_CTRL0_PLL_RS_MSB 5
+#define PHY_CTRL0_PLL_RS_LSB 3
+#define PHY_CTRL0_PLL_RS_MASK 0x00000038
+#define PHY_CTRL0_PLL_RS_GET(x) (((x) & PHY_CTRL0_PLL_RS_MASK) >> PHY_CTRL0_PLL_RS_LSB)
+#define PHY_CTRL0_PLL_RS_SET(x) (((x) << PHY_CTRL0_PLL_RS_LSB) & PHY_CTRL0_PLL_RS_MASK)
+#define PHY_CTRL0_PLL_RS_RESET 0x2 // 2
+#define PHY_CTRL0_PLL_ICP_MSB 2
+#define PHY_CTRL0_PLL_ICP_LSB 0
+#define PHY_CTRL0_PLL_ICP_MASK 0x00000007
+#define PHY_CTRL0_PLL_ICP_GET(x) (((x) & PHY_CTRL0_PLL_ICP_MASK) >> PHY_CTRL0_PLL_ICP_LSB)
+#define PHY_CTRL0_PLL_ICP_SET(x) (((x) << PHY_CTRL0_PLL_ICP_LSB) & PHY_CTRL0_PLL_ICP_MASK)
+#define PHY_CTRL0_PLL_ICP_RESET 0x5 // 5
+#define PHY_CTRL0_ADDRESS 0x18116c80
+#define PHY_CTRL0_OFFSET 0x0000
+// SW modifiable bits
+#define PHY_CTRL0_SW_MASK 0xffffffff
+// bits defined at reset
+#define PHY_CTRL0_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PHY_CTRL0_RESET 0x00000015
+
+#define PHY_CTRL1_PLL_OBS_MODE_N_MSB 31
+#define PHY_CTRL1_PLL_OBS_MODE_N_LSB 31
+#define PHY_CTRL1_PLL_OBS_MODE_N_MASK 0x80000000
+#define PHY_CTRL1_PLL_OBS_MODE_N_GET(x) (((x) & PHY_CTRL1_PLL_OBS_MODE_N_MASK) >> PHY_CTRL1_PLL_OBS_MODE_N_LSB)
+#define PHY_CTRL1_PLL_OBS_MODE_N_SET(x) (((x) << PHY_CTRL1_PLL_OBS_MODE_N_LSB) & PHY_CTRL1_PLL_OBS_MODE_N_MASK)
+#define PHY_CTRL1_PLL_OBS_MODE_N_RESET 0x1 // 1
+#define PHY_CTRL1_DISABLE_CLK_GATING_MSB 27
+#define PHY_CTRL1_DISABLE_CLK_GATING_LSB 27
+#define PHY_CTRL1_DISABLE_CLK_GATING_MASK 0x08000000
+#define PHY_CTRL1_DISABLE_CLK_GATING_GET(x) (((x) & PHY_CTRL1_DISABLE_CLK_GATING_MASK) >> PHY_CTRL1_DISABLE_CLK_GATING_LSB)
+#define PHY_CTRL1_DISABLE_CLK_GATING_SET(x) (((x) << PHY_CTRL1_DISABLE_CLK_GATING_LSB) & PHY_CTRL1_DISABLE_CLK_GATING_MASK)
+#define PHY_CTRL1_DISABLE_CLK_GATING_RESET 0x0 // 0
+#define PHY_CTRL1_ENABLE_REFCLK_GATE_MSB 26
+#define PHY_CTRL1_ENABLE_REFCLK_GATE_LSB 26
+#define PHY_CTRL1_ENABLE_REFCLK_GATE_MASK 0x04000000
+#define PHY_CTRL1_ENABLE_REFCLK_GATE_GET(x) (((x) & PHY_CTRL1_ENABLE_REFCLK_GATE_MASK) >> PHY_CTRL1_ENABLE_REFCLK_GATE_LSB)
+#define PHY_CTRL1_ENABLE_REFCLK_GATE_SET(x) (((x) << PHY_CTRL1_ENABLE_REFCLK_GATE_LSB) & PHY_CTRL1_ENABLE_REFCLK_GATE_MASK)
+#define PHY_CTRL1_ENABLE_REFCLK_GATE_RESET 0x1 // 1
+#define PHY_CTRL1_CLKOBS_SEL_MSB 25
+#define PHY_CTRL1_CLKOBS_SEL_LSB 23
+#define PHY_CTRL1_CLKOBS_SEL_MASK 0x03800000
+#define PHY_CTRL1_CLKOBS_SEL_GET(x) (((x) & PHY_CTRL1_CLKOBS_SEL_MASK) >> PHY_CTRL1_CLKOBS_SEL_LSB)
+#define PHY_CTRL1_CLKOBS_SEL_SET(x) (((x) << PHY_CTRL1_CLKOBS_SEL_LSB) & PHY_CTRL1_CLKOBS_SEL_MASK)
+#define PHY_CTRL1_CLKOBS_SEL_RESET 0x0 // 0
+#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MSB 22
+#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB 21
+#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK 0x00600000
+#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_GET(x) (((x) & PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK) >> PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB)
+#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_SET(x) (((x) << PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB) & PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK)
+#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_RESET 0x3 // 3
+#define PHY_CTRL1_USE_PLL_LOCKDETECT_MSB 20
+#define PHY_CTRL1_USE_PLL_LOCKDETECT_LSB 20
+#define PHY_CTRL1_USE_PLL_LOCKDETECT_MASK 0x00100000
+#define PHY_CTRL1_USE_PLL_LOCKDETECT_GET(x) (((x) & PHY_CTRL1_USE_PLL_LOCKDETECT_MASK) >> PHY_CTRL1_USE_PLL_LOCKDETECT_LSB)
+#define PHY_CTRL1_USE_PLL_LOCKDETECT_SET(x) (((x) << PHY_CTRL1_USE_PLL_LOCKDETECT_LSB) & PHY_CTRL1_USE_PLL_LOCKDETECT_MASK)
+#define PHY_CTRL1_USE_PLL_LOCKDETECT_RESET 0x0 // 0
+#define PHY_CTRL1_TX_PATTERN_SEL_MSB 19
+#define PHY_CTRL1_TX_PATTERN_SEL_LSB 18
+#define PHY_CTRL1_TX_PATTERN_SEL_MASK 0x000c0000
+#define PHY_CTRL1_TX_PATTERN_SEL_GET(x) (((x) & PHY_CTRL1_TX_PATTERN_SEL_MASK) >> PHY_CTRL1_TX_PATTERN_SEL_LSB)
+#define PHY_CTRL1_TX_PATTERN_SEL_SET(x) (((x) << PHY_CTRL1_TX_PATTERN_SEL_LSB) & PHY_CTRL1_TX_PATTERN_SEL_MASK)
+#define PHY_CTRL1_TX_PATTERN_SEL_RESET 0x0 // 0
+#define PHY_CTRL1_FORCE_SUSPEND_MSB 13
+#define PHY_CTRL1_FORCE_SUSPEND_LSB 13
+#define PHY_CTRL1_FORCE_SUSPEND_MASK 0x00002000
+#define PHY_CTRL1_FORCE_SUSPEND_GET(x) (((x) & PHY_CTRL1_FORCE_SUSPEND_MASK) >> PHY_CTRL1_FORCE_SUSPEND_LSB)
+#define PHY_CTRL1_FORCE_SUSPEND_SET(x) (((x) << PHY_CTRL1_FORCE_SUSPEND_LSB) & PHY_CTRL1_FORCE_SUSPEND_MASK)
+#define PHY_CTRL1_FORCE_SUSPEND_RESET 0x0 // 0
+#define PHY_CTRL1_NO_PLL_PWD_MSB 12
+#define PHY_CTRL1_NO_PLL_PWD_LSB 12
+#define PHY_CTRL1_NO_PLL_PWD_MASK 0x00001000
+#define PHY_CTRL1_NO_PLL_PWD_GET(x) (((x) & PHY_CTRL1_NO_PLL_PWD_MASK) >> PHY_CTRL1_NO_PLL_PWD_LSB)
+#define PHY_CTRL1_NO_PLL_PWD_SET(x) (((x) << PHY_CTRL1_NO_PLL_PWD_LSB) & PHY_CTRL1_NO_PLL_PWD_MASK)
+#define PHY_CTRL1_NO_PLL_PWD_RESET 0x0 // 0
+#define PHY_CTRL1_RX_RSVD_MSB 11
+#define PHY_CTRL1_RX_RSVD_LSB 9
+#define PHY_CTRL1_RX_RSVD_MASK 0x00000e00
+#define PHY_CTRL1_RX_RSVD_GET(x) (((x) & PHY_CTRL1_RX_RSVD_MASK) >> PHY_CTRL1_RX_RSVD_LSB)
+#define PHY_CTRL1_RX_RSVD_SET(x) (((x) << PHY_CTRL1_RX_RSVD_LSB) & PHY_CTRL1_RX_RSVD_MASK)
+#define PHY_CTRL1_RX_RSVD_RESET 0x0 // 0
+#define PHY_CTRL1_RX_SELVREF0P25_MSB 8
+#define PHY_CTRL1_RX_SELVREF0P25_LSB 8
+#define PHY_CTRL1_RX_SELVREF0P25_MASK 0x00000100
+#define PHY_CTRL1_RX_SELVREF0P25_GET(x) (((x) & PHY_CTRL1_RX_SELVREF0P25_MASK) >> PHY_CTRL1_RX_SELVREF0P25_LSB)
+#define PHY_CTRL1_RX_SELVREF0P25_SET(x) (((x) << PHY_CTRL1_RX_SELVREF0P25_LSB) & PHY_CTRL1_RX_SELVREF0P25_MASK)
+#define PHY_CTRL1_RX_SELVREF0P25_RESET 0x0 // 0
+#define PHY_CTRL1_RX_SELVREF0P6_MSB 7
+#define PHY_CTRL1_RX_SELVREF0P6_LSB 7
+#define PHY_CTRL1_RX_SELVREF0P6_MASK 0x00000080
+#define PHY_CTRL1_RX_SELVREF0P6_GET(x) (((x) & PHY_CTRL1_RX_SELVREF0P6_MASK) >> PHY_CTRL1_RX_SELVREF0P6_LSB)
+#define PHY_CTRL1_RX_SELVREF0P6_SET(x) (((x) << PHY_CTRL1_RX_SELVREF0P6_LSB) & PHY_CTRL1_RX_SELVREF0P6_MASK)
+#define PHY_CTRL1_RX_SELVREF0P6_RESET 0x1 // 1
+#define PHY_CTRL1_RX_SELIR_100M_MSB 6
+#define PHY_CTRL1_RX_SELIR_100M_LSB 5
+#define PHY_CTRL1_RX_SELIR_100M_MASK 0x00000060
+#define PHY_CTRL1_RX_SELIR_100M_GET(x) (((x) & PHY_CTRL1_RX_SELIR_100M_MASK) >> PHY_CTRL1_RX_SELIR_100M_LSB)
+#define PHY_CTRL1_RX_SELIR_100M_SET(x) (((x) << PHY_CTRL1_RX_SELIR_100M_LSB) & PHY_CTRL1_RX_SELIR_100M_MASK)
+#define PHY_CTRL1_RX_SELIR_100M_RESET 0x0 // 0
+#define PHY_CTRL1_RX_LOWR_PDET_MSB 4
+#define PHY_CTRL1_RX_LOWR_PDET_LSB 4
+#define PHY_CTRL1_RX_LOWR_PDET_MASK 0x00000010
+#define PHY_CTRL1_RX_LOWR_PDET_GET(x) (((x) & PHY_CTRL1_RX_LOWR_PDET_MASK) >> PHY_CTRL1_RX_LOWR_PDET_LSB)
+#define PHY_CTRL1_RX_LOWR_PDET_SET(x) (((x) << PHY_CTRL1_RX_LOWR_PDET_LSB) & PHY_CTRL1_RX_LOWR_PDET_MASK)
+#define PHY_CTRL1_RX_LOWR_PDET_RESET 0x1 // 1
+#define PHY_CTRL1_RX_BYPASSEQ_MSB 3
+#define PHY_CTRL1_RX_BYPASSEQ_LSB 3
+#define PHY_CTRL1_RX_BYPASSEQ_MASK 0x00000008
+#define PHY_CTRL1_RX_BYPASSEQ_GET(x) (((x) & PHY_CTRL1_RX_BYPASSEQ_MASK) >> PHY_CTRL1_RX_BYPASSEQ_LSB)
+#define PHY_CTRL1_RX_BYPASSEQ_SET(x) (((x) << PHY_CTRL1_RX_BYPASSEQ_LSB) & PHY_CTRL1_RX_BYPASSEQ_MASK)
+#define PHY_CTRL1_RX_BYPASSEQ_RESET 0x0 // 0
+#define PHY_CTRL1_RX_FORCERXON_MSB 2
+#define PHY_CTRL1_RX_FORCERXON_LSB 2
+#define PHY_CTRL1_RX_FORCERXON_MASK 0x00000004
+#define PHY_CTRL1_RX_FORCERXON_GET(x) (((x) & PHY_CTRL1_RX_FORCERXON_MASK) >> PHY_CTRL1_RX_FORCERXON_LSB)
+#define PHY_CTRL1_RX_FORCERXON_SET(x) (((x) << PHY_CTRL1_RX_FORCERXON_LSB) & PHY_CTRL1_RX_FORCERXON_MASK)
+#define PHY_CTRL1_RX_FORCERXON_RESET 0x1 // 1
+#define PHY_CTRL1_RX_FILBW_SEL_MSB 1
+#define PHY_CTRL1_RX_FILBW_SEL_LSB 0
+#define PHY_CTRL1_RX_FILBW_SEL_MASK 0x00000003
+#define PHY_CTRL1_RX_FILBW_SEL_GET(x) (((x) & PHY_CTRL1_RX_FILBW_SEL_MASK) >> PHY_CTRL1_RX_FILBW_SEL_LSB)
+#define PHY_CTRL1_RX_FILBW_SEL_SET(x) (((x) << PHY_CTRL1_RX_FILBW_SEL_LSB) & PHY_CTRL1_RX_FILBW_SEL_MASK)
+#define PHY_CTRL1_RX_FILBW_SEL_RESET 0x1 // 1
+#define PHY_CTRL1_ADDRESS 0x18116c84
+#define PHY_CTRL1_OFFSET 0x0004
+// SW modifiable bits
+#define PHY_CTRL1_SW_MASK 0x8ffc3fff
+// bits defined at reset
+#define PHY_CTRL1_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PHY_CTRL1_RESET 0x84600095
+
+#define PHY_CTRL2_PWD_EXTBIAS_MSB 31
+#define PHY_CTRL2_PWD_EXTBIAS_LSB 31
+#define PHY_CTRL2_PWD_EXTBIAS_MASK 0x80000000
+#define PHY_CTRL2_PWD_EXTBIAS_GET(x) (((x) & PHY_CTRL2_PWD_EXTBIAS_MASK) >> PHY_CTRL2_PWD_EXTBIAS_LSB)
+#define PHY_CTRL2_PWD_EXTBIAS_SET(x) (((x) << PHY_CTRL2_PWD_EXTBIAS_LSB) & PHY_CTRL2_PWD_EXTBIAS_MASK)
+#define PHY_CTRL2_PWD_EXTBIAS_RESET 0x0 // 0
+#define PHY_CTRL2_TX_RSVD_MSB 30
+#define PHY_CTRL2_TX_RSVD_LSB 27
+#define PHY_CTRL2_TX_RSVD_MASK 0x78000000
+#define PHY_CTRL2_TX_RSVD_GET(x) (((x) & PHY_CTRL2_TX_RSVD_MASK) >> PHY_CTRL2_TX_RSVD_LSB)
+#define PHY_CTRL2_TX_RSVD_SET(x) (((x) << PHY_CTRL2_TX_RSVD_LSB) & PHY_CTRL2_TX_RSVD_MASK)
+#define PHY_CTRL2_TX_RSVD_RESET 0x0 // 0
+#define PHY_CTRL2_TX_LCKDET_OVR_MSB 26
+#define PHY_CTRL2_TX_LCKDET_OVR_LSB 26
+#define PHY_CTRL2_TX_LCKDET_OVR_MASK 0x04000000
+#define PHY_CTRL2_TX_LCKDET_OVR_GET(x) (((x) & PHY_CTRL2_TX_LCKDET_OVR_MASK) >> PHY_CTRL2_TX_LCKDET_OVR_LSB)
+#define PHY_CTRL2_TX_LCKDET_OVR_SET(x) (((x) << PHY_CTRL2_TX_LCKDET_OVR_LSB) & PHY_CTRL2_TX_LCKDET_OVR_MASK)
+#define PHY_CTRL2_TX_LCKDET_OVR_RESET 0x0 // 0
+#define PHY_CTRL2_TX_MAN_CAL_MSB 25
+#define PHY_CTRL2_TX_MAN_CAL_LSB 22
+#define PHY_CTRL2_TX_MAN_CAL_MASK 0x03c00000
+#define PHY_CTRL2_TX_MAN_CAL_GET(x) (((x) & PHY_CTRL2_TX_MAN_CAL_MASK) >> PHY_CTRL2_TX_MAN_CAL_LSB)
+#define PHY_CTRL2_TX_MAN_CAL_SET(x) (((x) << PHY_CTRL2_TX_MAN_CAL_LSB) & PHY_CTRL2_TX_MAN_CAL_MASK)
+#define PHY_CTRL2_TX_MAN_CAL_RESET 0x3 // 3
+#define PHY_CTRL2_TX_CAL_SEL_MSB 21
+#define PHY_CTRL2_TX_CAL_SEL_LSB 21
+#define PHY_CTRL2_TX_CAL_SEL_MASK 0x00200000
+#define PHY_CTRL2_TX_CAL_SEL_GET(x) (((x) & PHY_CTRL2_TX_CAL_SEL_MASK) >> PHY_CTRL2_TX_CAL_SEL_LSB)
+#define PHY_CTRL2_TX_CAL_SEL_SET(x) (((x) << PHY_CTRL2_TX_CAL_SEL_LSB) & PHY_CTRL2_TX_CAL_SEL_MASK)
+#define PHY_CTRL2_TX_CAL_SEL_RESET 0x1 // 1
+#define PHY_CTRL2_TX_CAL_EN_MSB 20
+#define PHY_CTRL2_TX_CAL_EN_LSB 20
+#define PHY_CTRL2_TX_CAL_EN_MASK 0x00100000
+#define PHY_CTRL2_TX_CAL_EN_GET(x) (((x) & PHY_CTRL2_TX_CAL_EN_MASK) >> PHY_CTRL2_TX_CAL_EN_LSB)
+#define PHY_CTRL2_TX_CAL_EN_SET(x) (((x) << PHY_CTRL2_TX_CAL_EN_LSB) & PHY_CTRL2_TX_CAL_EN_MASK)
+#define PHY_CTRL2_TX_CAL_EN_RESET 0x1 // 1
+#define PHY_CTRL2_PWD_ISP_MSB 13
+#define PHY_CTRL2_PWD_ISP_LSB 8
+#define PHY_CTRL2_PWD_ISP_MASK 0x00003f00
+#define PHY_CTRL2_PWD_ISP_GET(x) (((x) & PHY_CTRL2_PWD_ISP_MASK) >> PHY_CTRL2_PWD_ISP_LSB)
+#define PHY_CTRL2_PWD_ISP_SET(x) (((x) << PHY_CTRL2_PWD_ISP_LSB) & PHY_CTRL2_PWD_ISP_MASK)
+#define PHY_CTRL2_PWD_ISP_RESET 0x1b // 27
+#define PHY_CTRL2_PWD_IPLL_MSB 7
+#define PHY_CTRL2_PWD_IPLL_LSB 2
+#define PHY_CTRL2_PWD_IPLL_MASK 0x000000fc
+#define PHY_CTRL2_PWD_IPLL_GET(x) (((x) & PHY_CTRL2_PWD_IPLL_MASK) >> PHY_CTRL2_PWD_IPLL_LSB)
+#define PHY_CTRL2_PWD_IPLL_SET(x) (((x) << PHY_CTRL2_PWD_IPLL_LSB) & PHY_CTRL2_PWD_IPLL_MASK)
+#define PHY_CTRL2_PWD_IPLL_RESET 0x1b // 27
+#define PHY_CTRL2_HSRXPHASE_PS_EN_MSB 1
+#define PHY_CTRL2_HSRXPHASE_PS_EN_LSB 1
+#define PHY_CTRL2_HSRXPHASE_PS_EN_MASK 0x00000002
+#define PHY_CTRL2_HSRXPHASE_PS_EN_GET(x) (((x) & PHY_CTRL2_HSRXPHASE_PS_EN_MASK) >> PHY_CTRL2_HSRXPHASE_PS_EN_LSB)
+#define PHY_CTRL2_HSRXPHASE_PS_EN_SET(x) (((x) << PHY_CTRL2_HSRXPHASE_PS_EN_LSB) & PHY_CTRL2_HSRXPHASE_PS_EN_MASK)
+#define PHY_CTRL2_HSRXPHASE_PS_EN_RESET 0x0 // 0
+#define PHY_CTRL2_HSTXBIAS_PS_EN_MSB 0
+#define PHY_CTRL2_HSTXBIAS_PS_EN_LSB 0
+#define PHY_CTRL2_HSTXBIAS_PS_EN_MASK 0x00000001
+#define PHY_CTRL2_HSTXBIAS_PS_EN_GET(x) (((x) & PHY_CTRL2_HSTXBIAS_PS_EN_MASK) >> PHY_CTRL2_HSTXBIAS_PS_EN_LSB)
+#define PHY_CTRL2_HSTXBIAS_PS_EN_SET(x) (((x) << PHY_CTRL2_HSTXBIAS_PS_EN_LSB) & PHY_CTRL2_HSTXBIAS_PS_EN_MASK)
+#define PHY_CTRL2_HSTXBIAS_PS_EN_RESET 0x0 // 0
+#define PHY_CTRL2_ADDRESS 0x18116c88
+#define PHY_CTRL2_OFFSET 0x0008
+// SW modifiable bits
+#define PHY_CTRL2_SW_MASK 0xfff03fff
+// bits defined at reset
+#define PHY_CTRL2_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PHY_CTRL2_RESET 0x00f01b6c
+
+#define PHY_CTRL3_SPARE_BITS_MSB 31
+#define PHY_CTRL3_SPARE_BITS_LSB 27
+#define PHY_CTRL3_SPARE_BITS_MASK 0xf8000000
+#define PHY_CTRL3_SPARE_BITS_GET(x) (((x) & PHY_CTRL3_SPARE_BITS_MASK) >> PHY_CTRL3_SPARE_BITS_LSB)
+#define PHY_CTRL3_SPARE_BITS_SET(x) (((x) << PHY_CTRL3_SPARE_BITS_LSB) & PHY_CTRL3_SPARE_BITS_MASK)
+#define PHY_CTRL3_SPARE_BITS_RESET 0x0 // 0
+#define PHY_CTRL3_SUS_RES_FIX_DIS_MSB 26
+#define PHY_CTRL3_SUS_RES_FIX_DIS_LSB 26
+#define PHY_CTRL3_SUS_RES_FIX_DIS_MASK 0x04000000
+#define PHY_CTRL3_SUS_RES_FIX_DIS_GET(x) (((x) & PHY_CTRL3_SUS_RES_FIX_DIS_MASK) >> PHY_CTRL3_SUS_RES_FIX_DIS_LSB)
+#define PHY_CTRL3_SUS_RES_FIX_DIS_SET(x) (((x) << PHY_CTRL3_SUS_RES_FIX_DIS_LSB) & PHY_CTRL3_SUS_RES_FIX_DIS_MASK)
+#define PHY_CTRL3_SUS_RES_FIX_DIS_RESET 0x0 // 0
+#define PHY_CTRL3_TX_STARTCAL_MSB 25
+#define PHY_CTRL3_TX_STARTCAL_LSB 25
+#define PHY_CTRL3_TX_STARTCAL_MASK 0x02000000
+#define PHY_CTRL3_TX_STARTCAL_GET(x) (((x) & PHY_CTRL3_TX_STARTCAL_MASK) >> PHY_CTRL3_TX_STARTCAL_LSB)
+#define PHY_CTRL3_TX_STARTCAL_SET(x) (((x) << PHY_CTRL3_TX_STARTCAL_LSB) & PHY_CTRL3_TX_STARTCAL_MASK)
+#define PHY_CTRL3_TX_STARTCAL_RESET 0x0 // 0
+#define PHY_CTRL3_TX_SELTEST_MSB 24
+#define PHY_CTRL3_TX_SELTEST_LSB 22
+#define PHY_CTRL3_TX_SELTEST_MASK 0x01c00000
+#define PHY_CTRL3_TX_SELTEST_GET(x) (((x) & PHY_CTRL3_TX_SELTEST_MASK) >> PHY_CTRL3_TX_SELTEST_LSB)
+#define PHY_CTRL3_TX_SELTEST_SET(x) (((x) << PHY_CTRL3_TX_SELTEST_LSB) & PHY_CTRL3_TX_SELTEST_MASK)
+#define PHY_CTRL3_TX_SELTEST_RESET 0x0 // 0
+#define PHY_CTRL3_TX_DISABLE_SHORT_DET_MSB 21
+#define PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB 21
+#define PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK 0x00200000
+#define PHY_CTRL3_TX_DISABLE_SHORT_DET_GET(x) (((x) & PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK) >> PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB)
+#define PHY_CTRL3_TX_DISABLE_SHORT_DET_SET(x) (((x) << PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB) & PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK)
+#define PHY_CTRL3_TX_DISABLE_SHORT_DET_RESET 0x0 // 0
+#define PHY_CTRL3_PWD_ITX_MSB 18
+#define PHY_CTRL3_PWD_ITX_LSB 0
+#define PHY_CTRL3_PWD_ITX_MASK 0x0007ffff
+#define PHY_CTRL3_PWD_ITX_GET(x) (((x) & PHY_CTRL3_PWD_ITX_MASK) >> PHY_CTRL3_PWD_ITX_LSB)
+#define PHY_CTRL3_PWD_ITX_SET(x) (((x) << PHY_CTRL3_PWD_ITX_LSB) & PHY_CTRL3_PWD_ITX_MASK)
+#define PHY_CTRL3_PWD_ITX_RESET 0x14765 // 83813
+#define PHY_CTRL3_ADDRESS 0x18116c8c
+#define PHY_CTRL3_OFFSET 0x000c
+// SW modifiable bits
+#define PHY_CTRL3_SW_MASK 0xffe7ffff
+// bits defined at reset
+#define PHY_CTRL3_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PHY_CTRL3_RESET 0x00014765
+
+#define PHY_CTRL4_PPRBS_ERR_CNT_MSB 31
+#define PHY_CTRL4_PPRBS_ERR_CNT_LSB 24
+#define PHY_CTRL4_PPRBS_ERR_CNT_MASK 0xff000000
+#define PHY_CTRL4_PPRBS_ERR_CNT_GET(x) (((x) & PHY_CTRL4_PPRBS_ERR_CNT_MASK) >> PHY_CTRL4_PPRBS_ERR_CNT_LSB)
+#define PHY_CTRL4_PPRBS_ERR_CNT_SET(x) (((x) << PHY_CTRL4_PPRBS_ERR_CNT_LSB) & PHY_CTRL4_PPRBS_ERR_CNT_MASK)
+#define PHY_CTRL4_PPRBS_ERR_CNT_RESET 0x0 // 0
+#define PHY_CTRL4_LS_PRBS_EN_MSB 21
+#define PHY_CTRL4_LS_PRBS_EN_LSB 21
+#define PHY_CTRL4_LS_PRBS_EN_MASK 0x00200000
+#define PHY_CTRL4_LS_PRBS_EN_GET(x) (((x) & PHY_CTRL4_LS_PRBS_EN_MASK) >> PHY_CTRL4_LS_PRBS_EN_LSB)
+#define PHY_CTRL4_LS_PRBS_EN_SET(x) (((x) << PHY_CTRL4_LS_PRBS_EN_LSB) & PHY_CTRL4_LS_PRBS_EN_MASK)
+#define PHY_CTRL4_LS_PRBS_EN_RESET 0x0 // 0
+#define PHY_CTRL4_PPRBS_TERM_SEL_MSB 20
+#define PHY_CTRL4_PPRBS_TERM_SEL_LSB 20
+#define PHY_CTRL4_PPRBS_TERM_SEL_MASK 0x00100000
+#define PHY_CTRL4_PPRBS_TERM_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_TERM_SEL_MASK) >> PHY_CTRL4_PPRBS_TERM_SEL_LSB)
+#define PHY_CTRL4_PPRBS_TERM_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_TERM_SEL_LSB) & PHY_CTRL4_PPRBS_TERM_SEL_MASK)
+#define PHY_CTRL4_PPRBS_TERM_SEL_RESET 0x0 // 0
+#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_MSB 19
+#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB 19
+#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK 0x00080000
+#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK) >> PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB)
+#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB) & PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK)
+#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_RESET 0x0 // 0
+#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_MSB 18
+#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB 18
+#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK 0x00040000
+#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK) >> PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB)
+#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB) & PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK)
+#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_RESET 0x0 // 0
+#define PHY_CTRL4_PPRBS_PAT_SEL_MSB 17
+#define PHY_CTRL4_PPRBS_PAT_SEL_LSB 16
+#define PHY_CTRL4_PPRBS_PAT_SEL_MASK 0x00030000
+#define PHY_CTRL4_PPRBS_PAT_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_PAT_SEL_MASK) >> PHY_CTRL4_PPRBS_PAT_SEL_LSB)
+#define PHY_CTRL4_PPRBS_PAT_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_PAT_SEL_LSB) & PHY_CTRL4_PPRBS_PAT_SEL_MASK)
+#define PHY_CTRL4_PPRBS_PAT_SEL_RESET 0x0 // 0
+#define PHY_CTRL4_PPRBS_TX_EN_MSB 15
+#define PHY_CTRL4_PPRBS_TX_EN_LSB 15
+#define PHY_CTRL4_PPRBS_TX_EN_MASK 0x00008000
+#define PHY_CTRL4_PPRBS_TX_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_TX_EN_MASK) >> PHY_CTRL4_PPRBS_TX_EN_LSB)
+#define PHY_CTRL4_PPRBS_TX_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_TX_EN_LSB) & PHY_CTRL4_PPRBS_TX_EN_MASK)
+#define PHY_CTRL4_PPRBS_TX_EN_RESET 0x0 // 0
+#define PHY_CTRL4_PPRBS_RX_EN_MSB 14
+#define PHY_CTRL4_PPRBS_RX_EN_LSB 14
+#define PHY_CTRL4_PPRBS_RX_EN_MASK 0x00004000
+#define PHY_CTRL4_PPRBS_RX_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_RX_EN_MASK) >> PHY_CTRL4_PPRBS_RX_EN_LSB)
+#define PHY_CTRL4_PPRBS_RX_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_RX_EN_LSB) & PHY_CTRL4_PPRBS_RX_EN_MASK)
+#define PHY_CTRL4_PPRBS_RX_EN_RESET 0x0 // 0
+#define PHY_CTRL4_PPRBS_SPEED_SEL_MSB 13
+#define PHY_CTRL4_PPRBS_SPEED_SEL_LSB 13
+#define PHY_CTRL4_PPRBS_SPEED_SEL_MASK 0x00002000
+#define PHY_CTRL4_PPRBS_SPEED_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_SPEED_SEL_MASK) >> PHY_CTRL4_PPRBS_SPEED_SEL_LSB)
+#define PHY_CTRL4_PPRBS_SPEED_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_SPEED_SEL_LSB) & PHY_CTRL4_PPRBS_SPEED_SEL_MASK)
+#define PHY_CTRL4_PPRBS_SPEED_SEL_RESET 0x0 // 0
+#define PHY_CTRL4_PPRBS_RX_INV_MSB 12
+#define PHY_CTRL4_PPRBS_RX_INV_LSB 12
+#define PHY_CTRL4_PPRBS_RX_INV_MASK 0x00001000
+#define PHY_CTRL4_PPRBS_RX_INV_GET(x) (((x) & PHY_CTRL4_PPRBS_RX_INV_MASK) >> PHY_CTRL4_PPRBS_RX_INV_LSB)
+#define PHY_CTRL4_PPRBS_RX_INV_SET(x) (((x) << PHY_CTRL4_PPRBS_RX_INV_LSB) & PHY_CTRL4_PPRBS_RX_INV_MASK)
+#define PHY_CTRL4_PPRBS_RX_INV_RESET 0x0 // 0
+#define PHY_CTRL4_PWD_IRX_MSB 11
+#define PHY_CTRL4_PWD_IRX_LSB 0
+#define PHY_CTRL4_PWD_IRX_MASK 0x00000fff
+#define PHY_CTRL4_PWD_IRX_GET(x) (((x) & PHY_CTRL4_PWD_IRX_MASK) >> PHY_CTRL4_PWD_IRX_LSB)
+#define PHY_CTRL4_PWD_IRX_SET(x) (((x) << PHY_CTRL4_PWD_IRX_LSB) & PHY_CTRL4_PWD_IRX_MASK)
+#define PHY_CTRL4_PWD_IRX_RESET 0x6dd // 1757
+#define PHY_CTRL4_ADDRESS 0x18116c90
+#define PHY_CTRL4_OFFSET 0x0010
+// SW modifiable bits
+#define PHY_CTRL4_SW_MASK 0xff3fffff
+// bits defined at reset
+#define PHY_CTRL4_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PHY_CTRL4_RESET 0x000006dd
+
+#define PHY_CTRL5_SPARE_BITS_MSB 31
+#define PHY_CTRL5_SPARE_BITS_LSB 30
+#define PHY_CTRL5_SPARE_BITS_MASK 0xc0000000
+#define PHY_CTRL5_SPARE_BITS_GET(x) (((x) & PHY_CTRL5_SPARE_BITS_MASK) >> PHY_CTRL5_SPARE_BITS_LSB)
+#define PHY_CTRL5_SPARE_BITS_SET(x) (((x) << PHY_CTRL5_SPARE_BITS_LSB) & PHY_CTRL5_SPARE_BITS_MASK)
+#define PHY_CTRL5_SPARE_BITS_RESET 0x0 // 0
+#define PHY_CTRL5_HOST_RES_FIX_EN_MSB 29
+#define PHY_CTRL5_HOST_RES_FIX_EN_LSB 29
+#define PHY_CTRL5_HOST_RES_FIX_EN_MASK 0x20000000
+#define PHY_CTRL5_HOST_RES_FIX_EN_GET(x) (((x) & PHY_CTRL5_HOST_RES_FIX_EN_MASK) >> PHY_CTRL5_HOST_RES_FIX_EN_LSB)
+#define PHY_CTRL5_HOST_RES_FIX_EN_SET(x) (((x) << PHY_CTRL5_HOST_RES_FIX_EN_LSB) & PHY_CTRL5_HOST_RES_FIX_EN_MASK)
+#define PHY_CTRL5_HOST_RES_FIX_EN_RESET 0x1 // 1
+#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MSB 28
+#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB 26
+#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK 0x1c000000
+#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK) >> PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB)
+#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB) & PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK)
+#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_RESET 0x6 // 6
+#define PHY_CTRL5_HOST_DISCON_DETECT_ON_MSB 25
+#define PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB 25
+#define PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK 0x02000000
+#define PHY_CTRL5_HOST_DISCON_DETECT_ON_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK) >> PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB)
+#define PHY_CTRL5_HOST_DISCON_DETECT_ON_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB) & PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK)
+#define PHY_CTRL5_HOST_DISCON_DETECT_ON_RESET 0x1 // 1
+#define PHY_CTRL5_HOST_DISCON_FIX_ON_MSB 24
+#define PHY_CTRL5_HOST_DISCON_FIX_ON_LSB 24
+#define PHY_CTRL5_HOST_DISCON_FIX_ON_MASK 0x01000000
+#define PHY_CTRL5_HOST_DISCON_FIX_ON_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_FIX_ON_MASK) >> PHY_CTRL5_HOST_DISCON_FIX_ON_LSB)
+#define PHY_CTRL5_HOST_DISCON_FIX_ON_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_FIX_ON_LSB) & PHY_CTRL5_HOST_DISCON_FIX_ON_MASK)
+#define PHY_CTRL5_HOST_DISCON_FIX_ON_RESET 0x1 // 1
+#define PHY_CTRL5_DM_PULLDOWN_MSB 23
+#define PHY_CTRL5_DM_PULLDOWN_LSB 23
+#define PHY_CTRL5_DM_PULLDOWN_MASK 0x00800000
+#define PHY_CTRL5_DM_PULLDOWN_GET(x) (((x) & PHY_CTRL5_DM_PULLDOWN_MASK) >> PHY_CTRL5_DM_PULLDOWN_LSB)
+#define PHY_CTRL5_DM_PULLDOWN_SET(x) (((x) << PHY_CTRL5_DM_PULLDOWN_LSB) & PHY_CTRL5_DM_PULLDOWN_MASK)
+#define PHY_CTRL5_DM_PULLDOWN_RESET 0x0 // 0
+#define PHY_CTRL5_DP_PULLDOWN_MSB 22
+#define PHY_CTRL5_DP_PULLDOWN_LSB 22
+#define PHY_CTRL5_DP_PULLDOWN_MASK 0x00400000
+#define PHY_CTRL5_DP_PULLDOWN_GET(x) (((x) & PHY_CTRL5_DP_PULLDOWN_MASK) >> PHY_CTRL5_DP_PULLDOWN_LSB)
+#define PHY_CTRL5_DP_PULLDOWN_SET(x) (((x) << PHY_CTRL5_DP_PULLDOWN_LSB) & PHY_CTRL5_DP_PULLDOWN_MASK)
+#define PHY_CTRL5_DP_PULLDOWN_RESET 0x0 // 0
+#define PHY_CTRL5_SUSPEND_N_MSB 21
+#define PHY_CTRL5_SUSPEND_N_LSB 21
+#define PHY_CTRL5_SUSPEND_N_MASK 0x00200000
+#define PHY_CTRL5_SUSPEND_N_GET(x) (((x) & PHY_CTRL5_SUSPEND_N_MASK) >> PHY_CTRL5_SUSPEND_N_LSB)
+#define PHY_CTRL5_SUSPEND_N_SET(x) (((x) << PHY_CTRL5_SUSPEND_N_LSB) & PHY_CTRL5_SUSPEND_N_MASK)
+#define PHY_CTRL5_SUSPEND_N_RESET 0x1 // 1
+#define PHY_CTRL5_TERM_SEL_MSB 20
+#define PHY_CTRL5_TERM_SEL_LSB 20
+#define PHY_CTRL5_TERM_SEL_MASK 0x00100000
+#define PHY_CTRL5_TERM_SEL_GET(x) (((x) & PHY_CTRL5_TERM_SEL_MASK) >> PHY_CTRL5_TERM_SEL_LSB)
+#define PHY_CTRL5_TERM_SEL_SET(x) (((x) << PHY_CTRL5_TERM_SEL_LSB) & PHY_CTRL5_TERM_SEL_MASK)
+#define PHY_CTRL5_TERM_SEL_RESET 0x0 // 0
+#define PHY_CTRL5_XCVR_SEL_MSB 19
+#define PHY_CTRL5_XCVR_SEL_LSB 18
+#define PHY_CTRL5_XCVR_SEL_MASK 0x000c0000
+#define PHY_CTRL5_XCVR_SEL_GET(x) (((x) & PHY_CTRL5_XCVR_SEL_MASK) >> PHY_CTRL5_XCVR_SEL_LSB)
+#define PHY_CTRL5_XCVR_SEL_SET(x) (((x) << PHY_CTRL5_XCVR_SEL_LSB) & PHY_CTRL5_XCVR_SEL_MASK)
+#define PHY_CTRL5_XCVR_SEL_RESET 0x0 // 0
+#define PHY_CTRL5_TEST_JK_OVERRIDE_MSB 17
+#define PHY_CTRL5_TEST_JK_OVERRIDE_LSB 17
+#define PHY_CTRL5_TEST_JK_OVERRIDE_MASK 0x00020000
+#define PHY_CTRL5_TEST_JK_OVERRIDE_GET(x) (((x) & PHY_CTRL5_TEST_JK_OVERRIDE_MASK) >> PHY_CTRL5_TEST_JK_OVERRIDE_LSB)
+#define PHY_CTRL5_TEST_JK_OVERRIDE_SET(x) (((x) << PHY_CTRL5_TEST_JK_OVERRIDE_LSB) & PHY_CTRL5_TEST_JK_OVERRIDE_MASK)
+#define PHY_CTRL5_TEST_JK_OVERRIDE_RESET 0x0 // 0
+#define PHY_CTRL5_FORCE_TEST_SE0_NAK_MSB 16
+#define PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB 16
+#define PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK 0x00010000
+#define PHY_CTRL5_FORCE_TEST_SE0_NAK_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK) >> PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB)
+#define PHY_CTRL5_FORCE_TEST_SE0_NAK_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB) & PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK)
+#define PHY_CTRL5_FORCE_TEST_SE0_NAK_RESET 0x0 // 0
+#define PHY_CTRL5_FORCE_TEST_K_MSB 15
+#define PHY_CTRL5_FORCE_TEST_K_LSB 15
+#define PHY_CTRL5_FORCE_TEST_K_MASK 0x00008000
+#define PHY_CTRL5_FORCE_TEST_K_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_K_MASK) >> PHY_CTRL5_FORCE_TEST_K_LSB)
+#define PHY_CTRL5_FORCE_TEST_K_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_K_LSB) & PHY_CTRL5_FORCE_TEST_K_MASK)
+#define PHY_CTRL5_FORCE_TEST_K_RESET 0x0 // 0
+#define PHY_CTRL5_FORCE_TEST_J_MSB 14
+#define PHY_CTRL5_FORCE_TEST_J_LSB 14
+#define PHY_CTRL5_FORCE_TEST_J_MASK 0x00004000
+#define PHY_CTRL5_FORCE_TEST_J_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_J_MASK) >> PHY_CTRL5_FORCE_TEST_J_LSB)
+#define PHY_CTRL5_FORCE_TEST_J_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_J_LSB) & PHY_CTRL5_FORCE_TEST_J_MASK)
+#define PHY_CTRL5_FORCE_TEST_J_RESET 0x0 // 0
+#define PHY_CTRL5_FORCE_IDDQ_MSB 13
+#define PHY_CTRL5_FORCE_IDDQ_LSB 13
+#define PHY_CTRL5_FORCE_IDDQ_MASK 0x00002000
+#define PHY_CTRL5_FORCE_IDDQ_GET(x) (((x) & PHY_CTRL5_FORCE_IDDQ_MASK) >> PHY_CTRL5_FORCE_IDDQ_LSB)
+#define PHY_CTRL5_FORCE_IDDQ_SET(x) (((x) << PHY_CTRL5_FORCE_IDDQ_LSB) & PHY_CTRL5_FORCE_IDDQ_MASK)
+#define PHY_CTRL5_FORCE_IDDQ_RESET 0x0 // 0
+#define PHY_CTRL5_EB_WATERMARK_MSB 12
+#define PHY_CTRL5_EB_WATERMARK_LSB 7
+#define PHY_CTRL5_EB_WATERMARK_MASK 0x00001f80
+#define PHY_CTRL5_EB_WATERMARK_GET(x) (((x) & PHY_CTRL5_EB_WATERMARK_MASK) >> PHY_CTRL5_EB_WATERMARK_LSB)
+#define PHY_CTRL5_EB_WATERMARK_SET(x) (((x) << PHY_CTRL5_EB_WATERMARK_LSB) & PHY_CTRL5_EB_WATERMARK_MASK)
+#define PHY_CTRL5_EB_WATERMARK_RESET 0x14 // 20
+#define PHY_CTRL5_TX_BIAS_DELAY_MSB 6
+#define PHY_CTRL5_TX_BIAS_DELAY_LSB 0
+#define PHY_CTRL5_TX_BIAS_DELAY_MASK 0x0000007f
+#define PHY_CTRL5_TX_BIAS_DELAY_GET(x) (((x) & PHY_CTRL5_TX_BIAS_DELAY_MASK) >> PHY_CTRL5_TX_BIAS_DELAY_LSB)
+#define PHY_CTRL5_TX_BIAS_DELAY_SET(x) (((x) << PHY_CTRL5_TX_BIAS_DELAY_LSB) & PHY_CTRL5_TX_BIAS_DELAY_MASK)
+#define PHY_CTRL5_TX_BIAS_DELAY_RESET 0x32 // 50
+#define PHY_CTRL5_ADDRESS 0x18116c94
+#define PHY_CTRL5_OFFSET 0x0014
+// SW modifiable bits
+#define PHY_CTRL5_SW_MASK 0xffffffff
+// bits defined at reset
+#define PHY_CTRL5_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PHY_CTRL5_RESET 0x3b200a32
+#define PHY_CTRL5_RESET_1 0x3b202a58
+
+#define PHY_CTRL6_SPARE_BITS_MSB 31
+#define PHY_CTRL6_SPARE_BITS_LSB 9
+#define PHY_CTRL6_SPARE_BITS_MASK 0xfffffe00
+#define PHY_CTRL6_SPARE_BITS_GET(x) (((x) & PHY_CTRL6_SPARE_BITS_MASK) >> PHY_CTRL6_SPARE_BITS_LSB)
+#define PHY_CTRL6_SPARE_BITS_SET(x) (((x) << PHY_CTRL6_SPARE_BITS_LSB) & PHY_CTRL6_SPARE_BITS_MASK)
+#define PHY_CTRL6_SPARE_BITS_RESET 0x0 // 0
+#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_MSB 8
+#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB 8
+#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK 0x00000100
+#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_GET(x) (((x) & PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK) >> PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB)
+#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_SET(x) (((x) << PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB) & PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK)
+#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_RESET 0x0 // 0
+#define PHY_CTRL6_XCVR_SEL_MSB 7
+#define PHY_CTRL6_XCVR_SEL_LSB 6
+#define PHY_CTRL6_XCVR_SEL_MASK 0x000000c0
+#define PHY_CTRL6_XCVR_SEL_GET(x) (((x) & PHY_CTRL6_XCVR_SEL_MASK) >> PHY_CTRL6_XCVR_SEL_LSB)
+#define PHY_CTRL6_XCVR_SEL_SET(x) (((x) << PHY_CTRL6_XCVR_SEL_LSB) & PHY_CTRL6_XCVR_SEL_MASK)
+#define PHY_CTRL6_XCVR_SEL_RESET 0x0 // 0
+#define PHY_CTRL6_XCVRSEL_OVERRIDE_MSB 5
+#define PHY_CTRL6_XCVRSEL_OVERRIDE_LSB 5
+#define PHY_CTRL6_XCVRSEL_OVERRIDE_MASK 0x00000020
+#define PHY_CTRL6_XCVRSEL_OVERRIDE_GET(x) (((x) & PHY_CTRL6_XCVRSEL_OVERRIDE_MASK) >> PHY_CTRL6_XCVRSEL_OVERRIDE_LSB)
+#define PHY_CTRL6_XCVRSEL_OVERRIDE_SET(x) (((x) << PHY_CTRL6_XCVRSEL_OVERRIDE_LSB) & PHY_CTRL6_XCVRSEL_OVERRIDE_MASK)
+#define PHY_CTRL6_XCVRSEL_OVERRIDE_RESET 0x0 // 0
+#define PHY_CTRL6_IDDIG_MSB 4
+#define PHY_CTRL6_IDDIG_LSB 4
+#define PHY_CTRL6_IDDIG_MASK 0x00000010
+#define PHY_CTRL6_IDDIG_GET(x) (((x) & PHY_CTRL6_IDDIG_MASK) >> PHY_CTRL6_IDDIG_LSB)
+#define PHY_CTRL6_IDDIG_SET(x) (((x) << PHY_CTRL6_IDDIG_LSB) & PHY_CTRL6_IDDIG_MASK)
+#define PHY_CTRL6_IDDIG_RESET 0x0 // 0
+#define PHY_CTRL6_SESSEND_MSB 3
+#define PHY_CTRL6_SESSEND_LSB 3
+#define PHY_CTRL6_SESSEND_MASK 0x00000008
+#define PHY_CTRL6_SESSEND_GET(x) (((x) & PHY_CTRL6_SESSEND_MASK) >> PHY_CTRL6_SESSEND_LSB)
+#define PHY_CTRL6_SESSEND_SET(x) (((x) << PHY_CTRL6_SESSEND_LSB) & PHY_CTRL6_SESSEND_MASK)
+#define PHY_CTRL6_SESSEND_RESET 0x0 // 0
+#define PHY_CTRL6_VBUSVALID_MSB 2
+#define PHY_CTRL6_VBUSVALID_LSB 2
+#define PHY_CTRL6_VBUSVALID_MASK 0x00000004
+#define PHY_CTRL6_VBUSVALID_GET(x) (((x) & PHY_CTRL6_VBUSVALID_MASK) >> PHY_CTRL6_VBUSVALID_LSB)
+#define PHY_CTRL6_VBUSVALID_SET(x) (((x) << PHY_CTRL6_VBUSVALID_LSB) & PHY_CTRL6_VBUSVALID_MASK)
+#define PHY_CTRL6_VBUSVALID_RESET 0x1 // 1
+#define PHY_CTRL6_BVALID_MSB 1
+#define PHY_CTRL6_BVALID_LSB 1
+#define PHY_CTRL6_BVALID_MASK 0x00000002
+#define PHY_CTRL6_BVALID_GET(x) (((x) & PHY_CTRL6_BVALID_MASK) >> PHY_CTRL6_BVALID_LSB)
+#define PHY_CTRL6_BVALID_SET(x) (((x) << PHY_CTRL6_BVALID_LSB) & PHY_CTRL6_BVALID_MASK)
+#define PHY_CTRL6_BVALID_RESET 0x1 // 1
+#define PHY_CTRL6_AVALID_MSB 0
+#define PHY_CTRL6_AVALID_LSB 0
+#define PHY_CTRL6_AVALID_MASK 0x00000001
+#define PHY_CTRL6_AVALID_GET(x) (((x) & PHY_CTRL6_AVALID_MASK) >> PHY_CTRL6_AVALID_LSB)
+#define PHY_CTRL6_AVALID_SET(x) (((x) << PHY_CTRL6_AVALID_LSB) & PHY_CTRL6_AVALID_MASK)
+#define PHY_CTRL6_AVALID_RESET 0x1 // 1
+#define PHY_CTRL6_ADDRESS 0x18116c98
+#define PHY_CTRL6_OFFSET 0x0018
+// SW modifiable bits
+#define PHY_CTRL6_SW_MASK 0xffffffff
+// bits defined at reset
+#define PHY_CTRL6_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PHY_CTRL6_RESET 0x00000007
+
+#define PHY_STATUS_TX_CAL_MSB 3
+#define PHY_STATUS_TX_CAL_LSB 0
+#define PHY_STATUS_TX_CAL_MASK 0x0000000f
+#define PHY_STATUS_TX_CAL_GET(x) (((x) & PHY_STATUS_TX_CAL_MASK) >> PHY_STATUS_TX_CAL_LSB)
+#define PHY_STATUS_TX_CAL_SET(x) (((x) << PHY_STATUS_TX_CAL_LSB) & PHY_STATUS_TX_CAL_MASK)
+#define PHY_STATUS_TX_CAL_RESET 0x0 // 0
+#define PHY_STATUS_ADDRESS 0x18116c9c
+#define PHY_STATUS_OFFSET 0x001c
+// SW modifiable bits
+#define PHY_STATUS_SW_MASK 0x0000000f
+// bits defined at reset
+#define PHY_STATUS_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PHY_STATUS_RESET 0x00000000
+
+#define PHY_CTRL7_PPRBS_ERROR_RATE_MSB 31
+#define PHY_CTRL7_PPRBS_ERROR_RATE_LSB 11
+#define PHY_CTRL7_PPRBS_ERROR_RATE_MASK 0xfffff800
+#define PHY_CTRL7_PPRBS_ERROR_RATE_GET(x) (((x) & PHY_CTRL7_PPRBS_ERROR_RATE_MASK) >> PHY_CTRL7_PPRBS_ERROR_RATE_LSB)
+#define PHY_CTRL7_PPRBS_ERROR_RATE_SET(x) (((x) << PHY_CTRL7_PPRBS_ERROR_RATE_LSB) & PHY_CTRL7_PPRBS_ERROR_RATE_MASK)
+#define PHY_CTRL7_PPRBS_ERROR_RATE_RESET 0xa000 // 40960
+#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MSB 10
+#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB 1
+#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK 0x000007fe
+#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_GET(x) (((x) & PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK) >> PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB)
+#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_SET(x) (((x) << PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB) & PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK)
+#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_RESET 0x0 // 0
+#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_MSB 0
+#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB 0
+#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK 0x00000001
+#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_GET(x) (((x) & PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK) >> PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB)
+#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_SET(x) (((x) << PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB) & PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK)
+#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_RESET 0x0 // 0
+#define PHY_CTRL7_ADDRESS 0x18116ca0
+#define PHY_CTRL7_OFFSET 0x0020
+// SW modifiable bits
+#define PHY_CTRL7_SW_MASK 0xffffffff
+// bits defined at reset
+#define PHY_CTRL7_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PHY_CTRL7_RESET 0x05000000
+
+#define PHY_CTRL8_USBPLL_PWD_MSB 7
+#define PHY_CTRL8_USBPLL_PWD_LSB 7
+#define PHY_CTRL8_USBPLL_PWD_MASK 0x00000080
+#define PHY_CTRL8_USBPLL_PWD_GET(x) (((x) & PHY_CTRL8_USBPLL_PWD_MASK) >> PHY_CTRL8_USBPLL_PWD_LSB)
+#define PHY_CTRL8_USBPLL_PWD_SET(x) (((x) << PHY_CTRL8_USBPLL_PWD_LSB) & PHY_CTRL8_USBPLL_PWD_MASK)
+#define PHY_CTRL8_USBPLL_PWD_RESET 0x0 // 0
+#define PHY_CTRL8_TX_FASTRISE_MSB 6
+#define PHY_CTRL8_TX_FASTRISE_LSB 4
+#define PHY_CTRL8_TX_FASTRISE_MASK 0x00000070
+#define PHY_CTRL8_TX_FASTRISE_GET(x) (((x) & PHY_CTRL8_TX_FASTRISE_MASK) >> PHY_CTRL8_TX_FASTRISE_LSB)
+#define PHY_CTRL8_TX_FASTRISE_SET(x) (((x) << PHY_CTRL8_TX_FASTRISE_LSB) & PHY_CTRL8_TX_FASTRISE_MASK)
+#define PHY_CTRL8_TX_FASTRISE_RESET 0x5 // 5
+#define PHY_CTRL8_TX_ENPRE_MSB 3
+#define PHY_CTRL8_TX_ENPRE_LSB 2
+#define PHY_CTRL8_TX_ENPRE_MASK 0x0000000c
+#define PHY_CTRL8_TX_ENPRE_GET(x) (((x) & PHY_CTRL8_TX_ENPRE_MASK) >> PHY_CTRL8_TX_ENPRE_LSB)
+#define PHY_CTRL8_TX_ENPRE_SET(x) (((x) << PHY_CTRL8_TX_ENPRE_LSB) & PHY_CTRL8_TX_ENPRE_MASK)
+#define PHY_CTRL8_TX_ENPRE_RESET 0x0 // 0
+#define PHY_CTRL8_RX_SQ_HYST_EN_MSB 1
+#define PHY_CTRL8_RX_SQ_HYST_EN_LSB 1
+#define PHY_CTRL8_RX_SQ_HYST_EN_MASK 0x00000002
+#define PHY_CTRL8_RX_SQ_HYST_EN_GET(x) (((x) & PHY_CTRL8_RX_SQ_HYST_EN_MASK) >> PHY_CTRL8_RX_SQ_HYST_EN_LSB)
+#define PHY_CTRL8_RX_SQ_HYST_EN_SET(x) (((x) << PHY_CTRL8_RX_SQ_HYST_EN_LSB) & PHY_CTRL8_RX_SQ_HYST_EN_MASK)
+#define PHY_CTRL8_RX_SQ_HYST_EN_RESET 0x0 // 0
+#define PHY_CTRL8_RX_SKIP2_MSB 0
+#define PHY_CTRL8_RX_SKIP2_LSB 0
+#define PHY_CTRL8_RX_SKIP2_MASK 0x00000001
+#define PHY_CTRL8_RX_SKIP2_GET(x) (((x) & PHY_CTRL8_RX_SKIP2_MASK) >> PHY_CTRL8_RX_SKIP2_LSB)
+#define PHY_CTRL8_RX_SKIP2_SET(x) (((x) << PHY_CTRL8_RX_SKIP2_LSB) & PHY_CTRL8_RX_SKIP2_MASK)
+#define PHY_CTRL8_RX_SKIP2_RESET 0x0 // 0
+#define PHY_CTRL8_ADDRESS 0x18116ca4
+#define PHY_CTRL8_OFFSET 0x0024
+// SW modifiable bits
+#define PHY_CTRL8_SW_MASK 0x000000ff
+// bits defined at reset
+#define PHY_CTRL8_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PHY_CTRL8_RESET 0x00000050
+#define CPU_DDR_CLOCK_CONTROL_SPARE_MSB 31
+#define CPU_DDR_CLOCK_CONTROL_SPARE_LSB 25
+#define CPU_DDR_CLOCK_CONTROL_SPARE_MASK 0xfe000000
+#define CPU_DDR_CLOCK_CONTROL_SPARE_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) >> CPU_DDR_CLOCK_CONTROL_SPARE_LSB)
+#define CPU_DDR_CLOCK_CONTROL_SPARE_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_SPARE_LSB) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK)
+#define CPU_DDR_CLOCK_CONTROL_SPARE_RESET 0x0 // 0
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MSB 24
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB)
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET 0x1 // 1
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB 23
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB 23
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK 0x00800000
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET 0x0 // 0
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB 22
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB 22
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK 0x00400000
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET 0x0 // 0
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MSB 21
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB 21
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK 0x00200000
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB)
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK)
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_RESET 0x1 // 1
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MSB 20
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB 20
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK 0x00100000
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_RESET 0x1 // 1
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB 19
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB)
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET 0x0 // 0
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB 14
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET 0x0 // 0
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB 9
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET 0x0 // 0
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB 4
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB)
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET 0x1 // 1
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB 3
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB)
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET 0x1 // 1
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB 2
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET 0x1 // 1
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB 1
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB 1
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK 0x00000002
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB)
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK)
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET 0x0 // 0
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB 0
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB 0
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK 0x00000001
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET 0x0 // 0
+#define CPU_DDR_CLOCK_CONTROL_ADDRESS 0x18050008
+
+#define PCIE_PLL_CONFIG_UPDATING_MSB 31
+#define PCIE_PLL_CONFIG_UPDATING_LSB 31
+#define PCIE_PLL_CONFIG_UPDATING_MASK 0x80000000
+#define PCIE_PLL_CONFIG_UPDATING_GET(x) (((x) & PCIE_PLL_CONFIG_UPDATING_MASK) >> PCIE_PLL_CONFIG_UPDATING_LSB)
+#define PCIE_PLL_CONFIG_UPDATING_SET(x) (((x) << PCIE_PLL_CONFIG_UPDATING_LSB) & PCIE_PLL_CONFIG_UPDATING_MASK)
+#define PCIE_PLL_CONFIG_UPDATING_RESET 0x0 // 0
+#define PCIE_PLL_CONFIG_PLLPWD_MSB 30
+#define PCIE_PLL_CONFIG_PLLPWD_LSB 30
+#define PCIE_PLL_CONFIG_PLLPWD_MASK 0x40000000
+#define PCIE_PLL_CONFIG_PLLPWD_GET(x) (((x) & PCIE_PLL_CONFIG_PLLPWD_MASK) >> PCIE_PLL_CONFIG_PLLPWD_LSB)
+#define PCIE_PLL_CONFIG_PLLPWD_SET(x) (((x) << PCIE_PLL_CONFIG_PLLPWD_LSB) & PCIE_PLL_CONFIG_PLLPWD_MASK)
+#define PCIE_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
+#define PCIE_PLL_CONFIG_BYPASS_MSB 16
+#define PCIE_PLL_CONFIG_BYPASS_LSB 16
+#define PCIE_PLL_CONFIG_BYPASS_MASK 0x00010000
+#define PCIE_PLL_CONFIG_BYPASS_GET(x) (((x) & PCIE_PLL_CONFIG_BYPASS_MASK) >> PCIE_PLL_CONFIG_BYPASS_LSB)
+#define PCIE_PLL_CONFIG_BYPASS_SET(x) (((x) << PCIE_PLL_CONFIG_BYPASS_LSB) & PCIE_PLL_CONFIG_BYPASS_MASK)
+#define PCIE_PLL_CONFIG_BYPASS_RESET 0x1 // 1
+#define PCIE_PLL_CONFIG_REFDIV_MSB 14
+#define PCIE_PLL_CONFIG_REFDIV_LSB 10
+#define PCIE_PLL_CONFIG_REFDIV_MASK 0x00007c00
+#define PCIE_PLL_CONFIG_REFDIV_GET(x) (((x) & PCIE_PLL_CONFIG_REFDIV_MASK) >> PCIE_PLL_CONFIG_REFDIV_LSB)
+#define PCIE_PLL_CONFIG_REFDIV_SET(x) (((x) << PCIE_PLL_CONFIG_REFDIV_LSB) & PCIE_PLL_CONFIG_REFDIV_MASK)
+#define PCIE_PLL_CONFIG_REFDIV_RESET 0x1 // 1
+#define PCIE_PLL_CONFIG_ADDRESS 0x18050010
+
+#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MSB 31
+#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB 31
+#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK 0x80000000
+#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) >> PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB)
+#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK)
+#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_RESET 0x1 // 1
+#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MSB 30
+#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB 30
+#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK 0x40000000
+#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) >> PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB)
+#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK)
+#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_RESET 0x1 // 1
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MSB 20
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB 15
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK 0x001f8000
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB)
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK)
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_RESET 0x13 // 19
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MSB 14
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB 1
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK 0x00007ffe
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB)
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK)
+#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_RESET 0x3fff // 16383
+#define PCIE_PLL_DITHER_DIV_MAX_ADDRESS 0x18050014
+
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MSB 20
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB 15
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK 0x001f8000
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB)
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK)
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_RESET 0x13 // 19
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MSB 14
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB 1
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK 0x00007ffe
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB)
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK)
+#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_RESET 0x399d // 14749
+#define PCIE_PLL_DITHER_DIV_MIN_ADDRESS 0x18050018
+
+#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MSB 31
+#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB 28
+#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK 0xf0000000
+#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) >> PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB)
+#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK)
+#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_RESET 0x0 // 0
+#define PCIE_PLL_DITHER_STEP_STEP_INT_MSB 24
+#define PCIE_PLL_DITHER_STEP_STEP_INT_LSB 15
+#define PCIE_PLL_DITHER_STEP_STEP_INT_MASK 0x01ff8000
+#define PCIE_PLL_DITHER_STEP_STEP_INT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) >> PCIE_PLL_DITHER_STEP_STEP_INT_LSB)
+#define PCIE_PLL_DITHER_STEP_STEP_INT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_INT_LSB) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK)
+#define PCIE_PLL_DITHER_STEP_STEP_INT_RESET 0x0 // 0
+#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MSB 14
+#define PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB 1
+#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK 0x00007ffe
+#define PCIE_PLL_DITHER_STEP_STEP_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) >> PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB)
+#define PCIE_PLL_DITHER_STEP_STEP_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK)
+#define PCIE_PLL_DITHER_STEP_STEP_FRAC_RESET 0xa // 10
+#define PCIE_PLL_DITHER_STEP_ADDRESS 0x1805001c
+
+
+
+// 32'h180f0008 (PCIE_PWR_MGMT)
+#define PCIE_PWR_MGMT_PME_INT_MSB 8
+#define PCIE_PWR_MGMT_PME_INT_LSB 8
+#define PCIE_PWR_MGMT_PME_INT_MASK 0x00000100
+#define PCIE_PWR_MGMT_PME_INT_GET(x) (((x) & PCIE_PWR_MGMT_PME_INT_MASK) >> PCIE_PWR_MGMT_PME_INT_LSB)
+#define PCIE_PWR_MGMT_PME_INT_SET(x) (((x) << PCIE_PWR_MGMT_PME_INT_LSB) & PCIE_PWR_MGMT_PME_INT_MASK)
+#define PCIE_PWR_MGMT_PME_INT_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MSB 7
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB 7
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK 0x00000080
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_GET(x) (((x) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) >> PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB)
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(x) (((x) << PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK)
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MSB 6
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB 6
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK 0x00000040
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) >> PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB)
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK)
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_RADM_PM_PME_MSB 5
+#define PCIE_PWR_MGMT_RADM_PM_PME_LSB 5
+#define PCIE_PWR_MGMT_RADM_PM_PME_MASK 0x00000020
+#define PCIE_PWR_MGMT_RADM_PM_PME_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) >> PCIE_PWR_MGMT_RADM_PM_PME_LSB)
+#define PCIE_PWR_MGMT_RADM_PM_PME_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_PME_LSB) & PCIE_PWR_MGMT_RADM_PM_PME_MASK)
+#define PCIE_PWR_MGMT_RADM_PM_PME_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_AUX_PM_EN_MSB 4
+#define PCIE_PWR_MGMT_AUX_PM_EN_LSB 4
+#define PCIE_PWR_MGMT_AUX_PM_EN_MASK 0x00000010
+#define PCIE_PWR_MGMT_AUX_PM_EN_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) >> PCIE_PWR_MGMT_AUX_PM_EN_LSB)
+#define PCIE_PWR_MGMT_AUX_PM_EN_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PM_EN_LSB) & PCIE_PWR_MGMT_AUX_PM_EN_MASK)
+#define PCIE_PWR_MGMT_AUX_PM_EN_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_READY_ENTR_L23_MSB 3
+#define PCIE_PWR_MGMT_READY_ENTR_L23_LSB 3
+#define PCIE_PWR_MGMT_READY_ENTR_L23_MASK 0x00000008
+#define PCIE_PWR_MGMT_READY_ENTR_L23_GET(x) (((x) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) >> PCIE_PWR_MGMT_READY_ENTR_L23_LSB)
+#define PCIE_PWR_MGMT_READY_ENTR_L23_SET(x) (((x) << PCIE_PWR_MGMT_READY_ENTR_L23_LSB) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK)
+#define PCIE_PWR_MGMT_READY_ENTR_L23_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_MSB 2
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_LSB 2
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_MASK 0x00000004
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) >> PCIE_PWR_MGMT_REQ_EXIT_L1_LSB)
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK)
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MSB 1
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB 1
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK 0x00000002
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) >> PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB)
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK)
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_AUX_PWR_DET_MSB 0
+#define PCIE_PWR_MGMT_AUX_PWR_DET_LSB 0
+#define PCIE_PWR_MGMT_AUX_PWR_DET_MASK 0x00000001
+#define PCIE_PWR_MGMT_AUX_PWR_DET_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) >> PCIE_PWR_MGMT_AUX_PWR_DET_LSB)
+#define PCIE_PWR_MGMT_AUX_PWR_DET_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PWR_DET_LSB) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK)
+#define PCIE_PWR_MGMT_AUX_PWR_DET_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_ADDRESS 0x180f0008
+#define PCIE_PWR_MGMT_OFFSET 0x0008
+// SW modifiable bits
+#define PCIE_PWR_MGMT_SW_MASK 0x000001ff
+// bits defined at reset
+#define PCIE_PWR_MGMT_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PCIE_PWR_MGMT_RESET 0x00000000
+
+
+// 32'h180600c0 (RST_CLKGAT_EN)
+#define RST_CLKGAT_EN_SPARE_MSB 31
+#define RST_CLKGAT_EN_SPARE_LSB 12
+#define RST_CLKGAT_EN_SPARE_MASK 0xfffff000
+#define RST_CLKGAT_EN_SPARE_GET(x) (((x) & RST_CLKGAT_EN_SPARE_MASK) >> RST_CLKGAT_EN_SPARE_LSB)
+#define RST_CLKGAT_EN_SPARE_SET(x) (((x) << RST_CLKGAT_EN_SPARE_LSB) & RST_CLKGAT_EN_SPARE_MASK)
+#define RST_CLKGAT_EN_SPARE_RESET 0x0 // 0
+#define RST_CLKGAT_EN_WMAC_MSB 9
+#define RST_CLKGAT_EN_WMAC_LSB 9
+#define RST_CLKGAT_EN_WMAC_MASK 0x00000200
+#define RST_CLKGAT_EN_WMAC_GET(x) (((x) & RST_CLKGAT_EN_WMAC_MASK) >> RST_CLKGAT_EN_WMAC_LSB)
+#define RST_CLKGAT_EN_WMAC_SET(x) (((x) << RST_CLKGAT_EN_WMAC_LSB) & RST_CLKGAT_EN_WMAC_MASK)
+#define RST_CLKGAT_EN_WMAC_RESET 0x1 // 1
+#define RST_CLKGAT_EN_USB1_MSB 7
+#define RST_CLKGAT_EN_USB1_LSB 7
+#define RST_CLKGAT_EN_USB1_MASK 0x00000080
+#define RST_CLKGAT_EN_USB1_GET(x) (((x) & RST_CLKGAT_EN_USB1_MASK) >> RST_CLKGAT_EN_USB1_LSB)
+#define RST_CLKGAT_EN_USB1_SET(x) (((x) << RST_CLKGAT_EN_USB1_LSB) & RST_CLKGAT_EN_USB1_MASK)
+#define RST_CLKGAT_EN_USB1_RESET 0x1 // 1
+#define RST_CLKGAT_EN_GE1_MSB 6
+#define RST_CLKGAT_EN_GE1_LSB 6
+#define RST_CLKGAT_EN_GE1_MASK 0x00000040
+#define RST_CLKGAT_EN_GE1_GET(x) (((x) & RST_CLKGAT_EN_GE1_MASK) >> RST_CLKGAT_EN_GE1_LSB)
+#define RST_CLKGAT_EN_GE1_SET(x) (((x) << RST_CLKGAT_EN_GE1_LSB) & RST_CLKGAT_EN_GE1_MASK)
+#define RST_CLKGAT_EN_GE1_RESET 0x1 // 1
+#define RST_CLKGAT_EN_GE0_MSB 5
+#define RST_CLKGAT_EN_GE0_LSB 5
+#define RST_CLKGAT_EN_GE0_MASK 0x00000020
+#define RST_CLKGAT_EN_GE0_GET(x) (((x) & RST_CLKGAT_EN_GE0_MASK) >> RST_CLKGAT_EN_GE0_LSB)
+#define RST_CLKGAT_EN_GE0_SET(x) (((x) << RST_CLKGAT_EN_GE0_LSB) & RST_CLKGAT_EN_GE0_MASK)
+#define RST_CLKGAT_EN_GE0_RESET 0x1 // 1
+#define RST_CLKGAT_EN_PCIE_RC_MSB 1
+#define RST_CLKGAT_EN_PCIE_RC_LSB 1
+#define RST_CLKGAT_EN_PCIE_RC_MASK 0x00000002
+#define RST_CLKGAT_EN_PCIE_RC_GET(x) (((x) & RST_CLKGAT_EN_PCIE_RC_MASK) >> RST_CLKGAT_EN_PCIE_RC_LSB)
+#define RST_CLKGAT_EN_PCIE_RC_SET(x) (((x) << RST_CLKGAT_EN_PCIE_RC_LSB) & RST_CLKGAT_EN_PCIE_RC_MASK)
+#define RST_CLKGAT_EN_PCIE_RC_RESET 0x1 // 1
+#define RST_CLKGAT_EN_ADDRESS 0x180600c0
+#define RST_CLKGAT_EN_OFFSET 0x00c0
+// SW modifiable bits
+#define RST_CLKGAT_EN_SW_MASK 0xfffff2e2
+// bits defined at reset
+#define RST_CLKGAT_EN_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define RST_CLKGAT_EN_RESET 0x000002e2
+
+
+
+#define PCIE_PHY_REG_1_ADDRESS 0x18116cc0
+#define PCIE_PHY_REG_3_ADDRESS 0x18116cc8
+
+
+
+
+
+#define LDO_POWER_CONTROL_PKG_SEL_MSB 5
+#define LDO_POWER_CONTROL_PKG_SEL_LSB 5
+#define LDO_POWER_CONTROL_PKG_SEL_MASK 0x00000020
+#define LDO_POWER_CONTROL_PKG_SEL_GET(x) (((x) & LDO_POWER_CONTROL_PKG_SEL_MASK) >> LDO_POWER_CONTROL_PKG_SEL_LSB)
+#define LDO_POWER_CONTROL_PKG_SEL_SET(x) (((x) << LDO_POWER_CONTROL_PKG_SEL_LSB) & LDO_POWER_CONTROL_PKG_SEL_MASK)
+#define LDO_POWER_CONTROL_PKG_SEL_RESET 0x0 // 0
+#define LDO_POWER_CONTROL_PWDLDO_CPU_MSB 4
+#define LDO_POWER_CONTROL_PWDLDO_CPU_LSB 4
+#define LDO_POWER_CONTROL_PWDLDO_CPU_MASK 0x00000010
+#define LDO_POWER_CONTROL_PWDLDO_CPU_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) >> LDO_POWER_CONTROL_PWDLDO_CPU_LSB)
+#define LDO_POWER_CONTROL_PWDLDO_CPU_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_CPU_LSB) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK)
+#define LDO_POWER_CONTROL_PWDLDO_CPU_RESET 0x0 // 0
+#define LDO_POWER_CONTROL_PWDLDO_DDR_MSB 3
+#define LDO_POWER_CONTROL_PWDLDO_DDR_LSB 3
+#define LDO_POWER_CONTROL_PWDLDO_DDR_MASK 0x00000008
+#define LDO_POWER_CONTROL_PWDLDO_DDR_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) >> LDO_POWER_CONTROL_PWDLDO_DDR_LSB)
+#define LDO_POWER_CONTROL_PWDLDO_DDR_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_DDR_LSB) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK)
+#define LDO_POWER_CONTROL_PWDLDO_DDR_RESET 0x0 // 0
+#define LDO_POWER_CONTROL_CPU_REFSEL_MSB 2
+#define LDO_POWER_CONTROL_CPU_REFSEL_LSB 1
+#define LDO_POWER_CONTROL_CPU_REFSEL_MASK 0x00000006
+#define LDO_POWER_CONTROL_CPU_REFSEL_GET(x) (((x) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) >> LDO_POWER_CONTROL_CPU_REFSEL_LSB)
+#define LDO_POWER_CONTROL_CPU_REFSEL_SET(x) (((x) << LDO_POWER_CONTROL_CPU_REFSEL_LSB) & LDO_POWER_CONTROL_CPU_REFSEL_MASK)
+#define LDO_POWER_CONTROL_CPU_REFSEL_RESET 0x3 // 3
+#define LDO_POWER_CONTROL_SELECT_DDR1_MSB 0
+#define LDO_POWER_CONTROL_SELECT_DDR1_LSB 0
+#define LDO_POWER_CONTROL_SELECT_DDR1_MASK 0x00000001
+#define LDO_POWER_CONTROL_SELECT_DDR1_GET(x) (((x) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) >> LDO_POWER_CONTROL_SELECT_DDR1_LSB)
+#define LDO_POWER_CONTROL_SELECT_DDR1_SET(x) (((x) << LDO_POWER_CONTROL_SELECT_DDR1_LSB) & LDO_POWER_CONTROL_SELECT_DDR1_MASK)
+#define LDO_POWER_CONTROL_SELECT_DDR1_RESET 0x0 // 0
+#define LDO_POWER_CONTROL_ADDRESS 0x18050020
+
+#define SWITCH_CLOCK_SPARE_SPARE_MSB 31
+#define SWITCH_CLOCK_SPARE_SPARE_LSB 12
+#define SWITCH_CLOCK_SPARE_SPARE_MASK 0xfffff000
+#define SWITCH_CLOCK_SPARE_SPARE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB)
+#define SWITCH_CLOCK_SPARE_SPARE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK)
+#define SWITCH_CLOCK_SPARE_SPARE_RESET 0x0 // 0
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB 11
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB 8
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0x00000f00
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB)
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK)
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET 0x5 // 5
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB 7
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB 7
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK 0x00000080
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB)
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK)
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET 0x0 // 0
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MSB 6
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB 6
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK 0x00000040
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB)
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK)
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_RESET 0x0 // 0
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MSB 5
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB 5
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK 0x00000020
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_GET(x) (((x) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) >> SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB)
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_SET(x) (((x) << SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK)
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_RESET 0x1 // 1
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MSB 4
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB 4
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK 0x00000010
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_GET(x) (((x) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) >> SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB)
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_SET(x) (((x) << SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK)
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_RESET 0x1 // 1
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MSB 3
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB 3
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK 0x00000008
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_GET(x) (((x) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) >> SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB)
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_SET(x) (((x) << SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK)
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_RESET 0x0 // 0
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MSB 2
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB 2
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK 0x00000004
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB)
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK)
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_RESET 0x0 // 0
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MSB 1
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB 1
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK 0x00000002
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) >> SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB)
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK)
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_RESET 0x0 // 0
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MSB 0
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB 0
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK 0x00000001
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB)
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK)
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_RESET 0x1 // 1
+#define SWITCH_CLOCK_SPARE_ADDRESS 0x18050024
+
+#define CURRENT_PCIE_PLL_DITHER_INT_MSB 20
+#define CURRENT_PCIE_PLL_DITHER_INT_LSB 15
+#define CURRENT_PCIE_PLL_DITHER_INT_MASK 0x001f8000
+#define CURRENT_PCIE_PLL_DITHER_INT_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_INT_MASK) >> CURRENT_PCIE_PLL_DITHER_INT_LSB)
+#define CURRENT_PCIE_PLL_DITHER_INT_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_INT_LSB) & CURRENT_PCIE_PLL_DITHER_INT_MASK)
+#define CURRENT_PCIE_PLL_DITHER_INT_RESET 0x1 // 1
+#define CURRENT_PCIE_PLL_DITHER_FRAC_MSB 13
+#define CURRENT_PCIE_PLL_DITHER_FRAC_LSB 0
+#define CURRENT_PCIE_PLL_DITHER_FRAC_MASK 0x00003fff
+#define CURRENT_PCIE_PLL_DITHER_FRAC_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) >> CURRENT_PCIE_PLL_DITHER_FRAC_LSB)
+#define CURRENT_PCIE_PLL_DITHER_FRAC_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_FRAC_LSB) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK)
+#define CURRENT_PCIE_PLL_DITHER_FRAC_RESET 0x0 // 0
+#define CURRENT_PCIE_PLL_DITHER_ADDRESS 0x18050028
+
+#define ETH_XMII_TX_INVERT_MSB 31
+#define ETH_XMII_TX_INVERT_LSB 31
+#define ETH_XMII_TX_INVERT_MASK 0x80000000
+#define ETH_XMII_TX_INVERT_GET(x) (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB)
+#define ETH_XMII_TX_INVERT_SET(x) (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK)
+#define ETH_XMII_TX_INVERT_RESET 0x0 // 0
+#define ETH_XMII_GIGE_QUAD_MSB 30
+#define ETH_XMII_GIGE_QUAD_LSB 30
+#define ETH_XMII_GIGE_QUAD_MASK 0x40000000
+#define ETH_XMII_GIGE_QUAD_GET(x) (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB)
+#define ETH_XMII_GIGE_QUAD_SET(x) (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK)
+#define ETH_XMII_GIGE_QUAD_RESET 0x0 // 0
+#define ETH_XMII_RX_DELAY_MSB 29
+#define ETH_XMII_RX_DELAY_LSB 28
+#define ETH_XMII_RX_DELAY_MASK 0x30000000
+#define ETH_XMII_RX_DELAY_GET(x) (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB)
+#define ETH_XMII_RX_DELAY_SET(x) (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK)
+#define ETH_XMII_RX_DELAY_RESET 0x0 // 0
+#define ETH_XMII_TX_DELAY_MSB 27
+#define ETH_XMII_TX_DELAY_LSB 26
+#define ETH_XMII_TX_DELAY_MASK 0x0c000000
+#define ETH_XMII_TX_DELAY_GET(x) (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB)
+#define ETH_XMII_TX_DELAY_SET(x) (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK)
+#define ETH_XMII_TX_DELAY_RESET 0x0 // 0
+#define ETH_XMII_GIGE_MSB 25
+#define ETH_XMII_GIGE_LSB 25
+#define ETH_XMII_GIGE_MASK 0x02000000
+#define ETH_XMII_GIGE_GET(x) (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB)
+#define ETH_XMII_GIGE_SET(x) (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK)
+#define ETH_XMII_GIGE_RESET 0x0 // 0
+#define ETH_XMII_OFFSET_PHASE_MSB 24
+#define ETH_XMII_OFFSET_PHASE_LSB 24
+#define ETH_XMII_OFFSET_PHASE_MASK 0x01000000
+#define ETH_XMII_OFFSET_PHASE_GET(x) (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB)
+#define ETH_XMII_OFFSET_PHASE_SET(x) (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK)
+#define ETH_XMII_OFFSET_PHASE_RESET 0x0 // 0
+#define ETH_XMII_OFFSET_COUNT_MSB 23
+#define ETH_XMII_OFFSET_COUNT_LSB 16
+#define ETH_XMII_OFFSET_COUNT_MASK 0x00ff0000
+#define ETH_XMII_OFFSET_COUNT_GET(x) (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB)
+#define ETH_XMII_OFFSET_COUNT_SET(x) (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK)
+#define ETH_XMII_OFFSET_COUNT_RESET 0x0 // 0
+#define ETH_XMII_PHASE1_COUNT_MSB 15
+#define ETH_XMII_PHASE1_COUNT_LSB 8
+#define ETH_XMII_PHASE1_COUNT_MASK 0x0000ff00
+#define ETH_XMII_PHASE1_COUNT_GET(x) (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB)
+#define ETH_XMII_PHASE1_COUNT_SET(x) (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK)
+#define ETH_XMII_PHASE1_COUNT_RESET 0x1 // 1
+#define ETH_XMII_PHASE0_COUNT_MSB 7
+#define ETH_XMII_PHASE0_COUNT_LSB 0
+#define ETH_XMII_PHASE0_COUNT_MASK 0x000000ff
+#define ETH_XMII_PHASE0_COUNT_GET(x) (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB)
+#define ETH_XMII_PHASE0_COUNT_SET(x) (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK)
+#define ETH_XMII_PHASE0_COUNT_RESET 0x1 // 1
+#define ETH_XMII_ADDRESS 0x1805002c
+
+#define BB_PLL_CONFIG_UPDATING_MSB 31
+#define BB_PLL_CONFIG_UPDATING_LSB 31
+#define BB_PLL_CONFIG_UPDATING_MASK 0x80000000
+#define BB_PLL_CONFIG_UPDATING_GET(x) (((x) & BB_PLL_CONFIG_UPDATING_MASK) >> BB_PLL_CONFIG_UPDATING_LSB)
+#define BB_PLL_CONFIG_UPDATING_SET(x) (((x) << BB_PLL_CONFIG_UPDATING_LSB) & BB_PLL_CONFIG_UPDATING_MASK)
+#define BB_PLL_CONFIG_UPDATING_RESET 0x1 // 1
+#define BB_PLL_CONFIG_PLLPWD_MSB 30
+#define BB_PLL_CONFIG_PLLPWD_LSB 30
+#define BB_PLL_CONFIG_PLLPWD_MASK 0x40000000
+#define BB_PLL_CONFIG_PLLPWD_GET(x) (((x) & BB_PLL_CONFIG_PLLPWD_MASK) >> BB_PLL_CONFIG_PLLPWD_LSB)
+#define BB_PLL_CONFIG_PLLPWD_SET(x) (((x) << BB_PLL_CONFIG_PLLPWD_LSB) & BB_PLL_CONFIG_PLLPWD_MASK)
+#define BB_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
+#define BB_PLL_CONFIG_SPARE_MSB 29
+#define BB_PLL_CONFIG_SPARE_LSB 29
+#define BB_PLL_CONFIG_SPARE_MASK 0x20000000
+#define BB_PLL_CONFIG_SPARE_GET(x) (((x) & BB_PLL_CONFIG_SPARE_MASK) >> BB_PLL_CONFIG_SPARE_LSB)
+#define BB_PLL_CONFIG_SPARE_SET(x) (((x) << BB_PLL_CONFIG_SPARE_LSB) & BB_PLL_CONFIG_SPARE_MASK)
+#define BB_PLL_CONFIG_SPARE_RESET 0x0 // 0
+#define BB_PLL_CONFIG_REFDIV_MSB 28
+#define BB_PLL_CONFIG_REFDIV_LSB 24
+#define BB_PLL_CONFIG_REFDIV_MASK 0x1f000000
+#define BB_PLL_CONFIG_REFDIV_GET(x) (((x) & BB_PLL_CONFIG_REFDIV_MASK) >> BB_PLL_CONFIG_REFDIV_LSB)
+#define BB_PLL_CONFIG_REFDIV_SET(x) (((x) << BB_PLL_CONFIG_REFDIV_LSB) & BB_PLL_CONFIG_REFDIV_MASK)
+#define BB_PLL_CONFIG_REFDIV_RESET 0x1 // 1
+#define BB_PLL_CONFIG_NINT_MSB 21
+#define BB_PLL_CONFIG_NINT_LSB 16
+#define BB_PLL_CONFIG_NINT_MASK 0x003f0000
+#define BB_PLL_CONFIG_NINT_GET(x) (((x) & BB_PLL_CONFIG_NINT_MASK) >> BB_PLL_CONFIG_NINT_LSB)
+#define BB_PLL_CONFIG_NINT_SET(x) (((x) << BB_PLL_CONFIG_NINT_LSB) & BB_PLL_CONFIG_NINT_MASK)
+#define BB_PLL_CONFIG_NINT_RESET 0x2 // 2
+#define BB_PLL_CONFIG_NFRAC_MSB 13
+#define BB_PLL_CONFIG_NFRAC_LSB 0
+#define BB_PLL_CONFIG_NFRAC_MASK 0x00003fff
+#define BB_PLL_CONFIG_NFRAC_GET(x) (((x) & BB_PLL_CONFIG_NFRAC_MASK) >> BB_PLL_CONFIG_NFRAC_LSB)
+#define BB_PLL_CONFIG_NFRAC_SET(x) (((x) << BB_PLL_CONFIG_NFRAC_LSB) & BB_PLL_CONFIG_NFRAC_MASK)
+#define BB_PLL_CONFIG_NFRAC_RESET 0xccc // 3276
+#define BB_PLL_CONFIG_ADDRESS 0x18050040
+
+#define DDR_PLL_DITHER_DITHER_EN_MSB 31
+#define DDR_PLL_DITHER_DITHER_EN_LSB 31
+#define DDR_PLL_DITHER_DITHER_EN_MASK 0x80000000
+#define DDR_PLL_DITHER_DITHER_EN_GET(x) (((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB)
+#define DDR_PLL_DITHER_DITHER_EN_SET(x) (((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK)
+#define DDR_PLL_DITHER_DITHER_EN_RESET 0x0 // 0
+#define DDR_PLL_DITHER_UPDATE_COUNT_MSB 30
+#define DDR_PLL_DITHER_UPDATE_COUNT_LSB 27
+#define DDR_PLL_DITHER_UPDATE_COUNT_MASK 0x78000000
+#define DDR_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER_UPDATE_COUNT_LSB)
+#define DDR_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & DDR_PLL_DITHER_UPDATE_COUNT_MASK)
+#define DDR_PLL_DITHER_UPDATE_COUNT_RESET 0xf // 15
+#define DDR_PLL_DITHER_NFRAC_STEP_MSB 26
+#define DDR_PLL_DITHER_NFRAC_STEP_LSB 20
+#define DDR_PLL_DITHER_NFRAC_STEP_MASK 0x07f00000
+#define DDR_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> DDR_PLL_DITHER_NFRAC_STEP_LSB)
+#define DDR_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) & DDR_PLL_DITHER_NFRAC_STEP_MASK)
+#define DDR_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1
+#define DDR_PLL_DITHER_NFRAC_MIN_MSB 19
+#define DDR_PLL_DITHER_NFRAC_MIN_LSB 10
+#define DDR_PLL_DITHER_NFRAC_MIN_MASK 0x000ffc00
+#define DDR_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MIN_MASK) >> DDR_PLL_DITHER_NFRAC_MIN_LSB)
+#define DDR_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MIN_LSB) & DDR_PLL_DITHER_NFRAC_MIN_MASK)
+#define DDR_PLL_DITHER_NFRAC_MIN_RESET 0x19 // 25
+#define DDR_PLL_DITHER_NFRAC_MAX_MSB 9
+#define DDR_PLL_DITHER_NFRAC_MAX_LSB 0
+#define DDR_PLL_DITHER_NFRAC_MAX_MASK 0x000003ff
+#define DDR_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MAX_MASK) >> DDR_PLL_DITHER_NFRAC_MAX_LSB)
+#define DDR_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MAX_LSB) & DDR_PLL_DITHER_NFRAC_MAX_MASK)
+#define DDR_PLL_DITHER_NFRAC_MAX_RESET 0x3e8 // 1000
+#define DDR_PLL_DITHER_ADDRESS 0x18050044
+
+#define CPU_PLL_DITHER_DITHER_EN_MSB 31
+#define CPU_PLL_DITHER_DITHER_EN_LSB 31
+#define CPU_PLL_DITHER_DITHER_EN_MASK 0x80000000
+#define CPU_PLL_DITHER_DITHER_EN_GET(x) (((x) & CPU_PLL_DITHER_DITHER_EN_MASK) >> CPU_PLL_DITHER_DITHER_EN_LSB)
+#define CPU_PLL_DITHER_DITHER_EN_SET(x) (((x) << CPU_PLL_DITHER_DITHER_EN_LSB) & CPU_PLL_DITHER_DITHER_EN_MASK)
+#define CPU_PLL_DITHER_DITHER_EN_RESET 0x0 // 0
+#define CPU_PLL_DITHER_UPDATE_COUNT_MSB 23
+#define CPU_PLL_DITHER_UPDATE_COUNT_LSB 18
+#define CPU_PLL_DITHER_UPDATE_COUNT_MASK 0x00fc0000
+#define CPU_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) >> CPU_PLL_DITHER_UPDATE_COUNT_LSB)
+#define CPU_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) & CPU_PLL_DITHER_UPDATE_COUNT_MASK)
+#define CPU_PLL_DITHER_UPDATE_COUNT_RESET 0x14 // 20
+#define CPU_PLL_DITHER_NFRAC_STEP_MSB 17
+#define CPU_PLL_DITHER_NFRAC_STEP_LSB 12
+#define CPU_PLL_DITHER_NFRAC_STEP_MASK 0x0003f000
+#define CPU_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_STEP_MASK) >> CPU_PLL_DITHER_NFRAC_STEP_LSB)
+#define CPU_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) & CPU_PLL_DITHER_NFRAC_STEP_MASK)
+#define CPU_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1
+#define CPU_PLL_DITHER_NFRAC_MIN_MSB 11
+#define CPU_PLL_DITHER_NFRAC_MIN_LSB 6
+#define CPU_PLL_DITHER_NFRAC_MIN_MASK 0x00000fc0
+#define CPU_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MIN_MASK) >> CPU_PLL_DITHER_NFRAC_MIN_LSB)
+#define CPU_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MIN_LSB) & CPU_PLL_DITHER_NFRAC_MIN_MASK)
+#define CPU_PLL_DITHER_NFRAC_MIN_RESET 0x3 // 3
+#define CPU_PLL_DITHER_NFRAC_MAX_MSB 5
+#define CPU_PLL_DITHER_NFRAC_MAX_LSB 0
+#define CPU_PLL_DITHER_NFRAC_MAX_MASK 0x0000003f
+#define CPU_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MAX_MASK) >> CPU_PLL_DITHER_NFRAC_MAX_LSB)
+#define CPU_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MAX_LSB) & CPU_PLL_DITHER_NFRAC_MAX_MASK)
+#define CPU_PLL_DITHER_NFRAC_MAX_RESET 0x3c // 60
+#define CPU_PLL_DITHER_ADDRESS 0x18050048
+
+#define RST_RESET_USB_EXT_PWR_SEQ_MSB 29
+#define RST_RESET_USB_EXT_PWR_SEQ_LSB 29
+#define RST_RESET_USB_EXT_PWR_SEQ_MASK 0x20000000
+#define RST_RESET_USB_EXT_PWR_SEQ_GET(x) (((x) & RST_RESET_USB_EXT_PWR_SEQ_MASK) >> RST_RESET_USB_EXT_PWR_SEQ_LSB)
+#define RST_RESET_USB_EXT_PWR_SEQ_SET(x) (((x) << RST_RESET_USB_EXT_PWR_SEQ_LSB) & RST_RESET_USB_EXT_PWR_SEQ_MASK)
+#define RST_RESET_USB_EXT_PWR_SEQ_RESET 0x1 // 1
+#define RST_RESET_EXTERNAL_RESET_MSB 28
+#define RST_RESET_EXTERNAL_RESET_LSB 28
+#define RST_RESET_EXTERNAL_RESET_MASK 0x10000000
+#define RST_RESET_EXTERNAL_RESET_GET(x) (((x) & RST_RESET_EXTERNAL_RESET_MASK) >> RST_RESET_EXTERNAL_RESET_LSB)
+#define RST_RESET_EXTERNAL_RESET_SET(x) (((x) << RST_RESET_EXTERNAL_RESET_LSB) & RST_RESET_EXTERNAL_RESET_MASK)
+#define RST_RESET_EXTERNAL_RESET_RESET 0x0 // 0
+#define RST_RESET_RTC_RESET_MSB 27
+#define RST_RESET_RTC_RESET_LSB 27
+#define RST_RESET_RTC_RESET_MASK 0x08000000
+#define RST_RESET_RTC_RESET_GET(x) (((x) & RST_RESET_RTC_RESET_MASK) >> RST_RESET_RTC_RESET_LSB)
+#define RST_RESET_RTC_RESET_SET(x) (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)
+#define RST_RESET_RTC_RESET_RESET 0x1 // 1
+#define RST_RESET_FULL_CHIP_RESET_MSB 24
+#define RST_RESET_FULL_CHIP_RESET_LSB 24
+#define RST_RESET_FULL_CHIP_RESET_MASK 0x01000000
+#define RST_RESET_FULL_CHIP_RESET_GET(x) (((x) & RST_RESET_FULL_CHIP_RESET_MASK) >> RST_RESET_FULL_CHIP_RESET_LSB)
+#define RST_RESET_FULL_CHIP_RESET_SET(x) (((x) << RST_RESET_FULL_CHIP_RESET_LSB) & RST_RESET_FULL_CHIP_RESET_MASK)
+#define RST_RESET_FULL_CHIP_RESET_RESET 0x0 // 0
+#define RST_RESET_GE1_MDIO_RESET_MSB 23
+#define RST_RESET_GE1_MDIO_RESET_LSB 23
+#define RST_RESET_GE1_MDIO_RESET_MASK 0x00800000
+#define RST_RESET_GE1_MDIO_RESET_GET(x) (((x) & RST_RESET_GE1_MDIO_RESET_MASK) >> RST_RESET_GE1_MDIO_RESET_LSB)
+#define RST_RESET_GE1_MDIO_RESET_SET(x) (((x) << RST_RESET_GE1_MDIO_RESET_LSB) & RST_RESET_GE1_MDIO_RESET_MASK)
+#define RST_RESET_GE1_MDIO_RESET_RESET 0x1 // 1
+#define RST_RESET_GE0_MDIO_RESET_MSB 22
+#define RST_RESET_GE0_MDIO_RESET_LSB 22
+#define RST_RESET_GE0_MDIO_RESET_MASK 0x00400000
+#define RST_RESET_GE0_MDIO_RESET_GET(x) (((x) & RST_RESET_GE0_MDIO_RESET_MASK) >> RST_RESET_GE0_MDIO_RESET_LSB)
+#define RST_RESET_GE0_MDIO_RESET_SET(x) (((x) << RST_RESET_GE0_MDIO_RESET_LSB) & RST_RESET_GE0_MDIO_RESET_MASK)
+#define RST_RESET_GE0_MDIO_RESET_RESET 0x1 // 1
+#define RST_RESET_CPU_NMI_MSB 21
+#define RST_RESET_CPU_NMI_LSB 21
+#define RST_RESET_CPU_NMI_MASK 0x00200000
+#define RST_RESET_CPU_NMI_GET(x) (((x) & RST_RESET_CPU_NMI_MASK) >> RST_RESET_CPU_NMI_LSB)
+#define RST_RESET_CPU_NMI_SET(x) (((x) << RST_RESET_CPU_NMI_LSB) & RST_RESET_CPU_NMI_MASK)
+#define RST_RESET_CPU_NMI_RESET 0x0 // 0
+#define RST_RESET_CPU_COLD_RESET_MSB 20
+#define RST_RESET_CPU_COLD_RESET_LSB 20
+#define RST_RESET_CPU_COLD_RESET_MASK 0x00100000
+#define RST_RESET_CPU_COLD_RESET_GET(x) (((x) & RST_RESET_CPU_COLD_RESET_MASK) >> RST_RESET_CPU_COLD_RESET_LSB)
+#define RST_RESET_CPU_COLD_RESET_SET(x) (((x) << RST_RESET_CPU_COLD_RESET_LSB) & RST_RESET_CPU_COLD_RESET_MASK)
+#define RST_RESET_CPU_COLD_RESET_RESET 0x0 // 0
+#define RST_RESET_DDR_RESET_MSB 16
+#define RST_RESET_DDR_RESET_LSB 16
+#define RST_RESET_DDR_RESET_MASK 0x00010000
+#define RST_RESET_DDR_RESET_GET(x) (((x) & RST_RESET_DDR_RESET_MASK) >> RST_RESET_DDR_RESET_LSB)
+#define RST_RESET_DDR_RESET_SET(x) (((x) << RST_RESET_DDR_RESET_LSB) & RST_RESET_DDR_RESET_MASK)
+#define RST_RESET_DDR_RESET_RESET 0x0 // 0
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_MSB 15
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_LSB 15
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_MASK 0x00008000
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_GET(x) (((x) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) >> RST_RESET_USB_PHY_PLL_PWD_EXT_LSB)
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_SET(x) (((x) << RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK)
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_RESET 0x0 // 0
+#define RST_RESET_GE1_MAC_RESET_MSB 13
+#define RST_RESET_GE1_MAC_RESET_LSB 13
+#define RST_RESET_GE1_MAC_RESET_MASK 0x00002000
+#define RST_RESET_GE1_MAC_RESET_GET(x) (((x) & RST_RESET_GE1_MAC_RESET_MASK) >> RST_RESET_GE1_MAC_RESET_LSB)
+#define RST_RESET_GE1_MAC_RESET_SET(x) (((x) << RST_RESET_GE1_MAC_RESET_LSB) & RST_RESET_GE1_MAC_RESET_MASK)
+#define RST_RESET_GE1_MAC_RESET_RESET 0x1 // 1
+#define RST_RESET_ETH_SWITCH_ARESET_MSB 12
+#define RST_RESET_ETH_SWITCH_ARESET_LSB 12
+#define RST_RESET_ETH_SWITCH_ARESET_MASK 0x00001000
+#define RST_RESET_ETH_SWITCH_ARESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_ARESET_MASK) >> RST_RESET_ETH_SWITCH_ARESET_LSB)
+#define RST_RESET_ETH_SWITCH_ARESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_ARESET_LSB) & RST_RESET_ETH_SWITCH_ARESET_MASK)
+#define RST_RESET_ETH_SWITCH_ARESET_RESET 0x1 // 1
+#define RST_RESET_USB_PHY_ARESET_MSB 11
+#define RST_RESET_USB_PHY_ARESET_LSB 11
+#define RST_RESET_USB_PHY_ARESET_MASK 0x00000800
+#define RST_RESET_USB_PHY_ARESET_GET(x) (((x) & RST_RESET_USB_PHY_ARESET_MASK) >> RST_RESET_USB_PHY_ARESET_LSB)
+#define RST_RESET_USB_PHY_ARESET_SET(x) (((x) << RST_RESET_USB_PHY_ARESET_LSB) & RST_RESET_USB_PHY_ARESET_MASK)
+#define RST_RESET_USB_PHY_ARESET_RESET 0x1 // 1
+#define RST_RESET_GE0_MAC_RESET_MSB 9
+#define RST_RESET_GE0_MAC_RESET_LSB 9
+#define RST_RESET_GE0_MAC_RESET_MASK 0x00000200
+#define RST_RESET_GE0_MAC_RESET_GET(x) (((x) & RST_RESET_GE0_MAC_RESET_MASK) >> RST_RESET_GE0_MAC_RESET_LSB)
+#define RST_RESET_GE0_MAC_RESET_SET(x) (((x) << RST_RESET_GE0_MAC_RESET_LSB) & RST_RESET_GE0_MAC_RESET_MASK)
+#define RST_RESET_GE0_MAC_RESET_RESET 0x1 // 1
+#define RST_RESET_ETH_SWITCH_RESET_MSB 8
+#define RST_RESET_ETH_SWITCH_RESET_LSB 8
+#define RST_RESET_ETH_SWITCH_RESET_MASK 0x00000100
+#define RST_RESET_ETH_SWITCH_RESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_RESET_MASK) >> RST_RESET_ETH_SWITCH_RESET_LSB)
+#define RST_RESET_ETH_SWITCH_RESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_RESET_LSB) & RST_RESET_ETH_SWITCH_RESET_MASK)
+#define RST_RESET_ETH_SWITCH_RESET_RESET 0x1 // 1
+#define RST_RESET_PCIE_PHY_RESET_MSB 7
+#define RST_RESET_PCIE_PHY_RESET_LSB 7
+#define RST_RESET_PCIE_PHY_RESET_MASK 0x00000080
+#define RST_RESET_PCIE_PHY_RESET_GET(x) (((x) & RST_RESET_PCIE_PHY_RESET_MASK) >> RST_RESET_PCIE_PHY_RESET_LSB)
+#define RST_RESET_PCIE_PHY_RESET_SET(x) (((x) << RST_RESET_PCIE_PHY_RESET_LSB) & RST_RESET_PCIE_PHY_RESET_MASK)
+#define RST_RESET_PCIE_PHY_RESET_RESET 0x1 // 1
+#define RST_RESET_PCIE_RESET_MSB 6
+#define RST_RESET_PCIE_RESET_LSB 6
+#define RST_RESET_PCIE_RESET_MASK 0x00000040
+#define RST_RESET_PCIE_RESET_GET(x) (((x) & RST_RESET_PCIE_RESET_MASK) >> RST_RESET_PCIE_RESET_LSB)
+#define RST_RESET_PCIE_RESET_SET(x) (((x) << RST_RESET_PCIE_RESET_LSB) & RST_RESET_PCIE_RESET_MASK)
+#define RST_RESET_PCIE_RESET_RESET 0x1 // 1
+#define RST_RESET_USB_HOST_RESET_MSB 5
+#define RST_RESET_USB_HOST_RESET_LSB 5
+#define RST_RESET_USB_HOST_RESET_MASK 0x00000020
+#define RST_RESET_USB_HOST_RESET_GET(x) (((x) & RST_RESET_USB_HOST_RESET_MASK) >> RST_RESET_USB_HOST_RESET_LSB)
+#define RST_RESET_USB_HOST_RESET_SET(x) (((x) << RST_RESET_USB_HOST_RESET_LSB) & RST_RESET_USB_HOST_RESET_MASK)
+#define RST_RESET_USB_HOST_RESET_RESET 0x1 // 1
+#define RST_RESET_USB_PHY_RESET_MSB 4
+#define RST_RESET_USB_PHY_RESET_LSB 4
+#define RST_RESET_USB_PHY_RESET_MASK 0x00000010
+#define RST_RESET_USB_PHY_RESET_GET(x) (((x) & RST_RESET_USB_PHY_RESET_MASK) >> RST_RESET_USB_PHY_RESET_LSB)
+#define RST_RESET_USB_PHY_RESET_SET(x) (((x) << RST_RESET_USB_PHY_RESET_LSB) & RST_RESET_USB_PHY_RESET_MASK)
+#define RST_RESET_USB_PHY_RESET_RESET 0x1 // 1
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MSB 3
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB 3
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK 0x00000008
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_GET(x) (((x) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) >> RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB)
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(x) (((x) << RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK)
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_RESET 0x0 // 0
+#define RST_RESET_ADDRESS 0x1806001c
+
+
+#define RST_MISC2_SPARE_MSB 31
+#define RST_MISC2_SPARE_LSB 26
+#define RST_MISC2_SPARE_MASK 0xfc000000
+#define RST_MISC2_SPARE_GET(x) (((x) & RST_MISC2_SPARE_MASK) >> RST_MISC2_SPARE_LSB)
+#define RST_MISC2_SPARE_SET(x) (((x) << RST_MISC2_SPARE_LSB) & RST_MISC2_SPARE_MASK)
+#define RST_MISC2_SPARE_RESET 0x0 // 0
+#define RST_MISC2_PCIE_CLKOBS1_SEL_MSB 19
+#define RST_MISC2_PCIE_CLKOBS1_SEL_LSB 19
+#define RST_MISC2_PCIE_CLKOBS1_SEL_MASK 0x00080000
+#define RST_MISC2_PCIE_CLKOBS1_SEL_GET(x) (((x) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK) >> RST_MISC2_PCIE_CLKOBS1_SEL_LSB)
+#define RST_MISC2_PCIE_CLKOBS1_SEL_SET(x) (((x) << RST_MISC2_PCIE_CLKOBS1_SEL_LSB) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK)
+#define RST_MISC2_PCIE_CLKOBS1_SEL_RESET 0x0 // 0
+#define RST_MISC2_EXT_HOST_WASP_RST_EN_MSB 18
+#define RST_MISC2_EXT_HOST_WASP_RST_EN_LSB 18
+#define RST_MISC2_EXT_HOST_WASP_RST_EN_MASK 0x00040000
+#define RST_MISC2_EXT_HOST_WASP_RST_EN_GET(x) (((x) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) >> RST_MISC2_EXT_HOST_WASP_RST_EN_LSB)
+#define RST_MISC2_EXT_HOST_WASP_RST_EN_SET(x) (((x) << RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK)
+#define RST_MISC2_EXT_HOST_WASP_RST_EN_RESET 0x0 // 0
+#define RST_MISC2_PERSTN_RCPHY_MSB 13
+#define RST_MISC2_PERSTN_RCPHY_LSB 13
+#define RST_MISC2_PERSTN_RCPHY_MASK 0x00002000
+#define RST_MISC2_PERSTN_RCPHY_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY_MASK) >> RST_MISC2_PERSTN_RCPHY_LSB)
+#define RST_MISC2_PERSTN_RCPHY_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY_LSB) & RST_MISC2_PERSTN_RCPHY_MASK)
+#define RST_MISC2_PERSTN_RCPHY_RESET 0x1 // 1
+#define RST_MISC2_RESERVED_MSB 3
+#define RST_MISC2_RESERVED_LSB 1
+#define RST_MISC2_RESERVED_MASK 0x0000000e
+#define RST_MISC2_RESERVED_GET(x) (((x) & RST_MISC2_RESERVED_MASK) >> RST_MISC2_RESERVED_LSB)
+#define RST_MISC2_RESERVED_SET(x) (((x) << RST_MISC2_RESERVED_LSB) & RST_MISC2_RESERVED_MASK)
+#define RST_MISC2_RESERVED_RESET 0x0 // 0
+#define RST_MISC2_ADDRESS 0x180600bc
+
+#define PCIE_APP_CFG_TYPE_MSB 21
+#define PCIE_APP_CFG_TYPE_LSB 20
+#define PCIE_APP_CFG_TYPE_MASK 0x00300000
+#define PCIE_APP_CFG_TYPE_GET(x) (((x) & PCIE_APP_CFG_TYPE_MASK) >> PCIE_APP_CFG_TYPE_LSB)
+#define PCIE_APP_CFG_TYPE_SET(x) (((x) << PCIE_APP_CFG_TYPE_LSB) & PCIE_APP_CFG_TYPE_MASK)
+#define PCIE_APP_CFG_TYPE_RESET 0x0 // 0
+#define PCIE_APP_PCIE_BAR_MSN_MSB 19
+#define PCIE_APP_PCIE_BAR_MSN_LSB 16
+#define PCIE_APP_PCIE_BAR_MSN_MASK 0x000f0000
+#define PCIE_APP_PCIE_BAR_MSN_GET(x) (((x) & PCIE_APP_PCIE_BAR_MSN_MASK) >> PCIE_APP_PCIE_BAR_MSN_LSB)
+#define PCIE_APP_PCIE_BAR_MSN_SET(x) (((x) << PCIE_APP_PCIE_BAR_MSN_LSB) & PCIE_APP_PCIE_BAR_MSN_MASK)
+#define PCIE_APP_PCIE_BAR_MSN_RESET 0x1 // 1
+#define PCIE_APP_CFG_BE_MSB 15
+#define PCIE_APP_CFG_BE_LSB 12
+#define PCIE_APP_CFG_BE_MASK 0x0000f000
+#define PCIE_APP_CFG_BE_GET(x) (((x) & PCIE_APP_CFG_BE_MASK) >> PCIE_APP_CFG_BE_LSB)
+#define PCIE_APP_CFG_BE_SET(x) (((x) << PCIE_APP_CFG_BE_LSB) & PCIE_APP_CFG_BE_MASK)
+#define PCIE_APP_CFG_BE_RESET 0xf // 15
+#define PCIE_APP_SLV_RESP_ERR_MAP_MSB 11
+#define PCIE_APP_SLV_RESP_ERR_MAP_LSB 6
+#define PCIE_APP_SLV_RESP_ERR_MAP_MASK 0x00000fc0
+#define PCIE_APP_SLV_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_SLV_RESP_ERR_MAP_MASK) >> PCIE_APP_SLV_RESP_ERR_MAP_LSB)
+#define PCIE_APP_SLV_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_SLV_RESP_ERR_MAP_LSB) & PCIE_APP_SLV_RESP_ERR_MAP_MASK)
+#define PCIE_APP_SLV_RESP_ERR_MAP_RESET 0x3f // 63
+#define PCIE_APP_MSTR_RESP_ERR_MAP_MSB 5
+#define PCIE_APP_MSTR_RESP_ERR_MAP_LSB 4
+#define PCIE_APP_MSTR_RESP_ERR_MAP_MASK 0x00000030
+#define PCIE_APP_MSTR_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK) >> PCIE_APP_MSTR_RESP_ERR_MAP_LSB)
+#define PCIE_APP_MSTR_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_MSTR_RESP_ERR_MAP_LSB) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK)
+#define PCIE_APP_MSTR_RESP_ERR_MAP_RESET 0x0 // 0
+#define PCIE_APP_INIT_RST_MSB 3
+#define PCIE_APP_INIT_RST_LSB 3
+#define PCIE_APP_INIT_RST_MASK 0x00000008
+#define PCIE_APP_INIT_RST_GET(x) (((x) & PCIE_APP_INIT_RST_MASK) >> PCIE_APP_INIT_RST_LSB)
+#define PCIE_APP_INIT_RST_SET(x) (((x) << PCIE_APP_INIT_RST_LSB) & PCIE_APP_INIT_RST_MASK)
+#define PCIE_APP_INIT_RST_RESET 0x0 // 0
+#define PCIE_APP_PM_XMT_TURNOFF_MSB 2
+#define PCIE_APP_PM_XMT_TURNOFF_LSB 2
+#define PCIE_APP_PM_XMT_TURNOFF_MASK 0x00000004
+#define PCIE_APP_PM_XMT_TURNOFF_GET(x) (((x) & PCIE_APP_PM_XMT_TURNOFF_MASK) >> PCIE_APP_PM_XMT_TURNOFF_LSB)
+#define PCIE_APP_PM_XMT_TURNOFF_SET(x) (((x) << PCIE_APP_PM_XMT_TURNOFF_LSB) & PCIE_APP_PM_XMT_TURNOFF_MASK)
+#define PCIE_APP_PM_XMT_TURNOFF_RESET 0x0 // 0
+#define PCIE_APP_UNLOCK_MSG_MSB 1
+#define PCIE_APP_UNLOCK_MSG_LSB 1
+#define PCIE_APP_UNLOCK_MSG_MASK 0x00000002
+#define PCIE_APP_UNLOCK_MSG_GET(x) (((x) & PCIE_APP_UNLOCK_MSG_MASK) >> PCIE_APP_UNLOCK_MSG_LSB)
+#define PCIE_APP_UNLOCK_MSG_SET(x) (((x) << PCIE_APP_UNLOCK_MSG_LSB) & PCIE_APP_UNLOCK_MSG_MASK)
+#define PCIE_APP_UNLOCK_MSG_RESET 0x0 // 0
+#define PCIE_APP_LTSSM_ENABLE_MSB 0
+#define PCIE_APP_LTSSM_ENABLE_LSB 0
+#define PCIE_APP_LTSSM_ENABLE_MASK 0x00000001
+#define PCIE_APP_LTSSM_ENABLE_GET(x) (((x) & PCIE_APP_LTSSM_ENABLE_MASK) >> PCIE_APP_LTSSM_ENABLE_LSB)
+#define PCIE_APP_LTSSM_ENABLE_SET(x) (((x) << PCIE_APP_LTSSM_ENABLE_LSB) & PCIE_APP_LTSSM_ENABLE_MASK)
+#define PCIE_APP_LTSSM_ENABLE_RESET 0x0 // 0
+#define PCIE_APP_ADDRESS 0x180f0000
+
+#define PCIE_PWR_MGMT_PME_INT_MSB 8
+#define PCIE_PWR_MGMT_PME_INT_LSB 8
+#define PCIE_PWR_MGMT_PME_INT_MASK 0x00000100
+#define PCIE_PWR_MGMT_PME_INT_GET(x) (((x) & PCIE_PWR_MGMT_PME_INT_MASK) >> PCIE_PWR_MGMT_PME_INT_LSB)
+#define PCIE_PWR_MGMT_PME_INT_SET(x) (((x) << PCIE_PWR_MGMT_PME_INT_LSB) & PCIE_PWR_MGMT_PME_INT_MASK)
+#define PCIE_PWR_MGMT_PME_INT_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MSB 7
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB 7
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK 0x00000080
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_GET(x) (((x) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) >> PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB)
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(x) (((x) << PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK)
+#define PCIE_PWR_MGMT_ASSERT_CLKREQN_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MSB 6
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB 6
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK 0x00000040
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) >> PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB)
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK)
+#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_RADM_PM_PME_MSB 5
+#define PCIE_PWR_MGMT_RADM_PM_PME_LSB 5
+#define PCIE_PWR_MGMT_RADM_PM_PME_MASK 0x00000020
+#define PCIE_PWR_MGMT_RADM_PM_PME_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) >> PCIE_PWR_MGMT_RADM_PM_PME_LSB)
+#define PCIE_PWR_MGMT_RADM_PM_PME_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_PME_LSB) & PCIE_PWR_MGMT_RADM_PM_PME_MASK)
+#define PCIE_PWR_MGMT_RADM_PM_PME_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_AUX_PM_EN_MSB 4
+#define PCIE_PWR_MGMT_AUX_PM_EN_LSB 4
+#define PCIE_PWR_MGMT_AUX_PM_EN_MASK 0x00000010
+#define PCIE_PWR_MGMT_AUX_PM_EN_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) >> PCIE_PWR_MGMT_AUX_PM_EN_LSB)
+#define PCIE_PWR_MGMT_AUX_PM_EN_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PM_EN_LSB) & PCIE_PWR_MGMT_AUX_PM_EN_MASK)
+#define PCIE_PWR_MGMT_AUX_PM_EN_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_READY_ENTR_L23_MSB 3
+#define PCIE_PWR_MGMT_READY_ENTR_L23_LSB 3
+#define PCIE_PWR_MGMT_READY_ENTR_L23_MASK 0x00000008
+#define PCIE_PWR_MGMT_READY_ENTR_L23_GET(x) (((x) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) >> PCIE_PWR_MGMT_READY_ENTR_L23_LSB)
+#define PCIE_PWR_MGMT_READY_ENTR_L23_SET(x) (((x) << PCIE_PWR_MGMT_READY_ENTR_L23_LSB) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK)
+#define PCIE_PWR_MGMT_READY_ENTR_L23_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_MSB 2
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_LSB 2
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_MASK 0x00000004
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) >> PCIE_PWR_MGMT_REQ_EXIT_L1_LSB)
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK)
+#define PCIE_PWR_MGMT_REQ_EXIT_L1_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MSB 1
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB 1
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK 0x00000002
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) >> PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB)
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK)
+#define PCIE_PWR_MGMT_REQ_ENTRY_L1_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_AUX_PWR_DET_MSB 0
+#define PCIE_PWR_MGMT_AUX_PWR_DET_LSB 0
+#define PCIE_PWR_MGMT_AUX_PWR_DET_MASK 0x00000001
+#define PCIE_PWR_MGMT_AUX_PWR_DET_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) >> PCIE_PWR_MGMT_AUX_PWR_DET_LSB)
+#define PCIE_PWR_MGMT_AUX_PWR_DET_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PWR_DET_LSB) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK)
+#define PCIE_PWR_MGMT_AUX_PWR_DET_RESET 0x0 // 0
+#define PCIE_PWR_MGMT_ADDRESS 0x180f0008
+#define PCIE_PWR_MGMT_OFFSET 0x0008
+// SW modifiable bits
+#define PCIE_PWR_MGMT_SW_MASK 0x000001ff
+// bits defined at reset
+#define PCIE_PWR_MGMT_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PCIE_PWR_MGMT_RESET 0x00000000
+
+#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MSB 31
+#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB 31
+#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK 0x80000000
+#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK) >> PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB)
+#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK)
+#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MSB 30
+#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB 29
+#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK 0x60000000
+#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK) >> PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB)
+#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK)
+#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_PERSTDELAY_MSB 28
+#define PCIE_PHY_REG_1_PERSTDELAY_LSB 27
+#define PCIE_PHY_REG_1_PERSTDELAY_MASK 0x18000000
+#define PCIE_PHY_REG_1_PERSTDELAY_GET(x) (((x) & PCIE_PHY_REG_1_PERSTDELAY_MASK) >> PCIE_PHY_REG_1_PERSTDELAY_LSB)
+#define PCIE_PHY_REG_1_PERSTDELAY_SET(x) (((x) << PCIE_PHY_REG_1_PERSTDELAY_LSB) & PCIE_PHY_REG_1_PERSTDELAY_MASK)
+#define PCIE_PHY_REG_1_PERSTDELAY_RESET 0x2 // 2
+#define PCIE_PHY_REG_1_CLKOBSSEL_MSB 26
+#define PCIE_PHY_REG_1_CLKOBSSEL_LSB 25
+#define PCIE_PHY_REG_1_CLKOBSSEL_MASK 0x06000000
+#define PCIE_PHY_REG_1_CLKOBSSEL_GET(x) (((x) & PCIE_PHY_REG_1_CLKOBSSEL_MASK) >> PCIE_PHY_REG_1_CLKOBSSEL_LSB)
+#define PCIE_PHY_REG_1_CLKOBSSEL_SET(x) (((x) << PCIE_PHY_REG_1_CLKOBSSEL_LSB) & PCIE_PHY_REG_1_CLKOBSSEL_MASK)
+#define PCIE_PHY_REG_1_CLKOBSSEL_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_DATAOBSEN_MSB 24
+#define PCIE_PHY_REG_1_DATAOBSEN_LSB 24
+#define PCIE_PHY_REG_1_DATAOBSEN_MASK 0x01000000
+#define PCIE_PHY_REG_1_DATAOBSEN_GET(x) (((x) & PCIE_PHY_REG_1_DATAOBSEN_MASK) >> PCIE_PHY_REG_1_DATAOBSEN_LSB)
+#define PCIE_PHY_REG_1_DATAOBSEN_SET(x) (((x) << PCIE_PHY_REG_1_DATAOBSEN_LSB) & PCIE_PHY_REG_1_DATAOBSEN_MASK)
+#define PCIE_PHY_REG_1_DATAOBSEN_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_FUNCTESTEN_MSB 23
+#define PCIE_PHY_REG_1_FUNCTESTEN_LSB 23
+#define PCIE_PHY_REG_1_FUNCTESTEN_MASK 0x00800000
+#define PCIE_PHY_REG_1_FUNCTESTEN_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTEN_MASK) >> PCIE_PHY_REG_1_FUNCTESTEN_LSB)
+#define PCIE_PHY_REG_1_FUNCTESTEN_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTEN_LSB) & PCIE_PHY_REG_1_FUNCTESTEN_MASK)
+#define PCIE_PHY_REG_1_FUNCTESTEN_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_SERDES_DISABLE_MSB 22
+#define PCIE_PHY_REG_1_SERDES_DISABLE_LSB 22
+#define PCIE_PHY_REG_1_SERDES_DISABLE_MASK 0x00400000
+#define PCIE_PHY_REG_1_SERDES_DISABLE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK) >> PCIE_PHY_REG_1_SERDES_DISABLE_LSB)
+#define PCIE_PHY_REG_1_SERDES_DISABLE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DISABLE_LSB) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK)
+#define PCIE_PHY_REG_1_SERDES_DISABLE_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_RXCLKINV_MSB 21
+#define PCIE_PHY_REG_1_RXCLKINV_LSB 21
+#define PCIE_PHY_REG_1_RXCLKINV_MASK 0x00200000
+#define PCIE_PHY_REG_1_RXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_RXCLKINV_MASK) >> PCIE_PHY_REG_1_RXCLKINV_LSB)
+#define PCIE_PHY_REG_1_RXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_RXCLKINV_LSB) & PCIE_PHY_REG_1_RXCLKINV_MASK)
+#define PCIE_PHY_REG_1_RXCLKINV_RESET 0x1 // 1
+#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MSB 20
+#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB 20
+#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK 0x00100000
+#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB)
+#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK)
+#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MSB 19
+#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB 19
+#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK 0x00080000
+#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB)
+#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK)
+#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_ENABLECLKREQ_MSB 18
+#define PCIE_PHY_REG_1_ENABLECLKREQ_LSB 18
+#define PCIE_PHY_REG_1_ENABLECLKREQ_MASK 0x00040000
+#define PCIE_PHY_REG_1_ENABLECLKREQ_GET(x) (((x) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK) >> PCIE_PHY_REG_1_ENABLECLKREQ_LSB)
+#define PCIE_PHY_REG_1_ENABLECLKREQ_SET(x) (((x) << PCIE_PHY_REG_1_ENABLECLKREQ_LSB) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK)
+#define PCIE_PHY_REG_1_ENABLECLKREQ_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_FORCELOOPBACK_MSB 17
+#define PCIE_PHY_REG_1_FORCELOOPBACK_LSB 17
+#define PCIE_PHY_REG_1_FORCELOOPBACK_MASK 0x00020000
+#define PCIE_PHY_REG_1_FORCELOOPBACK_GET(x) (((x) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK) >> PCIE_PHY_REG_1_FORCELOOPBACK_LSB)
+#define PCIE_PHY_REG_1_FORCELOOPBACK_SET(x) (((x) << PCIE_PHY_REG_1_FORCELOOPBACK_LSB) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK)
+#define PCIE_PHY_REG_1_FORCELOOPBACK_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_SEL_CLK_MSB 16
+#define PCIE_PHY_REG_1_SEL_CLK_LSB 15
+#define PCIE_PHY_REG_1_SEL_CLK_MASK 0x00018000
+#define PCIE_PHY_REG_1_SEL_CLK_GET(x) (((x) & PCIE_PHY_REG_1_SEL_CLK_MASK) >> PCIE_PHY_REG_1_SEL_CLK_LSB)
+#define PCIE_PHY_REG_1_SEL_CLK_SET(x) (((x) << PCIE_PHY_REG_1_SEL_CLK_LSB) & PCIE_PHY_REG_1_SEL_CLK_MASK)
+#define PCIE_PHY_REG_1_SEL_CLK_RESET 0x2 // 2
+#define PCIE_PHY_REG_1_SERDES_RX_EQ_MSB 14
+#define PCIE_PHY_REG_1_SERDES_RX_EQ_LSB 14
+#define PCIE_PHY_REG_1_SERDES_RX_EQ_MASK 0x00004000
+#define PCIE_PHY_REG_1_SERDES_RX_EQ_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK) >> PCIE_PHY_REG_1_SERDES_RX_EQ_LSB)
+#define PCIE_PHY_REG_1_SERDES_RX_EQ_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_RX_EQ_LSB) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK)
+#define PCIE_PHY_REG_1_SERDES_RX_EQ_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MSB 13
+#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB 13
+#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK 0x00002000
+#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK) >> PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB)
+#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK)
+#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_RESET 0x1 // 1
+#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MSB 12
+#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB 12
+#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK 0x00001000
+#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) >> PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB)
+#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK)
+#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MSB 11
+#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB 11
+#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK 0x00000800
+#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK) >> PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB)
+#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK)
+#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_SERDES_CDR_BW_MSB 10
+#define PCIE_PHY_REG_1_SERDES_CDR_BW_LSB 9
+#define PCIE_PHY_REG_1_SERDES_CDR_BW_MASK 0x00000600
+#define PCIE_PHY_REG_1_SERDES_CDR_BW_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK) >> PCIE_PHY_REG_1_SERDES_CDR_BW_LSB)
+#define PCIE_PHY_REG_1_SERDES_CDR_BW_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_CDR_BW_LSB) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK)
+#define PCIE_PHY_REG_1_SERDES_CDR_BW_RESET 0x3 // 3
+#define PCIE_PHY_REG_1_SERDES_TH_LOS_MSB 8
+#define PCIE_PHY_REG_1_SERDES_TH_LOS_LSB 7
+#define PCIE_PHY_REG_1_SERDES_TH_LOS_MASK 0x00000180
+#define PCIE_PHY_REG_1_SERDES_TH_LOS_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK) >> PCIE_PHY_REG_1_SERDES_TH_LOS_LSB)
+#define PCIE_PHY_REG_1_SERDES_TH_LOS_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TH_LOS_LSB) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK)
+#define PCIE_PHY_REG_1_SERDES_TH_LOS_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MSB 6
+#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB 6
+#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK 0x00000040
+#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK) >> PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB)
+#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK)
+#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_RESET 0x1 // 1
+#define PCIE_PHY_REG_1_SERDES_HALFTXDR_MSB 5
+#define PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB 5
+#define PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK 0x00000020
+#define PCIE_PHY_REG_1_SERDES_HALFTXDR_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK) >> PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB)
+#define PCIE_PHY_REG_1_SERDES_HALFTXDR_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK)
+#define PCIE_PHY_REG_1_SERDES_HALFTXDR_RESET 0x0 // 0
+#define PCIE_PHY_REG_1_SERDES_SEL_HSP_MSB 4
+#define PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB 4
+#define PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK 0x00000010
+#define PCIE_PHY_REG_1_SERDES_SEL_HSP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK) >> PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB)
+#define PCIE_PHY_REG_1_SERDES_SEL_HSP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK)
+#define PCIE_PHY_REG_1_SERDES_SEL_HSP_RESET 0x1 // 1
+#define PCIE_PHY_REG_1_S_MSB 3
+#define PCIE_PHY_REG_1_S_LSB 0
+#define PCIE_PHY_REG_1_S_MASK 0x0000000f
+#define PCIE_PHY_REG_1_S_GET(x) (((x) & PCIE_PHY_REG_1_S_MASK) >> PCIE_PHY_REG_1_S_LSB)
+#define PCIE_PHY_REG_1_S_SET(x) (((x) << PCIE_PHY_REG_1_S_LSB) & PCIE_PHY_REG_1_S_MASK)
+#define PCIE_PHY_REG_1_S_RESET 0xe // 14
+#define PCIE_PHY_REG_1_ADDRESS 0x18116cc0
+#define PCIE_PHY_REG_1_OFFSET 0x0000
+// SW modifiable bits
+#define PCIE_PHY_REG_1_SW_MASK 0xffffffff
+// bits defined at reset
+#define PCIE_PHY_REG_1_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PCIE_PHY_REG_1_RESET 0x1021265e
+#define PCIE_PHY_REG_1_RESET_1 0x0061060e
+
+// 32'h18116cc4 (PCIE_PHY_REG_2)
+#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MSB 31
+#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB 24
+#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK 0xff000000
+#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK) >> PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB)
+#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB) & PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK)
+#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_RESET 0x0 // 0
+#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MSB 23
+#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB 23
+#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK 0x00800000
+#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_GET(x) (((x) & PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK) >> PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB)
+#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_SET(x) (((x) << PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB) & PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK)
+#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_RESET 0x0 // 0
+#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MSB 22
+#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB 22
+#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK 0x00400000
+#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_GET(x) (((x) & PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK) >> PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB)
+#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_SET(x) (((x) << PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB) & PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK)
+#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_RESET 0x0 // 0
+#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_MSB 21
+#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB 21
+#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK 0x00200000
+#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK) >> PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB)
+#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB) & PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK)
+#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_RESET 0x0 // 0
+#define PCIE_PHY_REG_2_PRBS_START_MSB 20
+#define PCIE_PHY_REG_2_PRBS_START_LSB 20
+#define PCIE_PHY_REG_2_PRBS_START_MASK 0x00100000
+#define PCIE_PHY_REG_2_PRBS_START_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_START_MASK) >> PCIE_PHY_REG_2_PRBS_START_LSB)
+#define PCIE_PHY_REG_2_PRBS_START_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_START_LSB) & PCIE_PHY_REG_2_PRBS_START_MASK)
+#define PCIE_PHY_REG_2_PRBS_START_RESET 0x0 // 0
+#define PCIE_PHY_REG_2_PRBS_TS_NUM_MSB 19
+#define PCIE_PHY_REG_2_PRBS_TS_NUM_LSB 13
+#define PCIE_PHY_REG_2_PRBS_TS_NUM_MASK 0x000fe000
+#define PCIE_PHY_REG_2_PRBS_TS_NUM_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_TS_NUM_MASK) >> PCIE_PHY_REG_2_PRBS_TS_NUM_LSB)
+#define PCIE_PHY_REG_2_PRBS_TS_NUM_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_TS_NUM_LSB) & PCIE_PHY_REG_2_PRBS_TS_NUM_MASK)
+#define PCIE_PHY_REG_2_PRBS_TS_NUM_RESET 0x40 // 64
+#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_MSB 12
+#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB 12
+#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK 0x00001000
+#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK) >> PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB)
+#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB) & PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK)
+#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_RESET 0x0 // 0
+#define PCIE_PHY_REG_2_TXDETRXOVREN_MSB 11
+#define PCIE_PHY_REG_2_TXDETRXOVREN_LSB 11
+#define PCIE_PHY_REG_2_TXDETRXOVREN_MASK 0x00000800
+#define PCIE_PHY_REG_2_TXDETRXOVREN_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXOVREN_MASK) >> PCIE_PHY_REG_2_TXDETRXOVREN_LSB)
+#define PCIE_PHY_REG_2_TXDETRXOVREN_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXOVREN_LSB) & PCIE_PHY_REG_2_TXDETRXOVREN_MASK)
+#define PCIE_PHY_REG_2_TXDETRXOVREN_RESET 0x0 // 0
+#define PCIE_PHY_REG_2_DATAOBSPRBSERR_MSB 10
+#define PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB 10
+#define PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK 0x00000400
+#define PCIE_PHY_REG_2_DATAOBSPRBSERR_GET(x) (((x) & PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK) >> PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB)
+#define PCIE_PHY_REG_2_DATAOBSPRBSERR_SET(x) (((x) << PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB) & PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK)
+#define PCIE_PHY_REG_2_DATAOBSPRBSERR_RESET 0x0 // 0
+#define PCIE_PHY_REG_2_CDRREADYTIMER_MSB 9
+#define PCIE_PHY_REG_2_CDRREADYTIMER_LSB 6
+#define PCIE_PHY_REG_2_CDRREADYTIMER_MASK 0x000003c0
+#define PCIE_PHY_REG_2_CDRREADYTIMER_GET(x) (((x) & PCIE_PHY_REG_2_CDRREADYTIMER_MASK) >> PCIE_PHY_REG_2_CDRREADYTIMER_LSB)
+#define PCIE_PHY_REG_2_CDRREADYTIMER_SET(x) (((x) << PCIE_PHY_REG_2_CDRREADYTIMER_LSB) & PCIE_PHY_REG_2_CDRREADYTIMER_MASK)
+#define PCIE_PHY_REG_2_CDRREADYTIMER_RESET 0x7 // 7
+#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MSB 5
+#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB 1
+#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK 0x0000003e
+#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK) >> PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB)
+#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB) & PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK)
+#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_RESET 0xc // 12
+#define PCIE_PHY_REG_2_FORCEDETECT_MSB 0
+#define PCIE_PHY_REG_2_FORCEDETECT_LSB 0
+#define PCIE_PHY_REG_2_FORCEDETECT_MASK 0x00000001
+#define PCIE_PHY_REG_2_FORCEDETECT_GET(x) (((x) & PCIE_PHY_REG_2_FORCEDETECT_MASK) >> PCIE_PHY_REG_2_FORCEDETECT_LSB)
+#define PCIE_PHY_REG_2_FORCEDETECT_SET(x) (((x) << PCIE_PHY_REG_2_FORCEDETECT_LSB) & PCIE_PHY_REG_2_FORCEDETECT_MASK)
+#define PCIE_PHY_REG_2_FORCEDETECT_RESET 0x0 // 0
+#define PCIE_PHY_REG_2_ADDRESS 0x18116cc4
+#define PCIE_PHY_REG_2_OFFSET 0x0004
+// SW modifiable bits
+#define PCIE_PHY_REG_2_SW_MASK 0xffffffff
+// bits defined at reset
+#define PCIE_PHY_REG_2_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PCIE_PHY_REG_2_RESET 0x000801d8
+
+#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MSB 31
+#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB 28
+#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK 0xf0000000
+#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_GET(x) (((x) & PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK) >> PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB)
+#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_SET(x) (((x) << PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB) & PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK)
+#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_RESET 0x0 // 0
+#define PCIE_PHY_REG_3_SPARE_MSB 27
+#define PCIE_PHY_REG_3_SPARE_LSB 11
+#define PCIE_PHY_REG_3_SPARE_MASK 0x0ffff800
+#define PCIE_PHY_REG_3_SPARE_GET(x) (((x) & PCIE_PHY_REG_3_SPARE_MASK) >> PCIE_PHY_REG_3_SPARE_LSB)
+#define PCIE_PHY_REG_3_SPARE_SET(x) (((x) << PCIE_PHY_REG_3_SPARE_LSB) & PCIE_PHY_REG_3_SPARE_MASK)
+#define PCIE_PHY_REG_3_SPARE_RESET 0xa0b // 2571
+#define PCIE_PHY_REG_3_SEL_CLK100_MSB 10
+#define PCIE_PHY_REG_3_SEL_CLK100_LSB 10
+#define PCIE_PHY_REG_3_SEL_CLK100_MASK 0x00000400
+#define PCIE_PHY_REG_3_SEL_CLK100_GET(x) (((x) & PCIE_PHY_REG_3_SEL_CLK100_MASK) >> PCIE_PHY_REG_3_SEL_CLK100_LSB)
+#define PCIE_PHY_REG_3_SEL_CLK100_SET(x) (((x) << PCIE_PHY_REG_3_SEL_CLK100_LSB) & PCIE_PHY_REG_3_SEL_CLK100_MASK)
+#define PCIE_PHY_REG_3_SEL_CLK100_RESET 0x0 // 0
+#define PCIE_PHY_REG_3_EN_BEACONGEN_MSB 9
+#define PCIE_PHY_REG_3_EN_BEACONGEN_LSB 9
+#define PCIE_PHY_REG_3_EN_BEACONGEN_MASK 0x00000200
+#define PCIE_PHY_REG_3_EN_BEACONGEN_GET(x) (((x) & PCIE_PHY_REG_3_EN_BEACONGEN_MASK) >> PCIE_PHY_REG_3_EN_BEACONGEN_LSB)
+#define PCIE_PHY_REG_3_EN_BEACONGEN_SET(x) (((x) << PCIE_PHY_REG_3_EN_BEACONGEN_LSB) & PCIE_PHY_REG_3_EN_BEACONGEN_MASK)
+#define PCIE_PHY_REG_3_EN_BEACONGEN_RESET 0x0 // 0
+#define PCIE_PHY_REG_3_TXELECIDLE_MSB 8
+#define PCIE_PHY_REG_3_TXELECIDLE_LSB 8
+#define PCIE_PHY_REG_3_TXELECIDLE_MASK 0x00000100
+#define PCIE_PHY_REG_3_TXELECIDLE_GET(x) (((x) & PCIE_PHY_REG_3_TXELECIDLE_MASK) >> PCIE_PHY_REG_3_TXELECIDLE_LSB)
+#define PCIE_PHY_REG_3_TXELECIDLE_SET(x) (((x) << PCIE_PHY_REG_3_TXELECIDLE_LSB) & PCIE_PHY_REG_3_TXELECIDLE_MASK)
+#define PCIE_PHY_REG_3_TXELECIDLE_RESET 0x0 // 0
+#define PCIE_PHY_REG_3_SEL_CLK_MSB 7
+#define PCIE_PHY_REG_3_SEL_CLK_LSB 6
+#define PCIE_PHY_REG_3_SEL_CLK_MASK 0x000000c0
+#define PCIE_PHY_REG_3_SEL_CLK_GET(x) (((x) & PCIE_PHY_REG_3_SEL_CLK_MASK) >> PCIE_PHY_REG_3_SEL_CLK_LSB)
+#define PCIE_PHY_REG_3_SEL_CLK_SET(x) (((x) << PCIE_PHY_REG_3_SEL_CLK_LSB) & PCIE_PHY_REG_3_SEL_CLK_MASK)
+#define PCIE_PHY_REG_3_SEL_CLK_RESET 0x0 // 0
+#define PCIE_PHY_REG_3_RX_DET_REQ_MSB 5
+#define PCIE_PHY_REG_3_RX_DET_REQ_LSB 5
+#define PCIE_PHY_REG_3_RX_DET_REQ_MASK 0x00000020
+#define PCIE_PHY_REG_3_RX_DET_REQ_GET(x) (((x) & PCIE_PHY_REG_3_RX_DET_REQ_MASK) >> PCIE_PHY_REG_3_RX_DET_REQ_LSB)
+#define PCIE_PHY_REG_3_RX_DET_REQ_SET(x) (((x) << PCIE_PHY_REG_3_RX_DET_REQ_LSB) & PCIE_PHY_REG_3_RX_DET_REQ_MASK)
+#define PCIE_PHY_REG_3_RX_DET_REQ_RESET 0x0 // 0
+#define PCIE_PHY_REG_3_MODE_OCLK_IN_MSB 4
+#define PCIE_PHY_REG_3_MODE_OCLK_IN_LSB 4
+#define PCIE_PHY_REG_3_MODE_OCLK_IN_MASK 0x00000010
+#define PCIE_PHY_REG_3_MODE_OCLK_IN_GET(x) (((x) & PCIE_PHY_REG_3_MODE_OCLK_IN_MASK) >> PCIE_PHY_REG_3_MODE_OCLK_IN_LSB)
+#define PCIE_PHY_REG_3_MODE_OCLK_IN_SET(x) (((x) << PCIE_PHY_REG_3_MODE_OCLK_IN_LSB) & PCIE_PHY_REG_3_MODE_OCLK_IN_MASK)
+#define PCIE_PHY_REG_3_MODE_OCLK_IN_RESET 0x0 // 0
+#define PCIE_PHY_REG_3_EN_PLL_MSB 3
+#define PCIE_PHY_REG_3_EN_PLL_LSB 3
+#define PCIE_PHY_REG_3_EN_PLL_MASK 0x00000008
+#define PCIE_PHY_REG_3_EN_PLL_GET(x) (((x) & PCIE_PHY_REG_3_EN_PLL_MASK) >> PCIE_PHY_REG_3_EN_PLL_LSB)
+#define PCIE_PHY_REG_3_EN_PLL_SET(x) (((x) << PCIE_PHY_REG_3_EN_PLL_LSB) & PCIE_PHY_REG_3_EN_PLL_MASK)
+#define PCIE_PHY_REG_3_EN_PLL_RESET 0x1 // 1
+#define PCIE_PHY_REG_3_EN_LCKDT_MSB 2
+#define PCIE_PHY_REG_3_EN_LCKDT_LSB 2
+#define PCIE_PHY_REG_3_EN_LCKDT_MASK 0x00000004
+#define PCIE_PHY_REG_3_EN_LCKDT_GET(x) (((x) & PCIE_PHY_REG_3_EN_LCKDT_MASK) >> PCIE_PHY_REG_3_EN_LCKDT_LSB)
+#define PCIE_PHY_REG_3_EN_LCKDT_SET(x) (((x) << PCIE_PHY_REG_3_EN_LCKDT_LSB) & PCIE_PHY_REG_3_EN_LCKDT_MASK)
+#define PCIE_PHY_REG_3_EN_LCKDT_RESET 0x1 // 1
+#define PCIE_PHY_REG_3_EN_BUFS_RX_MSB 1
+#define PCIE_PHY_REG_3_EN_BUFS_RX_LSB 1
+#define PCIE_PHY_REG_3_EN_BUFS_RX_MASK 0x00000002
+#define PCIE_PHY_REG_3_EN_BUFS_RX_GET(x) (((x) & PCIE_PHY_REG_3_EN_BUFS_RX_MASK) >> PCIE_PHY_REG_3_EN_BUFS_RX_LSB)
+#define PCIE_PHY_REG_3_EN_BUFS_RX_SET(x) (((x) << PCIE_PHY_REG_3_EN_BUFS_RX_LSB) & PCIE_PHY_REG_3_EN_BUFS_RX_MASK)
+#define PCIE_PHY_REG_3_EN_BUFS_RX_RESET 0x0 // 0
+#define PCIE_PHY_REG_3_EN_MSB 0
+#define PCIE_PHY_REG_3_EN_LSB 0
+#define PCIE_PHY_REG_3_EN_MASK 0x00000001
+#define PCIE_PHY_REG_3_EN_GET(x) (((x) & PCIE_PHY_REG_3_EN_MASK) >> PCIE_PHY_REG_3_EN_LSB)
+#define PCIE_PHY_REG_3_EN_SET(x) (((x) << PCIE_PHY_REG_3_EN_LSB) & PCIE_PHY_REG_3_EN_MASK)
+#define PCIE_PHY_REG_3_EN_RESET 0x0 // 0
+#define PCIE_PHY_REG_3_ADDRESS 0x18116cc8
+#define PCIE_PHY_REG_3_OFFSET 0x0008
+// SW modifiable bits
+#define PCIE_PHY_REG_3_SW_MASK 0xffffffff
+// bits defined at reset
+#define PCIE_PHY_REG_3_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PCIE_PHY_REG_3_RESET 0x0050580c
+#define PCIE_PHY_REG_3_RESET_1 0x00505900
+
+#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_MSB 31
+#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB 11
+#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK 0xfffff800
+#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK) >> PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB)
+#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB) & PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK)
+#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_RESET 0xa000 // 40960
+#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MSB 10
+#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB 1
+#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK 0x000007fe
+#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK) >> PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB)
+#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB) & PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK)
+#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_RESET 0x0 // 0
+#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MSB 0
+#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB 0
+#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK 0x00000001
+#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK) >> PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB)
+#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB) & PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK)
+#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_RESET 0x0 // 0
+#define PCIE_PHY_REG_4_ADDRESS 0x18116ccc
+#define PCIE_PHY_REG_4_OFFSET 0x000c
+// SW modifiable bits
+#define PCIE_PHY_REG_4_SW_MASK 0xffffffff
+// bits defined at reset
+#define PCIE_PHY_REG_4_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define PCIE_PHY_REG_4_RESET 0x05000000
+
+#define XTAL_TCXODET_MSB 31
+#define XTAL_TCXODET_LSB 31
+#define XTAL_TCXODET_MASK 0x80000000
+#define XTAL_TCXODET_GET(x) (((x) & XTAL_TCXODET_MASK) >> XTAL_TCXODET_LSB)
+#define XTAL_TCXODET_SET(x) (((x) << XTAL_TCXODET_LSB) & XTAL_TCXODET_MASK)
+#define XTAL_TCXODET_RESET 0x0 // 0
+#define XTAL_XTAL_CAPINDAC_MSB 30
+#define XTAL_XTAL_CAPINDAC_LSB 24
+#define XTAL_XTAL_CAPINDAC_MASK 0x7f000000
+#define XTAL_XTAL_CAPINDAC_GET(x) (((x) & XTAL_XTAL_CAPINDAC_MASK) >> XTAL_XTAL_CAPINDAC_LSB)
+#define XTAL_XTAL_CAPINDAC_SET(x) (((x) << XTAL_XTAL_CAPINDAC_LSB) & XTAL_XTAL_CAPINDAC_MASK)
+#define XTAL_XTAL_CAPINDAC_RESET 0x4b // 75
+#define XTAL_XTAL_CAPOUTDAC_MSB 23
+#define XTAL_XTAL_CAPOUTDAC_LSB 17
+#define XTAL_XTAL_CAPOUTDAC_MASK 0x00fe0000
+#define XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & XTAL_XTAL_CAPOUTDAC_MASK) >> XTAL_XTAL_CAPOUTDAC_LSB)
+#define XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << XTAL_XTAL_CAPOUTDAC_LSB) & XTAL_XTAL_CAPOUTDAC_MASK)
+#define XTAL_XTAL_CAPOUTDAC_RESET 0x4b // 75
+#define XTAL_XTAL_DRVSTR_MSB 16
+#define XTAL_XTAL_DRVSTR_LSB 15
+#define XTAL_XTAL_DRVSTR_MASK 0x00018000
+#define XTAL_XTAL_DRVSTR_GET(x) (((x) & XTAL_XTAL_DRVSTR_MASK) >> XTAL_XTAL_DRVSTR_LSB)
+#define XTAL_XTAL_DRVSTR_SET(x) (((x) << XTAL_XTAL_DRVSTR_LSB) & XTAL_XTAL_DRVSTR_MASK)
+#define XTAL_XTAL_DRVSTR_RESET 0x0 // 0
+#define XTAL_XTAL_SHORTXIN_MSB 14
+#define XTAL_XTAL_SHORTXIN_LSB 14
+#define XTAL_XTAL_SHORTXIN_MASK 0x00004000
+#define XTAL_XTAL_SHORTXIN_GET(x) (((x) & XTAL_XTAL_SHORTXIN_MASK) >> XTAL_XTAL_SHORTXIN_LSB)
+#define XTAL_XTAL_SHORTXIN_SET(x) (((x) << XTAL_XTAL_SHORTXIN_LSB) & XTAL_XTAL_SHORTXIN_MASK)
+#define XTAL_XTAL_SHORTXIN_RESET 0x0 // 0
+#define XTAL_XTAL_LOCALBIAS_MSB 13
+#define XTAL_XTAL_LOCALBIAS_LSB 13
+#define XTAL_XTAL_LOCALBIAS_MASK 0x00002000
+#define XTAL_XTAL_LOCALBIAS_GET(x) (((x) & XTAL_XTAL_LOCALBIAS_MASK) >> XTAL_XTAL_LOCALBIAS_LSB)
+#define XTAL_XTAL_LOCALBIAS_SET(x) (((x) << XTAL_XTAL_LOCALBIAS_LSB) & XTAL_XTAL_LOCALBIAS_MASK)
+#define XTAL_XTAL_LOCALBIAS_RESET 0x1 // 1
+#define XTAL_XTAL_PWDCLKD_MSB 12
+#define XTAL_XTAL_PWDCLKD_LSB 12
+#define XTAL_XTAL_PWDCLKD_MASK 0x00001000
+#define XTAL_XTAL_PWDCLKD_GET(x) (((x) & XTAL_XTAL_PWDCLKD_MASK) >> XTAL_XTAL_PWDCLKD_LSB)
+#define XTAL_XTAL_PWDCLKD_SET(x) (((x) << XTAL_XTAL_PWDCLKD_LSB) & XTAL_XTAL_PWDCLKD_MASK)
+#define XTAL_XTAL_PWDCLKD_RESET 0x0 // 0
+#define XTAL_XTAL_BIAS2X_MSB 11
+#define XTAL_XTAL_BIAS2X_LSB 11
+#define XTAL_XTAL_BIAS2X_MASK 0x00000800
+#define XTAL_XTAL_BIAS2X_GET(x) (((x) & XTAL_XTAL_BIAS2X_MASK) >> XTAL_XTAL_BIAS2X_LSB)
+#define XTAL_XTAL_BIAS2X_SET(x) (((x) << XTAL_XTAL_BIAS2X_LSB) & XTAL_XTAL_BIAS2X_MASK)
+#define XTAL_XTAL_BIAS2X_RESET 0x0 // 0
+#define XTAL_XTAL_LBIAS2X_MSB 10
+#define XTAL_XTAL_LBIAS2X_LSB 10
+#define XTAL_XTAL_LBIAS2X_MASK 0x00000400
+#define XTAL_XTAL_LBIAS2X_GET(x) (((x) & XTAL_XTAL_LBIAS2X_MASK) >> XTAL_XTAL_LBIAS2X_LSB)
+#define XTAL_XTAL_LBIAS2X_SET(x) (((x) << XTAL_XTAL_LBIAS2X_LSB) & XTAL_XTAL_LBIAS2X_MASK)
+#define XTAL_XTAL_LBIAS2X_RESET 0x0 // 0
+#define XTAL_XTAL_SELVREG_MSB 9
+#define XTAL_XTAL_SELVREG_LSB 9
+#define XTAL_XTAL_SELVREG_MASK 0x00000200
+#define XTAL_XTAL_SELVREG_GET(x) (((x) & XTAL_XTAL_SELVREG_MASK) >> XTAL_XTAL_SELVREG_LSB)
+#define XTAL_XTAL_SELVREG_SET(x) (((x) << XTAL_XTAL_SELVREG_LSB) & XTAL_XTAL_SELVREG_MASK)
+#define XTAL_XTAL_SELVREG_RESET 0x0 // 0
+#define XTAL_XTAL_OSCON_MSB 8
+#define XTAL_XTAL_OSCON_LSB 8
+#define XTAL_XTAL_OSCON_MASK 0x00000100
+#define XTAL_XTAL_OSCON_GET(x) (((x) & XTAL_XTAL_OSCON_MASK) >> XTAL_XTAL_OSCON_LSB)
+#define XTAL_XTAL_OSCON_SET(x) (((x) << XTAL_XTAL_OSCON_LSB) & XTAL_XTAL_OSCON_MASK)
+#define XTAL_XTAL_OSCON_RESET 0x1 // 1
+#define XTAL_XTAL_PWDCLKIN_MSB 7
+#define XTAL_XTAL_PWDCLKIN_LSB 7
+#define XTAL_XTAL_PWDCLKIN_MASK 0x00000080
+#define XTAL_XTAL_PWDCLKIN_GET(x) (((x) & XTAL_XTAL_PWDCLKIN_MASK) >> XTAL_XTAL_PWDCLKIN_LSB)
+#define XTAL_XTAL_PWDCLKIN_SET(x) (((x) << XTAL_XTAL_PWDCLKIN_LSB) & XTAL_XTAL_PWDCLKIN_MASK)
+#define XTAL_XTAL_PWDCLKIN_RESET 0x0 // 0
+#define XTAL_LOCAL_XTAL_MSB 6
+#define XTAL_LOCAL_XTAL_LSB 6
+#define XTAL_LOCAL_XTAL_MASK 0x00000040
+#define XTAL_LOCAL_XTAL_GET(x) (((x) & XTAL_LOCAL_XTAL_MASK) >> XTAL_LOCAL_XTAL_LSB)
+#define XTAL_LOCAL_XTAL_SET(x) (((x) << XTAL_LOCAL_XTAL_LSB) & XTAL_LOCAL_XTAL_MASK)
+#define XTAL_LOCAL_XTAL_RESET 0x0 // 0
+#define XTAL_PWD_SWREGCLK_MSB 5
+#define XTAL_PWD_SWREGCLK_LSB 5
+#define XTAL_PWD_SWREGCLK_MASK 0x00000020
+#define XTAL_PWD_SWREGCLK_GET(x) (((x) & XTAL_PWD_SWREGCLK_MASK) >> XTAL_PWD_SWREGCLK_LSB)
+#define XTAL_PWD_SWREGCLK_SET(x) (((x) << XTAL_PWD_SWREGCLK_LSB) & XTAL_PWD_SWREGCLK_MASK)
+#define XTAL_PWD_SWREGCLK_RESET 0x0 // 0
+#define XTAL_LOCAL_EXT_CLK_OUT_EN_MSB 4
+#define XTAL_LOCAL_EXT_CLK_OUT_EN_LSB 4
+#define XTAL_LOCAL_EXT_CLK_OUT_EN_MASK 0x00000010
+#define XTAL_LOCAL_EXT_CLK_OUT_EN_GET(x) (((x) & XTAL_LOCAL_EXT_CLK_OUT_EN_MASK) >> XTAL_LOCAL_EXT_CLK_OUT_EN_LSB)
+#define XTAL_LOCAL_EXT_CLK_OUT_EN_SET(x) (((x) << XTAL_LOCAL_EXT_CLK_OUT_EN_LSB) & XTAL_LOCAL_EXT_CLK_OUT_EN_MASK)
+#define XTAL_LOCAL_EXT_CLK_OUT_EN_RESET 0x0 // 0
+#define XTAL_EXT_CLK_OUT_EN_MSB 3
+#define XTAL_EXT_CLK_OUT_EN_LSB 3
+#define XTAL_EXT_CLK_OUT_EN_MASK 0x00000008
+#define XTAL_EXT_CLK_OUT_EN_GET(x) (((x) & XTAL_EXT_CLK_OUT_EN_MASK) >> XTAL_EXT_CLK_OUT_EN_LSB)
+#define XTAL_EXT_CLK_OUT_EN_SET(x) (((x) << XTAL_EXT_CLK_OUT_EN_LSB) & XTAL_EXT_CLK_OUT_EN_MASK)
+#define XTAL_EXT_CLK_OUT_EN_RESET 0x0 // 0
+#define XTAL_XTAL_SVREG_MSB 2
+#define XTAL_XTAL_SVREG_LSB 2
+#define XTAL_XTAL_SVREG_MASK 0x00000004
+#define XTAL_XTAL_SVREG_GET(x) (((x) & XTAL_XTAL_SVREG_MASK) >> XTAL_XTAL_SVREG_LSB)
+#define XTAL_XTAL_SVREG_SET(x) (((x) << XTAL_XTAL_SVREG_LSB) & XTAL_XTAL_SVREG_MASK)
+#define XTAL_XTAL_SVREG_RESET 0x0 // 0
+#define XTAL_RBK_UDSEL_MSB 1
+#define XTAL_RBK_UDSEL_LSB 1
+#define XTAL_RBK_UDSEL_MASK 0x00000002
+#define XTAL_RBK_UDSEL_GET(x) (((x) & XTAL_RBK_UDSEL_MASK) >> XTAL_RBK_UDSEL_LSB)
+#define XTAL_RBK_UDSEL_SET(x) (((x) << XTAL_RBK_UDSEL_LSB) & XTAL_RBK_UDSEL_MASK)
+#define XTAL_RBK_UDSEL_RESET 0x0 // 0
+#define XTAL_SPARE_MSB 0
+#define XTAL_SPARE_LSB 0
+#define XTAL_SPARE_MASK 0x00000001
+#define XTAL_SPARE_GET(x) (((x) & XTAL_SPARE_MASK) >> XTAL_SPARE_LSB)
+#define XTAL_SPARE_SET(x) (((x) << XTAL_SPARE_LSB) & XTAL_SPARE_MASK)
+#define XTAL_SPARE_RESET 0x0 // 0
+#define XTAL_ADDRESS 0x181162c0
+
+#define XTAL2_TDC_COUNT_MSB 31
+#define XTAL2_TDC_COUNT_LSB 26
+#define XTAL2_TDC_COUNT_MASK 0xfc000000
+#define XTAL2_TDC_COUNT_GET(x) (((x) & XTAL2_TDC_COUNT_MASK) >> XTAL2_TDC_COUNT_LSB)
+#define XTAL2_TDC_COUNT_SET(x) (((x) << XTAL2_TDC_COUNT_LSB) & XTAL2_TDC_COUNT_MASK)
+#define XTAL2_TDC_COUNT_RESET 0x0 // 0
+#define XTAL2_TDC_PH_COUNT_MSB 25
+#define XTAL2_TDC_PH_COUNT_LSB 21
+#define XTAL2_TDC_PH_COUNT_MASK 0x03e00000
+#define XTAL2_TDC_PH_COUNT_GET(x) (((x) & XTAL2_TDC_PH_COUNT_MASK) >> XTAL2_TDC_PH_COUNT_LSB)
+#define XTAL2_TDC_PH_COUNT_SET(x) (((x) << XTAL2_TDC_PH_COUNT_LSB) & XTAL2_TDC_PH_COUNT_MASK)
+#define XTAL2_TDC_PH_COUNT_RESET 0x0 // 0
+#define XTAL2_DUTY_UP_MSB 20
+#define XTAL2_DUTY_UP_LSB 16
+#define XTAL2_DUTY_UP_MASK 0x001f0000
+#define XTAL2_DUTY_UP_GET(x) (((x) & XTAL2_DUTY_UP_MASK) >> XTAL2_DUTY_UP_LSB)
+#define XTAL2_DUTY_UP_SET(x) (((x) << XTAL2_DUTY_UP_LSB) & XTAL2_DUTY_UP_MASK)
+#define XTAL2_DUTY_UP_RESET 0x0 // 0
+#define XTAL2_DUTY_DN_MSB 15
+#define XTAL2_DUTY_DN_LSB 11
+#define XTAL2_DUTY_DN_MASK 0x0000f800
+#define XTAL2_DUTY_DN_GET(x) (((x) & XTAL2_DUTY_DN_MASK) >> XTAL2_DUTY_DN_LSB)
+#define XTAL2_DUTY_DN_SET(x) (((x) << XTAL2_DUTY_DN_LSB) & XTAL2_DUTY_DN_MASK)
+#define XTAL2_DUTY_DN_RESET 0x0 // 0
+#define XTAL2_DCA_BYPASS_MSB 10
+#define XTAL2_DCA_BYPASS_LSB 10
+#define XTAL2_DCA_BYPASS_MASK 0x00000400
+#define XTAL2_DCA_BYPASS_GET(x) (((x) & XTAL2_DCA_BYPASS_MASK) >> XTAL2_DCA_BYPASS_LSB)
+#define XTAL2_DCA_BYPASS_SET(x) (((x) << XTAL2_DCA_BYPASS_LSB) & XTAL2_DCA_BYPASS_MASK)
+#define XTAL2_DCA_BYPASS_RESET 0x1 // 1
+#define XTAL2_DCA_SWCAL_MSB 9
+#define XTAL2_DCA_SWCAL_LSB 9
+#define XTAL2_DCA_SWCAL_MASK 0x00000200
+#define XTAL2_DCA_SWCAL_GET(x) (((x) & XTAL2_DCA_SWCAL_MASK) >> XTAL2_DCA_SWCAL_LSB)
+#define XTAL2_DCA_SWCAL_SET(x) (((x) << XTAL2_DCA_SWCAL_LSB) & XTAL2_DCA_SWCAL_MASK)
+#define XTAL2_DCA_SWCAL_RESET 0x0 // 0
+#define XTAL2_FSM_UD_HOLD_MSB 8
+#define XTAL2_FSM_UD_HOLD_LSB 8
+#define XTAL2_FSM_UD_HOLD_MASK 0x00000100
+#define XTAL2_FSM_UD_HOLD_GET(x) (((x) & XTAL2_FSM_UD_HOLD_MASK) >> XTAL2_FSM_UD_HOLD_LSB)
+#define XTAL2_FSM_UD_HOLD_SET(x) (((x) << XTAL2_FSM_UD_HOLD_LSB) & XTAL2_FSM_UD_HOLD_MASK)
+#define XTAL2_FSM_UD_HOLD_RESET 0x0 // 0
+#define XTAL2_FSM_START_L_MSB 7
+#define XTAL2_FSM_START_L_LSB 7
+#define XTAL2_FSM_START_L_MASK 0x00000080
+#define XTAL2_FSM_START_L_GET(x) (((x) & XTAL2_FSM_START_L_MASK) >> XTAL2_FSM_START_L_LSB)
+#define XTAL2_FSM_START_L_SET(x) (((x) << XTAL2_FSM_START_L_LSB) & XTAL2_FSM_START_L_MASK)
+#define XTAL2_FSM_START_L_RESET 0x1 // 1
+#define XTAL2_FSM_DN_READBACK_MSB 6
+#define XTAL2_FSM_DN_READBACK_LSB 2
+#define XTAL2_FSM_DN_READBACK_MASK 0x0000007c
+#define XTAL2_FSM_DN_READBACK_GET(x) (((x) & XTAL2_FSM_DN_READBACK_MASK) >> XTAL2_FSM_DN_READBACK_LSB)
+#define XTAL2_FSM_DN_READBACK_SET(x) (((x) << XTAL2_FSM_DN_READBACK_LSB) & XTAL2_FSM_DN_READBACK_MASK)
+#define XTAL2_FSM_DN_READBACK_RESET 0x0 // 0
+#define XTAL2_TDC_SAT_FLAG_MSB 1
+#define XTAL2_TDC_SAT_FLAG_LSB 1
+#define XTAL2_TDC_SAT_FLAG_MASK 0x00000002
+#define XTAL2_TDC_SAT_FLAG_GET(x) (((x) & XTAL2_TDC_SAT_FLAG_MASK) >> XTAL2_TDC_SAT_FLAG_LSB)
+#define XTAL2_TDC_SAT_FLAG_SET(x) (((x) << XTAL2_TDC_SAT_FLAG_LSB) & XTAL2_TDC_SAT_FLAG_MASK)
+#define XTAL2_TDC_SAT_FLAG_RESET 0x0 // 0
+#define XTAL2_FSM_READY_MSB 0
+#define XTAL2_FSM_READY_LSB 0
+#define XTAL2_FSM_READY_MASK 0x00000001
+#define XTAL2_FSM_READY_GET(x) (((x) & XTAL2_FSM_READY_MASK) >> XTAL2_FSM_READY_LSB)
+#define XTAL2_FSM_READY_SET(x) (((x) << XTAL2_FSM_READY_LSB) & XTAL2_FSM_READY_MASK)
+#define XTAL2_FSM_READY_RESET 0x0 // 0
+#define XTAL2_ADDRESS 0x181162c4
+
+#define XTAL3_FSM_UP_READBACK_MSB 31
+#define XTAL3_FSM_UP_READBACK_LSB 27
+#define XTAL3_FSM_UP_READBACK_MASK 0xf8000000
+#define XTAL3_FSM_UP_READBACK_GET(x) (((x) & XTAL3_FSM_UP_READBACK_MASK) >> XTAL3_FSM_UP_READBACK_LSB)
+#define XTAL3_FSM_UP_READBACK_SET(x) (((x) << XTAL3_FSM_UP_READBACK_LSB) & XTAL3_FSM_UP_READBACK_MASK)
+#define XTAL3_FSM_UP_READBACK_RESET 0x0 // 0
+#define XTAL3_EVAL_LENGTH_MSB 26
+#define XTAL3_EVAL_LENGTH_LSB 16
+#define XTAL3_EVAL_LENGTH_MASK 0x07ff0000
+#define XTAL3_EVAL_LENGTH_GET(x) (((x) & XTAL3_EVAL_LENGTH_MASK) >> XTAL3_EVAL_LENGTH_LSB)
+#define XTAL3_EVAL_LENGTH_SET(x) (((x) << XTAL3_EVAL_LENGTH_LSB) & XTAL3_EVAL_LENGTH_MASK)
+#define XTAL3_EVAL_LENGTH_RESET 0x400 // 1024
+#define XTAL3_TDC_ERROR_FLAG_MSB 15
+#define XTAL3_TDC_ERROR_FLAG_LSB 15
+#define XTAL3_TDC_ERROR_FLAG_MASK 0x00008000
+#define XTAL3_TDC_ERROR_FLAG_GET(x) (((x) & XTAL3_TDC_ERROR_FLAG_MASK) >> XTAL3_TDC_ERROR_FLAG_LSB)
+#define XTAL3_TDC_ERROR_FLAG_SET(x) (((x) << XTAL3_TDC_ERROR_FLAG_LSB) & XTAL3_TDC_ERROR_FLAG_MASK)
+#define XTAL3_TDC_ERROR_FLAG_RESET 0x0 // 0
+#define XTAL3_HARMONIC_NUMBER_MSB 14
+#define XTAL3_HARMONIC_NUMBER_LSB 2
+#define XTAL3_HARMONIC_NUMBER_MASK 0x00007ffc
+#define XTAL3_HARMONIC_NUMBER_GET(x) (((x) & XTAL3_HARMONIC_NUMBER_MASK) >> XTAL3_HARMONIC_NUMBER_LSB)
+#define XTAL3_HARMONIC_NUMBER_SET(x) (((x) << XTAL3_HARMONIC_NUMBER_LSB) & XTAL3_HARMONIC_NUMBER_MASK)
+#define XTAL3_HARMONIC_NUMBER_RESET 0x51 // 81
+#define XTAL3_SPARE_MSB 1
+#define XTAL3_SPARE_LSB 0
+#define XTAL3_SPARE_MASK 0x00000003
+#define XTAL3_SPARE_GET(x) (((x) & XTAL3_SPARE_MASK) >> XTAL3_SPARE_LSB)
+#define XTAL3_SPARE_SET(x) (((x) << XTAL3_SPARE_LSB) & XTAL3_SPARE_MASK)
+#define XTAL3_SPARE_RESET 0x0 // 0
+#define XTAL3_ADDRESS 0x181162c8
+
+#define RST_REVISION_ID_ADDRESS 0x18060090
+#define is_drqfn() (!(ath_reg_rd(RST_REVISION_ID_ADDRESS) & 0x1000))
+
+#define RST_BOOTSTRAP_RES4_MSB 15
+#define RST_BOOTSTRAP_RES4_LSB 13
+#define RST_BOOTSTRAP_RES4_MASK 0x0000e000
+#define RST_BOOTSTRAP_RES4_GET(x) (((x) & RST_BOOTSTRAP_RES4_MASK) >> RST_BOOTSTRAP_RES4_LSB)
+#define RST_BOOTSTRAP_RES4_SET(x) (((x) << RST_BOOTSTRAP_RES4_LSB) & RST_BOOTSTRAP_RES4_MASK)
+#define RST_BOOTSTRAP_RES4_RESET 0x0 // 0
+#define RST_BOOTSTRAP_SW_OPTION2_MSB 12
+#define RST_BOOTSTRAP_SW_OPTION2_LSB 12
+#define RST_BOOTSTRAP_SW_OPTION2_MASK 0x00001000
+#define RST_BOOTSTRAP_SW_OPTION2_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION2_MASK) >> RST_BOOTSTRAP_SW_OPTION2_LSB)
+#define RST_BOOTSTRAP_SW_OPTION2_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION2_LSB) & RST_BOOTSTRAP_SW_OPTION2_MASK)
+#define RST_BOOTSTRAP_SW_OPTION2_RESET 0x0 // 0
+#define RST_BOOTSTRAP_SW_OPTION1_MSB 11
+#define RST_BOOTSTRAP_SW_OPTION1_LSB 11
+#define RST_BOOTSTRAP_SW_OPTION1_MASK 0x00000800
+#define RST_BOOTSTRAP_SW_OPTION1_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION1_MASK) >> RST_BOOTSTRAP_SW_OPTION1_LSB)
+#define RST_BOOTSTRAP_SW_OPTION1_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION1_LSB) & RST_BOOTSTRAP_SW_OPTION1_MASK)
+#define RST_BOOTSTRAP_SW_OPTION1_RESET 0x0 // 0
+#define RST_BOOTSTRAP_TESTROM_ENABLE_MSB 10
+#define RST_BOOTSTRAP_TESTROM_ENABLE_LSB 10
+#define RST_BOOTSTRAP_TESTROM_ENABLE_MASK 0x00000400
+#define RST_BOOTSTRAP_TESTROM_ENABLE_GET(x) (((x) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) >> RST_BOOTSTRAP_TESTROM_ENABLE_LSB)
+#define RST_BOOTSTRAP_TESTROM_ENABLE_SET(x) (((x) << RST_BOOTSTRAP_TESTROM_ENABLE_LSB) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK)
+#define RST_BOOTSTRAP_TESTROM_ENABLE_RESET 0x0 // 0
+#define RST_BOOTSTRAP_RES3_MSB 9
+#define RST_BOOTSTRAP_RES3_LSB 9
+#define RST_BOOTSTRAP_RES3_MASK 0x00000200
+#define RST_BOOTSTRAP_RES3_GET(x) (((x) & RST_BOOTSTRAP_RES3_MASK) >> RST_BOOTSTRAP_RES3_LSB)
+#define RST_BOOTSTRAP_RES3_SET(x) (((x) << RST_BOOTSTRAP_RES3_LSB) & RST_BOOTSTRAP_RES3_MASK)
+#define RST_BOOTSTRAP_RES3_RESET 0x0 // 0
+#define RST_BOOTSTRAP_SRIF_ENABLE_MSB 8
+#define RST_BOOTSTRAP_SRIF_ENABLE_LSB 8
+#define RST_BOOTSTRAP_SRIF_ENABLE_MASK 0x00000100
+#define RST_BOOTSTRAP_SRIF_ENABLE_GET(x) (((x) & RST_BOOTSTRAP_SRIF_ENABLE_MASK) >> RST_BOOTSTRAP_SRIF_ENABLE_LSB)
+#define RST_BOOTSTRAP_SRIF_ENABLE_SET(x) (((x) << RST_BOOTSTRAP_SRIF_ENABLE_LSB) & RST_BOOTSTRAP_SRIF_ENABLE_MASK)
+#define RST_BOOTSTRAP_SRIF_ENABLE_RESET 0x0 // 0
+#define RST_BOOTSTRAP_USB_MODE_MSB 7
+#define RST_BOOTSTRAP_USB_MODE_LSB 7
+#define RST_BOOTSTRAP_USB_MODE_MASK 0x00000080
+#define RST_BOOTSTRAP_USB_MODE_GET(x) (((x) & RST_BOOTSTRAP_USB_MODE_MASK) >> RST_BOOTSTRAP_USB_MODE_LSB)
+#define RST_BOOTSTRAP_USB_MODE_SET(x) (((x) << RST_BOOTSTRAP_USB_MODE_LSB) & RST_BOOTSTRAP_USB_MODE_MASK)
+#define RST_BOOTSTRAP_USB_MODE_RESET 0x0 // 0
+#define RST_BOOTSTRAP_RES2_MSB 6
+#define RST_BOOTSTRAP_RES2_LSB 6
+#define RST_BOOTSTRAP_RES2_MASK 0x00000040
+#define RST_BOOTSTRAP_RES2_GET(x) (((x) & RST_BOOTSTRAP_RES2_MASK) >> RST_BOOTSTRAP_RES2_LSB)
+#define RST_BOOTSTRAP_RES2_SET(x) (((x) << RST_BOOTSTRAP_RES2_LSB) & RST_BOOTSTRAP_RES2_MASK)
+#define RST_BOOTSTRAP_RES2_RESET 0x0 // 0
+#define RST_BOOTSTRAP_EJTAG_MODE_MSB 5
+#define RST_BOOTSTRAP_EJTAG_MODE_LSB 5
+#define RST_BOOTSTRAP_EJTAG_MODE_MASK 0x00000020
+#define RST_BOOTSTRAP_EJTAG_MODE_GET(x) (((x) & RST_BOOTSTRAP_EJTAG_MODE_MASK) >> RST_BOOTSTRAP_EJTAG_MODE_LSB)
+#define RST_BOOTSTRAP_EJTAG_MODE_SET(x) (((x) << RST_BOOTSTRAP_EJTAG_MODE_LSB) & RST_BOOTSTRAP_EJTAG_MODE_MASK)
+#define RST_BOOTSTRAP_EJTAG_MODE_RESET 0x0 // 0
+#define RST_BOOTSTRAP_REF_CLK_MSB 4
+#define RST_BOOTSTRAP_REF_CLK_LSB 4
+#define RST_BOOTSTRAP_REF_CLK_MASK 0x00000010
+#define RST_BOOTSTRAP_REF_CLK_GET(x) (((x) & RST_BOOTSTRAP_REF_CLK_MASK) >> RST_BOOTSTRAP_REF_CLK_LSB)
+#define RST_BOOTSTRAP_REF_CLK_SET(x) (((x) << RST_BOOTSTRAP_REF_CLK_LSB) & RST_BOOTSTRAP_REF_CLK_MASK)
+#define RST_BOOTSTRAP_REF_CLK_RESET 0x0 // 0
+#define RST_BOOTSTRAP_RES1_MSB 3
+#define RST_BOOTSTRAP_RES1_LSB 3
+#define RST_BOOTSTRAP_RES1_MASK 0x00000008
+#define RST_BOOTSTRAP_RES1_GET(x) (((x) & RST_BOOTSTRAP_RES1_MASK) >> RST_BOOTSTRAP_RES1_LSB)
+#define RST_BOOTSTRAP_RES1_SET(x) (((x) << RST_BOOTSTRAP_RES1_LSB) & RST_BOOTSTRAP_RES1_MASK)
+#define RST_BOOTSTRAP_RES1_RESET 0x0 // 0
+#define RST_BOOTSTRAP_RES0_MSB 2
+#define RST_BOOTSTRAP_RES0_LSB 2
+#define RST_BOOTSTRAP_RES0_MASK 0x00000004
+#define RST_BOOTSTRAP_RES0_GET(x) (((x) & RST_BOOTSTRAP_RES0_MASK) >> RST_BOOTSTRAP_RES0_LSB)
+#define RST_BOOTSTRAP_RES0_SET(x) (((x) << RST_BOOTSTRAP_RES0_LSB) & RST_BOOTSTRAP_RES0_MASK)
+#define RST_BOOTSTRAP_RES0_RESET 0x0 // 0
+#define RST_BOOTSTRAP_SDRAM_SELECT_MSB 1
+#define RST_BOOTSTRAP_SDRAM_SELECT_LSB 1
+#define RST_BOOTSTRAP_SDRAM_SELECT_MASK 0x00000002
+#define RST_BOOTSTRAP_SDRAM_SELECT_GET(x) (((x) & RST_BOOTSTRAP_SDRAM_SELECT_MASK) >> RST_BOOTSTRAP_SDRAM_SELECT_LSB)
+#define RST_BOOTSTRAP_SDRAM_SELECT_SET(x) (((x) << RST_BOOTSTRAP_SDRAM_SELECT_LSB) & RST_BOOTSTRAP_SDRAM_SELECT_MASK)
+#define RST_BOOTSTRAP_SDRAM_SELECT_RESET 0x0 // 0
+#define RST_BOOTSTRAP_DDR_SELECT_MSB 0
+#define RST_BOOTSTRAP_DDR_SELECT_LSB 0
+#define RST_BOOTSTRAP_DDR_SELECT_MASK 0x00000001
+#define RST_BOOTSTRAP_DDR_SELECT_GET(x) (((x) & RST_BOOTSTRAP_DDR_SELECT_MASK) >> RST_BOOTSTRAP_DDR_SELECT_LSB)
+#define RST_BOOTSTRAP_DDR_SELECT_SET(x) (((x) << RST_BOOTSTRAP_DDR_SELECT_LSB) & RST_BOOTSTRAP_DDR_SELECT_MASK)
+#define RST_BOOTSTRAP_DDR_SELECT_RESET 0x0 // 0
+#define RST_BOOTSTRAP_ADDRESS 0x180600b0
+
+#define RST_CLKGAT_EN_SPARE_MSB 31
+#define RST_CLKGAT_EN_SPARE_LSB 12
+#define RST_CLKGAT_EN_SPARE_MASK 0xfffff000
+#define RST_CLKGAT_EN_SPARE_GET(x) (((x) & RST_CLKGAT_EN_SPARE_MASK) >> RST_CLKGAT_EN_SPARE_LSB)
+#define RST_CLKGAT_EN_SPARE_SET(x) (((x) << RST_CLKGAT_EN_SPARE_LSB) & RST_CLKGAT_EN_SPARE_MASK)
+#define RST_CLKGAT_EN_SPARE_RESET 0x0 // 0
+#define RST_CLKGAT_EN_WMAC_MSB 9
+#define RST_CLKGAT_EN_WMAC_LSB 9
+#define RST_CLKGAT_EN_WMAC_MASK 0x00000200
+#define RST_CLKGAT_EN_WMAC_GET(x) (((x) & RST_CLKGAT_EN_WMAC_MASK) >> RST_CLKGAT_EN_WMAC_LSB)
+#define RST_CLKGAT_EN_WMAC_SET(x) (((x) << RST_CLKGAT_EN_WMAC_LSB) & RST_CLKGAT_EN_WMAC_MASK)
+#define RST_CLKGAT_EN_WMAC_RESET 0x1 // 1
+#define RST_CLKGAT_EN_USB1_MSB 7
+#define RST_CLKGAT_EN_USB1_LSB 7
+#define RST_CLKGAT_EN_USB1_MASK 0x00000080
+#define RST_CLKGAT_EN_USB1_GET(x) (((x) & RST_CLKGAT_EN_USB1_MASK) >> RST_CLKGAT_EN_USB1_LSB)
+#define RST_CLKGAT_EN_USB1_SET(x) (((x) << RST_CLKGAT_EN_USB1_LSB) & RST_CLKGAT_EN_USB1_MASK)
+#define RST_CLKGAT_EN_USB1_RESET 0x1 // 1
+#define RST_CLKGAT_EN_GE1_MSB 6
+#define RST_CLKGAT_EN_GE1_LSB 6
+#define RST_CLKGAT_EN_GE1_MASK 0x00000040
+#define RST_CLKGAT_EN_GE1_GET(x) (((x) & RST_CLKGAT_EN_GE1_MASK) >> RST_CLKGAT_EN_GE1_LSB)
+#define RST_CLKGAT_EN_GE1_SET(x) (((x) << RST_CLKGAT_EN_GE1_LSB) & RST_CLKGAT_EN_GE1_MASK)
+#define RST_CLKGAT_EN_GE1_RESET 0x1 // 1
+#define RST_CLKGAT_EN_GE0_MSB 5
+#define RST_CLKGAT_EN_GE0_LSB 5
+#define RST_CLKGAT_EN_GE0_MASK 0x00000020
+#define RST_CLKGAT_EN_GE0_GET(x) (((x) & RST_CLKGAT_EN_GE0_MASK) >> RST_CLKGAT_EN_GE0_LSB)
+#define RST_CLKGAT_EN_GE0_SET(x) (((x) << RST_CLKGAT_EN_GE0_LSB) & RST_CLKGAT_EN_GE0_MASK)
+#define RST_CLKGAT_EN_GE0_RESET 0x1 // 1
+#define RST_CLKGAT_EN_PCIE_RC_MSB 1
+#define RST_CLKGAT_EN_PCIE_RC_LSB 1
+#define RST_CLKGAT_EN_PCIE_RC_MASK 0x00000002
+#define RST_CLKGAT_EN_PCIE_RC_GET(x) (((x) & RST_CLKGAT_EN_PCIE_RC_MASK) >> RST_CLKGAT_EN_PCIE_RC_LSB)
+#define RST_CLKGAT_EN_PCIE_RC_SET(x) (((x) << RST_CLKGAT_EN_PCIE_RC_LSB) & RST_CLKGAT_EN_PCIE_RC_MASK)
+#define RST_CLKGAT_EN_PCIE_RC_RESET 0x1 // 1
+#define RST_CLKGAT_EN_ADDRESS 0x180600c0
+#define RST_CLKGAT_EN_OFFSET 0x00c0
+// SW modifiable bits
+#define RST_CLKGAT_EN_SW_MASK 0xfffff2e2
+// bits defined at reset
+#define RST_CLKGAT_EN_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define RST_CLKGAT_EN_RESET 0x000002e2
+
+#define GPIO_OE_ADDRESS 0x18040000
+#define GPIO_IN_ADDRESS 0x18040004/* by huangwenzhong, 03Sep13 */
+#define GPIO_OUT_ADDRESS 0x18040008
+#define GPIO_SPARE_ADDRESS 0x18040070
+
+
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MSB 31
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB 24
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK 0xff000000
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB)
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK)
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MSB 23
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB 16
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK 0x00ff0000
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB)
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK)
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MSB 15
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB 8
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK 0x0000ff00
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB)
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK)
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MSB 7
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB 0
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK 0x000000ff
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB)
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK)
+#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION0_ADDRESS 0x1804002c
+
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MSB 31
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB 24
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK 0xff000000
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_RESET 0xc // 12
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MSB 23
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB 16
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK 0x00ff0000
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_RESET 0x8 // 8
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MSB 15
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB 8
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK 0x0000ff00
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_RESET 0x9 // 9
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MSB 7
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB 0
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK 0x000000ff
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x5d // 93
+#define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030
+
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MSB 31
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB 24
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK 0xff000000
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB)
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK)
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MSB 23
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB 16
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK 0x00ff0000
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB)
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK)
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MSB 15
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB 8
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK 0x0000ff00
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB)
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK)
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MSB 7
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB 0
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK 0x000000ff
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB)
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK)
+#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION2_ADDRESS 0x18040034
+
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MSB 31
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB 24
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK 0xff000000
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB)
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK)
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MSB 23
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB 16
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK 0x00ff0000
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB)
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK)
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MSB 15
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB 8
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK 0x0000ff00
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB)
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK)
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MSB 7
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB 0
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK 0x000000ff
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB)
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK)
+#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION3_ADDRESS 0x18040038
+
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MSB 15
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB)
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK)
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_RESET 0x1 // 1
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MSB 7
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB 0
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK 0x000000ff
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB)
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK)
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_RESET 0x0 // 0
+#define GPIO_OUT_FUNCTION4_ADDRESS 0x1804003c
+
+#define GPIO_IN_ENABLE0_UART_SIN_MSB 15
+#define GPIO_IN_ENABLE0_UART_SIN_LSB 8
+#define GPIO_IN_ENABLE0_UART_SIN_MASK 0x0000ff00
+#define GPIO_IN_ENABLE0_UART_SIN_GET(x) (((x) & GPIO_IN_ENABLE0_UART_SIN_MASK) >> GPIO_IN_ENABLE0_UART_SIN_LSB)
+#define GPIO_IN_ENABLE0_UART_SIN_SET(x) (((x) << GPIO_IN_ENABLE0_UART_SIN_LSB) & GPIO_IN_ENABLE0_UART_SIN_MASK)
+#define GPIO_IN_ENABLE0_UART_SIN_RESET 0x80 // 128
+#define GPIO_IN_ENABLE0_SPI_DATA_IN_MSB 7
+#define GPIO_IN_ENABLE0_SPI_DATA_IN_LSB 0
+#define GPIO_IN_ENABLE0_SPI_DATA_IN_MASK 0x000000ff
+#define GPIO_IN_ENABLE0_SPI_DATA_IN_GET(x) (((x) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK) >> GPIO_IN_ENABLE0_SPI_DATA_IN_LSB)
+#define GPIO_IN_ENABLE0_SPI_DATA_IN_SET(x) (((x) << GPIO_IN_ENABLE0_SPI_DATA_IN_LSB) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK)
+#define GPIO_IN_ENABLE0_SPI_DATA_IN_RESET 0x8 // 8
+#define GPIO_IN_ENABLE0_ADDRESS 0x18040044
+
+#define GPIO_IN_ENABLE1_RES_MSB 31
+#define GPIO_IN_ENABLE1_RES_LSB 0
+#define GPIO_IN_ENABLE1_RES_MASK 0xffffffff
+#define GPIO_IN_ENABLE1_RES_GET(x) (((x) & GPIO_IN_ENABLE1_RES_MASK) >> GPIO_IN_ENABLE1_RES_LSB)
+#define GPIO_IN_ENABLE1_RES_SET(x) (((x) << GPIO_IN_ENABLE1_RES_LSB) & GPIO_IN_ENABLE1_RES_MASK)
+#define GPIO_IN_ENABLE1_RES_RESET 0x0 // 0
+#define GPIO_IN_ENABLE1_ADDRESS 0x18040048
+
+#define GPIO_IN_ENABLE2_RES_MSB 31
+#define GPIO_IN_ENABLE2_RES_LSB 0
+#define GPIO_IN_ENABLE2_RES_MASK 0xffffffff
+#define GPIO_IN_ENABLE2_RES_GET(x) (((x) & GPIO_IN_ENABLE2_RES_MASK) >> GPIO_IN_ENABLE2_RES_LSB)
+#define GPIO_IN_ENABLE2_RES_SET(x) (((x) << GPIO_IN_ENABLE2_RES_LSB) & GPIO_IN_ENABLE2_RES_MASK)
+#define GPIO_IN_ENABLE2_RES_RESET 0x0 // 0
+#define GPIO_IN_ENABLE2_ADDRESS 0x1804004c
+
+#define GPIO_IN_ENABLE3_RES_MSB 31
+#define GPIO_IN_ENABLE3_RES_LSB 0
+#define GPIO_IN_ENABLE3_RES_MASK 0xffffffff
+#define GPIO_IN_ENABLE3_RES_GET(x) (((x) & GPIO_IN_ENABLE3_RES_MASK) >> GPIO_IN_ENABLE3_RES_LSB)
+#define GPIO_IN_ENABLE3_RES_SET(x) (((x) << GPIO_IN_ENABLE3_RES_LSB) & GPIO_IN_ENABLE3_RES_MASK)
+#define GPIO_IN_ENABLE3_RES_RESET 0x0 // 0
+#define GPIO_IN_ENABLE3_ADDRESS 0x18040050
+
+#define GPIO_IN_ENABLE4_RES_MSB 31
+#define GPIO_IN_ENABLE4_RES_LSB 0
+#define GPIO_IN_ENABLE4_RES_MASK 0xffffffff
+#define GPIO_IN_ENABLE4_RES_GET(x) (((x) & GPIO_IN_ENABLE4_RES_MASK) >> GPIO_IN_ENABLE4_RES_LSB)
+#define GPIO_IN_ENABLE4_RES_SET(x) (((x) << GPIO_IN_ENABLE4_RES_LSB) & GPIO_IN_ENABLE4_RES_MASK)
+#define GPIO_IN_ENABLE4_RES_RESET 0x0 // 0
+#define GPIO_IN_ENABLE4_ADDRESS 0x18040054
+
+#define GPIO_IN_ENABLE5_WMAC_IN3_MSB 31
+#define GPIO_IN_ENABLE5_WMAC_IN3_LSB 24
+#define GPIO_IN_ENABLE5_WMAC_IN3_MASK 0xff000000
+#define GPIO_IN_ENABLE5_WMAC_IN3_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN3_MASK) >> GPIO_IN_ENABLE5_WMAC_IN3_LSB)
+#define GPIO_IN_ENABLE5_WMAC_IN3_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN3_LSB) & GPIO_IN_ENABLE5_WMAC_IN3_MASK)
+#define GPIO_IN_ENABLE5_WMAC_IN3_RESET 0x80 // 128
+#define GPIO_IN_ENABLE5_WMAC_IN2_MSB 23
+#define GPIO_IN_ENABLE5_WMAC_IN2_LSB 16
+#define GPIO_IN_ENABLE5_WMAC_IN2_MASK 0x00ff0000
+#define GPIO_IN_ENABLE5_WMAC_IN2_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN2_MASK) >> GPIO_IN_ENABLE5_WMAC_IN2_LSB)
+#define GPIO_IN_ENABLE5_WMAC_IN2_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN2_LSB) & GPIO_IN_ENABLE5_WMAC_IN2_MASK)
+#define GPIO_IN_ENABLE5_WMAC_IN2_RESET 0x80 // 128
+#define GPIO_IN_ENABLE5_WMAC_IN1_MSB 15
+#define GPIO_IN_ENABLE5_WMAC_IN1_LSB 8
+#define GPIO_IN_ENABLE5_WMAC_IN1_MASK 0x0000ff00
+#define GPIO_IN_ENABLE5_WMAC_IN1_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN1_MASK) >> GPIO_IN_ENABLE5_WMAC_IN1_LSB)
+#define GPIO_IN_ENABLE5_WMAC_IN1_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN1_LSB) & GPIO_IN_ENABLE5_WMAC_IN1_MASK)
+#define GPIO_IN_ENABLE5_WMAC_IN1_RESET 0x80 // 128
+#define GPIO_IN_ENABLE5_WMAC_IN0_MSB 7
+#define GPIO_IN_ENABLE5_WMAC_IN0_LSB 0
+#define GPIO_IN_ENABLE5_WMAC_IN0_MASK 0x000000ff
+#define GPIO_IN_ENABLE5_WMAC_IN0_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN0_MASK) >> GPIO_IN_ENABLE5_WMAC_IN0_LSB)
+#define GPIO_IN_ENABLE5_WMAC_IN0_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN0_LSB) & GPIO_IN_ENABLE5_WMAC_IN0_MASK)
+#define GPIO_IN_ENABLE5_WMAC_IN0_RESET 0x80 // 128
+#define GPIO_IN_ENABLE5_ADDRESS 0x18040058
+
+#define GPIO_IN_ENABLE6_WMAC_IN7_MSB 31
+#define GPIO_IN_ENABLE6_WMAC_IN7_LSB 24
+#define GPIO_IN_ENABLE6_WMAC_IN7_MASK 0xff000000
+#define GPIO_IN_ENABLE6_WMAC_IN7_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN7_MASK) >> GPIO_IN_ENABLE6_WMAC_IN7_LSB)
+#define GPIO_IN_ENABLE6_WMAC_IN7_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN7_LSB) & GPIO_IN_ENABLE6_WMAC_IN7_MASK)
+#define GPIO_IN_ENABLE6_WMAC_IN7_RESET 0x80 // 128
+#define GPIO_IN_ENABLE6_WMAC_IN6_MSB 23
+#define GPIO_IN_ENABLE6_WMAC_IN6_LSB 16
+#define GPIO_IN_ENABLE6_WMAC_IN6_MASK 0x00ff0000
+#define GPIO_IN_ENABLE6_WMAC_IN6_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN6_MASK) >> GPIO_IN_ENABLE6_WMAC_IN6_LSB)
+#define GPIO_IN_ENABLE6_WMAC_IN6_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN6_LSB) & GPIO_IN_ENABLE6_WMAC_IN6_MASK)
+#define GPIO_IN_ENABLE6_WMAC_IN6_RESET 0x80 // 128
+#define GPIO_IN_ENABLE6_WMAC_IN5_MSB 15
+#define GPIO_IN_ENABLE6_WMAC_IN5_LSB 8
+#define GPIO_IN_ENABLE6_WMAC_IN5_MASK 0x0000ff00
+#define GPIO_IN_ENABLE6_WMAC_IN5_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN5_MASK) >> GPIO_IN_ENABLE6_WMAC_IN5_LSB)
+#define GPIO_IN_ENABLE6_WMAC_IN5_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN5_LSB) & GPIO_IN_ENABLE6_WMAC_IN5_MASK)
+#define GPIO_IN_ENABLE6_WMAC_IN5_RESET 0x80 // 128
+#define GPIO_IN_ENABLE6_WMAC_IN4_MSB 7
+#define GPIO_IN_ENABLE6_WMAC_IN4_LSB 0
+#define GPIO_IN_ENABLE6_WMAC_IN4_MASK 0x000000ff
+#define GPIO_IN_ENABLE6_WMAC_IN4_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN4_MASK) >> GPIO_IN_ENABLE6_WMAC_IN4_LSB)
+#define GPIO_IN_ENABLE6_WMAC_IN4_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN4_LSB) & GPIO_IN_ENABLE6_WMAC_IN4_MASK)
+#define GPIO_IN_ENABLE6_WMAC_IN4_RESET 0x80 // 128
+#define GPIO_IN_ENABLE6_ADDRESS 0x1804005c
+
+#define GPIO_IN_ENABLE7_WMAC_IN11_MSB 31
+#define GPIO_IN_ENABLE7_WMAC_IN11_LSB 24
+#define GPIO_IN_ENABLE7_WMAC_IN11_MASK 0xff000000
+#define GPIO_IN_ENABLE7_WMAC_IN11_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN11_MASK) >> GPIO_IN_ENABLE7_WMAC_IN11_LSB)
+#define GPIO_IN_ENABLE7_WMAC_IN11_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN11_LSB) & GPIO_IN_ENABLE7_WMAC_IN11_MASK)
+#define GPIO_IN_ENABLE7_WMAC_IN11_RESET 0x80 // 128
+#define GPIO_IN_ENABLE7_WMAC_IN10_MSB 23
+#define GPIO_IN_ENABLE7_WMAC_IN10_LSB 16
+#define GPIO_IN_ENABLE7_WMAC_IN10_MASK 0x00ff0000
+#define GPIO_IN_ENABLE7_WMAC_IN10_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN10_MASK) >> GPIO_IN_ENABLE7_WMAC_IN10_LSB)
+#define GPIO_IN_ENABLE7_WMAC_IN10_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN10_LSB) & GPIO_IN_ENABLE7_WMAC_IN10_MASK)
+#define GPIO_IN_ENABLE7_WMAC_IN10_RESET 0x80 // 128
+#define GPIO_IN_ENABLE7_WMAC_IN9_MSB 15
+#define GPIO_IN_ENABLE7_WMAC_IN9_LSB 8
+#define GPIO_IN_ENABLE7_WMAC_IN9_MASK 0x0000ff00
+#define GPIO_IN_ENABLE7_WMAC_IN9_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN9_MASK) >> GPIO_IN_ENABLE7_WMAC_IN9_LSB)
+#define GPIO_IN_ENABLE7_WMAC_IN9_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN9_LSB) & GPIO_IN_ENABLE7_WMAC_IN9_MASK)
+#define GPIO_IN_ENABLE7_WMAC_IN9_RESET 0x80 // 128
+#define GPIO_IN_ENABLE7_WMAC_IN8_MSB 7
+#define GPIO_IN_ENABLE7_WMAC_IN8_LSB 0
+#define GPIO_IN_ENABLE7_WMAC_IN8_MASK 0x000000ff
+#define GPIO_IN_ENABLE7_WMAC_IN8_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN8_MASK) >> GPIO_IN_ENABLE7_WMAC_IN8_LSB)
+#define GPIO_IN_ENABLE7_WMAC_IN8_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN8_LSB) & GPIO_IN_ENABLE7_WMAC_IN8_MASK)
+#define GPIO_IN_ENABLE7_WMAC_IN8_RESET 0x80 // 128
+#define GPIO_IN_ENABLE7_ADDRESS 0x18040060
+
+#define GPIO_IN_ENABLE8_SRIF_SRESET_MSB 31
+#define GPIO_IN_ENABLE8_SRIF_SRESET_LSB 24
+#define GPIO_IN_ENABLE8_SRIF_SRESET_MASK 0xff000000
+#define GPIO_IN_ENABLE8_SRIF_SRESET_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SRESET_MASK) >> GPIO_IN_ENABLE8_SRIF_SRESET_LSB)
+#define GPIO_IN_ENABLE8_SRIF_SRESET_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SRESET_LSB) & GPIO_IN_ENABLE8_SRIF_SRESET_MASK)
+#define GPIO_IN_ENABLE8_SRIF_SRESET_RESET 0x80 // 128
+#define GPIO_IN_ENABLE8_SRIF_SIN_MSB 23
+#define GPIO_IN_ENABLE8_SRIF_SIN_LSB 16
+#define GPIO_IN_ENABLE8_SRIF_SIN_MASK 0x00ff0000
+#define GPIO_IN_ENABLE8_SRIF_SIN_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SIN_MASK) >> GPIO_IN_ENABLE8_SRIF_SIN_LSB)
+#define GPIO_IN_ENABLE8_SRIF_SIN_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SIN_LSB) & GPIO_IN_ENABLE8_SRIF_SIN_MASK)
+#define GPIO_IN_ENABLE8_SRIF_SIN_RESET 0x80 // 128
+#define GPIO_IN_ENABLE8_SRIF_SOT_MSB 15
+#define GPIO_IN_ENABLE8_SRIF_SOT_LSB 8
+#define GPIO_IN_ENABLE8_SRIF_SOT_MASK 0x0000ff00
+#define GPIO_IN_ENABLE8_SRIF_SOT_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SOT_MASK) >> GPIO_IN_ENABLE8_SRIF_SOT_LSB)
+#define GPIO_IN_ENABLE8_SRIF_SOT_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SOT_LSB) & GPIO_IN_ENABLE8_SRIF_SOT_MASK)
+#define GPIO_IN_ENABLE8_SRIF_SOT_RESET 0x80 // 128
+#define GPIO_IN_ENABLE8_SRIF_SCLK_MSB 7
+#define GPIO_IN_ENABLE8_SRIF_SCLK_LSB 0
+#define GPIO_IN_ENABLE8_SRIF_SCLK_MASK 0x000000ff
+#define GPIO_IN_ENABLE8_SRIF_SCLK_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SCLK_MASK) >> GPIO_IN_ENABLE8_SRIF_SCLK_LSB)
+#define GPIO_IN_ENABLE8_SRIF_SCLK_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SCLK_LSB) & GPIO_IN_ENABLE8_SRIF_SCLK_MASK)
+#define GPIO_IN_ENABLE8_SRIF_SCLK_RESET 0x80 // 128
+#define GPIO_IN_ENABLE8_ADDRESS 0x18040064
+
+#define GPIO_IN_ENABLE9_RES_MSB 31
+#define GPIO_IN_ENABLE9_RES_LSB 0
+#define GPIO_IN_ENABLE9_RES_MASK 0xffffffff
+#define GPIO_IN_ENABLE9_RES_GET(x) (((x) & GPIO_IN_ENABLE9_RES_MASK) >> GPIO_IN_ENABLE9_RES_LSB)
+#define GPIO_IN_ENABLE9_RES_SET(x) (((x) << GPIO_IN_ENABLE9_RES_LSB) & GPIO_IN_ENABLE9_RES_MASK)
+#define GPIO_IN_ENABLE9_RES_RESET 0x0 // 0
+#define GPIO_IN_ENABLE9_ADDRESS 0x18040068
+
+#define GPIO_FUNCTION_EXT_MDIO_SEL_MSB 11
+#define GPIO_FUNCTION_EXT_MDIO_SEL_LSB 11
+#define GPIO_FUNCTION_EXT_MDIO_SEL_MASK 0x00000800
+#define GPIO_FUNCTION_EXT_MDIO_SEL_GET(x) (((x) & GPIO_FUNCTION_EXT_MDIO_SEL_MASK) >> GPIO_FUNCTION_EXT_MDIO_SEL_LSB)
+#define GPIO_FUNCTION_EXT_MDIO_SEL_SET(x) (((x) << GPIO_FUNCTION_EXT_MDIO_SEL_LSB) & GPIO_FUNCTION_EXT_MDIO_SEL_MASK)
+#define GPIO_FUNCTION_EXT_MDIO_SEL_RESET 0x0 // 0
+#define GPIO_FUNCTION_CLK_OBS6_ENABLE_MSB 8
+#define GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB 8
+#define GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK 0x00000100
+#define GPIO_FUNCTION_CLK_OBS6_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB)
+#define GPIO_FUNCTION_CLK_OBS6_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK)
+#define GPIO_FUNCTION_CLK_OBS6_ENABLE_RESET 0x0 // 0
+#define GPIO_FUNCTION_CLK_OBS5_ENABLE_MSB 7
+#define GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB 7
+#define GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK 0x00000080
+#define GPIO_FUNCTION_CLK_OBS5_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB)
+#define GPIO_FUNCTION_CLK_OBS5_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK)
+#define GPIO_FUNCTION_CLK_OBS5_ENABLE_RESET 0x0 // 0
+#define GPIO_FUNCTION_CLK_OBS4_ENABLE_MSB 6
+#define GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB 6
+#define GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK 0x00000040
+#define GPIO_FUNCTION_CLK_OBS4_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB)
+#define GPIO_FUNCTION_CLK_OBS4_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK)
+#define GPIO_FUNCTION_CLK_OBS4_ENABLE_RESET 0x0 // 0
+#define GPIO_FUNCTION_CLK_OBS3_ENABLE_MSB 5
+#define GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB 5
+#define GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK 0x00000020
+#define GPIO_FUNCTION_CLK_OBS3_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB)
+#define GPIO_FUNCTION_CLK_OBS3_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK)
+#define GPIO_FUNCTION_CLK_OBS3_ENABLE_RESET 0x1 // 1
+#define GPIO_FUNCTION_CLK_OBS2_ENABLE_MSB 4
+#define GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB 4
+#define GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK 0x00000010
+#define GPIO_FUNCTION_CLK_OBS2_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB)
+#define GPIO_FUNCTION_CLK_OBS2_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK)
+#define GPIO_FUNCTION_CLK_OBS2_ENABLE_RESET 0x0 // 0
+#define GPIO_FUNCTION_CLK_OBS1_ENABLE_MSB 3
+#define GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB 3
+#define GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK 0x00000008
+#define GPIO_FUNCTION_CLK_OBS1_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB)
+#define GPIO_FUNCTION_CLK_OBS1_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK)
+#define GPIO_FUNCTION_CLK_OBS1_ENABLE_RESET 0x0 // 0
+#define GPIO_FUNCTION_CLK_OBS0_ENABLE_MSB 2
+#define GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB 2
+#define GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK 0x00000004
+#define GPIO_FUNCTION_CLK_OBS0_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB)
+#define GPIO_FUNCTION_CLK_OBS0_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK)
+#define GPIO_FUNCTION_CLK_OBS0_ENABLE_RESET 0x0 // 0
+#define GPIO_FUNCTION_DISABLE_JTAG_MSB 1
+#define GPIO_FUNCTION_DISABLE_JTAG_LSB 1
+#define GPIO_FUNCTION_DISABLE_JTAG_MASK 0x00000002
+#define GPIO_FUNCTION_DISABLE_JTAG_GET(x) (((x) & GPIO_FUNCTION_DISABLE_JTAG_MASK) >> GPIO_FUNCTION_DISABLE_JTAG_LSB)
+#define GPIO_FUNCTION_DISABLE_JTAG_SET(x) (((x) << GPIO_FUNCTION_DISABLE_JTAG_LSB) & GPIO_FUNCTION_DISABLE_JTAG_MASK)
+#define GPIO_FUNCTION_DISABLE_JTAG_RESET 0x0 // 0
+#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MSB 0
+#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB 0
+#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK 0x00000001
+#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_GET(x) (((x) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK) >> GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB)
+#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_SET(x) (((x) << GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK)
+#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_RESET 0x0 // 0
+#define GPIO_FUNCTION_ADDRESS 0x1804006c
+
+#define PCIE_RESET_EP_RESET_L_MSB 2
+#define PCIE_RESET_EP_RESET_L_LSB 2
+#define PCIE_RESET_EP_RESET_L_MASK 0x00000004
+#define PCIE_RESET_EP_RESET_L_GET(x) (((x) & PCIE_RESET_EP_RESET_L_MASK) >> PCIE_RESET_EP_RESET_L_LSB)
+#define PCIE_RESET_EP_RESET_L_SET(x) (((x) << PCIE_RESET_EP_RESET_L_LSB) & PCIE_RESET_EP_RESET_L_MASK)
+#define PCIE_RESET_EP_RESET_L_RESET 0x0 // 0
+#define PCIE_RESET_LINK_REQ_RESET_MSB 1
+#define PCIE_RESET_LINK_REQ_RESET_LSB 1
+#define PCIE_RESET_LINK_REQ_RESET_MASK 0x00000002
+#define PCIE_RESET_LINK_REQ_RESET_GET(x) (((x) & PCIE_RESET_LINK_REQ_RESET_MASK) >> PCIE_RESET_LINK_REQ_RESET_LSB)
+#define PCIE_RESET_LINK_REQ_RESET_SET(x) (((x) << PCIE_RESET_LINK_REQ_RESET_LSB) & PCIE_RESET_LINK_REQ_RESET_MASK)
+#define PCIE_RESET_LINK_REQ_RESET_RESET 0x0 // 0
+#define PCIE_RESET_LINK_UP_MSB 0
+#define PCIE_RESET_LINK_UP_LSB 0
+#define PCIE_RESET_LINK_UP_MASK 0x00000001
+#define PCIE_RESET_LINK_UP_GET(x) (((x) & PCIE_RESET_LINK_UP_MASK) >> PCIE_RESET_LINK_UP_LSB)
+#define PCIE_RESET_LINK_UP_SET(x) (((x) << PCIE_RESET_LINK_UP_LSB) & PCIE_RESET_LINK_UP_MASK)
+#define PCIE_RESET_LINK_UP_RESET 0x0 // 0
+#define PCIE_RESET_ADDRESS 0x180f0018
+
+#define ETH_CFG_ETH_SPARE_MSB 31
+#define ETH_CFG_ETH_SPARE_LSB 22
+#define ETH_CFG_ETH_SPARE_MASK 0xffc00000
+#define ETH_CFG_ETH_SPARE_GET(x) (((x) & ETH_CFG_ETH_SPARE_MASK) >> ETH_CFG_ETH_SPARE_LSB)
+#define ETH_CFG_ETH_SPARE_SET(x) (((x) << ETH_CFG_ETH_SPARE_LSB) & ETH_CFG_ETH_SPARE_MASK)
+#define ETH_CFG_ETH_SPARE_RESET 0x0 // 0
+#define ETH_CFG_SW_ACC_MSB_FIRST_MSB 13
+#define ETH_CFG_SW_ACC_MSB_FIRST_LSB 13
+#define ETH_CFG_SW_ACC_MSB_FIRST_MASK 0x00002000
+#define ETH_CFG_SW_ACC_MSB_FIRST_GET(x) (((x) & ETH_CFG_SW_ACC_MSB_FIRST_MASK) >> ETH_CFG_SW_ACC_MSB_FIRST_LSB)
+#define ETH_CFG_SW_ACC_MSB_FIRST_SET(x) (((x) << ETH_CFG_SW_ACC_MSB_FIRST_LSB) & ETH_CFG_SW_ACC_MSB_FIRST_MASK)
+#define ETH_CFG_SW_ACC_MSB_FIRST_RESET 0x1 // 1
+#define ETH_CFG_SW_APB_ACCESS_MSB 9
+#define ETH_CFG_SW_APB_ACCESS_LSB 9
+#define ETH_CFG_SW_APB_ACCESS_MASK 0x00000200
+#define ETH_CFG_SW_APB_ACCESS_GET(x) (((x) & ETH_CFG_SW_APB_ACCESS_MASK) >> ETH_CFG_SW_APB_ACCESS_LSB)
+#define ETH_CFG_SW_APB_ACCESS_SET(x) (((x) << ETH_CFG_SW_APB_ACCESS_LSB) & ETH_CFG_SW_APB_ACCESS_MASK)
+#define ETH_CFG_SW_APB_ACCESS_RESET 0x0 // 0
+#define ETH_CFG_SW_PHY_ADDR_SWAP_MSB 8
+#define ETH_CFG_SW_PHY_ADDR_SWAP_LSB 8
+#define ETH_CFG_SW_PHY_ADDR_SWAP_MASK 0x00000100
+#define ETH_CFG_SW_PHY_ADDR_SWAP_GET(x) (((x) & ETH_CFG_SW_PHY_ADDR_SWAP_MASK) >> ETH_CFG_SW_PHY_ADDR_SWAP_LSB)
+#define ETH_CFG_SW_PHY_ADDR_SWAP_SET(x) (((x) << ETH_CFG_SW_PHY_ADDR_SWAP_LSB) & ETH_CFG_SW_PHY_ADDR_SWAP_MASK)
+#define ETH_CFG_SW_PHY_ADDR_SWAP_RESET 0x0 // 0
+#define ETH_CFG_SW_PHY_SWAP_MSB 7
+#define ETH_CFG_SW_PHY_SWAP_LSB 7
+#define ETH_CFG_SW_PHY_SWAP_MASK 0x00000080
+#define ETH_CFG_SW_PHY_SWAP_GET(x) (((x) & ETH_CFG_SW_PHY_SWAP_MASK) >> ETH_CFG_SW_PHY_SWAP_LSB)
+#define ETH_CFG_SW_PHY_SWAP_SET(x) (((x) << ETH_CFG_SW_PHY_SWAP_LSB) & ETH_CFG_SW_PHY_SWAP_MASK)
+#define ETH_CFG_SW_PHY_SWAP_RESET 0x0 // 0
+#define ETH_CFG_SW_ONLY_MODE_MSB 6
+#define ETH_CFG_SW_ONLY_MODE_LSB 6
+#define ETH_CFG_SW_ONLY_MODE_MASK 0x00000040
+#define ETH_CFG_SW_ONLY_MODE_GET(x) (((x) & ETH_CFG_SW_ONLY_MODE_MASK) >> ETH_CFG_SW_ONLY_MODE_LSB)
+#define ETH_CFG_SW_ONLY_MODE_SET(x) (((x) << ETH_CFG_SW_ONLY_MODE_LSB) & ETH_CFG_SW_ONLY_MODE_MASK)
+#define ETH_CFG_SW_ONLY_MODE_RESET 0x0 // 0
+#define ETH_CFG_ADDRESS 0x18070000
+
+/*
+ * Address map
+ */
+#define ATH_PCI_MEM_BASE 0x10000000 /* 128M */
+#define ATH_APB_BASE 0x18000000 /* 384M */
+#define ATH_GE0_BASE 0x19000000 /* 16M */
+#define ATH_GE1_BASE 0x1a000000 /* 16M */
+#define ATH_USB_OHCI_BASE 0x1b000000
+#define ATH_USB_EHCI_BASE 0x1b000000
+#define ATH_USB_EHCI_BASE_1 0x1b000000
+#define ATH_USB_EHCI_BASE_2 0x1b400000
+#define ATH_SPI_BASE 0x1f000000
+
+/*
+ * Added the PCI LCL RESET register from u-boot
+ * ath_soc.h so that we can query the PCI LCL RESET
+ * register for the presence of WLAN H/W.
+ */
+#define ATH_PCI_LCL_BASE (ATH_APB_BASE+0x000f0000)
+#define ATH_PCI_LCL_APP (ATH_PCI_LCL_BASE+0x00)
+#define ATH_PCI_LCL_RESET (ATH_PCI_LCL_BASE+0x18)
+
+/*
+ * APB block
+ */
+#define ATH_DDR_CTL_BASE ATH_APB_BASE+0x00000000
+#define ATH_CPU_BASE ATH_APB_BASE+0x00010000
+#define ATH_UART_BASE ATH_APB_BASE+0x00020000
+#define ATH_USB_CONFIG_BASE ATH_APB_BASE+0x00030000
+#define ATH_GPIO_BASE ATH_APB_BASE+0x00040000
+#define ATH_PLL_BASE ATH_APB_BASE+0x00050000
+#define ATH_RESET_BASE ATH_APB_BASE+0x00060000
+#define ATH_DMA_BASE ATH_APB_BASE+0x000A0000
+#define ATH_SLIC_BASE ATH_APB_BASE+0x000A9000
+#define ATH_STEREO_BASE ATH_APB_BASE+0x000B0000
+#define ATH_PCI_CTLR_BASE ATH_APB_BASE+0x000F0000
+#define ATH_OTP_BASE ATH_APB_BASE+0x00130000
+//#define ATH_NAND_FLASH_BASE 0x1b800000u
+
+
+/*
+ * DDR Config values
+ */
+#define ATH_DDR_CONFIG_16BIT (1 << 31)
+#define ATH_DDR_CONFIG_PAGE_OPEN (1 << 30)
+#define ATH_DDR_CONFIG_CAS_LAT_SHIFT 27
+#define ATH_DDR_CONFIG_TMRD_SHIFT 23
+#define ATH_DDR_CONFIG_TRFC_SHIFT 17
+#define ATH_DDR_CONFIG_TRRD_SHIFT 13
+#define ATH_DDR_CONFIG_TRP_SHIFT 9
+#define ATH_DDR_CONFIG_TRCD_SHIFT 5
+#define ATH_DDR_CONFIG_TRAS_SHIFT 0
+
+#define ATH_DDR_CONFIG2_BL2 (2 << 0)
+#define ATH_DDR_CONFIG2_BL4 (4 << 0)
+#define ATH_DDR_CONFIG2_BL8 (8 << 0)
+
+#define ATH_DDR_CONFIG2_BT_IL (1 << 4)
+#define ATH_DDR_CONFIG2_CNTL_OE_EN (1 << 5)
+#define ATH_DDR_CONFIG2_PHASE_SEL (1 << 6)
+#define ATH_DDR_CONFIG2_DRAM_CKE (1 << 7)
+#define ATH_DDR_CONFIG2_TWR_SHIFT 8
+#define ATH_DDR_CONFIG2_TRTW_SHIFT 12
+#define ATH_DDR_CONFIG2_TRTP_SHIFT 17
+#define ATH_DDR_CONFIG2_TWTR_SHIFT 21
+#define ATH_DDR_CONFIG2_HALF_WIDTH_L (1 << 31)
+
+#define ATH_DDR_TAP_DEFAULT 0x18
+
+/*
+ * DDR block, gmac flushing
+ */
+#define ATH_DDR_GE0_FLUSH ATH_DDR_CTL_BASE+0x9c
+#define ATH_DDR_GE1_FLUSH ATH_DDR_CTL_BASE+0xa0
+#define ATH_DDR_USB_FLUSH ATH_DDR_CTL_BASE+0xa4
+#define ATH_DDR_PCIE_FLUSH ATH_DDR_CTL_BASE+0x88
+
+#define ATH_EEPROM_GE0_MAC_ADDR 0xbfff1000
+#define ATH_EEPROM_GE1_MAC_ADDR 0xbfff1006
+
+/*
+ * PLL block/CPU
+ */
+
+#define ATH_PLL_CONFIG ATH_PLL_BASE+0x0
+#define ATH_DDR_CLK_CTRL ATH_PLL_BASE+0x8
+
+
+#define PLL_DIV_SHIFT 0
+#define PLL_DIV_MASK 0x3ff
+#define REF_DIV_SHIFT 10
+#define REF_DIV_MASK 0xf
+#define AHB_DIV_SHIFT 19
+#define AHB_DIV_MASK 0x1
+#define DDR_DIV_SHIFT 22
+#define DDR_DIV_MASK 0x1
+#define ATH_DDR_PLL_CONFIG ATH_PLL_BASE+0x4
+#define ATH_ETH_XMII_CONFIG ATH_PLL_BASE+0x2c
+#define ATH_AUDIO_PLL_CONFIG ATH_PLL_BASE+0x30
+
+#define ATH_ETH_INT0_CLK ATH_PLL_BASE+0x14
+#define ATH_ETH_INT1_CLK ATH_PLL_BASE+0x18
+
+
+/*
+ * USB block
+ */
+#define ATH_USB_FLADJ_VAL ATH_USB_CONFIG_BASE
+#define ATH_USB_CONFIG ATH_USB_CONFIG_BASE+0x4
+#define ATH_USB_WINDOW 0x10000
+#define ATH_USB_MODE ATH_USB_EHCI_BASE+0x1a8
+
+/*
+ * PCI block
+ */
+#define ATH_PCI_WINDOW 0x8000000 /* 128MB */
+#define ATH_PCI_WINDOW0_OFFSET ATH_DDR_CTL_BASE+0x7c
+#define ATH_PCI_WINDOW1_OFFSET ATH_DDR_CTL_BASE+0x80
+#define ATH_PCI_WINDOW2_OFFSET ATH_DDR_CTL_BASE+0x84
+#define ATH_PCI_WINDOW3_OFFSET ATH_DDR_CTL_BASE+0x88
+#define ATH_PCI_WINDOW4_OFFSET ATH_DDR_CTL_BASE+0x8c
+#define ATH_PCI_WINDOW5_OFFSET ATH_DDR_CTL_BASE+0x90
+#define ATH_PCI_WINDOW6_OFFSET ATH_DDR_CTL_BASE+0x94
+#define ATH_PCI_WINDOW7_OFFSET ATH_DDR_CTL_BASE+0x98
+
+#define ATH_PCI_WINDOW0_VAL 0x10000000
+#define ATH_PCI_WINDOW1_VAL 0x11000000
+#define ATH_PCI_WINDOW2_VAL 0x12000000
+#define ATH_PCI_WINDOW3_VAL 0x13000000
+#define ATH_PCI_WINDOW4_VAL 0x14000000
+#define ATH_PCI_WINDOW5_VAL 0x15000000
+#define ATH_PCI_WINDOW6_VAL 0x16000000
+#define ATH_PCI_WINDOW7_VAL 0x07000000
+
+#define ath_write_pci_window(_no) \
+ ath_reg_wr(ATH_PCI_WINDOW##_no##_OFFSET, ATH_PCI_WINDOW##_no##_VAL);
+
+/*
+ * CRP. To access the host controller config and status registers
+ */
+#define ATH_PCI_CRP 0x180c0000
+#define ATH_PCI_DEV_CFGBASE 0x14000000
+#define ATH_PCI_CRP_AD_CBE ATH_PCI_CRP
+#define ATH_PCI_CRP_WRDATA ATH_PCI_CRP+0x4
+#define ATH_PCI_CRP_RDDATA ATH_PCI_CRP+0x8
+#define ATH_PCI_ERROR ATH_PCI_CRP+0x1c
+#define ATH_PCI_ERROR_ADDRESS ATH_PCI_CRP+0x20
+#define ATH_PCI_AHB_ERROR ATH_PCI_CRP+0x24
+#define ATH_PCI_AHB_ERROR_ADDRESS ATH_PCI_CRP+0x28
+
+#define ATH_CRP_CMD_WRITE 0x00010000
+#define ATH_CRP_CMD_READ 0x00000000
+
+/*
+ * PCI CFG. To generate config cycles
+ */
+#define ATH_PCI_CFG_AD ATH_PCI_CRP+0xc
+#define ATH_PCI_CFG_CBE ATH_PCI_CRP+0x10
+#define ATH_PCI_CFG_WRDATA ATH_PCI_CRP+0x14
+#define ATH_PCI_CFG_RDDATA ATH_PCI_CRP+0x18
+#define ATH_CFG_CMD_READ 0x0000000a
+#define ATH_CFG_CMD_WRITE 0x0000000b
+
+#define ATH_PCI_IDSEL_ADLINE_START 17
+
+#define ATH_SPI_FS (ATH_SPI_BASE+0x00)
+#define ATH_SPI_READ (ATH_SPI_BASE+0x00)
+#define ATH_SPI_CLOCK (ATH_SPI_BASE+0x04)
+#define ATH_SPI_WRITE (ATH_SPI_BASE+0x08)
+#define ATH_SPI_RD_STATUS (ATH_SPI_BASE+0x0c)
+#define ATH_SPI_SHIFT_DO (ATH_SPI_BASE+0x10)
+#define ATH_SPI_SHIFT_CNT (ATH_SPI_BASE+0x14)
+#define ATH_SPI_SHIFT_DI (ATH_SPI_BASE+0x18)
+#define ATH_SPI_D0_HIGH (1<<0) /* Pin spi_do */
+#define ATH_SPI_CLK_HIGH (1<<8) /* Pin spi_clk */
+
+#define ATH_SPI_CS_ENABLE_0 (6<<16) /* Pin gpio/cs0 (active low) */
+#define ATH_SPI_CS_ENABLE_1 (5<<16) /* Pin gpio/cs1 (active low) */
+#define ATH_SPI_CS_ENABLE_2 (3<<16) /* Pin gpio/cs2 (active low) */
+#define ATH_SPI_CS_DIS 0x70000
+#define ATH_SPI_CE_LOW 0x60000
+#define ATH_SPI_CE_HIGH 0x60100
+
+#define ATH_SPI_SECTOR_SIZE (1024*64)
+#define ATH_SPI_PAGE_SIZE 256
+
+#define ATH_RESET_GE0_MAC RST_RESET_GE0_MAC_RESET_SET(1)
+#define ATH_RESET_GE0_PHY RST_RESET_ETH_SWITCH_RESET_SET(1)
+#define ATH_RESET_GE1_MAC RST_RESET_GE1_MAC_RESET_SET(1)
+#define ATH_RESET_GE1_PHY RST_RESET_ETH_SWITCH_ARESET_SET(1)
+#define ATH_RESET_GE0_MDIO RST_RESET_GE0_MDIO_RESET_SET(1)
+#define ATH_RESET_GE1_MDIO RST_RESET_GE1_MDIO_RESET_SET(1)
+
+/*
+ * SOC
+ */
+#define ATH_SPI_CMD_WRITE_SR 0x01
+#define ATH_SPI_CMD_WREN 0x06
+#define ATH_SPI_CMD_RD_STATUS 0x05
+#define ATH_SPI_CMD_FAST_READ 0x0b
+#define ATH_SPI_CMD_PAGE_PROG 0x02
+#define ATH_SPI_CMD_SECTOR_ERASE 0xd8
+#define ATH_SPI_CMD_CHIP_ERASE 0xc7
+#define ATH_SPI_CMD_RDID 0x9f
+
+#define CPU_CLK_FROM_DDR_PLL CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(0)
+#define CPU_CLK_FROM_CPU_PLL CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+
+#define DDR_CLK_FROM_DDR_PLL CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define DDR_CLK_FROM_CPU_PLL CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(0)
+
+#if CPU_DDR_SYNC_MODE
+
+# define both_from_cpu 0
+# define both_from_ddr 1
+
+# if both_from_ddr
+# define CLK_SRC_CONTROL (CPU_CLK_FROM_DDR_PLL | DDR_CLK_FROM_DDR_PLL)
+# define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+# elif both_from_cpu
+# define CLK_SRC_CONTROL (CPU_CLK_FROM_CPU_PLL | DDR_CLK_FROM_CPU_PLL)
+# define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)
+# else
+# error "Invalid sync mode settings"
+# endif
+#else
+# define CLK_SRC_CONTROL (CPU_CLK_FROM_CPU_PLL | DDR_CLK_FROM_DDR_PLL)
+#endif
+
+
+/* SGMII DEFINES */
+
+// 32'h18070034 (SGMII_CONFIG)
+#define SGMII_CONFIG_BERT_ENABLE_MSB 14
+#define SGMII_CONFIG_BERT_ENABLE_LSB 14
+#define SGMII_CONFIG_BERT_ENABLE_MASK 0x00004000
+#define SGMII_CONFIG_BERT_ENABLE_GET(x) (((x) & SGMII_CONFIG_BERT_ENABLE_MASK) >> SGMII_CONFIG_BERT_ENABLE_LSB)
+#define SGMII_CONFIG_BERT_ENABLE_SET(x) (((x) << SGMII_CONFIG_BERT_ENABLE_LSB) & SGMII_CONFIG_BERT_ENABLE_MASK)
+#define SGMII_CONFIG_BERT_ENABLE_RESET 0x0 // 0
+#define SGMII_CONFIG_PRBS_ENABLE_MSB 13
+#define SGMII_CONFIG_PRBS_ENABLE_LSB 13
+#define SGMII_CONFIG_PRBS_ENABLE_MASK 0x00002000
+#define SGMII_CONFIG_PRBS_ENABLE_GET(x) (((x) & SGMII_CONFIG_PRBS_ENABLE_MASK) >> SGMII_CONFIG_PRBS_ENABLE_LSB)
+#define SGMII_CONFIG_PRBS_ENABLE_SET(x) (((x) << SGMII_CONFIG_PRBS_ENABLE_LSB) & SGMII_CONFIG_PRBS_ENABLE_MASK)
+#define SGMII_CONFIG_PRBS_ENABLE_RESET 0x0 // 0
+#define SGMII_CONFIG_MDIO_COMPLETE_MSB 12
+#define SGMII_CONFIG_MDIO_COMPLETE_LSB 12
+#define SGMII_CONFIG_MDIO_COMPLETE_MASK 0x00001000
+#define SGMII_CONFIG_MDIO_COMPLETE_GET(x) (((x) & SGMII_CONFIG_MDIO_COMPLETE_MASK) >> SGMII_CONFIG_MDIO_COMPLETE_LSB)
+#define SGMII_CONFIG_MDIO_COMPLETE_SET(x) (((x) << SGMII_CONFIG_MDIO_COMPLETE_LSB) & SGMII_CONFIG_MDIO_COMPLETE_MASK)
+#define SGMII_CONFIG_MDIO_COMPLETE_RESET 0x0 // 0
+#define SGMII_CONFIG_MDIO_PULSE_MSB 11
+#define SGMII_CONFIG_MDIO_PULSE_LSB 11
+#define SGMII_CONFIG_MDIO_PULSE_MASK 0x00000800
+#define SGMII_CONFIG_MDIO_PULSE_GET(x) (((x) & SGMII_CONFIG_MDIO_PULSE_MASK) >> SGMII_CONFIG_MDIO_PULSE_LSB)
+#define SGMII_CONFIG_MDIO_PULSE_SET(x) (((x) << SGMII_CONFIG_MDIO_PULSE_LSB) & SGMII_CONFIG_MDIO_PULSE_MASK)
+#define SGMII_CONFIG_MDIO_PULSE_RESET 0x0 // 0
+#define SGMII_CONFIG_MDIO_ENABLE_MSB 10
+#define SGMII_CONFIG_MDIO_ENABLE_LSB 10
+#define SGMII_CONFIG_MDIO_ENABLE_MASK 0x00000400
+#define SGMII_CONFIG_MDIO_ENABLE_GET(x) (((x) & SGMII_CONFIG_MDIO_ENABLE_MASK) >> SGMII_CONFIG_MDIO_ENABLE_LSB)
+#define SGMII_CONFIG_MDIO_ENABLE_SET(x) (((x) << SGMII_CONFIG_MDIO_ENABLE_LSB) & SGMII_CONFIG_MDIO_ENABLE_MASK)
+#define SGMII_CONFIG_MDIO_ENABLE_RESET 0x0 // 0
+#define SGMII_CONFIG_NEXT_PAGE_LOADED_MSB 9
+#define SGMII_CONFIG_NEXT_PAGE_LOADED_LSB 9
+#define SGMII_CONFIG_NEXT_PAGE_LOADED_MASK 0x00000200
+#define SGMII_CONFIG_NEXT_PAGE_LOADED_GET(x) (((x) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK) >> SGMII_CONFIG_NEXT_PAGE_LOADED_LSB)
+#define SGMII_CONFIG_NEXT_PAGE_LOADED_SET(x) (((x) << SGMII_CONFIG_NEXT_PAGE_LOADED_LSB) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK)
+#define SGMII_CONFIG_NEXT_PAGE_LOADED_RESET 0x0 // 0
+#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MSB 8
+#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB 8
+#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK 0x00000100
+#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_GET(x) (((x) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK) >> SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB)
+#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_SET(x) (((x) << SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK)
+#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_RESET 0x0 // 0
+#define SGMII_CONFIG_SPEED_MSB 7
+#define SGMII_CONFIG_SPEED_LSB 6
+#define SGMII_CONFIG_SPEED_MASK 0x000000c0
+#define SGMII_CONFIG_SPEED_GET(x) (((x) & SGMII_CONFIG_SPEED_MASK) >> SGMII_CONFIG_SPEED_LSB)
+#define SGMII_CONFIG_SPEED_SET(x) (((x) << SGMII_CONFIG_SPEED_LSB) & SGMII_CONFIG_SPEED_MASK)
+#define SGMII_CONFIG_SPEED_RESET 0x0 // 0
+#define SGMII_CONFIG_FORCE_SPEED_MSB 5
+#define SGMII_CONFIG_FORCE_SPEED_LSB 5
+#define SGMII_CONFIG_FORCE_SPEED_MASK 0x00000020
+#define SGMII_CONFIG_FORCE_SPEED_GET(x) (((x) & SGMII_CONFIG_FORCE_SPEED_MASK) >> SGMII_CONFIG_FORCE_SPEED_LSB)
+#define SGMII_CONFIG_FORCE_SPEED_SET(x) (((x) << SGMII_CONFIG_FORCE_SPEED_LSB) & SGMII_CONFIG_FORCE_SPEED_MASK)
+#define SGMII_CONFIG_FORCE_SPEED_RESET 0x0 // 0
+#define SGMII_CONFIG_MR_REG4_CHANGED_MSB 4
+#define SGMII_CONFIG_MR_REG4_CHANGED_LSB 4
+#define SGMII_CONFIG_MR_REG4_CHANGED_MASK 0x00000010
+#define SGMII_CONFIG_MR_REG4_CHANGED_GET(x) (((x) & SGMII_CONFIG_MR_REG4_CHANGED_MASK) >> SGMII_CONFIG_MR_REG4_CHANGED_LSB)
+#define SGMII_CONFIG_MR_REG4_CHANGED_SET(x) (((x) << SGMII_CONFIG_MR_REG4_CHANGED_LSB) & SGMII_CONFIG_MR_REG4_CHANGED_MASK)
+#define SGMII_CONFIG_MR_REG4_CHANGED_RESET 0x0 // 0
+#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MSB 3
+#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB 3
+#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK 0x00000008
+#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_GET(x) (((x) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK) >> SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB)
+#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_SET(x) (((x) << SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK)
+#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_RESET 0x0 // 0
+#define SGMII_CONFIG_MODE_CTRL_MSB 2
+#define SGMII_CONFIG_MODE_CTRL_LSB 0
+#define SGMII_CONFIG_MODE_CTRL_MASK 0x00000007
+#define SGMII_CONFIG_MODE_CTRL_GET(x) (((x) & SGMII_CONFIG_MODE_CTRL_MASK) >> SGMII_CONFIG_MODE_CTRL_LSB)
+#define SGMII_CONFIG_MODE_CTRL_SET(x) (((x) << SGMII_CONFIG_MODE_CTRL_LSB) & SGMII_CONFIG_MODE_CTRL_MASK)
+#define SGMII_CONFIG_MODE_CTRL_RESET 0x0 // 0
+#define SGMII_CONFIG_ADDRESS 0x18070034
+
+
+
+// 32'h1807001c (MR_AN_CONTROL)
+#define MR_AN_CONTROL_PHY_RESET_MSB 15
+#define MR_AN_CONTROL_PHY_RESET_LSB 15
+#define MR_AN_CONTROL_PHY_RESET_MASK 0x00008000
+#define MR_AN_CONTROL_PHY_RESET_GET(x) (((x) & MR_AN_CONTROL_PHY_RESET_MASK) >> MR_AN_CONTROL_PHY_RESET_LSB)
+#define MR_AN_CONTROL_PHY_RESET_SET(x) (((x) << MR_AN_CONTROL_PHY_RESET_LSB) & MR_AN_CONTROL_PHY_RESET_MASK)
+#define MR_AN_CONTROL_PHY_RESET_RESET 0x0 // 0
+#define MR_AN_CONTROL_LOOPBACK_MSB 14
+#define MR_AN_CONTROL_LOOPBACK_LSB 14
+#define MR_AN_CONTROL_LOOPBACK_MASK 0x00004000
+#define MR_AN_CONTROL_LOOPBACK_GET(x) (((x) & MR_AN_CONTROL_LOOPBACK_MASK) >> MR_AN_CONTROL_LOOPBACK_LSB)
+#define MR_AN_CONTROL_LOOPBACK_SET(x) (((x) << MR_AN_CONTROL_LOOPBACK_LSB) & MR_AN_CONTROL_LOOPBACK_MASK)
+#define MR_AN_CONTROL_LOOPBACK_RESET 0x0 // 0
+#define MR_AN_CONTROL_SPEED_SEL0_MSB 13
+#define MR_AN_CONTROL_SPEED_SEL0_LSB 13
+#define MR_AN_CONTROL_SPEED_SEL0_MASK 0x00002000
+#define MR_AN_CONTROL_SPEED_SEL0_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL0_MASK) >> MR_AN_CONTROL_SPEED_SEL0_LSB)
+#define MR_AN_CONTROL_SPEED_SEL0_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL0_LSB) & MR_AN_CONTROL_SPEED_SEL0_MASK)
+#define MR_AN_CONTROL_SPEED_SEL0_RESET 0x0 // 0
+#define MR_AN_CONTROL_AN_ENABLE_MSB 12
+#define MR_AN_CONTROL_AN_ENABLE_LSB 12
+#define MR_AN_CONTROL_AN_ENABLE_MASK 0x00001000
+#define MR_AN_CONTROL_AN_ENABLE_GET(x) (((x) & MR_AN_CONTROL_AN_ENABLE_MASK) >> MR_AN_CONTROL_AN_ENABLE_LSB)
+#define MR_AN_CONTROL_AN_ENABLE_SET(x) (((x) << MR_AN_CONTROL_AN_ENABLE_LSB) & MR_AN_CONTROL_AN_ENABLE_MASK)
+#define MR_AN_CONTROL_AN_ENABLE_RESET 0x1 // 1
+#define MR_AN_CONTROL_POWER_DOWN_MSB 11
+#define MR_AN_CONTROL_POWER_DOWN_LSB 11
+#define MR_AN_CONTROL_POWER_DOWN_MASK 0x00000800
+#define MR_AN_CONTROL_POWER_DOWN_GET(x) (((x) & MR_AN_CONTROL_POWER_DOWN_MASK) >> MR_AN_CONTROL_POWER_DOWN_LSB)
+#define MR_AN_CONTROL_POWER_DOWN_SET(x) (((x) << MR_AN_CONTROL_POWER_DOWN_LSB) & MR_AN_CONTROL_POWER_DOWN_MASK)
+#define MR_AN_CONTROL_POWER_DOWN_RESET 0x0 // 0
+#define MR_AN_CONTROL_RESTART_AN_MSB 9
+#define MR_AN_CONTROL_RESTART_AN_LSB 9
+#define MR_AN_CONTROL_RESTART_AN_MASK 0x00000200
+#define MR_AN_CONTROL_RESTART_AN_GET(x) (((x) & MR_AN_CONTROL_RESTART_AN_MASK) >> MR_AN_CONTROL_RESTART_AN_LSB)
+#define MR_AN_CONTROL_RESTART_AN_SET(x) (((x) << MR_AN_CONTROL_RESTART_AN_LSB) & MR_AN_CONTROL_RESTART_AN_MASK)
+#define MR_AN_CONTROL_RESTART_AN_RESET 0x0 // 0
+#define MR_AN_CONTROL_DUPLEX_MODE_MSB 8
+#define MR_AN_CONTROL_DUPLEX_MODE_LSB 8
+#define MR_AN_CONTROL_DUPLEX_MODE_MASK 0x00000100
+#define MR_AN_CONTROL_DUPLEX_MODE_GET(x) (((x) & MR_AN_CONTROL_DUPLEX_MODE_MASK) >> MR_AN_CONTROL_DUPLEX_MODE_LSB)
+#define MR_AN_CONTROL_DUPLEX_MODE_SET(x) (((x) << MR_AN_CONTROL_DUPLEX_MODE_LSB) & MR_AN_CONTROL_DUPLEX_MODE_MASK)
+#define MR_AN_CONTROL_DUPLEX_MODE_RESET 0x1 // 1
+#define MR_AN_CONTROL_SPEED_SEL1_MSB 6
+#define MR_AN_CONTROL_SPEED_SEL1_LSB 6
+#define MR_AN_CONTROL_SPEED_SEL1_MASK 0x00000040
+#define MR_AN_CONTROL_SPEED_SEL1_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL1_MASK) >> MR_AN_CONTROL_SPEED_SEL1_LSB)
+#define MR_AN_CONTROL_SPEED_SEL1_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL1_LSB) & MR_AN_CONTROL_SPEED_SEL1_MASK)
+#define MR_AN_CONTROL_SPEED_SEL1_RESET 0x1 // 1
+#define MR_AN_CONTROL_ADDRESS 0x1807001c
+
+
+
+
+
+// 32'h18070014 (SGMII_RESET)
+#define SGMII_RESET_HW_RX_125M_N_MSB 4
+#define SGMII_RESET_HW_RX_125M_N_LSB 4
+#define SGMII_RESET_HW_RX_125M_N_MASK 0x00000010
+#define SGMII_RESET_HW_RX_125M_N_GET(x) (((x) & SGMII_RESET_HW_RX_125M_N_MASK) >> SGMII_RESET_HW_RX_125M_N_LSB)
+#define SGMII_RESET_HW_RX_125M_N_SET(x) (((x) << SGMII_RESET_HW_RX_125M_N_LSB) & SGMII_RESET_HW_RX_125M_N_MASK)
+#define SGMII_RESET_HW_RX_125M_N_RESET 0x0 // 0
+#define SGMII_RESET_TX_125M_N_MSB 3
+#define SGMII_RESET_TX_125M_N_LSB 3
+#define SGMII_RESET_TX_125M_N_MASK 0x00000008
+#define SGMII_RESET_TX_125M_N_GET(x) (((x) & SGMII_RESET_TX_125M_N_MASK) >> SGMII_RESET_TX_125M_N_LSB)
+#define SGMII_RESET_TX_125M_N_SET(x) (((x) << SGMII_RESET_TX_125M_N_LSB) & SGMII_RESET_TX_125M_N_MASK)
+#define SGMII_RESET_TX_125M_N_RESET 0x0 // 0
+#define SGMII_RESET_RX_125M_N_MSB 2
+#define SGMII_RESET_RX_125M_N_LSB 2
+#define SGMII_RESET_RX_125M_N_MASK 0x00000004
+#define SGMII_RESET_RX_125M_N_GET(x) (((x) & SGMII_RESET_RX_125M_N_MASK) >> SGMII_RESET_RX_125M_N_LSB)
+#define SGMII_RESET_RX_125M_N_SET(x) (((x) << SGMII_RESET_RX_125M_N_LSB) & SGMII_RESET_RX_125M_N_MASK)
+#define SGMII_RESET_RX_125M_N_RESET 0x0 // 0
+#define SGMII_RESET_TX_CLK_N_MSB 1
+#define SGMII_RESET_TX_CLK_N_LSB 1
+#define SGMII_RESET_TX_CLK_N_MASK 0x00000002
+#define SGMII_RESET_TX_CLK_N_GET(x) (((x) & SGMII_RESET_TX_CLK_N_MASK) >> SGMII_RESET_TX_CLK_N_LSB)
+#define SGMII_RESET_TX_CLK_N_SET(x) (((x) << SGMII_RESET_TX_CLK_N_LSB) & SGMII_RESET_TX_CLK_N_MASK)
+#define SGMII_RESET_TX_CLK_N_RESET 0x0 // 0
+#define SGMII_RESET_RX_CLK_N_MSB 0
+#define SGMII_RESET_RX_CLK_N_LSB 0
+#define SGMII_RESET_RX_CLK_N_MASK 0x00000001
+#define SGMII_RESET_RX_CLK_N_GET(x) (((x) & SGMII_RESET_RX_CLK_N_MASK) >> SGMII_RESET_RX_CLK_N_LSB)
+#define SGMII_RESET_RX_CLK_N_SET(x) (((x) << SGMII_RESET_RX_CLK_N_LSB) & SGMII_RESET_RX_CLK_N_MASK)
+#define SGMII_RESET_RX_CLK_N_RESET 0x0 // 0
+#define SGMII_RESET_ADDRESS 0x18070014
+
+
+
+// 32'h18070038 (SGMII_MAC_RX_CONFIG)
+#define SGMII_MAC_RX_CONFIG_LINK_MSB 15
+#define SGMII_MAC_RX_CONFIG_LINK_LSB 15
+#define SGMII_MAC_RX_CONFIG_LINK_MASK 0x00008000
+#define SGMII_MAC_RX_CONFIG_LINK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_LINK_MASK) >> SGMII_MAC_RX_CONFIG_LINK_LSB)
+#define SGMII_MAC_RX_CONFIG_LINK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_LINK_LSB) & SGMII_MAC_RX_CONFIG_LINK_MASK)
+#define SGMII_MAC_RX_CONFIG_LINK_RESET 0x0 // 0
+#define SGMII_MAC_RX_CONFIG_ACK_MSB 14
+#define SGMII_MAC_RX_CONFIG_ACK_LSB 14
+#define SGMII_MAC_RX_CONFIG_ACK_MASK 0x00004000
+#define SGMII_MAC_RX_CONFIG_ACK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ACK_MASK) >> SGMII_MAC_RX_CONFIG_ACK_LSB)
+#define SGMII_MAC_RX_CONFIG_ACK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ACK_LSB) & SGMII_MAC_RX_CONFIG_ACK_MASK)
+#define SGMII_MAC_RX_CONFIG_ACK_RESET 0x0 // 0
+#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MSB 12
+#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB 12
+#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK 0x00001000
+#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK) >> SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB)
+#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK)
+#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_RESET 0x0 // 0
+#define SGMII_MAC_RX_CONFIG_SPEED_MODE_MSB 11
+#define SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB 10
+#define SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK 0x00000c00
+#define SGMII_MAC_RX_CONFIG_SPEED_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK) >> SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB)
+#define SGMII_MAC_RX_CONFIG_SPEED_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK)
+#define SGMII_MAC_RX_CONFIG_SPEED_MODE_RESET 0x0 // 0
+#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MSB 8
+#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB 8
+#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK 0x00000100
+#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB)
+#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK)
+#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_RESET 0x0 // 0
+#define SGMII_MAC_RX_CONFIG_PAUSE_MSB 7
+#define SGMII_MAC_RX_CONFIG_PAUSE_LSB 7
+#define SGMII_MAC_RX_CONFIG_PAUSE_MASK 0x00000080
+#define SGMII_MAC_RX_CONFIG_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_PAUSE_LSB)
+#define SGMII_MAC_RX_CONFIG_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_PAUSE_MASK)
+#define SGMII_MAC_RX_CONFIG_PAUSE_RESET 0x0 // 0
+#define SGMII_MAC_RX_CONFIG_RES0_MSB 0
+#define SGMII_MAC_RX_CONFIG_RES0_LSB 0
+#define SGMII_MAC_RX_CONFIG_RES0_MASK 0x00000001
+#define SGMII_MAC_RX_CONFIG_RES0_GET(x) (((x) & SGMII_MAC_RX_CONFIG_RES0_MASK) >> SGMII_MAC_RX_CONFIG_RES0_LSB)
+#define SGMII_MAC_RX_CONFIG_RES0_SET(x) (((x) << SGMII_MAC_RX_CONFIG_RES0_LSB) & SGMII_MAC_RX_CONFIG_RES0_MASK)
+#define SGMII_MAC_RX_CONFIG_RES0_RESET 0x1 // 1
+#define SGMII_MAC_RX_CONFIG_ADDRESS 0x18070038
+
+// 32'h18070058 (SGMII_DEBUG)
+#define SGMII_DEBUG_ARB_STATE_MSB 27
+#define SGMII_DEBUG_ARB_STATE_LSB 24
+#define SGMII_DEBUG_ARB_STATE_MASK 0x0f000000
+#define SGMII_DEBUG_ARB_STATE_GET(x) (((x) & SGMII_DEBUG_ARB_STATE_MASK) >> SGMII_DEBUG_ARB_STATE_LSB)
+#define SGMII_DEBUG_ARB_STATE_SET(x) (((x) << SGMII_DEBUG_ARB_STATE_LSB) & SGMII_DEBUG_ARB_STATE_MASK)
+#define SGMII_DEBUG_ARB_STATE_RESET 0x0 // 0
+#define SGMII_DEBUG_RX_SYNC_STATE_MSB 23
+#define SGMII_DEBUG_RX_SYNC_STATE_LSB 16
+#define SGMII_DEBUG_RX_SYNC_STATE_MASK 0x00ff0000
+#define SGMII_DEBUG_RX_SYNC_STATE_GET(x) (((x) & SGMII_DEBUG_RX_SYNC_STATE_MASK) >> SGMII_DEBUG_RX_SYNC_STATE_LSB)
+#define SGMII_DEBUG_RX_SYNC_STATE_SET(x) (((x) << SGMII_DEBUG_RX_SYNC_STATE_LSB) & SGMII_DEBUG_RX_SYNC_STATE_MASK)
+#define SGMII_DEBUG_RX_SYNC_STATE_RESET 0x0 // 0
+#define SGMII_DEBUG_RX_STATE_MSB 15
+#define SGMII_DEBUG_RX_STATE_LSB 8
+#define SGMII_DEBUG_RX_STATE_MASK 0x0000ff00
+#define SGMII_DEBUG_RX_STATE_GET(x) (((x) & SGMII_DEBUG_RX_STATE_MASK) >> SGMII_DEBUG_RX_STATE_LSB)
+#define SGMII_DEBUG_RX_STATE_SET(x) (((x) << SGMII_DEBUG_RX_STATE_LSB) & SGMII_DEBUG_RX_STATE_MASK)
+#define SGMII_DEBUG_RX_STATE_RESET 0x0 // 0
+#define SGMII_DEBUG_TX_STATE_MSB 7
+#define SGMII_DEBUG_TX_STATE_LSB 0
+#define SGMII_DEBUG_TX_STATE_MASK 0x000000ff
+#define SGMII_DEBUG_TX_STATE_GET(x) (((x) & SGMII_DEBUG_TX_STATE_MASK) >> SGMII_DEBUG_TX_STATE_LSB)
+#define SGMII_DEBUG_TX_STATE_SET(x) (((x) << SGMII_DEBUG_TX_STATE_LSB) & SGMII_DEBUG_TX_STATE_MASK)
+#define SGMII_DEBUG_TX_STATE_RESET 0x0 // 0
+#define SGMII_DEBUG_ADDRESS 0x18070058
+#define SGMII_DEBUG_OFFSET 0x0058
+
+
+
+// 32'h18070060 (SGMII_INTERRUPT_MASK)
+#define SGMII_INTERRUPT_MASK_MASK_MSB 7
+#define SGMII_INTERRUPT_MASK_MASK_LSB 0
+#define SGMII_INTERRUPT_MASK_MASK_MASK 0x000000ff
+#define SGMII_INTERRUPT_MASK_MASK_GET(x) (((x) & SGMII_INTERRUPT_MASK_MASK_MASK) >> SGMII_INTERRUPT_MASK_MASK_LSB)
+#define SGMII_INTERRUPT_MASK_MASK_SET(x) (((x) << SGMII_INTERRUPT_MASK_MASK_LSB) & SGMII_INTERRUPT_MASK_MASK_MASK)
+#define SGMII_INTERRUPT_MASK_MASK_RESET 0x0 // 0
+#define SGMII_INTERRUPT_MASK_ADDRESS 0x18070060
+
+
+
+
+// 32'h1807005c (SGMII_INTERRUPT)
+#define SGMII_INTERRUPT_INTR_MSB 7
+#define SGMII_INTERRUPT_INTR_LSB 0
+#define SGMII_INTERRUPT_INTR_MASK 0x000000ff
+#define SGMII_INTERRUPT_INTR_GET(x) (((x) & SGMII_INTERRUPT_INTR_MASK) >> SGMII_INTERRUPT_INTR_LSB)
+#define SGMII_INTERRUPT_INTR_SET(x) (((x) << SGMII_INTERRUPT_INTR_LSB) & SGMII_INTERRUPT_INTR_MASK)
+#define SGMII_INTERRUPT_INTR_RESET 0x0 // 0
+#define SGMII_INTERRUPT_ADDRESS 0x1807005c
+#define SGMII_INTERRUPT_OFFSET 0x005c
+// SW modifiable bits
+#define SGMII_INTERRUPT_SW_MASK 0x000000ff
+// bits defined at reset
+#define SGMII_INTERRUPT_RSTMASK 0xffffffff
+// reset value (ignore bits undefined at reset)
+#define SGMII_INTERRUPT_RESET 0x00000000
+
+// 32'h18070060 (SGMII_INTERRUPT_MASK)
+#define SGMII_INTERRUPT_MASK_MASK_MSB 7
+#define SGMII_INTERRUPT_MASK_MASK_LSB 0
+#define SGMII_INTERRUPT_MASK_MASK_MASK 0x000000ff
+#define SGMII_INTERRUPT_MASK_MASK_GET(x) (((x) & SGMII_INTERRUPT_MASK_MASK_MASK) >> SGMII_INTERRUPT_MASK_MASK_LSB)
+#define SGMII_INTERRUPT_MASK_MASK_SET(x) (((x) << SGMII_INTERRUPT_MASK_MASK_LSB) & SGMII_INTERRUPT_MASK_MASK_MASK)
+#define SGMII_INTERRUPT_MASK_MASK_RESET 0x0 // 0
+#define SGMII_INTERRUPT_MASK_ADDRESS 0x18070060
+
+
+#define SGMII_LINK_FAIL (1 << 0)
+#define SGMII_DUPLEX_ERR (1 << 1)
+#define SGMII_MR_AN_COMPLETE (1 << 2)
+#define SGMII_LINK_MAC_CHANGE (1 << 3)
+#define SGMII_DUPLEX_MODE_CHANGE (1 << 4)
+#define SGMII_SPEED_MODE_MAC_CHANGE (1 << 5)
+#define SGMII_RX_QUIET_CHANGE (1 << 6)
+#define SGMII_RX_MDIO_COMP_CHANGE (1 << 7)
+
+#define SGMII_INTR SGMII_LINK_FAIL | \
+ SGMII_LINK_MAC_CHANGE | \
+ SGMII_DUPLEX_MODE_CHANGE | \
+ SGMII_SPEED_MODE_MAC_CHANGE
+
+
+// 32'h18050048 (ETH_SGMII)
+#define ETH_SGMII_TX_INVERT_MSB 31
+#define ETH_SGMII_TX_INVERT_LSB 31
+#define ETH_SGMII_TX_INVERT_MASK 0x80000000
+#define ETH_SGMII_TX_INVERT_GET(x) (((x) & ETH_SGMII_TX_INVERT_MASK) >> ETH_SGMII_TX_INVERT_LSB)
+#define ETH_SGMII_TX_INVERT_SET(x) (((x) << ETH_SGMII_TX_INVERT_LSB) & ETH_SGMII_TX_INVERT_MASK)
+#define ETH_SGMII_TX_INVERT_RESET 0x0 // 0
+#define ETH_SGMII_GIGE_QUAD_MSB 30
+#define ETH_SGMII_GIGE_QUAD_LSB 30
+#define ETH_SGMII_GIGE_QUAD_MASK 0x40000000
+#define ETH_SGMII_GIGE_QUAD_GET(x) (((x) & ETH_SGMII_GIGE_QUAD_MASK) >> ETH_SGMII_GIGE_QUAD_LSB)
+#define ETH_SGMII_GIGE_QUAD_SET(x) (((x) << ETH_SGMII_GIGE_QUAD_LSB) & ETH_SGMII_GIGE_QUAD_MASK)
+#define ETH_SGMII_GIGE_QUAD_RESET 0x0 // 0
+#define ETH_SGMII_RX_DELAY_MSB 29
+#define ETH_SGMII_RX_DELAY_LSB 28
+#define ETH_SGMII_RX_DELAY_MASK 0x30000000
+#define ETH_SGMII_RX_DELAY_GET(x) (((x) & ETH_SGMII_RX_DELAY_MASK) >> ETH_SGMII_RX_DELAY_LSB)
+#define ETH_SGMII_RX_DELAY_SET(x) (((x) << ETH_SGMII_RX_DELAY_LSB) & ETH_SGMII_RX_DELAY_MASK)
+#define ETH_SGMII_RX_DELAY_RESET 0x0 // 0
+#define ETH_SGMII_TX_DELAY_MSB 27
+#define ETH_SGMII_TX_DELAY_LSB 26
+#define ETH_SGMII_TX_DELAY_MASK 0x0c000000
+#define ETH_SGMII_TX_DELAY_GET(x) (((x) & ETH_SGMII_TX_DELAY_MASK) >> ETH_SGMII_TX_DELAY_LSB)
+#define ETH_SGMII_TX_DELAY_SET(x) (((x) << ETH_SGMII_TX_DELAY_LSB) & ETH_SGMII_TX_DELAY_MASK)
+#define ETH_SGMII_TX_DELAY_RESET 0x0 // 0
+#define ETH_SGMII_CLK_SEL_MSB 25
+#define ETH_SGMII_CLK_SEL_LSB 25
+#define ETH_SGMII_CLK_SEL_MASK 0x02000000
+#define ETH_SGMII_CLK_SEL_GET(x) (((x) & ETH_SGMII_CLK_SEL_MASK) >> ETH_SGMII_CLK_SEL_LSB)
+#define ETH_SGMII_CLK_SEL_SET(x) (((x) << ETH_SGMII_CLK_SEL_LSB) & ETH_SGMII_CLK_SEL_MASK)
+#define ETH_SGMII_CLK_SEL_RESET 0x1 // 1
+#define ETH_SGMII_GIGE_MSB 24
+#define ETH_SGMII_GIGE_LSB 24
+#define ETH_SGMII_GIGE_MASK 0x01000000
+#define ETH_SGMII_GIGE_GET(x) (((x) & ETH_SGMII_GIGE_MASK) >> ETH_SGMII_GIGE_LSB)
+#define ETH_SGMII_GIGE_SET(x) (((x) << ETH_SGMII_GIGE_LSB) & ETH_SGMII_GIGE_MASK)
+#define ETH_SGMII_GIGE_RESET 0x1 // 1
+#define ETH_SGMII_PHASE1_COUNT_MSB 15
+#define ETH_SGMII_PHASE1_COUNT_LSB 8
+#define ETH_SGMII_PHASE1_COUNT_MASK 0x0000ff00
+#define ETH_SGMII_PHASE1_COUNT_GET(x) (((x) & ETH_SGMII_PHASE1_COUNT_MASK) >> ETH_SGMII_PHASE1_COUNT_LSB)
+#define ETH_SGMII_PHASE1_COUNT_SET(x) (((x) << ETH_SGMII_PHASE1_COUNT_LSB) & ETH_SGMII_PHASE1_COUNT_MASK)
+#define ETH_SGMII_PHASE1_COUNT_RESET 0x1 // 1
+#define ETH_SGMII_PHASE0_COUNT_MSB 7
+#define ETH_SGMII_PHASE0_COUNT_LSB 0
+#define ETH_SGMII_PHASE0_COUNT_MASK 0x000000ff
+#define ETH_SGMII_PHASE0_COUNT_GET(x) (((x) & ETH_SGMII_PHASE0_COUNT_MASK) >> ETH_SGMII_PHASE0_COUNT_LSB)
+#define ETH_SGMII_PHASE0_COUNT_SET(x) (((x) << ETH_SGMII_PHASE0_COUNT_LSB) & ETH_SGMII_PHASE0_COUNT_MASK)
+#define ETH_SGMII_PHASE0_COUNT_RESET 0x1 // 1
+#define ETH_SGMII_ADDRESS 0x18050048
+
+#endif /* _QCA953X_H */
#define WASP_REF_CLK_25 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */
#define WASP_RAM_TYPE(a) ((a) & 0x3)
-#define CFG_934X_SDRAM_CONFIG_VAL 0x7fbe8cd0
-#define CFG_934X_SDRAM_MODE_VAL_INIT 0x133
-#define CFG_934X_SDRAM_MODE_VAL 0x33
-#define CFG_934X_SDRAM_CONFIG2_VAL 0x959f66a8
-#define CFG_934X_SDRAM_TAP_VAL 0x1f1f
-
-#define CFG_934X_DDR1_CONFIG_VAL 0x7fd48cd0 // 0xc7d48cd0
-#define CFG_934X_DDR1_MODE_VAL_INIT 0x133
-#define CFG_934X_DDR1_EXT_MODE_VAL 0x0
-#define CFG_934X_DDR1_MODE_VAL 0x33
-#define CFG_934X_DDR1_CONFIG2_VAL 0x99d0e6a8 // 0x9dd0e6a8
-
-#if (CFG_PLL_FREQ == CFG_PLL_500_500_250)
-#define CFG_934X_DDR2_CONFIG_VAL 0xcfbc8cd0
-#define CFG_934X_DDR2_MODE_VAL_INIT 0x143
-#define CFG_934X_DDR2_EXT_MODE_VAL 0x402
-#define CFG_934X_DDR2_MODE_VAL 0x43
-#define CFG_934X_DDR2_CONFIG2_VAL 0xa5d0e6a8
-#define CFG_934X_DDR2_EN_TWL_VAL 0x1659
-#define CFG_934X_DDR2_TAP_VAL 0
-#elif (CFG_PLL_FREQ == CFG_PLL_650_600_300) || \
- (CFG_PLL_FREQ == CFG_PLL_600_600_300) || \
- (CFG_PLL_FREQ == CFG_PLL_600_550_275) || \
- (CFG_PLL_FREQ == CFG_PLL_600_575_287)
-
-#define CFG_934X_DDR2_CONFIG_VAL 0xcfd48cd0
-#define CFG_934X_DDR2_MODE_VAL_INIT 0x143
-#define CFG_934X_DDR2_EXT_MODE_VAL 0x402
-#define CFG_934X_DDR2_MODE_VAL 0x43
-#define CFG_934X_DDR2_CONFIG2_VAL 0xa1d0e6a8
-#define CFG_934X_DDR2_EN_TWL_VAL 0x1659
-#define CFG_934X_DDR2_TAP_VAL 0x5
-#else
-/*
-* Date: 2011-030-24
-* Name: Charles Teng
-* Reason: patch from LSDK-9.2.0.312
-*/
-#define CFG_934X_DDR2_CONFIG_VAL 0xc7d48cd0
-#define CFG_934X_DDR2_MODE_VAL_INIT 0x133
-#define CFG_934X_DDR2_EXT_MODE_VAL_INIT 0x382
-#define CFG_934X_DDR2_EXT_MODE_VAL 0x402
-#define CFG_934X_DDR2_MODE_VAL 0x33
-#define CFG_934X_DDR2_CONFIG2_VAL 0x9dd0e6a8
-#define CFG_934X_DDR2_EN_TWL_VAL 0xe59
-#define CFG_934X_DDR2_TAP_VAL 0x10012
-#endif
-
-#define CFG_934X_DDR1_TAP_VAL 0x14
-
#define AR7240_REV_ID_AR7130 0xa0
#define AR7240_REV_ID_AR7141 0xa1
#define AR7240_REV_ID_AR7161 0xa2
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x14 // 20\r
#define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030\r
\r
-\r
-#if (CFG_PLL_FREQ == CFG_PLL_400_400_200)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(32)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(20)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_400_200_200)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(32)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(20)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(2)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(2)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(15)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_1_2G_400_200)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(48)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(32)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_500_1G_250)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(48)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(40)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_550_1_1G_275)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(44)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_400_200)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_332_166)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(26)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_332_200)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(26)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_266_133)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_266_200)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_566_550_275)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(22)\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(13)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)\r
-\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40)\r
- #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9)\r
- #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(768) | DDR_PLL_DITHER_NFRAC_MAX_SET(768)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_566_525_262)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(13)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)\r
-\r
- #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40)\r
- #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9)\r
- #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(128) | DDR_PLL_DITHER_NFRAC_MAX_SET(128)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_566_500_250)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)\r
-\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40)\r
- #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9)\r
- #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(512) | DDR_PLL_DITHER_NFRAC_MAX_SET(512)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_566_475_237)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- /*\r
- * Date: 2011-030-24\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.312\r
- */\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(19)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(11)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)\r
-\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(41) | CPU_PLL_DITHER_NFRAC_MAX_SET(41)\r
- #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9)\r
- #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(1023)\r
- /*\r
- * Date: 2011-030-24\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.312\r
- */\r
- #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(895) | DDR_PLL_DITHER_NFRAC_MAX_SET(1023)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_566_450_225)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(36)\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(22)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)\r
-\r
- #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40)\r
- #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9)\r
- #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(512) | DDR_PLL_DITHER_NFRAC_MAX_SET(512)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_566_400_200)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(16)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(10)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)\r
-\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40)\r
- #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9)\r
- #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_560_480_240)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(19)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)\r
-\r
- #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(25) | CPU_PLL_DITHER_NFRAC_MAX_SET(25)\r
- #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(204) | DDR_PLL_DITHER_NFRAC_MAX_SET(204)\r
- #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_650_600_300)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(26)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_600_300)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_550_275)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(22)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_650_325)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(26)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_525_262)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_575_287)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(23)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(14)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_450_200)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(18)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_533_400_200)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(21)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(13)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20)\r
-\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_533_500_250)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(21)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(13)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_350_175)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(28)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_300_150)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(15)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_400_300)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(32)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_500_400_200)\r
-\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(20)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(12)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- /*\r
- * Date: 2011-030-21\r
- * Name: Charles Teng\r
- * Reason: patch from LSDK-9.2.0.303\r
- * WASP 1.1 support\r
- */\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20)\r
-\r
- #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(32) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
- #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_700_400_200)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(28)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(17)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(3)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_600_500_250)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24)\r
- #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#elif (CFG_PLL_FREQ == CFG_PLL_500_500_250)\r
-\r
- #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(20)\r
- #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)\r
- #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1)\r
- #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(20)\r
- #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)\r
- #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1)\r
- #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)\r
-\r
- #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0)\r
-\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)\r
- #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)\r
- #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)\r
-\r
-#endif\r
-\r
#endif /* _AR934X_SOC_H */\r
* Returns the uncached address of a sdram address
*/
#ifndef __ASSEMBLY__
-#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
-/* We use a 36 bit physical address map here and
- cannot access physical memory directly from core */
-#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
-#elif defined(CONFIG_AR7100) || defined(CONFIG_AR7240)
#define UNCACHED_SDRAM(a) KSEG1ADDR((a))
-#else /* !CONFIG_AR7100 */
-#define UNCACHED_SDRAM(a) PHYSADDR(a)
-#endif /* CONFIG_AU1X00 */
#endif /* __ASSEMBLY__ */
/*
* Map an address to a certain kernel segment
+++ /dev/null
-/*
- * Atheros AR933x SOC registers definitions
- *
- * Copyright (C) 2014 Piotr Dymacz <piotr@dymacz.pl>
- * Copyright (C) 2008-2010 Atheros Communications Inc.
- *
- * SPDX-License-Identifier:GPL-2.0
- */
-
-#ifndef _AR933X_H_
-#define _AR933X_H_
-
-/*
- * Helper macros
- */
-#define _BIT(_x) (1 << (_x))
-#define _BITS(_start, _bits) (((1UL << (_bits)) - 1) << _start)
-
-/*
- * Address map
- */
-#define DDR_BASE_REG 0x00000000
-#define APB_BASE_REG 0x18000000
-#define ETH0_AHB_BASE_REG 0x19000000
-#define ETH1_AHB_BASE_REG 0x1A000000
-#define USB_AHB_BASE_REG 0x1B000000
-#define FLASH_BASE_REG 0x1F000000
-
-/*
- * APB block
- */
-#define DDR_CTRL_BASE_REG APB_BASE_REG + 0x00000000
-#define UART_BASE_REG APB_BASE_REG + 0x00020000
-#define USB_CONFIG_BASE_REG APB_BASE_REG + 0x00030000
-#define GPIO_BASE_REG APB_BASE_REG + 0x00040000
-#define PLL_BASE_REG APB_BASE_REG + 0x00050000
-#define RESET_BASE_REG APB_BASE_REG + 0x00060000
-#define GMAC_BASE_REG APB_BASE_REG + 0x00070000
-#define SLIC_BASE_REG APB_BASE_REG + 0x00090000
-#define RTC_BASE_REG APB_BASE_REG + 0x00107000
-
-/*
- * DDR registers
- */
-#define DDR_CONFIG_REG DDR_CTRL_BASE_REG + 0x00
-#define DDR_CONFIG2_REG DDR_CTRL_BASE_REG + 0x04
-#define DDR_MODE_REG DDR_CTRL_BASE_REG + 0x08
-#define DDR_EXTENDED_MODE_REG DDR_CTRL_BASE_REG + 0x0C
-#define DDR_CONTROL_REG DDR_CTRL_BASE_REG + 0x10
-#define DDR_REFRESH_REG DDR_CTRL_BASE_REG + 0x14
-#define DDR_RD_DATA_THIS_CYCLE_REG DDR_CTRL_BASE_REG + 0x18
-#define DDR_TAP_CONTROL_0_REG DDR_CTRL_BASE_REG + 0x1C
-#define DDR_TAP_CONTROL_1_REG DDR_CTRL_BASE_REG + 0x20
-#define DDR_WB_FLUSH_GE0_REG DDR_CTRL_BASE_REG + 0x7C
-#define DDR_WB_FLUSH_GE1_REG DDR_CTRL_BASE_REG + 0x80
-#define DDR_WB_FLUSH_USB_REG DDR_CTRL_BASE_REG + 0x84
-#define DDR_DDR2_CONFIG_REG DDR_CTRL_BASE_REG + 0x8C
-#define DDR_EMR2_REG DDR_CTRL_BASE_REG + 0x90
-#define DDR_EMR3_REG DDR_CTRL_BASE_REG + 0x94
-#define DDR_BURST_REG DDR_CTRL_BASE_REG + 0x98
-
-/*
- * AHB
- */
-#define AHB_MASTER_TOUT_MAX_REG APB_BASE_REG + 0x9C
-#define AHB_MASTER_TOUT_CURRENT_REG APB_BASE_REG + 0xA0
-#define AHB_MASTER_TOUT_SLV_ADDR_REG APB_BASE_REG + 0xA4
-
-/*
- * UART registers
- */
-#define UART_DATA_REG UART_BASE_REG + 0x00
-#define UART_CS_REG UART_BASE_REG + 0x04
-#define UART_CLOCK_REG UART_BASE_REG + 0x08
-#define UART_INT_REG UART_BASE_REG + 0x0C
-#define UART_INT_EN_REG UART_BASE_REG + 0x10
-
-/*
- * UART registers _BIT fields
- */
-#define UART_CS_PAR_MODE_SHIFT 0
-#define UART_CS_PAR_MODE_MASK _BITS(UART_CS_PAR_MODE_SHIFT, 2)
-#define UART_CS_PAR_MODE_NO_VAL 0x0
-#define UART_CS_PAR_MODE_ODD_VAL 0x2
-#define UART_CS_PAR_MODE_OVEN_VAL 0x3
-
-#define UART_CS_IFACE_MODE_SHIFT 2
-#define UART_CS_IFACE_MODE_MASK _BITS(UART_CS_IFACE_MODE_SHIFT, 2)
-#define UART_CS_IFACE_MODE_DISABLE_VAL 0x0
-#define UART_CS_IFACE_MODE_DTE_VAL 0x1
-#define UART_CS_IFACE_MODE_DCE_VAL 0x2
-
-#define UART_CS_FLOW_MODE_SHIFT 4
-#define UART_CS_FLOW_MODE_MASK _BITS(UART_CS_FLOW_MODE_SHIFT, 2)
-#define UART_CS_FLOW_MODE_NO_VAL 0x0
-#define UART_CS_FLOW_MODE_HW_VAL 0x2
-#define UART_CS_FLOW_MODE_INV_VAL 0x3
-
-#define UART_CS_DMA_EN_SHIFT 6
-#define UART_CS_DMA_EN_MASK (1 << UART_CS_DMA_EN_SHIFT)
-#define UART_CS_RX_READY_ORIDE_SHIFT 7
-#define UART_CS_RX_READY_ORIDE_MASK (1 << UART_CS_RX_READY_ORIDE_SHIFT)
-#define UART_CS_TX_READY_ORIDE_SHIFT 8
-#define UART_CS_TX_READY_ORIDE_MASK (1 << UART_CS_TX_READY_ORIDE_SHIFT)
-#define UART_CS_TX_READY_SHIFT 9
-#define UART_CS_TX_READY_MASK (1 << UART_CS_TX_READY_SHIFT)
-#define UART_CS_RX_BREAK_SHIFT 10
-#define UART_CS_RX_BREAK_MASK (1 << UART_CS_RX_BREAK_SHIFT)
-#define UART_CS_TX_BREAK_SHIFT 11
-#define UART_CS_TX_BREAK_MASK (1 << UART_CS_TX_BREAK_SHIFT)
-#define UART_CS_HOST_INT_SHIFT 12
-#define UART_CS_HOST_INT_MASK (1 << UART_CS_HOST_INT_SHIFT)
-#define UART_CS_HOST_INT_EN_SHIFT 13
-#define UART_CS_HOST_INT_EN_MASK (1 << UART_CS_HOST_INT_EN_SHIFT)
-#define UART_CS_TX_BUSY_SHIFT 14
-#define UART_CS_TX_BUSY_MASK (1 << UART_CS_TX_BUSY_SHIFT)
-#define UART_CS_RX_BUSY_SHIFT 15
-#define UART_CS_RX_BUSY_MASK (1 << UART_CS_RX_BUSY_SHIFT)
-
-#define UART_RX_CSR_SHIFT 8
-#define UART_RX_CSR_MASK (1 << UART_RX_CSR_SHIFT)
-#define UART_TX_CSR_SHIFT 9
-#define UART_TX_CSR_MASK (1 << UART_TX_CSR_SHIFT)
-#define UART_TX_RX_DATA_SHIFT 0
-#define UART_TX_RX_DATA_MASK _BITS(UART_TX_RX_DATA_SHIFT, 8)
-#define UART_CLOCK_SCALE_SHIFT 16
-#define UART_CLOCK_SCALE_MASK _BITS(UART_CLOCK_SCALE_SHIFT, 8)
-#define UART_CLOCK_STEP_SHIFT 0
-#define UART_CLOCK_STEP_MASK _BITS(UART_CLOCK_STEP_SHIFT, 16)
-
-#define UART_CLOCK_SCALE_MAX_VAL 0xFF
-#define UART_CLOCK_STEP_MAX_VAL 0xFFFF
-
-/*
- * GPIO registers
- */
-#define GPIO_COUNT 30
-#define GPIO_OE_REG GPIO_BASE_REG + 0x00
-#define GPIO_IN_REG GPIO_BASE_REG + 0x04
-#define GPIO_OUT_REG GPIO_BASE_REG + 0x08
-#define GPIO_SET_REG GPIO_BASE_REG + 0x0C
-#define GPIO_CLEAR_REG GPIO_BASE_REG + 0x10
-#define GPIO_INT_ENABLE_REG GPIO_BASE_REG + 0x14
-#define GPIO_INT_TYPE_REG GPIO_BASE_REG + 0x18
-#define GPIO_INT_POLARITY_REG GPIO_BASE_REG + 0x1C
-#define GPIO_INT_PENDING_REG GPIO_BASE_REG + 0x20
-#define GPIO_INT_MASK_REG GPIO_BASE_REG + 0x24
-#define GPIO_FUNCTION_1_REG GPIO_BASE_REG + 0x28
-#define GPIO_IN_ETH_SWITCH_LED_REG GPIO_BASE_REG + 0x2C
-#define GPIO_FUNCTION_2_REG GPIO_BASE_REG + 0x30
-
-/*
- * GPIO registers _BIT fields
- */
-#define _GPIO_X_MASK(_gpio) (1 << _gpio)
-#define GPIO0 _GPIO_X_MASK(0)
-#define GPIO1 _GPIO_X_MASK(1)
-#define GPIO2 _GPIO_X_MASK(2)
-#define GPIO3 _GPIO_X_MASK(3)
-#define GPIO4 _GPIO_X_MASK(4)
-#define GPIO5 _GPIO_X_MASK(5)
-#define GPIO6 _GPIO_X_MASK(6)
-#define GPIO7 _GPIO_X_MASK(7)
-#define GPIO8 _GPIO_X_MASK(8)
-#define GPIO9 _GPIO_X_MASK(9)
-#define GPIO10 _GPIO_X_MASK(10)
-#define GPIO11 _GPIO_X_MASK(11)
-#define GPIO12 _GPIO_X_MASK(12)
-#define GPIO13 _GPIO_X_MASK(13)
-#define GPIO14 _GPIO_X_MASK(14)
-#define GPIO15 _GPIO_X_MASK(15)
-#define GPIO16 _GPIO_X_MASK(16)
-#define GPIO17 _GPIO_X_MASK(17)
-#define GPIO18 _GPIO_X_MASK(18)
-#define GPIO19 _GPIO_X_MASK(19)
-#define GPIO20 _GPIO_X_MASK(20)
-#define GPIO21 _GPIO_X_MASK(21)
-#define GPIO22 _GPIO_X_MASK(22)
-#define GPIO23 _GPIO_X_MASK(23)
-#define GPIO24 _GPIO_X_MASK(24)
-#define GPIO25 _GPIO_X_MASK(25)
-#define GPIO26 _GPIO_X_MASK(26)
-#define GPIO27 _GPIO_X_MASK(27)
-#define GPIO28 _GPIO_X_MASK(28)
-#define GPIO29 _GPIO_X_MASK(29)
-
-#define GPIO_FUNCTION_1_EJTAG_DIS_SHIFT 0
-#define GPIO_FUNCTION_1_EJTAG_DIS_MASK (1 << GPIO_FUNCTION_1_EJTAG_DIS_SHIFT)
-#define GPIO_FUNCTION_1_UART_EN_SHIFT 1
-#define GPIO_FUNCTION_1_UART_EN_MASK (1 << GPIO_FUNCTION_1_UART_EN_SHIFT)
-#define GPIO_FUNCTION_1_UART_RTS_CTS_EN_SHIFT 2
-#define GPIO_FUNCTION_1_UART_RTS_CTS_EN_MASK (1 << GPIO_FUNCTION_1_UART_RTS_CTS_EN_SHIFT)
-
-/*
- * PLL control registers
- */
-#define CPU_PLL_CONFIG_REG PLL_BASE_REG + 0x00
-#define CPU_PLL_CONFIG2_REG PLL_BASE_REG + 0x04
-#define CPU_CLOCK_CONTROL_REG PLL_BASE_REG + 0x08
-#define CPU_PLL_DITHER_FRAC_REG PLL_BASE_REG + 0x10
-#define CPU_PLL_DITHER_REG PLL_BASE_REG + 0x14
-#define ETHSW_CLOCK_CONTROL_REG PLL_BASE_REG + 0x24
-#define ETH_XMII_CONTROL_REG PLL_BASE_REG + 0x2C
-#define USB_SUSPEND_REG PLL_BASE_REG + 0x40
-#define WLAN_CLOCK_CONTROL_REG PLL_BASE_REG + 0x44
-#define CPU_PLL_CONTROL_2_REG RTC_BASE_REG + 0x3C
-
-/*
- * CPU PLL configuration (CPU_PLL_CONFIG) register _BIT fields
- */
-#define CPU_PLL_CONFIG_DIV_INT_SHIFT 10
-#define CPU_PLL_CONFIG_DIV_INT_MASK _BITS(CPU_PLL_CONFIG_DIV_INT_SHIFT, 6)
-#define CPU_PLL_CONFIG_REFDIV_SHIFT 16
-#define CPU_PLL_CONFIG_REFDIV_MASK _BITS(CPU_PLL_CONFIG_REFDIV_SHIFT, 5)
-#define CPU_PLL_CONFIG_RANGE_SHIFT 21
-#define CPU_PLL_CONFIG_RANGE_MASK (1 << CPU_PLL_CONFIG_RANGE_SHIFT)
-#define CPU_PLL_CONFIG_OUTDIV_SHIFT 23
-#define CPU_PLL_CONFIG_OUTDIV_MASK _BITS(CPU_PLL_CONFIG_OUTDIV_SHIFT, 3)
-#define CPU_PLL_CONFIG_CPU_PLLPWD_SHIFT 30
-#define CPU_PLL_CONFIG_CPU_PLLPWD_MASK (1 << CPU_PLL_CONFIG_CPU_PLLPWD_SHIFT)
-#define CPU_PLL_CONFIG_UPDATING_SHIFT 31
-#define CPU_PLL_CONFIG_UPDATING_MASK (1 << CPU_PLL_CONFIG_UPDATING_SHIFT)
-
-/*
- * Clock configuration (CPU_CLOCK_CONTROL) register _BIT fields
- */
-#define CPU_CLOCK_CONTROL_BYPASS_SHIFT 2
-#define CPU_CLOCK_CONTROL_BYPASS_MASK (1 << CPU_CLOCK_CONTROL_BYPASS_SHIFT)
-#define CPU_CLOCK_CONTROL_CPU_POST_DIV_SHIFT 5
-#define CPU_CLOCK_CONTROL_CPU_POST_DIV_MASK _BITS(CPU_CLOCK_CONTROL_CPU_POST_DIV_SHIFT, 2)
-#define CPU_CLOCK_CONTROL_DDR_POST_DIV_SHIFT 10
-#define CPU_CLOCK_CONTROL_DDR_POST_DIV_MASK _BITS(CPU_CLOCK_CONTROL_DDR_POST_DIV_SHIFT, 2)
-#define CPU_CLOCK_CONTROL_AHB_POST_DIV_SHIFT 15
-#define CPU_CLOCK_CONTROL_AHB_POST_DIV_MASK _BITS(CPU_CLOCK_CONTROL_AHB_POST_DIV_SHIFT, 2)
-
-/*
- * Helper macros for PLL and clock configuration
- */
-/*
- * TODO: remove them from board config file
-#define CPU_PLL_CONFIG_VAL(divint, refdiv, range, outdiv, pllpwd) \
- ( ((0x3F & divint) << 10) | \
- ((0x1F & refdiv) << 16) | \
- ((0x1 & range) << 21) | \
- ((0x7 & outdiv) << 23) | \
- ((0x1 & pllpwd) << 30) )
-
-#define CPU_CLOCK_CONTROL_VAL(bypass, cpudiv, ddrdiv, ahbdiv) \
- ( ((0x1 & bypass) << 2) | \
- ((0x3 & (cpudiv - 1)) << 5) | \
- ((0x3 & (ddrdiv - 1)) << 10) | \
- ((0x3 & (ahbdiv - 1)) << 15) )
-*/
-
-/*
- * Reset control registers
- */
-#define RESET_REG RESET_BASE_REG + 0x1C
-#define BOOTSTRAP_STATUS_REG RESET_BASE_REG + 0xAC
-#define USB_PHY_RESET_CONTROL_REG RESET_BASE_REG + 0xB0
-
-/*
- * Bootstrap (BOOT_STRAP) register _BIT fields
- */
-#define BOOTSTRAP_SEL_25_40M_SHIFT 0
-#define BOOTSTRAP_SEL_25_40M_MASK (1 << BOOTSTRAP_SEL_25_40M_SHIFT)
-#define BOOTSTRAP_BOOT_FROM_SPI_SHIFT 1
-#define BOOTSTRAP_BOOT_FROM_SPI_MASK (1 << BOOTSTRAP_BOOT_FROM_SPI_SHIFT)
-#define BOOTSTRAP_EEPBUSY_SHIFT 4
-#define BOOTSTRAP_EEPBUSY_MASK (1 << BOOTSTRAP_EEPBUSY_SHIFT)
-#define BOOTSTRAP_MEM_TYPE_SHIFT 12
-#define BOOTSTRAP_MEM_TYPE_MASK _BITS(BOOTSTRAP_MEM_TYPE_SHIFT, 2)
-
-/*
- * Memory type
- */
-#define BOOTSTRAP_MEM_TYPE_SDRAM_VAL 0x0
-#define BOOTSTRAP_MEM_TYPE_DDR1_VAL 0x1
-#define BOOTSTRAP_MEM_TYPE_DDR2_VAL 0x2
-
-/*
- * Reset (RST_RESET) register _BIT fields
- */
-#define RESET_I2S_RESET_SHIFT 0
-#define RESET_I2S_RESET_MASK (1 << RESET_I2S_RESET_SHIFT)
-#define RESET_MBOX_RESET_SHIFT 1
-#define RESET_MBOX_RESET_MASK (1 << RESET_MBOX_RESET_SHIFT)
-#define RESET_USB_SUSPEND_OVERRIDE_SHIFT 3
-#define RESET_USB_SUSPEND_OVERRIDE_MASK (1 << RESET_USB_SUSPEND_OVERRIDE_SHIFT)
-#define RESET_USB_PHY_RESET_SHIFT 4
-#define RESET_USB_PHY_RESET_MASK (1 << RESET_USB_PHY_RESET_SHIFT)
-#define RESET_USB_HOST_RESET_SHIFT 5
-#define RESET_USB_HOST_RESET_MASK (1 << RESET_USB_HOST_RESET_SHIFT)
-#define RESET_ETH_SWITCH_RESET_SHIFT 8
-#define RESET_ETH_SWITCH_RESET_MASK (1 << RESET_ETH_SWITCH_RESET_SHIFT)
-#define RESET_GE0_MAC_RESET_SHIFT 9
-#define RESET_GE0_MAC_RESET_MASK (1 << RESET_GE0_MAC_RESET_SHIFT)
-#define RESET_WLAN_RESET_SHIFT 11
-#define RESET_WLAN_RESET_MASK (1 << RESET_WLAN_RESET_SHIFT)
-#define RESET_GE1_MAC_RESET_SHIFT 13
-#define RESET_GE1_MAC_RESET_MASK (1 << RESET_GE1_MAC_RESET_SHIFT)
-#define RESET_SWITCH_ANALOG_RESET_SHIFT 14
-#define RESET_SWITCH_ANALOG_RESET_MASK (1 << RESET_SWITCH_ANALOG_RESET_SHIFT)
-#define RESET_DDR_RESET_SHIFT 16
-#define RESET_DDR_RESET_MASK (1 << RESET_DDR_RESET_SHIFT)
-#define RESET_CPU_COLD_RESET_SHIFT 20
-#define RESET_CPU_COLD_RESET_MASK (1 << RESET_CPU_COLD_RESET_SHIFT)
-#define RESET_CPU_NMI_SHIFT 21
-#define RESET_CPU_NMI_MASK (1 << RESET_CPU_NMI_SHIFT)
-#define RESET_GE0_MDIO_RESET_SHIFT 22
-#define RESET_GE0_MDIO_RESET_MASK (1 << RESET_GE0_MDIO_RESET_SHIFT)
-#define RESET_GE1_MDIO_RESET_SHIFT 23
-#define RESET_GE1_MDIO_RESET_MASK (1 << RESET_GE1_MDIO_RESET_SHIFT)
-#define RESET_FULL_CHIP_RESET_SHIFT 24
-#define RESET_FULL_CHIP_RESET_MASK (1 << RESET_FULL_CHIP_RESET_SHIFT)
-#define RESET_EXTERNAL_RESET_SHIFT 28
-#define RESET_EXTERNAL_RESET_MASK (1 << RESET_EXTERNAL_RESET_SHIFT)
-
-/*
- * RTC interface registers
- */
-#define RTC_RESET_REG RTC_BASE_REG + 0x40
-#define RTC_STATUS_REG RTC_BASE_REG + 0x44
-#define RTC_FORCE_DERIVED_REG RTC_BASE_REG + 0x48
-#define RTC_FORCE_WAKE_REG RTC_BASE_REG + 0x4C
-#define RTC_INT_CAUSE_REG RTC_BASE_REG + 0x50
-#define RTC_INT_CAUSE_CLEAR_REG RTC_BASE_REG + 0x50
-#define RTC_INT_ENABLE_REG RTC_BASE_REG + 0x54
-#define RTC_INT_MASK_REG RTC_BASE_REG + 0x58
-
-/*
- * RTC sleep status (RTC_STATUS) register _BIT fields
- */
-#define RTC_STATUS_SHUDOWN_SHIFT 0
-#define RTC_STATUS_SHUDOWN_MASK (1 << RTC_STATUS_SHUDOWN_SHIFT)
-#define RTC_STATUS_ON_SHIFT 1
-#define RTC_STATUS_ON_MASK (1 << RTC_STATUS_ON_SHIFT)
-#define RTC_STATUS_SLEEP_SHIFT 2
-#define RTC_STATUS_SLEEP_MASK (1 << RTC_STATUS_SLEEP_SHIFT)
-#define RTC_STATUS_WAKEUP_SHIFT 3
-#define RTC_STATUS_WAKEUP_MASK (1 << RTC_STATUS_WAKEUP_SHIFT)
-#define RTC_STATUS_COLD_RESET_SHIFT 4
-#define RTC_STATUS_COLD_RESET_MASK (1 << RTC_STATUS_COLD_RESET_SHIFT)
-#define RTC_STATUS_PLL_CHANGING_SHIFT 5
-#define RTC_STATUS_PLL_CHANGING_MASK (1 << RTC_STATUS_PLL_CHANGING_SHIFT)
-
-/*
- * SPI serial flash registers
- */
-#define SPI_FUNCTION_SELECT_REG FLASH_BASE_REG + 0x0
-#define SPI_CONTROL_REG FLASH_BASE_REG + 0x4
-#define SPI_IO_CONTROL_REG FLASH_BASE_REG + 0x8
-#define SPI_READ_DATA_REG FLASH_BASE_REG + 0xC
-
-#ifndef __ASSEMBLY__
-struct ar933x_spi_flash_regs {
- u32 function_select;
- u32 control;
- u32 io_control;
- u32 read_data;
-};
-
-struct ar933x_reset1_regs {
- u32 general_timer0;
- u32 general_timer0_reload;
- u32 watchdog_timer_control;
- u32 watchdog_timer;
- u32 misc_interrupt_mask;
- u32 global_interrupt_mask;
- u32 reset;
-};
-
-struct ar933x_reset2_regs {
- u32 revision_id;
- u32 general_timer1;
- u32 general_timer1_reload;
- u32 general_timer2;
- u32 general_timer2_reload;
- u32 general_timer3;
- u32 general_timer3_reload;
- u32 boot_strap;
- u32 usb_phy_reset_control;
-};
-
-extern const struct ar933x_spi_flash_regs *ar933x_spi_flash;
-extern const struct ar933x_reset1_regs *ar933x_reset1;
-extern const struct ar933x_reset2_regs *ar933x_reset2;
-
-extern int ar933x_40MHz_xtal(void);
-#endif /* !__ASSEMBLY__ */
-
-/*
- * Read, write, set and clear macros
- */
-#define ar933x_reg_read(_addr) *(volatile unsigned int *)(KSEG1ADDR(_addr))
-#define ar933x_reg_write(_addr, _val) ((*(volatile unsigned int *)KSEG1ADDR(_addr)) = (_val))
-
-#define ar933x_reg_read_set(_addr, _mask) \
- ar933x_reg_write((_addr), (ar933x_reg_read((_addr)) | (_mask)))
-
-#define ar933x_reg_read_clear(_addr, _mask) \
- ar933x_reg_write((_addr), (ar933x_reg_read((_addr)) & ~(_mask)))
-
-#endif /* _AR933X_H_ */
/*
* Macros to access the system control coprocessor
*/
+#define __read_32bit_c0_register(source, sel) \
+({ int __res; \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ "mfc0\t%0, " #source "\n\t" \
+ : "=r" (__res)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips32\n\t" \
+ "mfc0\t%0, " #source ", " #sel "\n\t" \
+ ".set\tmips0\n\t" \
+ : "=r" (__res)); \
+ __res; \
+})
+
#define read_32bit_cp0_register(source) \
({ int __res; \
__asm__ __volatile__( \
#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
+/*
+ * MIPS processor ID, based on:
+ * Linux/arch/mips/include/asm/cpu.h
+ */
+#define read_c0_prid() __read_32bit_c0_register($15, 0)
+#define PRID_IMP_MASK 0xFF00
+
+#define PRID_IMP_QEMU_GENERIC 0x0000
+#define PRID_IMP_4KC 0x8000
+#define PRID_IMP_5KC 0x8100
+#define PRID_IMP_20KC 0x8200
+#define PRID_IMP_4KEC 0x8400
+#define PRID_IMP_4KSC 0x8600
+#define PRID_IMP_25KF 0x8800
+#define PRID_IMP_5KE 0x8900
+#define PRID_IMP_4KECR2 0x9000
+#define PRID_IMP_4KEMPR2 0x9100
+#define PRID_IMP_4KSD 0x9200
+#define PRID_IMP_24K 0x9300
+#define PRID_IMP_34K 0x9500
+#define PRID_IMP_24KE 0x9600
+#define PRID_IMP_74K 0x9700
+#define PRID_IMP_1004K 0x9900
+#define PRID_IMP_1074K 0x9a00
+#define PRID_IMP_M14KC 0x9c00
+#define PRID_IMP_M14KEC 0x9e00
+#define PRID_IMP_INTERAPTIV_UP 0xa000
+#define PRID_IMP_INTERAPTIV_MP 0xa100
+#define PRID_IMP_PROAPTIV_UP 0xa200
+#define PRID_IMP_PROAPTIV_MP 0xa300
+#define PRID_IMP_M5150 0xa700
+#define PRID_IMP_P5600 0xa800
+
#endif /* _ASM_MIPSREGS_H */
--- /dev/null
+/*
+ * vim: tabstop=8 : noexpandtab
+ */
+
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ATHEROS_H
+#define _ATHEROS_H
+
+/*
+ * Set everything to zero. The corresponding header will
+ * undef and re-define the appropriate ones
+ */
+#define is_ar7100() (0)
+
+
+#define is_ar7240() (0)
+#define is_ar7241() (0)
+#define is_ar7242() (0)
+
+#define is_ar9330() (0)
+#define is_ar933x() (0)
+#define is_hornet() (0)
+
+#define is_ar934x() (0)
+#define is_wasp() (0)
+
+#define is_qca955x() (0)
+#define is_sco() (0)
+
+#define is_qca953x() (0)
+#define is_hb() (0)
+
+#define is_qca956x() (0)
+
+#define ATH_CONSOLE_BAUD 115200
+
+#define AR7240_REV_1_2 0xc2
+
+#ifdef CONFIG_ATH_EMULATION
+#define is_emu() (1)
+#else
+#define is_emu() (0)
+#endif
+
+#ifdef CONFIG_F1E_PHY
+#define is_f1e() 1
+#else
+#define is_f1e() 0
+#endif
+#ifdef CONFIG_F2E_PHY
+#define is_f2e() 1
+#else
+#define is_f2e() 0
+#endif
+#ifdef CONFIG_ATHRS16_PHY
+#define is_s16() 1
+#else
+#define is_s16() 0
+#endif
+
+#ifdef CONFIG_ATHRS17_PHY
+#define is_s17() 1
+#else
+#define is_s17() 0
+#endif
+
+#ifdef CONFIG_ATHR_8033_PHY
+#define is_ar8033() 1
+#else
+#define is_ar8033() 0
+#endif
+
+#ifdef CONFIG_VIR_PHY
+#define is_vir_phy() 1
+#else
+#define is_vir_phy() 0
+#endif
+
+#ifdef CFG_ATHRS27_PHY
+#define is_s27() 1
+#else
+#define is_s27() 0
+#endif
+
+#define ath_arch_init_irq() /* nothing */
+
+#ifndef __ASSEMBLY__
+
+int ath_uart_freq(void);
+
+typedef unsigned int ath_reg_t;
+
+#ifdef COMPRESSED_UBOOT
+# define prmsg(...)
+#else
+# define prmsg printf
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#define ath_reg_rd(_phys) (*(volatile ath_reg_t *)KSEG1ADDR(_phys))
+
+#define ath_reg_wr_nf(_phys, _val) \
+ ((*(volatile ath_reg_t *)KSEG1ADDR(_phys)) = (_val))
+
+#define ath_reg_wr(_phys, _val) do { \
+ ath_reg_wr_nf(_phys, _val); \
+ ath_reg_rd(_phys); \
+} while(0)
+
+#define ath_reg_rmw_set(_reg, _mask) do { \
+ ath_reg_wr((_reg), (ath_reg_rd((_reg)) | (_mask))); \
+ ath_reg_rd((_reg)); \
+} while(0)
+
+#define ath_reg_rmw_clear(_reg, _mask) do { \
+ ath_reg_wr((_reg), (ath_reg_rd((_reg)) & ~(_mask))); \
+ ath_reg_rd((_reg)); \
+} while(0)
+
+#define ath_uart_rd(y) ath_reg_rd((ATH_UART_BASE+y))
+#define ath_uart_wr(x, z) ath_reg_wr((ATH_UART_BASE+x), z)
+
+#define REG_OFFSET 4
+
+#define OFS_RCV_BUFFER (0 * REG_OFFSET)
+#define OFS_TRANS_HOLD (0 * REG_OFFSET)
+#define OFS_SEND_BUFFER (0 * REG_OFFSET)
+#define OFS_INTR_ENABLE (1 * REG_OFFSET)
+#define OFS_INTR_ID (2 * REG_OFFSET)
+#define OFS_DATA_FORMAT (3 * REG_OFFSET)
+#define OFS_LINE_CONTROL (3 * REG_OFFSET)
+#define OFS_MODEM_CONTROL (4 * REG_OFFSET)
+#define OFS_RS232_OUTPUT (4 * REG_OFFSET)
+#define OFS_LINE_STATUS (5 * REG_OFFSET)
+#define OFS_MODEM_STATUS (6 * REG_OFFSET)
+#define OFS_RS232_INPUT (6 * REG_OFFSET)
+#define OFS_SCRATCH_PAD (7 * REG_OFFSET)
+
+#define OFS_DIVISOR_LSB (0 * REG_OFFSET)
+#define OFS_DIVISOR_MSB (1 * REG_OFFSET)
+
+/*
+ * PLL Config for different CPU/DDR/AHB frequencies
+ */
+#define CFG_PLL_720_600_200 0x01
+#define CFG_PLL_720_680_240 0x02
+#define CFG_PLL_720_600_240 0x03
+#define CFG_PLL_680_680_226 0x04
+#define CFG_PLL_720_600_300 0x05
+#define CFG_PLL_400_400_200 0x06
+#define CFG_PLL_560_450_220 0x07
+#define CFG_PLL_550_400_200 0x08
+#define CFG_PLL_550_600_200 0x09
+#define CFG_PLL_600_600_200 0x0a
+#define CFG_PLL_750_400_250 0x0b
+#define CFG_PLL_800_400_266 0x0c
+#define CFG_PLL_750_667_250 0x0d
+#define CFG_PLL_800_600_266 0x0e
+#define CFG_PLL_800_667_266 0x0f
+#define CFG_PLL_810_700_270 0x10
+#define CFG_PLL_810_666_270 0x11
+#define CFG_PLL_775_650_258 0x12
+#define CFG_PLL_650_400_200 0x13
+#define CFG_PLL_650_600_200 0x14
+
+#define UBOOT_SIZE (256 * 1024)
+#define PLL_FLASH_ADDR (CFG_FLASH_BASE + UBOOT_SIZE)
+#define PLL_CONFIG_VAL_F (PLL_FLASH_ADDR + CFG_FLASH_SECTOR_SIZE - 0x20)
+#define PLL_MAGIC 0xaabbccdd
+#define SRIF_PLL_CONFIG_VAL_F (PLL_CONFIG_VAL_F - 12)
+#define SRIF_PLL_MAGIC 0x73726966 /* srif */
+
+#include <config.h>
+
+#if defined(CONFIG_MACH_AR724x)
+# include <724x.h>
+#elif defined(CONFIG_MACH_AR933x)
+# include <933x.h>
+#elif defined(CONFIG_MACH_AR934x)
+# include <934x.h>
+#elif defined(CONFIG_MACH_QCA955x)
+# include <955x.h>
+#elif defined(CONFIG_MACH_QCA953x)
+# include <953x.h>
+#elif defined(CONFIG_MACH_QCA956x)
+# include <956x.h>
+#else
+# error "Building U-Boot for unknown device"
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define ATH_MEM_SDRAM 1
+#define ATH_MEM_DDR1 2
+#define ATH_MEM_DDR2 3
+/*
+ * GPIO Access & Control
+ */
+void ath_gpio_init(void);
+void ath_gpio_down(void);
+void ath_gpio_up(void);
+
+void ath_gpio_irq_init(int);
+/*
+ * GPIO Helper Functions
+ */
+void ath_gpio_enable_slic(void);
+
+/* enable UART block, takes away GPIO 10 and 9 */
+void ath_gpio_enable_uart(void);
+
+/* enable STEREO block, takes away GPIO 11,8,7, and 6 */
+void ath_gpio_enable_stereo(void);
+
+/* allow CS0/CS1 to be controlled via SPI register, takes away GPIO0/GPIO1 */
+void ath_gpio_enable_spi_cs1_cs0(void);
+
+/* allow GPIO0/GPIO1 to be used as SCL/SDA for software based i2c */
+void ath_gpio_enable_i2c_on_gpio_0_1(void);
+
+/*
+ * GPIO General Functions
+ */
+void ath_gpio_drive_low(unsigned int mask);
+void ath_gpio_drive_high(unsigned int mask);
+
+unsigned int ath_gpio_float_high_test(unsigned int mask);
+
+/* Functions to access SPI through software. Example:
+ *
+ * ath_spi_down(); ---------------------- disable others from accessing SPI bus taking semaphore
+ * ath_spi_enable_soft_access(); -------- disable HW control of SPI
+ *
+ * <board specific chip select routine>
+ *
+ * <read/write SPI using using custom routine or general purposeflash routines
+ * Custom routine may use:
+ *
+ * ath_spi_raw_output_u8(unsigned char)
+ * ath_spi_raw_output_u32(unsigned int)
+ * ath_spi_raw_input_u32()
+ *
+ * General purpose flash routines:
+ * ath_spi_flash_read_page(unsigned int addr, unsigned char *data, int len);
+ * ath_spi_flash_write_page(unsigned int addr, unsigned char *data, int len);
+ * ath_spi_flash_sector_erase(unsigned int addr);
+ * >
+ *
+ * <board specific chip deselect routine>
+ *
+ * ath_spi_disable_soft_acess(); ------- enable HW control of SPI bus
+ * ath_spi_up(); ----------------------- enable others to access SPI bus releasing semaphore
+ */
+void ath_spi_init(void);
+void ath_spi_down(void);
+void ath_spi_up(void);
+
+static inline void
+ath_spi_enable_soft_access(void)
+{
+ ath_reg_wr_nf(ATH_SPI_FS, 1);
+}
+
+static inline void
+ath_spi_disable_soft_access(void)
+{
+ ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_DIS);
+ ath_reg_wr_nf(ATH_SPI_FS, 0);
+}
+
+void ath_spi_raw_output_u8(unsigned char val);
+void ath_spi_raw_output_u32(unsigned int val);
+unsigned int ath_spi_raw_input_u8(void);
+unsigned int ath_spi_raw_input_u32(void);
+
+void ath_spi_flash_read_page(unsigned int addr, unsigned char *data, int len);
+void ath_spi_flash_write_page(unsigned int addr, unsigned char *data, int len);
+void ath_spi_flash_sector_erase(unsigned int addr);
+
+/*
+ * Allow access to cs0-2 when GPIO Function enables cs0-2 through SPI register.
+ */
+static inline void
+ath_spi_enable_cs0(void)
+{
+ unsigned int cs;
+ ath_spi_down();
+ ath_spi_enable_soft_access();
+ cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS;
+ ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_0 | cs);
+}
+
+static inline void
+ath_spi_enable_cs1(void)
+{
+ unsigned int cs;
+#if defined(CONFIG_MACH_AR934x) || \
+ defined(CONFIG_MACH_QCA955x)
+ ath_spi_down();
+ ath_spi_init();
+ ath_spi_enable_soft_access();
+ cs = ath_reg_rd(ATH_SPI_WRITE) & ATH_SPI_CS_DIS;
+ ath_reg_wr_nf(ATH_SPI_WRITE, cs | ATH_SPI_CLK_HIGH);
+ cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS;
+ ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs | ATH_SPI_CLK_HIGH);
+ ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs);
+#else
+ ath_spi_down();
+ ath_spi_enable_soft_access();
+ cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS;
+ ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs);
+#endif
+}
+
+static inline void
+ath_spi_disable_cs(void)
+{
+ unsigned int cs = ath_reg_rd(ATH_SPI_WRITE) | ATH_SPI_CS_DIS;
+ ath_reg_wr_nf(ATH_SPI_WRITE, cs);
+ ath_spi_disable_soft_access();
+ ath_spi_up();
+}
+
+/*
+ * Example usage to access BOOT flash
+ */
+static inline void
+ath_spi_flash_cs0_sector_erase(unsigned int addr)
+{
+ ath_spi_enable_cs0();
+ ath_spi_flash_sector_erase(addr);
+ ath_spi_disable_cs();
+}
+
+static inline void
+ath_spi_flash_cs0_write_page(unsigned int addr, unsigned char *data, int len)
+{
+ ath_spi_enable_cs0();
+ ath_spi_flash_write_page(addr, data, len);
+ ath_spi_disable_cs();
+}
+
+#endif /* __ASSEMBLY__ */
+
+
+#endif /* _ATHEROS_H */
+++ /dev/null
-/*
- * This file is a modified version of bzlib.h from the bzip2-1.0.2
- * distribution which can be found at http://sources.redhat.com/bzip2/
- */
-
-/*-------------------------------------------------------------*/
-/*--- Public header file for the library. ---*/
-/*--- bzlib.h ---*/
-/*-------------------------------------------------------------*/
-
-/*--
- This file is a part of bzip2 and/or libbzip2, a program and
- library for lossless, block-sorting data compression.
-
- Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. The origin of this software must not be misrepresented; you must
- not claim that you wrote the original software. If you use this
- software in a product, an acknowledgment in the product
- documentation would be appreciated but is not required.
-
- 3. Altered source versions must be plainly marked as such, and must
- not be misrepresented as being the original software.
-
- 4. The name of the author may not be used to endorse or promote
- products derived from this software without specific prior written
- permission.
-
- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
- Julian Seward, Cambridge, UK.
- jseward@acm.org
- bzip2/libbzip2 version 1.0 of 21 March 2000
-
- This program is based on (at least) the work of:
- Mike Burrows
- David Wheeler
- Peter Fenwick
- Alistair Moffat
- Radford Neal
- Ian H. Witten
- Robert Sedgewick
- Jon L. Bentley
-
- For more information on these sources, see the manual.
---*/
-
-
-#ifndef _BZLIB_H
-#define _BZLIB_H
-
-/* Configure for U-Boot environment */
-#define BZ_NO_STDIO
-#define BZ_NO_COMPRESS
-/* End of configuration for U-Boot environment */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define BZ_RUN 0
-#define BZ_FLUSH 1
-#define BZ_FINISH 2
-
-#define BZ_OK 0
-#define BZ_RUN_OK 1
-#define BZ_FLUSH_OK 2
-#define BZ_FINISH_OK 3
-#define BZ_STREAM_END 4
-#define BZ_SEQUENCE_ERROR (-1)
-#define BZ_PARAM_ERROR (-2)
-#define BZ_MEM_ERROR (-3)
-#define BZ_DATA_ERROR (-4)
-#define BZ_DATA_ERROR_MAGIC (-5)
-#define BZ_IO_ERROR (-6)
-#define BZ_UNEXPECTED_EOF (-7)
-#define BZ_OUTBUFF_FULL (-8)
-#define BZ_CONFIG_ERROR (-9)
-
-typedef
- struct {
- char *next_in;
- unsigned int avail_in;
- unsigned int total_in_lo32;
- unsigned int total_in_hi32;
-
- char *next_out;
- unsigned int avail_out;
- unsigned int total_out_lo32;
- unsigned int total_out_hi32;
-
- void *state;
-
- void *(*bzalloc)(void *,int,int);
- void (*bzfree)(void *,void *);
- void *opaque;
- }
- bz_stream;
-
-
-#ifndef BZ_IMPORT
-#define BZ_EXPORT
-#endif
-
-#ifdef _WIN32
-# include <windows.h>
-# ifdef small
- /* windows.h define small to char */
-# undef small
-# endif
-# ifdef BZ_EXPORT
-# define BZ_API(func) WINAPI func
-# define BZ_EXTERN extern
-# else
- /* import windows dll dynamically */
-# define BZ_API(func) (WINAPI * func)
-# define BZ_EXTERN
-# endif
-#else
-# define BZ_API(func) func
-# define BZ_EXTERN extern
-#endif
-
-
-/*-- Core (low-level) library functions --*/
-
-BZ_EXTERN int BZ_API(BZ2_bzCompressInit) (
- bz_stream* strm,
- int blockSize100k,
- int verbosity,
- int workFactor
- );
-
-BZ_EXTERN int BZ_API(BZ2_bzCompress) (
- bz_stream* strm,
- int action
- );
-
-BZ_EXTERN int BZ_API(BZ2_bzCompressEnd) (
- bz_stream* strm
- );
-
-BZ_EXTERN int BZ_API(BZ2_bzDecompressInit) (
- bz_stream *strm,
- int verbosity,
- int small
- );
-
-BZ_EXTERN int BZ_API(BZ2_bzDecompress) (
- bz_stream* strm
- );
-
-BZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) (
- bz_stream *strm
- );
-
-
-/*-- High(er) level library functions --*/
-
-#ifndef BZ_NO_STDIO
-#define BZ_MAX_UNUSED 5000
-
-/* Need a definitition for FILE */
-#include <stdio.h>
-
-typedef void BZFILE;
-
-BZ_EXTERN BZFILE* BZ_API(BZ2_bzReadOpen) (
- int* bzerror,
- FILE* f,
- int verbosity,
- int small,
- void* unused,
- int nUnused
- );
-
-BZ_EXTERN void BZ_API(BZ2_bzReadClose) (
- int* bzerror,
- BZFILE* b
- );
-
-BZ_EXTERN void BZ_API(BZ2_bzReadGetUnused) (
- int* bzerror,
- BZFILE* b,
- void** unused,
- int* nUnused
- );
-
-BZ_EXTERN int BZ_API(BZ2_bzRead) (
- int* bzerror,
- BZFILE* b,
- void* buf,
- int len
- );
-
-BZ_EXTERN BZFILE* BZ_API(BZ2_bzWriteOpen) (
- int* bzerror,
- FILE* f,
- int blockSize100k,
- int verbosity,
- int workFactor
- );
-
-BZ_EXTERN void BZ_API(BZ2_bzWrite) (
- int* bzerror,
- BZFILE* b,
- void* buf,
- int len
- );
-
-BZ_EXTERN void BZ_API(BZ2_bzWriteClose) (
- int* bzerror,
- BZFILE* b,
- int abandon,
- unsigned int* nbytes_in,
- unsigned int* nbytes_out
- );
-
-BZ_EXTERN void BZ_API(BZ2_bzWriteClose64) (
- int* bzerror,
- BZFILE* b,
- int abandon,
- unsigned int* nbytes_in_lo32,
- unsigned int* nbytes_in_hi32,
- unsigned int* nbytes_out_lo32,
- unsigned int* nbytes_out_hi32
- );
-#endif
-
-
-/*-- Utility functions --*/
-
-BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffCompress) (
- char* dest,
- unsigned int* destLen,
- char* source,
- unsigned int sourceLen,
- int blockSize100k,
- int verbosity,
- int workFactor
- );
-
-BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffDecompress) (
- char* dest,
- unsigned int* destLen,
- char* source,
- unsigned int sourceLen,
- int small,
- int verbosity
- );
-
-
-/*--
- Code contributed by Yoshioka Tsuneo
- (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp),
- to support better zlib compatibility.
- This code is not _officially_ part of libbzip2 (yet);
- I haven't tested it, documented it, or considered the
- threading-safeness of it.
- If this code breaks, please contact both Yoshioka and me.
---*/
-
-BZ_EXTERN const char * BZ_API(BZ2_bzlibVersion) (
- void
- );
-
-#ifndef BZ_NO_STDIO
-BZ_EXTERN BZFILE * BZ_API(BZ2_bzopen) (
- const char *path,
- const char *mode
- );
-
-BZ_EXTERN BZFILE * BZ_API(BZ2_bzdopen) (
- int fd,
- const char *mode
- );
-
-BZ_EXTERN int BZ_API(BZ2_bzread) (
- BZFILE* b,
- void* buf,
- int len
- );
-
-BZ_EXTERN int BZ_API(BZ2_bzwrite) (
- BZFILE* b,
- void* buf,
- int len
- );
-
-BZ_EXTERN int BZ_API(BZ2_bzflush) (
- BZFILE* b
- );
-
-BZ_EXTERN void BZ_API(BZ2_bzclose) (
- BZFILE* b
- );
-
-BZ_EXTERN const char * BZ_API(BZ2_bzerror) (
- BZFILE *b,
- int *errnum
- );
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/*-------------------------------------------------------------*/
-/*--- end bzlib.h ---*/
-/*-------------------------------------------------------------*/
--- /dev/null
+/*
+ * Commands related with PLL/clocks settings
+ * for Qualcomm/Atheros WiSoCs
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _CMD_QCACLK_H_
+#define _CMD_QCACLK_H_
+
+#include <soc/qca_soc_common.h>
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #include <soc/ar933x_pll_init.h>
+#else
+ #include <soc/qca95xx_pll_init.h>
+#endif
+
+#ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET
+
+ #ifndef CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET
+ #error "Missing definition for CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET"
+ #endif
+
+ #ifndef CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE
+ #error "Missing definition for CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE"
+ #endif
+
+ #if (SOC_TYPE & QCA_AR933X_SOC)
+typedef struct {
+ u32 cpu_pll_cfg;
+ u32 cpu_clk_ctrl;
+ u32 cpu_pll_dit;
+} pll_regs;
+ #else
+typedef struct {
+ u32 cpu_pll_cfg;
+ u32 ddr_pll_cfg;
+ u32 cpu_ddr_clk_ctrl;
+ u32 cpu_pll_dit;
+ u32 ddr_pll_dit;
+} pll_regs;
+ #endif /* SOC_TYPE & QCA_AR933X_SOC */
+
+typedef struct {
+ u32 spi_ctrl;
+ pll_regs regs;
+} clk_cfg_flash;
+
+/*
+ * Contains:
+ * 1. CPU, RAM, AHB and SPI clocks [MHz]
+ * 2. Target SPI_CONTROL register value
+ * 3. Target PLL related register values,
+ * for 25 and 40 MHz XTAL types
+ */
+typedef struct {
+ u16 cpu_clk;
+ u16 ddr_clk;
+ u16 ahb_clk;
+ u8 spi_clk;
+
+ u32 spi_ctrl;
+
+ pll_regs xtal_25mhz;
+ pll_regs xtal_40mhz;
+} clk_profile;
+
+static const clk_profile clk_profiles[] = {
+ #if (SOC_TYPE & QCA_AR933X_SOC)
+ {
+ /* Tested! */
+ 100, 100, 50, 12,
+ _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(10, 1, 1, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 100, 100, 100, 25,
+ _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 150, 150, 150, 25,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 160, 160, 80, 20,
+ _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(615)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(16, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 200, 200, 100, 25,
+ _ar933x_spi_ctrl_addr_reg_val(4, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 200, 200, 200, 25,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 300, 300, 150, 25,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 350, 350, 175, 29,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(17, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
+ },
+ },
+ {
+ /* Tested! */
+ 400, 400, 200, 25,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 410, 410, 205, 25,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(820)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
+ },
+ },
+ {
+ /* Tested! */
+ 420, 420, 210, 26,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(33, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(615)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 430, 430, 215, 26,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(34, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(410)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
+ },
+ },
+ {
+ /* Tested! */
+ 440, 440, 220, 27,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(35, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(205)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(22, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 450, 450, 225, 28,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(45, 2, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 460, 460, 230, 28,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(820)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 470, 470, 235, 29,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(37, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(615)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
+ },
+ },
+ {
+ /* Tested! */
+ 480, 480, 240, 30,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(38, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(410)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 490, 490, 245, 30,
+ _ar933x_spi_ctrl_addr_reg_val(8, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(39, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(205)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
+ },
+ },
+ {
+ /* Tested! */
+ 500, 500, 250, 25,
+ _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 510, 510, 255, 25,
+ _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(820)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
+ },
+ },
+ {
+ /* Tested! */
+ 520, 520, 260, 26,
+ _ar933x_spi_ctrl_addr_reg_val(10, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(41, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(615)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 530, 265, 132, 22,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(42, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(410)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
+ },
+ },
+ {
+ /* Tested! */
+ 540, 270, 135, 22,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(43, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(205)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 550, 275, 137, 22,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
+ },
+ },
+ {
+ /* Tested! */
+ 560, 280, 140, 23,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(820)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ {
+ /* Tested! */
+ 570, 285, 142, 23,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(45, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(615)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(512)
+ },
+ },
+ {
+ /* Tested! */
+ 580, 290, 145, 24,
+ _ar933x_spi_ctrl_addr_reg_val(6, 1, 0),
+ {
+ _ar933x_cpu_pll_cfg_reg_val(46, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(410)
+ }, {
+ _ar933x_cpu_pll_cfg_reg_val(29, 1, 0, 1),
+ _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4),
+ _ar933x_cpu_pll_dither_frac_reg_val(0)
+ },
+ },
+ #else
+ {
+ /* Tested! */
+ 100, 100, 100, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(28, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(35, 2, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 125, 100, 100, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(16),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 150, 150, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 150, 150, 150, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 160, 160, 80, 10,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(26, 1, 0, 1, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 0, 1, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 170, 170, 85, 10,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(34, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(34, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 5, 10, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(17, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(17, 1, 0, 1, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 180, 180, 90, 11,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 1, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 200, 200, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 200, 200, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 200, 200, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 300, 200, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 300, 200, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 300, 200, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 300, 300, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 300, 300, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 300, 300, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 350, 350, 175, 21,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(14, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(35, 4, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(35, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 360, 360, 180, 22,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 380, 380, 190, 23,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(13),
+ _qca95xx_ddr_pll_dither_reg_val(205)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(19, 1, 0, 1, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 1, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 400, 200, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 400, 200, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 400, 200, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 400, 300, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 400, 300, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 400, 300, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 400, 300, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 400, 400, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 400, 400, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 200, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 200, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 200, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 300, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 300, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 300, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 300, 250, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 300, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 400, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 400, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 400, 250, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 500, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 500, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 500, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 500, 250, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 500, 500, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 550, 200, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 550, 200, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 550, 200, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 550, 300, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 550, 300, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 550, 300, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 550, 300, 275, 27,
+ _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 550, 300, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 550, 375, 250, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(30, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 550, 400, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 560, 450, 225, 28,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(26),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 200, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 200, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 200, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 300, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 300, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 300, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 300, 250, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 300, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 400, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 400, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 400, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 400, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 450, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 450, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 450, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 450, 225, 28,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 450, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 500, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 500, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 500, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 500, 250, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 500, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 550, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 550, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 550, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 550, 275, 27,
+ _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 550, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 600, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 600, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 600, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 600, 250, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 600, 600, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 200, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 200, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 200, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 300, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 300, 150, 18,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 300, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 300, 300, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 400, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 400, 155, 19,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 400, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 400, 310, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 500, 100, 12,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 500, 155, 19,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 500, 166, 20,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 500, 206, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 500, 250, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 620, 500, 310, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(52),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 650, 400, 200, 25,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(16),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 650, 420, 210, 26,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(820)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(42, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(16),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ }, {
+ /* Tested! */
+ 650, 450, 225, 28,
+ _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2),
+ {
+ _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(0),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ }, {
+ _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0),
+ _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0),
+ _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1),
+ _qca95xx_cpu_pll_dither_reg_val(16),
+ _qca95xx_ddr_pll_dither_reg_val(0)
+ },
+ },
+ #endif /* SOC_TYPE & QCA_AR933X_SOC */
+};
+
+/* Number of all profiles */
+static u32 clk_profiles_cnt = sizeof(clk_profiles) / sizeof(clk_profile);
+
+#endif /* CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET */
+
+#endif /* _CMD_QCACLK_H_ */
void hang(void) __attribute__ ((noreturn));
/* */
-long int initdram(void);
-void print_size(ulong, const char *);
+long int dram_init(void);
+int timer_init(void);
+void full_reset(void);
+void all_led_on(void);
+void all_led_off(void);
+void print_size(ulong, const char *);
+void print_board_info(void);
+void macaddr_init(unsigned char *);
+void flash_print_name(void);
+void cpu_name(char *name);
+unsigned int main_cpu_clk(void);
/* common/main.c */
void main_loop (void);
* Only TP-Link OFW and OpenWrt for TP-Link routers
* use different (simply) image header
*/
-#if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) && \
- !defined(CONFIG_FOR_DLINK_DIR505_A1) && \
- !defined(CONFIG_FOR_DRAGINO_V2) && \
- !defined(CONFIG_FOR_MESH_POTATO_V2)
+#ifdef CONFIG_TPLINK_IMAGE_HEADER
#include "tpLinuxTag.h"
-#endif
-
-/* common/cmd_bootm.c */
-#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || \
- defined(CONFIG_FOR_DLINK_DIR505_A1) || \
- defined(CONFIG_FOR_DRAGINO_V2) || \
- defined(CONFIG_FOR_MESH_POTATO_V2)
-void print_image_hdr(image_header_t *hdr);
-#else
void print_image_hdr(tplink_image_header_t *hdr);
-#endif
+#else
+void print_image_hdr(image_header_t *hdr);
+#endif /* CONFIG_TPLINK_IMAGE_HEADER */
extern ulong load_addr; /* Default Load Address */
/* lib_$(ARCH)/time.c */
void udelay (unsigned long);
+#define milisecdelay(_x) udelay((_x) * 1000)
ulong usec2ticks (unsigned long usec);
ulong ticks2usec (unsigned long ticks);
int init_timebase (void);
int sprintf(char * buf, const char *fmt, ...);
int vsprintf(char *buf, const char *fmt, va_list args);
-/* lib_generic/crc32.c */
-ulong crc32 (ulong, const unsigned char *, uint);
-ulong crc32_no_comp (ulong, const unsigned char *, uint);
-
/* common/console.c */
int console_init_f(void); /* Before relocation; uses the serial stuff */
int console_init_r(void); /* After relocation; uses the console stuff */
#include <configs/ar7240.h>
#include <config.h>
+#include <soc/soc_common.h>
+
+/*
+ * GPIO configuration
+ */
+#if defined(CONFIG_FOR_TPLINK_WR703N_V1) ||\
+ defined(CONFIG_FOR_TPLINK_WR710N_V1)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO GPIO27
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS GPIO11
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
+
+#elif defined(CONFIG_FOR_TPLINK_MR10U_V1)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO GPIO27
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS GPIO11
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
+
+#elif defined(CONFIG_FOR_TPLINK_WR720N_V3)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO GPIO27
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO11 | GPIO18 | GPIO20)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
+
+#elif defined(CONFIG_FOR_TPLINK_MR13U_V1)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO GPIO27
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO6 | GPIO7 | GPIO11)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
+
+#elif defined(CONFIG_FOR_DLINK_DIR505_A1)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO26 | GPIO27)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ #define CONFIG_QCA_GPIO_MASK_INPUTS GPIO11
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+
+#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO GPIO27
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ #define CONFIG_QCA_GPIO_MASK_INPUTS GPIO11
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+
+#elif defined(CONFIG_FOR_TPLINK_MR3020_V1)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI GPIO0
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO17 | GPIO26 | GPIO27)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO |\
+ CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI |\
+ GPIO8)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO11 | GPIO18 | GPIO20)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
+
+#elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO17 | GPIO26 | GPIO27)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS GPIO11
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO18)
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
+
+#elif defined(CONFIG_FOR_TPLINK_WR740N_V4)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI (GPIO0 | GPIO1 | GPIO13 | GPIO14 | GPIO15 | GPIO16)
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO17 | GPIO27)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO |\
+ CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO11 | GPIO26)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
+
+#elif defined(CONFIG_FOR_TPLINK_MR3220_V2)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI (GPIO0 | GPIO1 | GPIO13 | GPIO14 | GPIO15 | GPIO16 | GPIO26)
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO17 | GPIO27)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO |\
+ CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI |\
+ GPIO8)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO11)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO8)
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
+
+#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO13 | GPIO15 | GPIO17 | GPIO27)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO11)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+
+#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI (GPIO13 | GPIO14)
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO GPIO0
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO |\
+ CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS GPIO11
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
+
+#elif defined(CONFIG_FOR_DRAGINO_V2) ||\
+ defined(CONFIG_FOR_MESH_POTATO_V2)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI (GPIO0 | GPIO28)
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO13 | GPIO17)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO |\
+ CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS GPIO11
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
+
+#elif defined(CONFIG_FOR_GL_INET)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI (GPIO0 | GPIO13)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
+ #define CONFIG_QCA_GPIO_MASK_INPUTS GPIO11
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_LO CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_HI
+
+#endif
/*
* FLASH and environment organization
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(ART)"
+#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
+
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),64k(u-boot-env),16128k(firmware),64k(ART)"
+
#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(ART)"
defined(CONFIG_FOR_MESH_POTATO_V2)
#define CFG_LOAD_ADDR 0x9F040000
#define UPDATE_SCRIPT_FW_ADDR "0x9F040000"
+#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
+ #define CFG_LOAD_ADDR 0x9F030000
+ #define UPDATE_SCRIPT_FW_ADDR "0x9F030000"
#else
#define CFG_LOAD_ADDR 0x9F020000
#define UPDATE_SCRIPT_FW_ADDR "0x9F020000"
#elif defined(CONFIG_FOR_DRAGINO_V2) || \
defined(CONFIG_FOR_MESH_POTATO_V2)
#define CONFIG_BOOTCOMMAND "bootm 0x9F040000"
+#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
+ #define CONFIG_BOOTCOMMAND "bootm 0x9F030000"
#else
#define CONFIG_BOOTCOMMAND "bootm 0x9F020000"
#endif
#define CFG_PROMPT "dr_boot> "
#endif
-#undef CFG_HZ
-#define CFG_HZ bd->bi_cfg_hz
-#undef CPU_PLL_CONFIG_VAL
-#undef CPU_CLK_CONTROL_VAL
-
-// CPU-RAM-AHB frequency setting
-#ifndef CFG_PLL_FREQ
- #define CFG_PLL_FREQ CFG_PLL_400_400_200
+#if defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
+ #if defined(CFG_PROMPT)
+ #undef CFG_PROMPT
+ #endif
+ #define CFG_PROMPT "BSB> "
#endif
/*
- * CPU_PLL_DITHER_FRAC_VAL
- *
- * Value written into CPU PLL Dither FRAC Register (PLL_DITHER_FRAC)
- *
- * bits 0..9 NFRAC_MAX => 1000 (0x3E8)
- * bits 10..13 NFRAC_MIN => 0 (minimum value is used)
- * bits 20..29 NFRAC_STEP => 1
- *
- */
-#define CPU_PLL_DITHER_FRAC_VAL 0x001003E8
-
-/*
- * CPU_PLL_SETTLE_TIME_VAL
- *
- * Value written into CPU Phase Lock Loop Configuration Register 2 (CPU_PLL_CONFIG2)
- *
- * bits 0..11 SETTLE_TIME => 850 (0x352)
- *
+ * PLL/Clocks configuration
*/
-#if CONFIG_40MHZ_XTAL_SUPPORT
- #define CPU_PLL_SETTLE_TIME_VAL 0x00000550
-#else
- #define CPU_PLL_SETTLE_TIME_VAL 0x00000352
+#ifdef CFG_HZ
+ #undef CFG_HZ
#endif
+#define CFG_HZ bd->bi_cfg_hz
-/*
- * CPU_CLK_CONTROL_VAL
- *
- * In CPU_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
- * After PLL configuration we nedd to clear this bit
- *
- * Values written into CPU Clock Control Register CLOCK_CONTROL
- *
- * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test purposes. Software must enable the CPU PLL for normal operation and then set this bit to 0)
- * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1)
- * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1)
- * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2)
- *
- */
-
-/*
- * CPU_PLL_CONFIG_VAL
- *
- * In CPU_PLL_CONFIG_VAL bit 30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
- * After PLL configuration we need to clear this bit
- *
- * Values written into CPU Phase Lock Loop Configuration (CPU_PLL_CONFIG)
- *
- * bits 10..15 (6bit) DIV_INT (The integer part of the DIV to CPU PLL) => 32 (0x20)
- * bits 16..20 (5bit) REFDIV (Reference clock divider) => 1 (0x1) [doesn't start at values different than 1 (maybe need to change other dividers?)]
- * bits 21 (1bit) RANGE (Determine the VCO frequency range of the CPU PLL) => 0 (0x0) [doesn't have impact on clock values]
- * bits 23..25 (3bit) OUTDIV (Define the ratio between VCO output and PLL output => 1 (0x1) [value == 0 is illegal!]
- * VCOOUT * (1/2^OUTDIV) = PLLOUT)
- */
+#define CONFIG_QCA_PLL QCA_PLL_PRESET_400_400_200
-/*
- * = PLL CALCULATION =============
- * PLL = ((25 MHz / REFDIV) * DIV_INT) / (2 ^ OUTDIV) // XTAL=25 MHz
- * OR
- * PLL = ((40 MHz / REFDIV) * DIV_INT) / (2 ^ OUTDIV) // XTAL=40 MHz
- *
- * CPU = PLL / CPU_POST_DIV
- * DDR = PLL / DDR_POST_DIV
- * AHB = PLL / AHB_POST_DIV
- *
- */
/*
- * AR7240_SPI_CONTROL
- *
- * Value written into SPI Control (SPI_CONTROL) register
- *
- * bits 0..5 (6bit) CLOCK_DIVIDER (Specifies the clock divider setting. Actual clock frequency would be (AHB_CLK / ((CLOCK_DIVIDER+1)*2)) )
- * bits 6 (1bit) REMAP_DISABLE (Remaps 4 MB space over unless explicitly disabled by setting this bit to 1. If set to 1, 16 MB is accessible.)
- *
+ * For PLL/clocks recovery use reset button by default
*/
-
-/*
- * CPU_PLL_CONFIG and CPU_CLK_CONTROL registers values generator
- */
-#define MAKE_AR9331_CPU_PLL_CONFIG_VAL(divint, refdiv, range, outdiv) ( ((0x3F & divint) << 10) | \
- ((0x1F & refdiv) << 16) | \
- ((0x1 & range) << 21) | \
- ((0x7 & outdiv) << 23) )
-
-#define MAKE_AR9331_CPU_CLK_CONTROL_VAL(cpudiv, ddrdiv, ahbdiv) ( ((0x3 & (cpudiv - 1)) << 5) | \
- ((0x3 & (ddrdiv - 1)) << 10) | \
- ((0x3 & (ahbdiv - 1)) << 15) )
-
-#define MAKE_AR9331_SPI_CONTROL_VAL(spidiv) ( ((spidiv >> 1) - 1) | 0x40 )
-
-/*
- * Default values (400/400/200 MHz) for O/C recovery mode
- */
-
-// CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
-#define CPU_CLK_CONTROL_VAL_DEFAULT MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
-#if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 20 (40 MHz * 20/2 = 400 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL_DEFAULT MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
-#else
- // DIV_INT = 32 (25 MHz * 32/2 = 400 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL_DEFAULT MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 1)
+#ifdef CONFIG_GPIO_RESET_BTN
+ #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN CONFIG_GPIO_RESET_BTN
#endif
-// CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
-#define AR7240_SPI_CONTROL_DEFAULT MAKE_AR9331_SPI_CONTROL_VAL(6)
-
-#if (CFG_PLL_FREQ == CFG_PLL_200_200_100)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 20 (40 MHz * 20/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 2)
- #else
- // DIV_INT = 32 (25 MHz * 32/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 2)
- #endif
-
- // CLOCK_DIVIDER = 1 (SPI clock = 100 / 4 ~ 25 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
-
- #define CFG_HZ_FALLBACK (200000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_200_200_200)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 1
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 20 (40 MHz * 20/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 2)
- #else
- // DIV_INT = 32 (25 MHz * 32/4 = 200 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(32, 1, 0, 2)
- #endif
-
- // CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
-
- #define CFG_HZ_FALLBACK (200000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_225_225_112)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- #define FREQUENCY_NOT_SUPPORTED
- #else
- // DIV_INT = 36 (25 MHz * 36/4 = 225 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 2)
- #endif
-
- // CLOCK_DIVIDER = 1 (SPI clock = 112 / 4 ~ 28 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
-
- #define CFG_HZ_FALLBACK (225000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_225_225_225)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 1
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- #define FREQUENCY_NOT_SUPPORTED
- #else
- // DIV_INT = 36 (25 MHz * 36/4 = 225 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 2)
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 225 / 8 ~ 28 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (225000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_250_250_125)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 25 (40 MHz * 25/4 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 2)
- #else
- // DIV_INT = 20 (25 MHz * 20/2 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 1 (SPI clock = 125 / 4 ~ 31 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
-
- #define CFG_HZ_FALLBACK (250000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_250_250_250)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 1
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 1)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 25 (40 MHz * 25/4 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 2
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 2)
- #else
- // DIV_INT = 20 (25 MHz * 20/2 = 250 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(20, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (250000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 15 (40 MHz * 15/2 = 300 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(15, 1, 0, 1)
- #else
- // DIV_INT = 24 (25 MHz * 24/2 = 300 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(24, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 2 (SPI clock = 150 / 6 ~ 25 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
-
- #define CFG_HZ_FALLBACK (300000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_325_325_162)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- #define FREQUENCY_NOT_SUPPORTED
- #else
- // DIV_INT = 26 (25 MHz * 26/2 = 325 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(26, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 2 (SPI clock = 162 / 6 ~ 27 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
-
- #define CFG_HZ_FALLBACK (325000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_350_350_175)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- #define FREQUENCY_NOT_SUPPORTED
- #else
- // DIV_INT = 28 (25 MHz * 28/2 = 350 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(28, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 2 (SPI clock = 175 / 6 ~ 29 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
-
- #define CFG_HZ_FALLBACK (350000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_360_360_180)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 18 (40 MHz * 18/2 = 360 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(18, 1, 0, 1)
- #else
- // DIV_INT = 29 (25 MHz * 28/2 = 362 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(29, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 2 (SPI clock = 180 / 6 ~ 30 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
-
- #define CFG_HZ_FALLBACK (360000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_380_380_190)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 19 (40 MHz * 19/2 = 380 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(19, 1, 0, 1)
- #else
- #define FREQUENCY_NOT_SUPPORTED
- #endif
-
- // CLOCK_DIVIDER = 2 (SPI clock = 190 / 6 ~ 32 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
-
- #define CFG_HZ_FALLBACK (380000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_400_400_200)
-
- // default configuration
- #define CPU_CLK_CONTROL_VAL CPU_CLK_CONTROL_VAL_DEFAULT
- #define CPU_PLL_CONFIG_VAL CPU_PLL_CONFIG_VAL_DEFAULT
- #define AR7240_SPI_CONTROL AR7240_SPI_CONTROL_DEFAULT
-
- #define CFG_HZ_FALLBACK (400000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_412_412_206)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- #define FREQUENCY_NOT_SUPPORTED
- #else
- // DIV_INT = 33 (25 MHz * 33/2 = 412 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(33, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 2 (SPI clock = 206 / 6 ~ 34 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
-
- #define CFG_HZ_FALLBACK (412000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_420_420_210)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 21 (40 MHz * 21/2 = 420 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(21, 1, 0, 1)
- #else
- #define FREQUENCY_NOT_SUPPORTED
- #endif
-
- // CLOCK_DIVIDER = 2 (SPI clock = 210 / 6 ~ 35 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
-
- #define CFG_HZ_FALLBACK (420000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_425_425_212)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- #define FREQUENCY_NOT_SUPPORTED
- #else
- // DIV_INT = 34 (25 MHz * 34/2 = 425 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(34, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 2 (SPI clock = 212 / 6 ~ 35 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
-
- #define CFG_HZ_FALLBACK (425000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_437_437_218)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- #define FREQUENCY_NOT_SUPPORTED
- #else
- // DIV_INT = 35 (25 MHz * 35/2 = 437 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(35, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 218 / 8 ~ 27 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (437000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_440_440_220)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 22 (40 MHz * 22/2 = 440 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(22, 1, 0, 1)
- #else
- #define FREQUENCY_NOT_SUPPORTED
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 220 / 8 ~ 27 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (440000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_450_450_225)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- #define FREQUENCY_NOT_SUPPORTED
- #else
- // DIV_INT = 36 (25 MHz * 36/2 = 450 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(36, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 225 / 8 ~ 28 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (450000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_460_460_230)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 23 (40 MHz * 23/2 = 460 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(23, 1, 0, 1)
- #else
- // DIV_INT = 37 (25 MHz * 36/2 = 462 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(37, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 230 / 8 ~ 29 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (460000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_475_475_237)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- #define FREQUENCY_NOT_SUPPORTED
- #else
- // DIV_INT = 38 (25 MHz * 38/2 = 475 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(38, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 237 / 8 ~ 30 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (475000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_480_480_240)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 24 (40 MHz * 24/2 = 480 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(24, 1, 0, 1)
- #else
- #define FREQUENCY_NOT_SUPPORTED
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 240 / 8 ~ 30 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (480000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_487_487_243)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- #define FREQUENCY_NOT_SUPPORTED
- #else
- // DIV_INT = 39 (25 MHz * 39/2 = 487 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(39, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 243 / 8 ~ 30 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (487000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_500_500_250)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 25 (40 MHz * 25/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 1)
- #else
- // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(40, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (500000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_500_250_250)
-
- // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 25 (40 MHz * 25/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(25, 1, 0, 1)
- #else
- // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(40, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (500000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_520_520_260)
-
- // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 1, 2)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 26 (40 MHz * 26/2 = 520 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(26, 1, 0, 1)
- #else
- #define FREQUENCY_NOT_SUPPORTED
- #endif
-
- // CLOCK_DIVIDER = 3 (SPI clock = 260 / 8 ~ 32 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(8)
-
- #define CFG_HZ_FALLBACK (520000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_525_262_131)
-
- // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- #define FREQUENCY_NOT_SUPPORTED
- #else
- // DIV_INT = 42 (25 MHz * 42/2 = 525 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(42, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 1 (SPI clock = 131 / 4 ~ 33 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
-
- #define CFG_HZ_FALLBACK (525000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_560_280_140)
-
- // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 28 (40 MHz * 28/2 = 560 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(28, 1, 0, 1)
- #else
- // DIV_INT = 45 (25 MHz * 45/2 = 562 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(45, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 1 (SPI clock = 140 / 4 ~ 35 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
-
- #define CFG_HZ_FALLBACK (560000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_580_290_145)
-
- // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 4)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 29 (40 MHz * 29/2 = 580 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(29, 1, 0, 1)
- #else
- #define FREQUENCY_NOT_SUPPORTED
- #endif
-
- // CLOCK_DIVIDER = 1 (SPI clock = 145 / 4 ~ 36 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(4)
-
- #define CFG_HZ_FALLBACK (580000000LU/2)
-
-#elif (CFG_PLL_FREQ == CFG_PLL_600_300_200)
-
- // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 3
- #define CPU_CLK_CONTROL_VAL MAKE_AR9331_CPU_CLK_CONTROL_VAL(1, 2, 3)
-
- #if CONFIG_40MHZ_XTAL_SUPPORT
- // DIV_INT = 30 (40 MHz * 30/2 = 600 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(30, 1, 0, 1)
- #else
- // DIV_INT = 48 (25 MHz * 48/2 = 600 MHz), REFDIV = 1, RANGE = 0, OUTDIV = 1
- #define CPU_PLL_CONFIG_VAL MAKE_AR9331_CPU_PLL_CONFIG_VAL(48, 1, 0, 1)
- #endif
-
- // CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz)
- #define AR7240_SPI_CONTROL MAKE_AR9331_SPI_CONTROL_VAL(6)
-
- #define CFG_HZ_FALLBACK (600000000LU/2)
-
-#elif defined(CFG_PLL_FREQ)
- #error Unknown frequency setting!
-#endif
-
-/*
- * Check if clocks configuration is valid
- */
-#ifdef FREQUENCY_NOT_SUPPORTED
- #error Selected frequency setting is not supported with your reference clock!
+#ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW
+ #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW 1
#endif
/*
#define CFG_ENV_ADDR 0x9F040000
#define CFG_ENV_SIZE 0x8000
#define CFG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
+ #define CFG_ENV_ADDR 0x9F020000
+ #define CFG_ENV_SIZE 0x8000
+ #define CFG_ENV_SECT_SIZE 0x10000
#else
#define CFG_ENV_ADDR 0x9F01EC00
#define CFG_ENV_SIZE 0x1000
#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || \
defined(CONFIG_FOR_DRAGINO_V2) || \
- defined(CONFIG_FOR_MESH_POTATO_V2)
+ defined(CONFIG_FOR_MESH_POTATO_V2) || \
+ defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
#define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
CFG_CMD_DHCP | \
#define CONFIG_NETCONSOLE
#define CONFIG_NETCONSOLE_PORT 6666
-/* DDR init values */
-#if CONFIG_40MHZ_XTAL_SUPPORT
- #define CFG_DDR_REFRESH_VAL 0x4270
-#else
- #define CFG_DDR_REFRESH_VAL 0x4186
-#endif
-
-#define CFG_DDR_CONFIG_VAL 0x7fbc8cd0
-#define CFG_DDR_MODE_VAL_INIT 0x133
-
-#ifdef LOW_DRIVE_STRENGTH
- #define CFG_DDR_EXT_MODE_VAL 0x2
-#else
- #define CFG_DDR_EXT_MODE_VAL 0x0
-#endif
-
-#define CFG_DDR_MODE_VAL 0x33
-#define CFG_DDR_TRTW_VAL 0x1f
-#define CFG_DDR_TWTR_VAL 0x1e
-
-//#define CFG_DDR_CONFIG2_VAL 0x99d0e6a8 // HORNET 1.0
-#define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8 // HORNET 1.1
-#define CFG_DDR_RD_DATA_THIS_CYCLE_VAL 0x00ff
-#define CFG_DDR_TAP0_VAL 0x8
-#define CFG_DDR_TAP1_VAL 0x9
-
-/* DDR2 Init values */
-#define CFG_DDR2_EXT_MODE_VAL 0x402
-
#define CONFIG_NET_MULTI
/* choose eth1 first for tftpboot interface added by ZJin, 110328 */
defined(CONFIG_FOR_MESH_POTATO_V2)
#define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x30000"
#define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES
+#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
+ #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x20000"
+ #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES
#else
// TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
#define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x1EC00"
#elif defined(CONFIG_FOR_DRAGINO_V2) || \
defined(CONFIG_FOR_MESH_POTATO_V2)
#define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x40000
+#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
+ #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x30000
#else
#define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
#endif
#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
// GS-Oolite v1: 128k(U-Boot + MAC),64k(ART)
#define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
+#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
+ // Black Swift board: 128k(U-Boot),64k(U-Boot env),64k(ART)
+ #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (256 * 1024)
#else
// TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
#define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
#define CFG_BOOTM_LEN (16 << 20) /* 16 MB */
#undef DEBUG
-#define milisecdelay(_x) udelay((_x) * 1000)
/* MAC address, model and PIN number offsets in FLASH */
#if defined(CONFIG_FOR_DLINK_DIR505_A1)
#define OFFSET_MAC_DATA_BLOCK 0x010000
#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
#define OFFSET_MAC_ADDRESS 0x00FC00
+#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
+ // Black Swift board has only one MAC address at the beginning of ART partition
+ #define OFFSET_MAC_DATA_BLOCK 0xFF0000
+ #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
+ #define OFFSET_MAC_ADDRESS 0x000000
#else
#define OFFSET_MAC_DATA_BLOCK 0x010000
#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
!defined(CONFIG_FOR_GS_OOLITE_V1_DEV) && \
!defined(CONFIG_FOR_DRAGINO_V2) && \
!defined(CONFIG_FOR_MESH_POTATO_V2) && \
- !defined(CONFIG_FOR_GL_INET)
+ !defined(CONFIG_FOR_GL_INET) && \
+ !defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
#define OFFSET_ROUTER_MODEL 0x00FD00
#endif
/*
* PLL and clocks configurations from FLASH
- *
- * We need space for 4x 32-bit variables:
- * - PLL_MAGIC_VARIABLE
- * - values of registers:
- * - CPU_PLL_CONFIG (page 70 in datasheet)
- * - CLOCK_CONTROL (page 71)
- * - SPI_CONTROL (page 261)
*/
-#if defined(CONFIG_FOR_DLINK_DIR505_A1)
+#if defined(CONFIG_FOR_DLINK_DIR505_A1) || \
+ defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
/*
+ * For DIR505 A1:
* We will store PLL and CLOCK registers
* configuration at the end of MAC data
* partition (3rd 64 KiB block)
+ * ----
+ * For Black Swift board:
+ * We will store PLL and CLOCK registers
+ * configuration at the end of environment
+ * sector (64 KB, environment uses only part!)
*/
- #define PLL_IN_FLASH_MAGIC 0x504C4C73
- #define PLL_IN_FLASH_DATA_BLOCK_OFFSET 0x00020000
- #define PLL_IN_FLASH_DATA_BLOCK_LENGTH 0x00010000
- #define PLL_IN_FLASH_MAGIC_OFFSET 0x0000FFF0 // last 16 bytes
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00020000
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000
+
#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
/*
* We will store PLL and CLOCK registers
* configuration at the end of environment
* sector (64 KB, environment uses only half!)
*/
- #define PLL_IN_FLASH_MAGIC 0x504C4C73
- #define PLL_IN_FLASH_DATA_BLOCK_OFFSET 0x00040000
- #define PLL_IN_FLASH_DATA_BLOCK_LENGTH 0x00010000
- #define PLL_IN_FLASH_MAGIC_OFFSET 0x0000FFF0 // last 16 bytes
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00040000
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000
+
#elif defined(CONFIG_FOR_DRAGINO_V2) || \
defined(CONFIG_FOR_MESH_POTATO_V2)
/*
* configuration at the end of environment
* sector (64 KB, environment uses only half!)
*/
- #define PLL_IN_FLASH_MAGIC 0x504C4C73
- #define PLL_IN_FLASH_DATA_BLOCK_OFFSET 0x00030000
- #define PLL_IN_FLASH_DATA_BLOCK_LENGTH 0x00010000
- #define PLL_IN_FLASH_MAGIC_OFFSET 0x0000FFF0 // last 16 bytes
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00030000
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000
+
#else
/*
* All TP-Link routers have a lot of unused space
* We will store there PLL and CLOCK
* registers configuration.
*/
- #define PLL_IN_FLASH_MAGIC 0x504C4C73
- #define PLL_IN_FLASH_DATA_BLOCK_OFFSET 0x00010000
- #define PLL_IN_FLASH_DATA_BLOCK_LENGTH 0x00010000
- #define PLL_IN_FLASH_MAGIC_OFFSET 0x0000FFF0 // last 16 bytes
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00010000
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000
+
+#endif
+
+#if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
+ /* Use last 32 bytes */
+ #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET (CFG_FLASH_BASE + \
+ CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
+ 0x0000FFE0)
#endif
#include <cmd_confdefs.h>
--- /dev/null
+/*
+ * This file contains the configuration parameters for the DB12x (AR9344) board.
+ */
+
+#ifndef _AP143_CONFIG_H
+#define _AP143_CONFIG_H
+
+#include <config.h>
+#include <soc/soc_common.h>
+
+/*
+ * GPIO configuration
+ */
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO GPIO13
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ #define CONFIG_QCA_GPIO_MASK_INPUTS GPIO12
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+
+#elif defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO3 | GPIO4 | GPIO11 | GPIO13 |\
+ GPIO14 | GPIO15 | GPIO16)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO12 | GPIO17)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#ifndef CONFIG_BOOTDELAY
+ #define CONFIG_BOOTDELAY 1
+#endif
+
+#define CFG_LONGHELP
+
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 600, 1200, 2400, 4800, 9600, 14400, \
+ 19200, 28800, 38400, 56000, 57600, 115200 }
+
+#define CFG_ALT_MEMTEST
+#define CFG_HUSH_PARSER
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size, was: def + 16 */
+#define CFG_MAXARGS 16 /* max number of command */
+#define CFG_MALLOC_LEN 512*1024 /* def: 128*1024 */
+#define CFG_BOOTPARAMS_LEN 512*1024 /* def: 128 */
+#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
+#define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x200000) /* RAM test start = CFG_SDRAM_BASE + 2 MB */
+#define CFG_MEMTEST_END (CFG_SDRAM_BASE + bd->bi_memsize - 0x200001) /* RAM test end = CFG_SDRAM_BASE + RAM size - 2 MB - 1 Byte */
+#define CFG_RX_ETH_BUFFER 16
+
+#if defined(CONFIG_SILENT_CONSOLE)
+ #define SILENT_ENV_VARIABLE "silent=1\0"
+#else
+ #define SILENT_ENV_VARIABLE ""
+#endif
+
+#define CFG_DCACHE_SIZE 32768
+#define CFG_ICACHE_SIZE 65536
+#define CFG_CACHELINE_SIZE 32
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash
+#define CFG_FLASH_SECTOR_SIZE 64 * 1024
+
+/*
+ * We boot from this flash
+ */
+#define CFG_FLASH_BASE 0x9F000000
+#ifdef COMPRESSED_UBOOT
+ #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE
+ #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE
+#endif
+
+/*
+ * The following #defines are needed to get flash environment right
+ */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (192 << 10)
+
+/*
+ * Default bootargs
+ */
+#undef CONFIG_BOOTARGS
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN)
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)"
+#elif defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N)
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
+#endif
+
+/*
+ * Other env default values
+ */
+#undef CONFIG_BOOTFILE
+#define CONFIG_BOOTFILE "firmware.bin"
+
+#undef CONFIG_LOADADDR
+#define CONFIG_LOADADDR 0x80800000
+
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ #define CFG_LOAD_ADDR 0x9F020000
+ #define UPDATE_SCRIPT_FW_ADDR "0x9F020000"
+ #define CONFIG_BOOTCOMMAND "bootm 0x9F020000"
+#endif
+
+#define CONFIG_IPADDR 192.168.1.1
+#define CONFIG_SERVERIP 192.168.1.2
+
+/*
+ * PLL/Clocks configuration
+ */
+#ifdef CFG_HZ
+ #undef CFG_HZ
+#endif
+#define CFG_HZ bd->bi_cfg_hz
+
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ #define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200
+#endif
+
+/*
+ * For PLL/clocks recovery use reset button by default
+ */
+#ifdef CONFIG_GPIO_RESET_BTN
+ #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN CONFIG_GPIO_RESET_BTN
+#endif
+
+#ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW
+ #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW 1
+#endif
+
+/*
+ * Address and size of Primary Environment Sector
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#undef CFG_ENV_IS_NOWHERE
+
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ #define CFG_ENV_ADDR 0x9F01EC00
+ #define CFG_ENV_SIZE 0x1000
+ #define CFG_ENV_SECT_SIZE 0x10000
+#endif
+
+/*
+ * Available commands
+ */
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_PING | \
+ CFG_CMD_FLASH | \
+ CFG_CMD_NET | \
+ CFG_CMD_RUN | \
+ CFG_CMD_DATE | \
+ CFG_CMD_SNTP | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_BOOTD | \
+ CFG_CMD_ITEST | \
+ CFG_CMD_ENV | \
+ CFG_CMD_LOADB)
+#endif
+
+// Enable NetConsole and custom NetConsole port
+#define CONFIG_NETCONSOLE
+#define CONFIG_NETCONSOLE_PORT 6666
+
+/*
+ * Web Failsafe configuration
+ */
+#define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR
+#define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE
+
+// Firmware partition offset
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
+#endif
+
+// U-Boot partition size
+#define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
+
+// TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x1EC00"
+ #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "0x20000"
+#endif
+
+// ART partition size
+#define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024)
+
+// max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
+// TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
+#endif
+
+// progress state info
+#define WEBFAILSAFE_PROGRESS_START 0
+#define WEBFAILSAFE_PROGRESS_TIMEOUT 1
+#define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2
+#define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3
+#define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4
+
+// update type
+#define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0
+#define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1
+#define WEBFAILSAFE_UPGRADE_TYPE_ART 2
+
+/*-----------------------------------------------------------------------*/
+
+/*
+ * Additional environment variables for simple upgrades
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS "uboot_addr=0x9F000000\0" \
+ "uboot_name=uboot.bin\0" \
+ "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
+ "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \
+ "uboot_upg=" \
+ "if ping $serverip; then " \
+ "mw.b $loadaddr 0xFF $uboot_backup_size && " \
+ "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \
+ "tftp $loadaddr $uboot_name && " \
+ "if itest.l $filesize <= $uboot_size; then " \
+ "erase $uboot_addr +$uboot_backup_size && " \
+ "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \
+ "echo OK!; " \
+ "else " \
+ "echo ERROR! Wrong file size!; " \
+ "fi; " \
+ "else " \
+ "echo ERROR! Server not reachable!; " \
+ "fi\0" \
+ SILENT_ENV_VARIABLE
+
+/*
+ * Cache lock for stack
+ */
+#define CFG_INIT_SP_OFFSET 0x1000
+#define CONFIG_INIT_SRAM_SP_OFFSET 0xbd001800
+
+/* For Merlin, both PCI, PCI-E interfaces are valid */
+#define ATH_ART_PCICFG_OFFSET 12
+/* use eth1(LAN) as the net interface */
+#define CONFIG_AG7240_SPEPHY
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI 1
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ #define WLANCAL 0x9fff1000
+ #define BOARDCAL 0x9fff0000
+#endif
+#define CFG_MII0_RMII 1
+#define CFG_BOOTM_LEN (16 << 20) /* 16 MB */
+
+#undef DEBUG
+
+/* MAC address, model and PIN number offsets in FLASH */
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ #define OFFSET_MAC_DATA_BLOCK 0x010000
+ #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
+ #define OFFSET_MAC_ADDRESS 0x00FC00
+ #define OFFSET_ROUTER_MODEL 0x00FD00
+ #define OFFSET_PIN_NUMBER 0x00FE00
+#endif
+
+/*
+ * PLL and clocks configurations from FLASH
+ */
+#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ /*
+ * All TP-Link routers have a lot of unused space
+ * in FLASH, in second 64 KiB block.
+ * We will store there PLL and CLOCK
+ * registers configuration.
+ */
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00010000
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000
+
+#endif
+
+#if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
+ /* Use last 32 bytes */
+ #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET (CFG_FLASH_BASE + \
+ CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
+ 0x0000FFE0)
+#endif
+
+#include <cmd_confdefs.h>
+
+#endif /* __AP143_CONFIG_H */
#define SILENT_ENV_VARIABLE ""
#endif
-/*
- ** PLL Config for different CPU/DDR/AHB frequencies
- */
-#define CFG_PLL_200_200_100 1
-#define CFG_PLL_200_200_200 2
-#define CFG_PLL_225_225_112 3
-#define CFG_PLL_225_225_225 4
-#define CFG_PLL_250_250_125 5
-#define CFG_PLL_250_250_250 6
-#define CFG_PLL_300_300_150 7
-#define CFG_PLL_325_325_162 8
-#define CFG_PLL_350_350_175 9
-#define CFG_PLL_360_360_180 10
-#define CFG_PLL_380_380_190 11
-#define CFG_PLL_400_400_200 12
-#define CFG_PLL_412_412_206 13
-#define CFG_PLL_420_420_210 14
-#define CFG_PLL_425_425_212 15
-#define CFG_PLL_437_437_218 16
-#define CFG_PLL_440_440_220 17
-#define CFG_PLL_450_450_225 18
-#define CFG_PLL_460_460_230 19
-#define CFG_PLL_475_475_237 20
-#define CFG_PLL_480_480_240 21
-#define CFG_PLL_487_487_243 22
-#define CFG_PLL_500_500_250 23
-#define CFG_PLL_500_250_250 24
-#define CFG_PLL_520_520_260 25
-#define CFG_PLL_525_262_131 26
-#define CFG_PLL_560_280_140 27
-#define CFG_PLL_580_290_145 28
-#define CFG_PLL_600_300_200 29
-
-// WASP
-#define CFG_PLL_566_400_200 101
-#define CFG_PLL_566_500_250 102
-#define CFG_PLL_600_1_2G_400_200 103
-#define CFG_PLL_560_480_240 104
-#define CFG_PLL_533_400_200 105
-
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#include <configs/ar7240.h>
#include <config.h>
+#include <soc/soc_common.h>
+
+/*
+ * GPIO configuration
+ */
+#if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO11 | GPIO12 | GPIO13 | GPIO14 | GPIO15)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO21 | GPIO22)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO16 | GPIO17)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO21 | GPIO22)
+
+#elif defined(CONFIG_FOR_TPLINK_WDR3500_V1)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO11 | GPIO13 | GPIO14 | GPIO15 | GPIO18 |\
+ GPIO19 | GPIO20 | GPIO21 | GPIO22)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO12)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO16 | GPIO17)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO12)
+
+#elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO11 | GPIO12 | GPIO13 | GPIO14 | GPIO15 |\
+ GPIO18 | GPIO19 | GPIO20 | GPIO21)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO4)
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO16 | GPIO17)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO4)
+
+#elif defined(CONFIG_FOR_TPLINK_WR841N_V8)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO12 | GPIO13 | GPIO14 | GPIO15 | GPIO18 |\
+ GPIO19 | GPIO20 | GPIO21)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO16 | GPIO17)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+
+#elif defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
+ /* LEDs */
+ #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO (GPIO13 | GPIO14 | GPIO15 | GPIO18)
+
+ /* Outputs, inputs */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+ #define CONFIG_QCA_GPIO_MASK_INPUTS (GPIO16 | GPIO17)
+
+ /* Initial states */
+ #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
+
+#endif
/*
* FLASH and environment organization
#define CONFIG_IPADDR 192.168.1.1
#define CONFIG_SERVERIP 192.168.1.2
-#undef CFG_PLL_FREQ
-#undef CFG_HZ
+/*
+ * PLL/Clocks configuration
+ */
+#ifdef CFG_HZ
+ #undef CFG_HZ
+#endif
+#define CFG_HZ bd->bi_cfg_hz
-// CPU-RAM-AHB frequency setting
-#if !defined(CONFIG_AP123)
-#define CFG_PLL_FREQ CFG_PLL_560_480_240
-#define CFG_HZ_FALLBACK (560000000LU/2)
-#else
-#define CFG_PLL_FREQ CFG_PLL_533_400_200
-#define CFG_HZ_FALLBACK (535000000LU/2)
+/* For now, use some safe clocks for all AR934x */
+#define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200
+
+
+/*
+ * For PLL/clocks recovery use reset button by default
+ */
+#ifdef CONFIG_GPIO_RESET_BTN
+ #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN CONFIG_GPIO_RESET_BTN
+#endif
+
+#ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW
+ #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW 1
#endif
-#define CFG_HZ bd->bi_cfg_hz
-#define AR7240_SPI_CONTROL 0x43
-#define AR7240_SPI_CONTROL_DEFAULT AR7240_SPI_CONTROL
/*
* MIPS32 24K Processor Core Family Software User's Manual
*
/*
* Cache lock for stack
*/
-#define CFG_INIT_SP_OFFSET 0x1000
+#define CFG_INIT_SP_OFFSET 0x1000
+#define CONFIG_INIT_SRAM_SP_OFFSET 0xbd007000
/*
* Address and size of Primary Environment Sector
#define CONFIG_NETCONSOLE
#define CONFIG_NETCONSOLE_PORT 6666
-/* DDR settings for WASP */
-#define CFG_DDR_REFRESH_VAL 0x4270
-#define CFG_DDR_CONFIG_VAL 0xc7bc8cd0
-#define CFG_DDR_MODE_VAL_INIT 0x133
-#define CFG_DDR_EXT_MODE_VAL 0x0
-#define CFG_DDR_MODE_VAL 0x33
-#define CFG_DDR_TRTW_VAL 0x1f
-#define CFG_DDR_TWTR_VAL 0x1e
-#define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8
-
-#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff
-#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff
-
-#if DDR2_32BIT_SUPPORT
- #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32
-#else
- #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16
-#endif
-
-#define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL 0xffff
-#define CFG_SDRAM_RD_DATA_THIS_CYCLE_VAL 0xffffffff
-
-/* DDR2 Init values */
-#define CFG_DDR2_EXT_MODE_VAL 0x402
-
#define CONFIG_NET_MULTI
#ifdef CFG_ATHRS27_PHY
#define CFG_BOOTM_LEN (16 << 20) /* 16 MB */
#undef DEBUG
-#define milisecdelay(_x) udelay((_x) * 1000)
/* MAC address, model and PIN number offsets in FLASH */
#define OFFSET_MAC_DATA_BLOCK 0x010000
#define OFFSET_ROUTER_MODEL 0x00FD00
#define OFFSET_PIN_NUMBER 0x00FE00
+/*
+ * PLL and clocks configurations from FLASH
+ */
+#if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) || \
+ defined(CONFIG_FOR_TPLINK_WDR3500_V1) || \
+ defined(CONFIG_FOR_TPLINK_MR3420_V2) || \
+ defined(CONFIG_FOR_TPLINK_WR841N_V8) || \
+ defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
+ /*
+ * All TP-Link routers have a lot of unused space
+ * in FLASH, in second 64 KiB block.
+ * We will store there PLL and CLOCK
+ * registers configuration.
+ */
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00010000
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000
+
+#endif
+
+#if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
+ /* Use last 32 bytes */
+ #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET (CFG_FLASH_BASE + \
+ CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
+ 0x0000FFE0)
+#endif
+
#include <cmd_confdefs.h>
#endif /* __CONFIG_H */
/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2005 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:GPL-2.0
*/
#ifndef _FLASH_H_
#define _FLASH_H_
#ifndef CFG_NO_FLASH
-/*-----------------------------------------------------------------------
- * FLASH Info: contains chip specific data, per FLASH bank
- */
+/*
+ * Struct for info about FLASH chip/bank, with:
+ * - manufacturer and model names
+ * - JEDEC ID (combined device & manufacturer code)
+ * - total bank size in bytes
+ * - size of erase unit in bytes
+ * - bank number
+ * - size of program page in bytes
+ * - number of erase units
+ * - erase command
+ * - physical sector start addresses
+ */
typedef struct {
- ulong size; /* total bank size in bytes */
- ulong sector_size; /* size of erase unit in bytes */
- ushort sector_count; /* number of erase units */
- ulong flash_id; /* combined device & manufacturer code */
- ulong start[CFG_MAX_FLASH_SECT]; /* physical sector start addresses */
+ char *manuf_name;
+ char *model_name;
+ u32 flash_id;
+ u32 size;
+ u32 sector_size;
+ u32 bank;
+ u16 page_size;
+ u16 sector_count;
+ u8 erase_cmd;
+ u32 start[CFG_MAX_FLASH_SECT];
} flash_info_t;
+extern flash_info_t flash_info[];
+
+/*
+ * Struct for info about supported SPI NOR FLASH chips, with:
+ * - model names
+ * - JEDEC ID (combined device & manufacturer code)
+ * - total size in bytes
+ * - size of erase unit in bytes
+ * - size of program page in bytes
+ * - erase command
+ */
+typedef struct {
+ char *model_name;
+ u32 flash_id;
+ u32 size;
+ u32 sector_size;
+ u16 page_size;
+ u8 erase_cmd;
+} spi_nor_ids_info_t;
+
+extern const spi_nor_ids_info_t spi_nor_ids[];
+extern const u32 spi_nor_ids_count;
/* Prototypes */
-extern unsigned long flash_init (void);
-extern int flash_erase(flash_info_t *, int, int);
+u32 flash_init(void);
+u32 flash_erase(flash_info_t *info, u32 s_first, u32 s_last);
+const char *flash_manuf_name(u32 jedec_id);
+
extern int flash_sect_erase(ulong addr_first, ulong addr_last);
/* common/flash.c */
extern int flash_write(char *, ulong, ulong);
extern flash_info_t *addr2info(ulong);
-extern int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+extern u32 write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt);
-/*-----------------------------------------------------------------------
- * return codes from flash_write():
- */
-#define ERR_OK 0
-#define ERR_TIMOUT 1
-#define ERR_NOT_ERASED 2
-#define ERR_PROTECTED 4
-#define ERR_INVAL 8
-#define ERR_ALIGN 16
-#define ERR_UNKNOWN_FLASH_VENDOR 32
-#define ERR_UNKNOWN_FLASH_TYPE 64
-#define ERR_PROG_ERROR 128
-
-/*-----------------------------------------------------------------------
- * Device IDs
- */
-#define FLASH_CUSTOM 0x1111
-#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
+/* Useful size */
+#define SIZE_4KiB 4 * 1024
+#define SIZE_64KiB 64 * 1024
+
+#define SIZE_4MiB 4 * 1024 * 1024
+#define SIZE_8MiB 8 * 1024 * 1024
+#define SIZE_16MiB 16 * 1024 * 1024
+#define SIZE_32MiB 32 * 1024 * 1024
+#define SIZE_64MiB 64 * 1024 * 1024
+
+/* Return codes from flash_write(): */
+#define ERR_OK 0
+#define ERR_TIMOUT 1
+#define ERR_NOT_ERASED 2
+#define ERR_PROTECTED 4
+#define ERR_INVAL 8
+#define ERR_ALIGN 16
+#define ERR_UNKNOWN_FLASH_VENDOR 32
+#define ERR_UNKNOWN_FLASH_TYPE 64
+#define ERR_PROG_ERROR 128
+
+/* FLASH vendors IDs */
+#define FLASH_VENDOR_JEDEC_ATMEL 0x1F
+#define FLASH_VENDOR_JEDEC_EON 0x1C
+#define FLASH_VENDOR_JEDEC_MACRONIX 0xC2
+#define FLASH_VENDOR_JEDEC_MICRON 0x20
+#define FLASH_VENDOR_JEDEC_SPANSION 0x01
+#define FLASH_VENDOR_JEDEC_WINBOND 0xEF
+
+/* Device IDs */
+#define FLASH_UNKNOWN 0xFFFFFF
+#define FLASH_CUSTOM 0x111111
+
+/* Basic SPI FLASH commands */
+#define SPI_FLASH_CMD_WRSR 0x01
+#define SPI_FLASH_CMD_PP 0x02
+#define SPI_FLASH_CMD_READ 0x03
+#define SPI_FLASH_CMD_WRDI 0x04
+#define SPI_FLASH_CMD_RDSR 0x05
+#define SPI_FLASH_CMD_WREN 0x06
+
+/* SPI FLASH erase related commands */
+#define SPI_FLASH_CMD_ES_4KB 0x20
+#define SPI_FLASH_CMD_ES_32KB 0x52
+#define SPI_FLASH_CMD_ES_64KB 0xD8
+#define SPI_FLASH_CMD_ES_ALL 0xC7
+
+/* Other SPI FLASH commands */
+#define SPI_FLASH_CMD_JEDEC 0x9F
+#define SPI_FLASH_CMD_SFDP 0x5A
+
+/* SFDP related defines */
+#define SPI_FLASH_SFDP_SIGN 0x50444653
#endif /* !CFG_NO_FLASH */
#ifndef _LINUX_BITOPS_H
#define _LINUX_BITOPS_H
+/*
+ * Helper macros
+ */
+#define BIT(_x) (1 << (_x))
+#define BITS(_start, _bits) (((1 << (_bits)) - 1) << _start)
+#define CHECK_BIT(_var, _pos) ((_var) & (1 << (_pos)))
+#ifndef __ASSEMBLY__
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
-
static inline int generic_ffs(int x)
{
int r = 1;
* hweightN: returns the hamming weight (i.e. the number
* of bits set) of a N-bit word
*/
-
static inline unsigned int generic_hweight32(unsigned int w)
{
unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555);
#include <asm/bitops.h>
+#endif /* !__ASSEMBLY__ */
#endif
--- /dev/null
+/*
+ * Helper defines and macros related with
+ * PLL and clocks configurations for
+ * Qualcomm/Atheros AR933x WiSoC
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _AR933X_PLL_INIT_H_
+#define _AR933X_PLL_INIT_H_
+
+#include <soc/qca_soc_common.h>
+
+/* CPU_PLL_CONFIG */
+#define _ar933x_cpu_pll_cfg_reg_val(_nint, \
+ _refdiv, \
+ _range, \
+ _outdiv) \
+ \
+ ((_nint << QCA_PLL_CPU_PLL_CFG_NINT_SHIFT) & QCA_PLL_CPU_PLL_CFG_NINT_MASK) |\
+ ((_refdiv << QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK) |\
+ ((_range << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT) & QCA_PLL_CPU_PLL_CFG_RANGE_MASK) |\
+ ((_outdiv << QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK)
+
+/* CPU_CLOCK_CONTROL */
+#define _ar933x_cpu_clk_ctrl_reg_val(_cpudiv, \
+ _ddrdiv, \
+ _ahbdiv) \
+ \
+ (((_cpudiv - 1) << QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT) &\
+ QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK) |\
+ (((_ddrdiv - 1) << QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT) &\
+ QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK) |\
+ (((_ahbdiv - 1) << QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT) &\
+ QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK)
+
+/* PLL_DITHER_FRAC */
+#define _ar933x_cpu_pll_dither_frac_reg_val(_nfracmin) \
+ ((_nfracmin << QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT) &\
+ QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK)
+
+/* SPI_CONTROL_ADDR */
+#define _ar933x_spi_ctrl_addr_reg_val(_clk_div, \
+ _remap_dis, \
+ _reloc_spi) \
+ \
+ ((((_clk_div / 2) - 1) << QCA_SPI_CTRL_CLK_DIV_SHIFT) & QCA_SPI_CTRL_CLK_DIV_MASK) |\
+ ((_remap_dis << QCA_SPI_CTRL_REMAP_DIS_SHIFT) & QCA_SPI_CTRL_REMAP_DIS_MASK) |\
+ ((_reloc_spi << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) & QCA_SPI_CTRL_SPI_RELOCATE_MASK)
+
+/*
+ * =============================
+ * PLL configuration preset list
+ * =============================
+ */
+#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(10, 1, 1, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(615)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(16, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(17, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_410_410_205) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(820)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_420_420_210) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(33, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(615)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_430_430_215) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(34, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(410)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_440_440_220) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(35, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(205)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(22, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_450_450_225) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(45, 2, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_460_460_230) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(820)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_470_470_235) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(37, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(615)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_480_480_240) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(38, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(410)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_490_490_245) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(39, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(205)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_510_510_255) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(820)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_520_520_260) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(41, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(615)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_530_265_132) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(42, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(410)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_540_270_135) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(43, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(205)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_275_137) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_560_280_140) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(820)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_570_285_142) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(45, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(615)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_580_290_145) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(46, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(410)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(29, 1, 0, 1)
+ #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
+
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
+
+#else
+ #error "QCA PLL configuration not supported or not selected!"
+#endif
+
+/*
+ * Safe configuration, used in "O/C recovery" mode:
+ * CPU/DDR/AHB/SPI: 400/400/200/20
+ */
+#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
+#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+#define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(0)
+
+#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
+#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
+#define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(0)
+
+#define QCA_SPI_CTRL_REG_VAL_SAFE _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
+
+/*
+ * Default values (if not defined above)
+ */
+
+/* Maximum clock for SPI NOR FLASH */
+#ifndef CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ
+ #define CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ 30
+#endif
+
+/* SPI_CONTROL_ADDR register value */
+#ifndef QCA_SPI_CTRL_REG_VAL
+ #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(8, 1, 0)
+#endif
+
+/* CPU PLL dither register values */
+#ifndef QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(0)
+#endif
+
+#ifndef QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(0)
+#endif
+
+/* CPU PLL settle time */
+#define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL25 0x550
+#define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL40 0x352
+
+#endif /* _AR933X_PLL_INIT_H_ */
--- /dev/null
+/*
+ * MediaTek/Ralink Wireless SOC common registers definitions
+ *
+ * Copyright (C) 2014 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _MTK_SOC_COMMON_H_
+#define _MTK_SOC_COMMON_H_
+
+#include <soc/soc_common.h>
+
+#endif /* _MTK_SOC_COMMON_H_ */
--- /dev/null
+/*
+ * Helper defines and macros related with
+ * PLL and clocks configurations for
+ * Qualcomm/Atheros AR934x and QCA95xx WiSoCs
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _QCA95XX_PLL_INIT_H_
+#define _QCA95XX_PLL_INIT_H_
+
+#include <soc/qca_soc_common.h>
+
+/* CPU_PLL_CONFIG */
+#define _qca95xx_cpu_pll_cfg_reg_val(_nint, \
+ _refdiv, \
+ _range, \
+ _outdiv, \
+ _dis) \
+ \
+ ((_nint << QCA_PLL_CPU_PLL_CFG_NINT_SHIFT) & QCA_PLL_CPU_PLL_CFG_NINT_MASK) |\
+ ((_refdiv << QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK) |\
+ ((_range << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT) & QCA_PLL_CPU_PLL_CFG_RANGE_MASK) |\
+ ((_outdiv << QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK) |\
+ ((_dis << QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT) & QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK)
+
+/* DDR_PLL_CONFIG */
+#define _qca95xx_ddr_pll_cfg_reg_val(_nint, \
+ _refdiv, \
+ _range, \
+ _outdiv, \
+ _dis) \
+ \
+ ((_nint << QCA_PLL_DDR_PLL_CFG_NINT_SHIFT) & QCA_PLL_DDR_PLL_CFG_NINT_MASK) |\
+ ((_refdiv << QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_DDR_PLL_CFG_REFDIV_MASK) |\
+ ((_range << QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT) & QCA_PLL_DDR_PLL_CFG_RANGE_MASK) |\
+ ((_outdiv << QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK) |\
+ ((_dis << QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT) & QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK)
+
+/* CPU_DDR_CLOCK_CONTROL */
+#define _qca95xx_cpu_ddr_clk_ctrl_reg_val(_cpudiv, \
+ _ddrdiv, \
+ _ahbdiv, \
+ _cpu_from_cpupll, \
+ _ddr_from_ddrpll, \
+ _ahb_from_ddrpll) \
+ \
+ (((_cpudiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &\
+ QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) |\
+ (((_ddrdiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &\
+ QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) |\
+ (((_ahbdiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &\
+ QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) |\
+ ((_cpu_from_cpupll << QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT) &\
+ QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK) |\
+ ((_ddr_from_ddrpll << QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT) &\
+ QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK) |\
+ ((_ahb_from_ddrpll << QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT) &\
+ QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK)
+
+/* CPU/DDR_PLL_DITHER */
+#define _qca95xx_cpu_pll_dither_reg_val(_nfracmin) \
+ ((_nfracmin << QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT) &\
+ QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK)
+
+#define _qca95xx_ddr_pll_dither_reg_val(_nfracmin) \
+ ((_nfracmin << QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT) &\
+ QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK)
+
+/* SPI_CONTROL_ADDR */
+#define _qca95xx_spi_ctrl_addr_reg_val(_clk_div, \
+ _remap_dis, \
+ _reloc_spi, \
+ _tshsl_cnt) \
+ \
+ ((((_clk_div / 2) - 1) << QCA_SPI_CTRL_CLK_DIV_SHIFT) & QCA_SPI_CTRL_CLK_DIV_MASK) |\
+ ((_remap_dis << QCA_SPI_CTRL_REMAP_DIS_SHIFT) & QCA_SPI_CTRL_REMAP_DIS_MASK) |\
+ ((_reloc_spi << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) & QCA_SPI_CTRL_SPI_RELOCATE_MASK) |\
+ ((_tshsl_cnt << QCA_SPI_CTRL_TSHSL_CNT_SHIFT) & QCA_SPI_CTRL_TSHSL_CNT_MASK)
+
+/*
+ * =============================
+ * PLL configuration preset list
+ * =============================
+ */
+#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(28, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(35, 2, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(25, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(26, 1, 0, 1, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 1, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_170_170_85) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(34, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(34, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 5, 10, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(17, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(17, 1, 0, 1, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_180_180_90) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 1, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(14, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(35, 4, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(35, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_360_360_180) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_380_380_190) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(13)
+ #define QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_ddr_pll_dither_reg_val(205)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(19, 1, 0, 1, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 1, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_250) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_250) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_275) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 0)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_375_250) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(30, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_400_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_560_450_225) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(26)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_250) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_225) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_250) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_275) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_250) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_150) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_300) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_155) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_310) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_100) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_155) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_166) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_206) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_250) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_310) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0)
+
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_400_200) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_420_210) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_ddr_pll_dither_reg_val(820)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(42, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16)
+
+#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_450_225) /* Tested! */
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+
+ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0)
+ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0)
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16)
+
+#else
+ #error "QCA PLL configuration not supported or not selected!"
+#endif
+
+/*
+ * Safe configuration, used in "O/C recovery" mode:
+ * CPU/DDR/AHB/SPI: 400/400/200/20
+ */
+#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0)
+#define QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_SAFE_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL25 _qca95xx_cpu_pll_dither_reg_val(0)
+#define QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL25 _qca95xx_ddr_pll_dither_reg_val(0)
+
+#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0)
+#define QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_SAFE_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1)
+#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL40 _qca95xx_cpu_pll_dither_reg_val(0)
+#define QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL40 _qca95xx_ddr_pll_dither_reg_val(0)
+
+#define QCA_SPI_CTRL_REG_VAL_SAFE _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2)
+
+/*
+ * Default values (if not defined above)
+ */
+
+/* Maximum clock for SPI NOR FLASH */
+#ifndef CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ
+ #define CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ 30
+#endif
+
+/* SPI_CONTROL_ADDR register value */
+#ifndef QCA_SPI_CTRL_REG_VAL
+ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2)
+#endif
+
+/* CPU PLL dither register values */
+#ifndef QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(0)
+#endif
+
+#ifndef QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40
+ #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(0)
+#endif
+
+/* DDR PLL dither register values */
+#ifndef QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25
+ #define QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_ddr_pll_dither_reg_val(0)
+#endif
+
+#ifndef QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL40
+ #define QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_ddr_pll_dither_reg_val(0)
+#endif
+
+#endif /* _QCA95XX_PLL_INIT_H_ */
--- /dev/null
+/*
+ * Qualcomm/Atheros WiSoCs DRAM related functions and defines
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _QCA_DRAM_H_
+#define _QCA_DRAM_H_
+
+/*
+ * Prepare DDR SDRAM mode register value
+ * For now use always burst length == 8
+ */
+#define DDR_SDRAM_MR_BURST_LEN_SHIFT 0
+#define DDR_SDRAM_MR_BURST_LEN_MASK BITS(DDR_SDRAM_MR_BURST_LEN_SHIFT, 3)
+#define DDR_SDRAM_MR_BURST_INTERLEAVE_SHIFT 3
+#define DDR_SDRAM_MR_BURST_INTERLEAVE_MASK (1 << DDR_SDRAM_MR_BURST_INTERLEAVE_SHIFT)
+#define DDR_SDRAM_MR_CAS_LAT_SHIFT 4
+#define DDR_SDRAM_MR_CAS_LAT_MASK BITS(DDR_SDRAM_MR_CAS_LAT_SHIFT, 3)
+#define DDR_SDRAM_MR_DLL_RESET_SHIFT 8
+#define DDR_SDRAM_MR_DLL_RESET_MASK (1 << DDR_SDRAM_MR_DLL_RESET_SHIFT)
+#define DDR_SDRAM_MR_WR_RECOVERY_SHIFT 9
+#define DDR_SDRAM_MR_WR_RECOVERY_MASK BITS(DDR_SDRAM_MR_WR_RECOVERY_SHIFT, 3)
+
+#define _ddr_sdram_mr_val(_burst_i, \
+ _cas_lat, \
+ _dll_res, \
+ _wr_rcov) \
+ \
+ ((0x3 << DDR_SDRAM_MR_BURST_LEN_SHIFT) & DDR_SDRAM_MR_BURST_LEN_MASK) |\
+ ((_cas_lat << DDR_SDRAM_MR_CAS_LAT_SHIFT) & DDR_SDRAM_MR_CAS_LAT_MASK) |\
+ ((_dll_res << DDR_SDRAM_MR_DLL_RESET_SHIFT) & DDR_SDRAM_MR_DLL_RESET_MASK) |\
+ (((_wr_rcov - 1) << DDR_SDRAM_MR_WR_RECOVERY_SHIFT) & DDR_SDRAM_MR_WR_RECOVERY_MASK) |\
+ ((_burst_i << DDR_SDRAM_MR_BURST_INTERLEAVE_SHIFT) & DDR_SDRAM_MR_BURST_INTERLEAVE_MASK)
+
+/* Prepare DDR SDRAM extended mode register value */
+#define DDR_SDRAM_EMR_DLL_EN_SHIFT 0
+#define DDR_SDRAM_EMR_DLL_EN_MASK (1 << DDR_SDRAM_EMR_DLL_EN_SHIFT)
+#define DDR_SDRAM_EMR_WEAK_STRENGTH_SHIFT 1
+#define DDR_SDRAM_EMR_WEAK_STRENGTH_MASK (1 << DDR_SDRAM_EMR_WEAK_STRENGTH_SHIFT)
+#define DDR_SDRAM_EMR_OCD_PRG_SHIFT 7
+#define DDR_SDRAM_EMR_OCD_PRG_MASK BITS(DDR_SDRAM_EMR_OCD_PRG_SHIFT, 3)
+#define DDR_SDRAM_EMR_OCD_EXIT_VAL 0
+#define DDR_SDRAM_EMR_OCD_DEFAULT_VAL 7
+#define DDR_SDRAM_EMR_NDQS_DIS_SHIFT 10
+#define DDR_SDRAM_EMR_NDQS_DIS_MASK (1 << DDR_SDRAM_EMR_NDQS_DIS_SHIFT)
+#define DDR_SDRAM_EMR_RDQS_EN_SHIFT 11
+#define DDR_SDRAM_EMR_RDQS_EN_MASK (1 << DDR_SDRAM_EMR_RDQS_EN_SHIFT)
+#define DDR_SDRAM_EMR_OBUF_DIS_SHIFT 12
+#define DDR_SDRAM_EMR_OBUF_DIS_MASK (1 << DDR_SDRAM_EMR_OBUF_DIS_SHIFT)
+
+#define _ddr_sdram_emr_val(_dll_dis, \
+ _drv_weak, \
+ _ocd_prg, \
+ _ndqs_dis, \
+ _rdqs_en, \
+ _obuf_dis) \
+ \
+ ((_dll_dis << DDR_SDRAM_EMR_DLL_EN_SHIFT) & DDR_SDRAM_EMR_DLL_EN_MASK) |\
+ ((_ocd_prg << DDR_SDRAM_EMR_OCD_PRG_SHIFT) & DDR_SDRAM_EMR_OCD_PRG_MASK) |\
+ ((_ndqs_dis << DDR_SDRAM_EMR_NDQS_DIS_SHIFT) & DDR_SDRAM_EMR_NDQS_DIS_MASK) |\
+ ((_rdqs_en << DDR_SDRAM_EMR_RDQS_EN_SHIFT) & DDR_SDRAM_EMR_RDQS_EN_MASK) |\
+ ((_obuf_dis << DDR_SDRAM_EMR_OBUF_DIS_SHIFT) & DDR_SDRAM_EMR_OBUF_DIS_MASK) |\
+ ((_drv_weak << DDR_SDRAM_EMR_WEAK_STRENGTH_SHIFT) & DDR_SDRAM_EMR_WEAK_STRENGTH_MASK)
+
+/* Prepare DDR SDRAM extended mode register 2 value */
+#define DDR_SDRAM_EMR2_PASR_SHIFT 0
+#define DDR_SDRAM_EMR2_PASR_MASK BITS(DDR_SDRAM_EMR2_PASR_SHIFT, 3)
+#define DDR_SDRAM_EMR2_DCC_EN_SHIFT 3
+#define DDR_SDRAM_EMR2_DCC_EN_MASK (1 << DDR_SDRAM_EMR2_DCC_EN_SHIFT)
+#define DDR_SDRAM_EMR2_SRF_EN_SHIFT 7
+#define DDR_SDRAM_EMR2_SRF_EN_MASK (1 << DDR_SDRAM_EMR2_SRF_EN_SHIFT)
+
+#define _ddr_sdram_emr2_val(_pasr, \
+ _dcc_en, \
+ _srf_en) \
+ \
+ ((_pasr << DDR_SDRAM_EMR2_PASR_SHIFT) & DDR_SDRAM_EMR2_PASR_MASK) |\
+ ((_dcc_en << DDR_SDRAM_EMR2_DCC_EN_SHIFT) & DDR_SDRAM_EMR2_DCC_EN_MASK) |\
+ ((_srf_en << DDR_SDRAM_EMR2_SRF_EN_SHIFT) & DDR_SDRAM_EMR2_SRF_EN_MASK)
+
+/*
+ * DDR timing related controller register values
+ */
+
+/* DDR_CONFIG */
+#define _qca_ddr_cfg_reg_val(_tras, \
+ _trcd, \
+ _trp, \
+ _trrd, \
+ _trfc, \
+ _tmrd, \
+ _cas, \
+ _opage) \
+ \
+ ((_tras << QCA_DDR_CFG_TRAS_SHIFT) & QCA_DDR_CFG_TRAS_MASK) |\
+ ((_trcd << QCA_DDR_CFG_TRCD_SHIFT) & QCA_DDR_CFG_TRCD_MASK) |\
+ ((_trp << QCA_DDR_CFG_TRP_SHIFT) & QCA_DDR_CFG_TRP_MASK) |\
+ ((_trrd << QCA_DDR_CFG_TRRD_SHIFT) & QCA_DDR_CFG_TRRD_MASK) |\
+ ((_trfc << QCA_DDR_CFG_TRFC_SHIFT) & QCA_DDR_CFG_TRFC_MASK) |\
+ ((_tmrd << QCA_DDR_CFG_TMRD_SHIFT) & QCA_DDR_CFG_TMRD_MASK) |\
+ ((_cas << QCA_DDR_CFG_CAS_3LSB_SHIFT) & QCA_DDR_CFG_CAS_3LSB_MASK) |\
+ ((_opage << QCA_DDR_CFG_PAGE_CLOSE_SHIFT) & QCA_DDR_CFG_PAGE_CLOSE_MASK) |\
+ (((_cas & 0x8) >> 3) << QCA_DDR_CFG_CAS_MSB_SHIFT)
+
+/* DDR_CONFIG2 */
+#define _qca_ddr_cfg2_reg_val(_burst_type, \
+ _ctrl_oe_en, \
+ _phase_sel, \
+ _cke, \
+ _twr, \
+ _trtw, \
+ _trtp, \
+ _twtr, \
+ _gate_lat, \
+ _half_width) \
+ \
+ (0x8 << QCA_DDR_CFG2_BURST_LEN_SHIFT) |\
+ ((_burst_type << QCA_DDR_CFG2_BURST_TYPE_SHIFT) & QCA_DDR_CFG2_BURST_TYPE_MASK) |\
+ ((_ctrl_oe_en << QCA_DDR_CFG2_CTRL_OE_EN_SHIFT) & QCA_DDR_CFG2_CTRL_OE_EN_MASK) |\
+ ((_phase_sel << QCA_DDR_CFG2_PHASE_SEL_SHIFT) & QCA_DDR_CFG2_PHASE_SEL_MASK) |\
+ ((_cke << QCA_DDR_CFG2_CKE_SHIFT) & QCA_DDR_CFG2_CKE_MASK) |\
+ ((_twr << QCA_DDR_CFG2_TWR_SHIFT) & QCA_DDR_CFG2_TWR_MASK) |\
+ ((_trtw << QCA_DDR_CFG2_TRTW_SHIFT) & QCA_DDR_CFG2_TRTW_MASK) |\
+ ((_trtp << QCA_DDR_CFG2_TRTP_SHIFT) & QCA_DDR_CFG2_TRTP_MASK) |\
+ ((_twtr << QCA_DDR_CFG2_TWTR_SHIFT) & QCA_DDR_CFG2_TWTR_MASK) |\
+ ((_half_width << QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT) & QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK) |\
+ ((_gate_lat << QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT) & QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK)
+
+/* DDR_DDR2_CONFIG */
+#define _qca_ddr_ddr2_cfg_reg_val(_ddr2_en, \
+ _tfaw, \
+ _twl) \
+ \
+ ((_ddr2_en << QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT) & QCA_DDR_DDR2_CFG_DDR2_EN_MASK) |\
+ ((_tfaw << QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT) & QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK) |\
+ ((_twl << QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT) & QCA_DDR_DDR2_CFG_DDR2_TWL_MASK)
+
+/*
+ * DDR control functions
+ */
+
+/* Force MRS (mode register set) */
+static inline void qca_dram_force_mrs(void)
+{
+ qca_soc_reg_write(QCA_DDR_CTRL_REG,
+ QCA_DDR_CTRL_FORCE_MRS_MASK);
+}
+
+/* Force EMRS (extended mode register set) */
+static inline void qca_dram_force_emrs(void)
+{
+ qca_soc_reg_write(QCA_DDR_CTRL_REG,
+ QCA_DDR_CTRL_FORCE_EMRS_MASK);
+}
+
+/* Force EMR2S (extended mode register 2 set) */
+static inline void qca_dram_force_emr2s(void)
+{
+ qca_soc_reg_write(QCA_DDR_CTRL_REG,
+ QCA_DDR_CTRL_FORCE_EMR2S_MASK);
+}
+
+/* Force EMR3S (extended mode register 3 set) */
+static inline void qca_dram_force_emr3s(void)
+{
+ qca_soc_reg_write(QCA_DDR_CTRL_REG,
+ QCA_DDR_CTRL_FORCE_EMR3S_MASK);
+}
+
+/* Force auto refresh */
+static inline void qca_dram_force_aref(void)
+{
+ qca_soc_reg_write(QCA_DDR_CTRL_REG,
+ QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK);
+}
+
+/* Force precharge all */
+static inline void qca_dram_force_preall(void)
+{
+ qca_soc_reg_write(QCA_DDR_CTRL_REG,
+ QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK);
+}
+
+/*
+ * DDR setup related functions
+ */
+
+/* Sets DDR mode register value and issue MRS update */
+static inline void qca_dram_set_mr(u32 value)
+{
+ qca_soc_reg_write(QCA_DDR_MR_REG, value);
+ qca_dram_force_mrs();
+}
+
+/* Sets DDR extended mode register value and issue EMRS update */
+static inline void qca_dram_set_emr(u32 value)
+{
+ qca_soc_reg_write(QCA_DDR_EMR_REG, value);
+ qca_dram_force_emrs();
+}
+
+/* Sets DDR extended mode register 2 value and issue EMR2S update */
+static inline void qca_dram_set_emr2(u32 value)
+{
+ qca_soc_reg_write(QCA_DDR_EMR2_REG, value);
+ qca_dram_force_emr2s();
+}
+
+/* Sets DDR extended mode register 3 value and issue EMR3S update */
+static inline void qca_dram_set_emr3(u32 value)
+{
+ qca_soc_reg_write(QCA_DDR_EMR3_REG, value);
+ qca_dram_force_emr3s();
+}
+
+#endif /* _QCA_DRAM_H_ */
--- /dev/null
+/*
+ * List of predefined PLL configurations for Qualcomm/Atheros Wireless SOC
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _QCA_PLL_LIST_H_
+#define _QCA_PLL_LIST_H_
+
+#define QCA_PLL_PRESET_25_25_12 1
+#define QCA_PLL_PRESET_25_25_25 2
+#define QCA_PLL_PRESET_50_50_25 3
+#define QCA_PLL_PRESET_50_50_50 4
+#define QCA_PLL_PRESET_75_75_25 5
+#define QCA_PLL_PRESET_75_75_50 6
+#define QCA_PLL_PRESET_75_75_75 7
+#define QCA_PLL_PRESET_100_100_25 8
+#define QCA_PLL_PRESET_100_100_50 9
+#define QCA_PLL_PRESET_100_100_100 10
+#define QCA_PLL_PRESET_125_50_25 11
+#define QCA_PLL_PRESET_125_50_50 12
+#define QCA_PLL_PRESET_125_62_25 13
+#define QCA_PLL_PRESET_125_62_50 14
+#define QCA_PLL_PRESET_125_62_62 15
+#define QCA_PLL_PRESET_125_100_25 16
+#define QCA_PLL_PRESET_125_100_50 17
+#define QCA_PLL_PRESET_125_100_62 18
+#define QCA_PLL_PRESET_125_100_100 19
+#define QCA_PLL_PRESET_150_150_75 20
+#define QCA_PLL_PRESET_150_150_100 21
+#define QCA_PLL_PRESET_150_150_150 22
+#define QCA_PLL_PRESET_160_160_80 23
+#define QCA_PLL_PRESET_170_170_85 24
+#define QCA_PLL_PRESET_180_180_90 25
+#define QCA_PLL_PRESET_200_200_100 26
+#define QCA_PLL_PRESET_200_200_150 27
+#define QCA_PLL_PRESET_200_200_200 28
+#define QCA_PLL_PRESET_300_200_100 29
+#define QCA_PLL_PRESET_300_200_150 30
+#define QCA_PLL_PRESET_300_200_200 31
+#define QCA_PLL_PRESET_300_300_100 32
+#define QCA_PLL_PRESET_300_300_150 33
+#define QCA_PLL_PRESET_300_300_200 34
+#define QCA_PLL_PRESET_350_350_175 35
+#define QCA_PLL_PRESET_360_360_180 36
+#define QCA_PLL_PRESET_380_380_190 37
+#define QCA_PLL_PRESET_400_200_100 38
+#define QCA_PLL_PRESET_400_200_150 39
+#define QCA_PLL_PRESET_400_200_200 40
+#define QCA_PLL_PRESET_400_300_100 41
+#define QCA_PLL_PRESET_400_300_150 42
+#define QCA_PLL_PRESET_400_300_200 43
+#define QCA_PLL_PRESET_400_300_300 44
+#define QCA_PLL_PRESET_400_400_200 45
+#define QCA_PLL_PRESET_400_400_300 46
+#define QCA_PLL_PRESET_410_410_205 47
+#define QCA_PLL_PRESET_420_420_210 48
+#define QCA_PLL_PRESET_430_430_215 49
+#define QCA_PLL_PRESET_440_440_220 50
+#define QCA_PLL_PRESET_450_450_225 51
+#define QCA_PLL_PRESET_460_460_230 52
+#define QCA_PLL_PRESET_470_470_235 53
+#define QCA_PLL_PRESET_480_480_240 54
+#define QCA_PLL_PRESET_490_490_245 55
+#define QCA_PLL_PRESET_500_200_100 56
+#define QCA_PLL_PRESET_500_200_150 57
+#define QCA_PLL_PRESET_500_200_200 58
+#define QCA_PLL_PRESET_500_300_100 59
+#define QCA_PLL_PRESET_500_300_150 60
+#define QCA_PLL_PRESET_500_300_200 61
+#define QCA_PLL_PRESET_500_300_250 62
+#define QCA_PLL_PRESET_500_300_300 63
+#define QCA_PLL_PRESET_500_400_100 64
+#define QCA_PLL_PRESET_500_400_200 65
+#define QCA_PLL_PRESET_500_400_250 66
+#define QCA_PLL_PRESET_500_500_100 67
+#define QCA_PLL_PRESET_500_500_150 68
+#define QCA_PLL_PRESET_500_500_200 69
+#define QCA_PLL_PRESET_500_500_250 70
+#define QCA_PLL_PRESET_500_500_300 71
+#define QCA_PLL_PRESET_510_510_255 72
+#define QCA_PLL_PRESET_520_520_260 73
+#define QCA_PLL_PRESET_530_265_132 74
+#define QCA_PLL_PRESET_540_275_135 75
+#define QCA_PLL_PRESET_550_200_100 76
+#define QCA_PLL_PRESET_550_200_150 77
+#define QCA_PLL_PRESET_550_200_200 78
+#define QCA_PLL_PRESET_550_275_137 79
+#define QCA_PLL_PRESET_550_300_100 80
+#define QCA_PLL_PRESET_550_300_150 81
+#define QCA_PLL_PRESET_550_300_200 82
+#define QCA_PLL_PRESET_550_300_275 83
+#define QCA_PLL_PRESET_550_300_300 84
+#define QCA_PLL_PRESET_550_375_250 85
+#define QCA_PLL_PRESET_550_400_200 86
+#define QCA_PLL_PRESET_560_280_140 87
+#define QCA_PLL_PRESET_560_450_225 88
+#define QCA_PLL_PRESET_570_285_142 89
+#define QCA_PLL_PRESET_580_290_145 90
+#define QCA_PLL_PRESET_600_200_100 91
+#define QCA_PLL_PRESET_600_200_150 92
+#define QCA_PLL_PRESET_600_200_200 93
+#define QCA_PLL_PRESET_600_300_100 94
+#define QCA_PLL_PRESET_600_300_150 95
+#define QCA_PLL_PRESET_600_300_200 96
+#define QCA_PLL_PRESET_600_300_250 97
+#define QCA_PLL_PRESET_600_300_300 98
+#define QCA_PLL_PRESET_600_400_100 99
+#define QCA_PLL_PRESET_600_400_150 100
+#define QCA_PLL_PRESET_600_400_200 101
+#define QCA_PLL_PRESET_600_400_300 102
+#define QCA_PLL_PRESET_600_450_100 103
+#define QCA_PLL_PRESET_600_450_150 104
+#define QCA_PLL_PRESET_600_450_200 105
+#define QCA_PLL_PRESET_600_450_225 106
+#define QCA_PLL_PRESET_600_450_300 107
+#define QCA_PLL_PRESET_600_500_100 108
+#define QCA_PLL_PRESET_600_500_150 109
+#define QCA_PLL_PRESET_600_500_200 110
+#define QCA_PLL_PRESET_600_500_250 111
+#define QCA_PLL_PRESET_600_500_300 112
+#define QCA_PLL_PRESET_600_550_100 113
+#define QCA_PLL_PRESET_600_550_150 114
+#define QCA_PLL_PRESET_600_550_200 115
+#define QCA_PLL_PRESET_600_550_275 116
+#define QCA_PLL_PRESET_600_550_300 117
+#define QCA_PLL_PRESET_600_600_100 118
+#define QCA_PLL_PRESET_600_600_150 119
+#define QCA_PLL_PRESET_600_600_200 120
+#define QCA_PLL_PRESET_600_600_250 121
+#define QCA_PLL_PRESET_600_600_300 122
+#define QCA_PLL_PRESET_620_200_100 123
+#define QCA_PLL_PRESET_620_200_150 124
+#define QCA_PLL_PRESET_620_200_200 125
+#define QCA_PLL_PRESET_620_300_100 126
+#define QCA_PLL_PRESET_620_300_150 127
+#define QCA_PLL_PRESET_620_300_200 128
+#define QCA_PLL_PRESET_620_300_300 129
+#define QCA_PLL_PRESET_620_400_100 130
+#define QCA_PLL_PRESET_620_400_155 131
+#define QCA_PLL_PRESET_620_400_200 132
+#define QCA_PLL_PRESET_620_400_310 133
+#define QCA_PLL_PRESET_620_500_100 134
+#define QCA_PLL_PRESET_620_500_155 135
+#define QCA_PLL_PRESET_620_500_166 136
+#define QCA_PLL_PRESET_620_500_206 137
+#define QCA_PLL_PRESET_620_500_250 138
+#define QCA_PLL_PRESET_620_500_310 139
+#define QCA_PLL_PRESET_650_400_200 140
+#define QCA_PLL_PRESET_650_420_210 141
+#define QCA_PLL_PRESET_650_450_225 142
+
+#endif /* _QCA_PLL_LIST_H_ */
--- /dev/null
+/*
+ * Qualcomm/Atheros Wireless SOC common registers definitions
+ *
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2014 Qualcomm Atheros, Inc.
+ * Copyright (C) 2008-2010 Atheros Communications Inc.
+ *
+ * Partially based on:
+ * Linux/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _QCA_SOC_COMMON_H_
+#define _QCA_SOC_COMMON_H_
+
+#include <soc/soc_common.h>
+
+/*
+ * Address map
+ */
+#define QCA_APB_BASE_REG 0x18000000
+#define QCA_FLASH_BASE_REG 0x1F000000
+
+/*
+ * APB block
+ */
+#define QCA_DDR_CTRL_BASE_REG QCA_APB_BASE_REG + 0x00000000
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000
+#else
+ #define QCA_LSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000
+ #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00500000
+#endif
+
+#define QCA_USB_CFG_BASE_REG QCA_APB_BASE_REG + 0x00030000
+#define QCA_GPIO_BASE_REG QCA_APB_BASE_REG + 0x00040000
+#define QCA_PLL_BASE_REG QCA_APB_BASE_REG + 0x00050000
+#define QCA_RST_BASE_REG QCA_APB_BASE_REG + 0x00060000
+#define QCA_GMAC_BASE_REG QCA_APB_BASE_REG + 0x00070000
+#define QCA_RTC_BASE_REG QCA_APB_BASE_REG + 0x00107000
+#define QCA_PLL_SRIF_BASE_REG QCA_APB_BASE_REG + 0x00116000
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x00090000
+#elif (SOC_TYPE & QCA_AR934X_SOC) |\
+ (SOC_TYPE & QCA_AR955X_SOC)
+ #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x000A9000
+#endif
+
+/*
+ * DDR registers
+ */
+#define QCA_DDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x000
+#define QCA_DDR_CFG2_REG QCA_DDR_CTRL_BASE_REG + 0x004
+#define QCA_DDR_MR_REG QCA_DDR_CTRL_BASE_REG + 0x008
+#define QCA_DDR_EMR_REG QCA_DDR_CTRL_BASE_REG + 0x00C
+#define QCA_DDR_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x010
+#define QCA_DDR_REFRESH_REG QCA_DDR_CTRL_BASE_REG + 0x014
+#define QCA_DDR_RD_DATA_THIS_CYCLE_REG QCA_DDR_CTRL_BASE_REG + 0x018
+#define QCA_DDR_TAP_CTRL_0_REG QCA_DDR_CTRL_BASE_REG + 0x01C
+#define QCA_DDR_TAP_CTRL_1_REG QCA_DDR_CTRL_BASE_REG + 0x020
+#define QCA_DDR_TAP_CTRL_2_REG QCA_DDR_CTRL_BASE_REG + 0x024
+#define QCA_DDR_TAP_CTRL_3_REG QCA_DDR_CTRL_BASE_REG + 0x028
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x07C
+ #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x080
+ #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x084
+ #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x08C
+ #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x090
+ #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x094
+ #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x098
+ #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x09C
+ #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0A0
+ #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0A4
+ #define QCA_SDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0D8
+#else
+ #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x09C
+ #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x0A0
+ #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x0A4
+ #define QCA_DDR_WB_FLUSH_PCIE_REG QCA_DDR_CTRL_BASE_REG + 0x0A8
+ #define QCA_DDR_WB_FLUSH_WMAC_REG QCA_DDR_CTRL_BASE_REG + 0x0AC
+ #define QCA_DDR_WB_FLUSH_SRC1_REG QCA_DDR_CTRL_BASE_REG + 0x0B0
+ #define QCA_DDR_WB_FLUSH_SRC2_REG QCA_DDR_CTRL_BASE_REG + 0x0B4
+ #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0B8
+ #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x0BC
+ #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x0C0
+ #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x0C4
+ #define QCA_DDR_BURST2_REG QCA_DDR_CTRL_BASE_REG + 0x0C8
+ #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x0CC
+ #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0D0
+ #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0D4
+ #define QCA_DDR_FSM_WAIT_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x0E4
+ #define QCA_DDR_CTRL_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x108
+ #define QCA_DDR_SELF_REFRESH_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x110
+ #define QCA_DDR_SELF_REFRESH_TIMER_REG QCA_DDR_CTRL_BASE_REG + 0x114
+ #define QCA_DDR_WMAC_FLUSH_REG QCA_DDR_CTRL_BASE_REG + 0x128
+ #define QCA_DDR_CFG3_REG QCA_DDR_CTRL_BASE_REG + 0x15C
+
+ /*
+ * Below register addresses and names come directly form Atheros (Q)SDK code:
+ * tap-955x.S/tap-953x.S/tap-956x.S, as they do not exist in any datasheet
+ */
+ #define QCA_DDR_PERF_MASK_ADDR_0_REG QCA_DDR_CTRL_BASE_REG + 0x02C
+ #define QCA_DDR_PERF_MASK_AHB_GE0_0_REG QCA_DDR_CTRL_BASE_REG + 0x034
+ #define QCA_DDR_PERF_COMP_AHB_GE0_0_REG QCA_DDR_CTRL_BASE_REG + 0x038
+ #define QCA_DDR_PERF_MASK_AHB_GE1_0_REG QCA_DDR_CTRL_BASE_REG + 0x03C
+ #define QCA_DDR_PERF_COMP_AHB_GE1_0_REG QCA_DDR_CTRL_BASE_REG + 0x040
+ #define QCA_DDR_PERF_COMP_ADDR_1_REG QCA_DDR_CTRL_BASE_REG + 0x068
+ #define QCA_DDR_PERF_MASK_AHB_GE0_1_REG QCA_DDR_CTRL_BASE_REG + 0x06C
+ #define QCA_DDR_PERF_COMP_AHB_GE0_1_REG QCA_DDR_CTRL_BASE_REG + 0x070
+ #define QCA_DDR_PERF_MASK_AHB_GE1_1_REG QCA_DDR_CTRL_BASE_REG + 0x074
+ #define QCA_DDR_PERF_COMP_AHB_GE1_1_REG QCA_DDR_CTRL_BASE_REG + 0x078
+ #define QCA_DDR_BIST_REG QCA_DDR_CTRL_BASE_REG + 0x11C
+ #define QCA_DDR_BIST_STATUS_REG QCA_DDR_CTRL_BASE_REG + 0x120
+#endif
+
+/*
+ * DDR registers BIT fields
+ */
+
+/* DDR_CONFIG register (DDR DRAM configuration) */
+#define QCA_DDR_CFG_TRAS_SHIFT 0
+#define QCA_DDR_CFG_TRAS_MASK BITS(QCA_DDR_CFG_TRAS_SHIFT, 5)
+#define QCA_DDR_CFG_TRCD_SHIFT 5
+#define QCA_DDR_CFG_TRCD_MASK BITS(QCA_DDR_CFG_TRCD_SHIFT, 4)
+#define QCA_DDR_CFG_TRP_SHIFT 9
+#define QCA_DDR_CFG_TRP_MASK BITS(QCA_DDR_CFG_TRP_SHIFT, 4)
+#define QCA_DDR_CFG_TRRD_SHIFT 13
+#define QCA_DDR_CFG_TRRD_MASK BITS(QCA_DDR_CFG_TRRD_SHIFT, 4)
+#define QCA_DDR_CFG_TRFC_SHIFT 17
+#define QCA_DDR_CFG_TRFC_MASK BITS(QCA_DDR_CFG_TRFC_SHIFT, 6)
+#define QCA_DDR_CFG_TMRD_SHIFT 23
+#define QCA_DDR_CFG_TMRD_MASK BITS(QCA_DDR_CFG_TMRD_SHIFT, 4)
+#define QCA_DDR_CFG_CAS_3LSB_SHIFT 27
+#define QCA_DDR_CFG_CAS_3LSB_MASK BITS(QCA_DDR_CFG_CAS_3LSB_SHIFT, 3)
+#define QCA_DDR_CFG_PAGE_CLOSE_SHIFT 30
+#define QCA_DDR_CFG_PAGE_CLOSE_MASK BIT(QCA_DDR_CFG_PAGE_CLOSE_SHIFT)
+#define QCA_DDR_CFG_CAS_MSB_SHIFT 31
+#define QCA_DDR_CFG_CAS_MSB_MASK BIT(QCA_DDR_CFG_CAS_MSB_SHIFT)
+
+/* DDR_CONFIG2 register (DDR DRAM configuration 2) */
+#define QCA_DDR_CFG2_BURST_LEN_SHIFT 0
+#define QCA_DDR_CFG2_BURST_LEN_MASK BITS(QCA_DDR_CFG2_BURST_LEN_SHIFT, 4)
+#define QCA_DDR_CFG2_BURST_TYPE_SHIFT 4
+#define QCA_DDR_CFG2_BURST_TYPE_MASK BIT(QCA_DDR_CFG2_BURST_TYPE_SHIFT)
+#define QCA_DDR_CFG2_CTRL_OE_EN_SHIFT 5
+#define QCA_DDR_CFG2_CTRL_OE_EN_MASK BIT(QCA_DDR_CFG2_CTRL_OE_EN_SHIFT)
+#define QCA_DDR_CFG2_PHASE_SEL_SHIFT 6
+#define QCA_DDR_CFG2_PHASE_SEL_MASK BIT(QCA_DDR_CFG2_PHASE_SEL_SHIFT)
+#define QCA_DDR_CFG2_CKE_SHIFT 7
+#define QCA_DDR_CFG2_CKE_MASK BIT(QCA_DDR_CFG2_CKE_SHIFT)
+#define QCA_DDR_CFG2_TWR_SHIFT 8
+#define QCA_DDR_CFG2_TWR_MASK BITS(QCA_DDR_CFG2_TWR_SHIFT, 4)
+#define QCA_DDR_CFG2_TRTW_SHIFT 12
+#define QCA_DDR_CFG2_TRTW_MASK BITS(QCA_DDR_CFG2_TRTW_SHIFT, 5)
+#define QCA_DDR_CFG2_TRTP_SHIFT 17
+#define QCA_DDR_CFG2_TRTP_MASK BITS(QCA_DDR_CFG2_TRTP_SHIFT, 4)
+#define QCA_DDR_CFG2_TWTR_SHIFT 21
+#define QCA_DDR_CFG2_TWTR_MASK BITS(QCA_DDR_CFG2_TWTR_SHIFT, 5)
+#define QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT 26
+#define QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK BITS(QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT, 4)
+#define QCA_DDR_CFG2_SWAP_A26_A27_SHIFT 30
+#define QCA_DDR_CFG2_SWAP_A26_A27_MASK BIT(QCA_DDR_CFG2_SWAP_A26_A27_SHIFT)
+#define QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT 31
+#define QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK BIT(QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT)
+
+/* DDR_MODE register (DDR mode register value) */
+#define QCA_DDR_MR_VALUE_SHIFT 0
+#define QCA_DDR_MR_VALUE_MASK BITS(QCA_DDR_MR_VALUE_SHIFT, 14)
+
+/* DDR_EMR registers (DDR extended mode register 1/2/3 values) */
+#define QCA_DDR_EMR_VALUE_SHIFT 0
+#define QCA_DDR_EMR_VALUE_MASK BITS(QCA_DDR_EMR_VALUE_SHIFT, 14)
+
+/* DDR_CONTROL register (DDR control) */
+#define QCA_DDR_CTRL_FORCE_MRS_SHIFT 0
+#define QCA_DDR_CTRL_FORCE_MRS_MASK BIT(QCA_DDR_CTRL_FORCE_MRS_SHIFT)
+#define QCA_DDR_CTRL_FORCE_EMRS_SHIFT 1
+#define QCA_DDR_CTRL_FORCE_EMRS_MASK BIT(QCA_DDR_CTRL_FORCE_EMRS_SHIFT)
+#define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT 2
+#define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK BIT(QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT)
+#define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT 3
+#define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK BIT(QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT)
+#define QCA_DDR_CTRL_FORCE_EMR2S_SHIFT 4
+#define QCA_DDR_CTRL_FORCE_EMR2S_MASK BIT(QCA_DDR_CTRL_FORCE_EMR2S_SHIFT)
+#define QCA_DDR_CTRL_FORCE_EMR3S_SHIFT 5
+#define QCA_DDR_CTRL_FORCE_EMR3S_MASK BIT(QCA_DDR_CTRL_FORCE_EMR3S_SHIFT)
+
+/* DDR_REFRESH register (DDR refresh control and configuration) */
+#define QCA_DDR_REFRESH_PERIOD_SHIFT 0
+#define QCA_DDR_REFRESH_PERIOD_MASK BITS(QCA_DDR_REFRESH_PERIOD_SHIFT, 14)
+#define QCA_DDR_REFRESH_EN_SHIFT 14
+#define QCA_DDR_REFRESH_EN_MASK BIT(QCA_DDR_REFRESH_EN_SHIFT)
+
+/* DDR_RD_DATA_THIS_CYCLE register (DDR read data capture bit mask) */
+#define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT 0
+#define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_MASK BITS(QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT, 32)
+
+/* TAP_CONTROL_X registers (DQS delay tap control for byte X) */
+#if (SOC_TYPE & QCA_AR933X_SOC) |\
+ (SOC_TYPE & QCA_AR934X_SOC)
+ #define QCA_DDR_TAP_CTRL_TAP_L_SHIFT 0
+ #define QCA_DDR_TAP_CTRL_TAP_L_MASK BITS(QCA_DDR_TAP_CTRL_TAP_L_SHIFT, 5)
+ #define QCA_DDR_TAP_CTRL_TAP_H_SHIFT 8
+ #define QCA_DDR_TAP_CTRL_TAP_H_MASK BITS(QCA_DDR_TAP_CTRL_TAP_H_SHIFT, 5)
+ #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT 16
+ #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_MASK BIT(QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT)
+#else
+ #define QCA_DDR_TAP_CTRL_TAP_SHIFT 0
+ #define QCA_DDR_TAP_CTRL_TAP_MASK BITS(QCA_DDR_TAP_CTRL_TAP_SHIFT, 6)
+#endif
+
+/* DDR_DDR2_CONFIG register (DDR2 configuration) */
+#define QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT 0
+#define QCA_DDR_DDR2_CFG_DDR2_EN_MASK BIT(QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT)
+#define QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT 2
+#define QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT, 6)
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT 10
+ #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 3)
+#else
+ #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT 10
+ #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 4)
+#endif
+
+/* DDR_BURST (DDR bank arbiter per client burst size) */
+#define QCA_DDR_BURST_GE0_MAX_BL_SHIFT 0
+#define QCA_DDR_BURST_GE0_MAX_BL_MASK BITS(QCA_DDR_BURST_GE0_MAX_BL_SHIFT, 4)
+#define QCA_DDR_BURST_GE1_MAX_BL_SHIFT 4
+#define QCA_DDR_BURST_GE1_MAX_BL_MASK BITS(QCA_DDR_BURST_GE1_MAX_BL_SHIFT, 4)
+#define QCA_DDR_BURST_PCIE_MAX_BL_SHIFT 8
+#define QCA_DDR_BURST_PCIE_MAX_BL_MASK BITS(QCA_DDR_BURST_PCIE_MAX_BL_SHIFT, 4)
+#define QCA_DDR_BURST_USB_MAX_BL_SHIFT 12
+#define QCA_DDR_BURST_USB_MAX_BL_MASK BITS(QCA_DDR_BURST_USB_MAX_BL_SHIFT, 4)
+#define QCA_DDR_BURST_CPU_MAX_BL_SHIFT 16
+#define QCA_DDR_BURST_CPU_MAX_BL_MASK BITS(QCA_DDR_BURST_CPU_MAX_BL_SHIFT, 4)
+#define QCA_DDR_BURST_MAX_READ_BURST_SHIFT 20
+#define QCA_DDR_BURST_MAX_READ_BURST_MASK BITS(QCA_DDR_BURST_MAX_READ_BURST_SHIFT, 4)
+#define QCA_DDR_BURST_MAX_WRITE_BURST_SHIFT 24
+#define QCA_DDR_BURST_MAX_WRITE_BURST_MASK BITS(QCA_DDR_BURST_MAX_WRITE_BURST_SHIFT, 4)
+#define QCA_DDR_BURST_RWP_MASK_EN_SHIFT 28
+#define QCA_DDR_BURST_RWP_MASK_EN_MASK BITS(QCA_DDR_BURST_RWP_MASK_EN_SHIFT, 2)
+#define QCA_DDR_BURST_CPU_PRIO_BE_SHIFT 30
+#define QCA_DDR_BURST_CPU_PRIO_BE_MASK BIT(QCA_DDR_BURST_CPU_PRIO_BE_SHIFT)
+#define QCA_DDR_BURST_CPU_PRIO_SHIFT 31
+#define QCA_DDR_BURST_CPU_PRIO_MASK BIT(QCA_DDR_BURST_CPU_PRIO_SHIFT)
+
+/* DDR_BURST2 (DDR bank arbiter per client burst size 2) */
+#define QCA_DDR_BURST2_WMAC_MAX_BL_SHIFT 0
+#define QCA_DDR_BURST2_WMAC_MAX_BL_MASK BITS(QCA_DDR_BURST2_WMAC_MAX_BL_SHIFT, 4)
+#define QCA_DDR_BURST2_MISC_SRC1_MAX_BL_SHIFT 4
+#define QCA_DDR_BURST2_MISC_SRC1_MAX_BL_MASK BITS(QCA_DDR_BURST2_MISC_SRC1_MAX_BL_SHIFT, 4)
+#define QCA_DDR_BURST2_MISC_SRC2_MAX_BL_SHIFT 8
+#define QCA_DDR_BURST2_MISC_SRC2_MAX_BL_MASK BITS(QCA_DDR_BURST2_MISC_SRC2_MAX_BL_SHIFT, 4)
+
+/* DDR_CTRL_CFG (DDR controller configuration) */
+#define QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT 0
+#define QCA_DDR_CTRL_CFG_SDRAM_EN_MASK BIT(QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT)
+#define QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT 1
+#define QCA_DDR_CTRL_CFG_HALF_WIDTH_MASK BIT(QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT)
+#define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT 2
+#define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_MASK BIT(QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT)
+#define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT 3
+#define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_MASK BIT(QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT)
+#define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT 4
+#define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_MASK BIT(QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT)
+#define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT 6
+#define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_MASK BIT(QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT)
+
+/* DDR_CONFIG3 register (DDR DRAM configuration 3) */
+#define QCA_DDR_CFG3_TRFC_LSB_SHIFT 0
+#define QCA_DDR_CFG3_TRFC_LSB_MASK BITS(QCA_DDR_CFG3_TRFC_LSB_SHIFT, 2)
+#define QCA_DDR_CFG3_TRAS_MSB_SHIFT 2
+#define QCA_DDR_CFG3_TRAS_MSB_MASK BIT(QCA_DDR_CFG3_TRAS_MSB_SHIFT)
+#define QCA_DDR_CFG3_TWR_MSB_SHIFT 3
+#define QCA_DDR_CFG3_TWR_MSB_MASK BIT(QCA_DDR_CFG3_TWR_MSB_SHIFT)
+
+/* DDR_BIST (unknown, not described in datasheet, based on code only) */
+#define QCA_DDR_BIST_TEST_EN_SHIFT 0
+#define QCA_DDR_BIST_TEST_EN_MASK BIT(QCA_DDR_BIST_TEST_EN_SHIFT)
+
+/* DDR_BIST_STATUS (unknown, not described in datasheet, based on code only) */
+#define QCA_DDR_BIST_STATUS_DONE_SHIFT 0
+#define QCA_DDR_BIST_STATUS_DONE_MASK BIT(QCA_DDR_BIST_STATUS_DONE_SHIFT)
+#define QCA_DDR_BIST_STATUS_PASS_CNT_SHIFT 1
+#define QCA_DDR_BIST_STATUS_PASS_CNT_MASK BITS(QCA_DDR_BIST_STATUS_PASS_CNT_SHIFT, 8)
+#define QCA_DDR_BIST_STATUS_FAIL_CNT_SHIFT 9
+#define QCA_DDR_BIST_STATUS_FAIL_CNT_MASK BITS(QCA_DDR_BIST_STATUS_FAIL_CNT_SHIFT, 8)
+
+/* DDR_PERF_COMP_ADDR_1 (unknown, not described in datasheet, based on code only) */
+#define QCA_DDR_PERF_COMP_ADDR_1_TEST_CNT_SHIFT 1
+#define QCA_DDR_PERF_COMP_ADDR_1_TEST_CNT_MASK BITS(QCA_DDR_PERF_COMP_ADDR_1_TEST_CNT_SHIFT, 8)
+
+/*
+ * Low-Speed UART registers
+ */
+#define QCA_LSUART_RBR_REG QCA_LSUART_BASE_REG + 0x00
+#define QCA_LSUART_THR_REG QCA_LSUART_BASE_REG + 0x00
+#define QCA_LSUART_DLL_REG QCA_LSUART_BASE_REG + 0x00
+#define QCA_LSUART_DLH_REG QCA_LSUART_BASE_REG + 0x04
+#define QCA_LSUART_IER_REG QCA_LSUART_BASE_REG + 0x04
+#define QCA_LSUART_IIR_REG QCA_LSUART_BASE_REG + 0x08
+#define QCA_LSUART_FCR_REG QCA_LSUART_BASE_REG + 0x08
+#define QCA_LSUART_LCR_REG QCA_LSUART_BASE_REG + 0x0C
+#define QCA_LSUART_MCR_REG QCA_LSUART_BASE_REG + 0x10
+#define QCA_LSUART_LSR_REG QCA_LSUART_BASE_REG + 0x14
+#define QCA_LSUART_MSR_REG QCA_LSUART_BASE_REG + 0x18
+
+/*
+ * Low-Speed UART registers BIT fields
+ */
+
+/* RBR register (Receive buffer) */
+#define QCA_LSUART_RBR_RBR_SHIFT 0
+#define QCA_LSUART_RBR_RBR_MASK BITS(QCA_LSUART_RBR_RBR_SHIFT, 8)
+
+/* THR register (Transmit holding) */
+#define QCA_LSUART_THR_THR_SHIFT 0
+#define QCA_LSUART_THR_THR_MASK BITS(QCA_LSUART_THR_THR_SHIFT, 8)
+
+/* DLL register (Divisor latch low) */
+#define QCA_LSUART_DLL_DLL_SHIFT 0
+#define QCA_LSUART_DLL_DLL_MASK BITS(QCA_LSUART_DLL_DLL_SHIFT, 8)
+
+/* DLH register (Divisor latch high) */
+#define QCA_LSUART_DLH_DLH_SHIFT 0
+#define QCA_LSUART_DLH_DLH_MASK BITS(QCA_LSUART_DLH_DLH_SHIFT, 8)
+
+/* IER register (Interrupt enable) */
+#define QCA_LSUART_IER_ERBFI_SHIFT 0
+#define QCA_LSUART_IER_ERBFI_MASK BIT(QCA_LSUART_IER_ERBFI_SHIFT)
+#define QCA_LSUART_IER_ETBEI_SHIFT 1
+#define QCA_LSUART_IER_ETBEI_MASK BIT(QCA_LSUART_IER_ETBEI_SHIFT)
+#define QCA_LSUART_IER_ELSI_SHIFT 2
+#define QCA_LSUART_IER_ELSI_MASK BIT(QCA_LSUART_IER_ELSI_SHIFT)
+#define QCA_LSUART_IER_EDDSI_SHIFT 3
+#define QCA_LSUART_IER_EDDSI_MASK BIT(QCA_LSUART_IER_EDDSI_SHIFT)
+
+/* IIR register (Interrupt identity) */
+#define QCA_LSUART_IIR_IID_SHIFT 0
+#define QCA_LSUART_IIR_IID_MASK BITS(QCA_LSUART_IIR_IID_SHIFT, 4)
+#define QCA_LSUART_IIR_FIFO_STATUS_SHIFT 6
+#define QCA_LSUART_IIR_FIFO_STATUS_MASK BITS(QCA_LSUART_IIR_FIFO_STATUS_SHIFT, 2)
+
+/* FCR register (FIFO control) */
+#define QCA_LSUART_FCR_FIFO_EN_SHIFT 0
+#define QCA_LSUART_FCR_EDDSI_MASK BIT(QCA_LSUART_FCR_FIFO_EN_SHIFT)
+#define QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT 1
+#define QCA_LSUART_FCR_RCVR_FIFO_RST_MASK BIT(QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT)
+#define QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT 2
+#define QCA_LSUART_FCR_XMIT_FIFO_RST_MASK BIT(QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT)
+#define QCA_LSUART_FCR_DMA_MODE_SHIFT 3
+#define QCA_LSUART_FCR_DMA_MODE_MASK BIT(QCA_LSUART_FCR_DMA_MODE_SHIFT)
+#define QCA_LSUART_FCR_RCVR_TRIG_SHIFT 6
+#define QCA_LSUART_FCR_RCVR_TRIG_MASK BITS(QCA_LSUART_FCR_RCVR_TRIG_SHIFT, 2)
+
+/* LCR register (Line control) */
+#define QCA_LSUART_LCR_CLS_SHIFT 0
+#define QCA_LSUART_LCR_CLS_MASK BITS(QCA_LSUART_LCR_CLS_SHIFT, 2)
+#define QCA_LSUART_LCR_CLS_5BIT_VAL 0x0
+#define QCA_LSUART_LCR_CLS_6BIT_VAL 0x1
+#define QCA_LSUART_LCR_CLS_7BIT_VAL 0x2
+#define QCA_LSUART_LCR_CLS_8BIT_VAL 0x3
+#define QCA_LSUART_LCR_STOP_SHIFT 2
+#define QCA_LSUART_LCR_STOP_MASK BIT(QCA_LSUART_LCR_STOP_SHIFT)
+#define QCA_LSUART_LCR_PEN_SHIFT 3
+#define QCA_LSUART_LCR_PEN_MASK BIT(QCA_LSUART_LCR_PEN_SHIFT)
+#define QCA_LSUART_LCR_EPS_SHIFT 4
+#define QCA_LSUART_LCR_EPS_MASK BIT(QCA_LSUART_LCR_EPS_SHIFT)
+#define QCA_LSUART_LCR_BREAK_SHIFT 6
+#define QCA_LSUART_LCR_BREAK_MASK BIT(QCA_LSUART_LCR_BREAK_SHIFT)
+#define QCA_LSUART_LCR_DLAB_SHIFT 7
+#define QCA_LSUART_LCR_DLAB_MASK BIT(QCA_LSUART_LCR_DLAB_SHIFT)
+
+/* MCR register (Modem control) */
+#define QCA_LSUART_MCR_DTR_SHIFT 0
+#define QCA_LSUART_MCR_DTR_MASK BIT(QCA_LSUART_MCR_DTR_SHIFT)
+#define QCA_LSUART_MCR_RTS_SHIFT 1
+#define QCA_LSUART_MCR_RTS_MASK BIT(QCA_LSUART_MCR_RTS_SHIFT)
+#define QCA_LSUART_MCR_OUT1_SHIFT 2
+#define QCA_LSUART_MCR_OUT1_MASK BIT(QCA_LSUART_MCR_OUT1_SHIFT)
+#define QCA_LSUART_MCR_OUT2_SHIFT 3
+#define QCA_LSUART_MCR_OUT2_MASK BIT(QCA_LSUART_MCR_OUT2_SHIFT)
+#define QCA_LSUART_MCR_LOOPBACK_SHIFT 5
+#define QCA_LSUART_MCR_LOOPBACK_MASK BIT(QCA_LSUART_MCR_LOOPBACK_SHIFT)
+
+/* LSR register (Line status) */
+#define QCA_LSUART_LSR_DR_SHIFT 0
+#define QCA_LSUART_LSR_DR_MASK BIT(QCA_LSUART_LSR_DR_SHIFT)
+#define QCA_LSUART_LSR_OE_SHIFT 1
+#define QCA_LSUART_LSR_OE_MASK BIT(QCA_LSUART_LSR_OE_SHIFT)
+#define QCA_LSUART_LSR_PE_SHIFT 2
+#define QCA_LSUART_LSR_PE_MASK BIT(QCA_LSUART_LSR_PE_SHIFT)
+#define QCA_LSUART_LSR_FE_SHIFT 3
+#define QCA_LSUART_LSR_FE_MASK BIT(QCA_LSUART_LSR_FE_SHIFT)
+#define QCA_LSUART_LSR_BI_SHIFT 4
+#define QCA_LSUART_LSR_BI_MASK BIT(QCA_LSUART_LSR_BI_SHIFT)
+#define QCA_LSUART_LSR_THRE_SHIFT 5
+#define QCA_LSUART_LSR_THRE_MASK BIT(QCA_LSUART_LSR_THRE_SHIFT)
+#define QCA_LSUART_LSR_TEMT_SHIFT 6
+#define QCA_LSUART_LSR_TEMT_MASK BIT(QCA_LSUART_LSR_TEMT_SHIFT)
+#define QCA_LSUART_LSR_FERR_SHIFT 7
+#define QCA_LSUART_LSR_FERR_MASK BIT(QCA_LSUART_LSR_FERR_SHIFT)
+
+/* MCR register (Modem status) */
+#define QCA_LSUART_MCR_DCTS_SHIFT 0
+#define QCA_LSUART_MCR_DCTS_MASK BIT(QCA_LSUART_MCR_DCTS_SHIFT)
+#define QCA_LSUART_MCR_DDSR_SHIFT 1
+#define QCA_LSUART_MCR_DDSR_MASK BIT(QCA_LSUART_MCR_DDSR_SHIFT)
+#define QCA_LSUART_MCR_TERI_SHIFT 2
+#define QCA_LSUART_MCR_TERI_MASK BIT(QCA_LSUART_MCR_TERI_SHIFT)
+#define QCA_LSUART_MCR_DDCD_SHIFT 3
+#define QCA_LSUART_MCR_DDCD_MASK BIT(QCA_LSUART_MCR_DDCD_SHIFT)
+#define QCA_LSUART_MCR_CTS_SHIFT 4
+#define QCA_LSUART_MCR_CTS_MASK BIT(QCA_LSUART_MCR_CTS_SHIFT)
+#define QCA_LSUART_MCR_DSR_SHIFT 5
+#define QCA_LSUART_MCR_DSR_MASK BIT(QCA_LSUART_MCR_DSR_SHIFT)
+#define QCA_LSUART_MCR_RI_SHIFT 6
+#define QCA_LSUART_MCR_RI_MASK BIT(QCA_LSUART_MCR_RI_SHIFT)
+#define QCA_LSUART_MCR_DCD_SHIFT 7
+#define QCA_LSUART_MCR_DCD_MASK BIT(QCA_LSUART_MCR_DCD_SHIFT)
+
+/*
+ * High-Speed UART registers
+ */
+#define QCA_HSUART_DATA_REG QCA_HSUART_BASE_REG + 0x00
+#define QCA_HSUART_CS_REG QCA_HSUART_BASE_REG + 0x04
+#define QCA_HSUART_CLK_REG QCA_HSUART_BASE_REG + 0x08
+#define QCA_HSUART_INT_REG QCA_HSUART_BASE_REG + 0x0C
+#define QCA_HSUART_INT_EN_REG QCA_HSUART_BASE_REG + 0x10
+
+/*
+ * High-Speed UART registers BIT fields
+ */
+
+/* UART_DATA register (UART transmit and RX FIFO interface ) */
+#define QCA_HSUART_DATA_TX_RX_DATA_SHIFT 0
+#define QCA_HSUART_DATA_TX_RX_DATA_MASK BITS(QCA_HSUART_DATA_TX_RX_DATA_SHIFT, 8)
+#define QCA_HSUART_DATA_RX_CSR_SHIFT 8
+#define QCA_HSUART_DATA_RX_CSR_MASK BIT(QCA_HSUART_DATA_RX_CSR_SHIFT)
+#define QCA_HSUART_DATA_TX_CSR_SHIFT 9
+#define QCA_HSUART_DATA_TX_CSR_MASK BIT(QCA_HSUART_DATA_TX_CSR_SHIFT)
+
+/* UART_CS register (UART configuration and status) */
+#define QCA_HSUART_CS_PAR_MODE_SHIFT 0
+#define QCA_HSUART_CS_PAR_MODE_MASK BITS(QCA_HSUART_CS_PAR_MODE_SHIFT, 2)
+#define QCA_HSUART_CS_PAR_MODE_NO_VAL 0x0
+#define QCA_HSUART_CS_PAR_MODE_ODD_VAL 0x2
+#define QCA_HSUART_CS_PAR_MODE_OVEN_VAL 0x3
+#define QCA_HSUART_CS_IFACE_MODE_SHIFT 2
+#define QCA_HSUART_CS_IFACE_MODE_MASK BITS(QCA_HSUART_CS_IFACE_MODE_SHIFT, 2)
+#define QCA_HSUART_CS_IFACE_MODE_DISABLE_VAL 0x0
+#define QCA_HSUART_CS_IFACE_MODE_DTE_VAL 0x1
+#define QCA_HSUART_CS_IFACE_MODE_DCE_VAL 0x2
+#define QCA_HSUART_CS_FLOW_MODE_SHIFT 4
+#define QCA_HSUART_CS_FLOW_MODE_MASK BITS(QCA_HSUART_CS_FLOW_MODE_SHIFT, 2)
+#define QCA_HSUART_CS_FLOW_MODE_NO_VAL 0x0
+#define QCA_HSUART_CS_FLOW_MODE_HW_VAL 0x2
+#define QCA_HSUART_CS_FLOW_MODE_INV_VAL 0x3
+#define QCA_HSUART_CS_DMA_EN_SHIFT 6
+#define QCA_HSUART_CS_DMA_EN_MASK BIT(QCA_HSUART_CS_DMA_EN_SHIFT)
+#define QCA_HSUART_CS_RX_READY_ORIDE_SHIFT 7
+#define QCA_HSUART_CS_RX_READY_ORIDE_MASK BIT(QCA_HSUART_CS_RX_READY_ORIDE_SHIFT)
+#define QCA_HSUART_CS_TX_READY_ORIDE_SHIFT 8
+#define QCA_HSUART_CS_TX_READY_ORIDE_MASK BIT(QCA_HSUART_CS_TX_READY_ORIDE_SHIFT)
+#define QCA_HSUART_CS_TX_READY_SHIFT 9
+#define QCA_HSUART_CS_TX_READY_MASK BIT(QCA_HSUART_CS_TX_READY_SHIFT)
+#define QCA_HSUART_CS_RX_BREAK_SHIFT 10
+#define QCA_HSUART_CS_RX_BREAK_MASK BIT(QCA_HSUART_CS_RX_BREAK_SHIFT)
+#define QCA_HSUART_CS_TX_BREAK_SHIFT 11
+#define QCA_HSUART_CS_TX_BREAK_MASK BIT(QCA_HSUART_CS_TX_BREAK_SHIFT)
+#define QCA_HSUART_CS_HOST_INT_SHIFT 12
+#define QCA_HSUART_CS_HOST_INT_MASK BIT(QCA_HSUART_CS_HOST_INT_SHIFT)
+#define QCA_HSUART_CS_HOST_INT_EN_SHIFT 13
+#define QCA_HSUART_CS_HOST_INT_EN_MASK BIT(QCA_HSUART_CS_HOST_INT_EN_SHIFT)
+#define QCA_HSUART_CS_TX_BUSY_SHIFT 14
+#define QCA_HSUART_CS_TX_BUSY_MASK BIT(QCA_HSUART_CS_TX_BUSY_SHIFT)
+#define QCA_HSUART_CS_RX_BUSY_SHIFT 15
+#define QCA_HSUART_CS_RX_BUSY_MASK BIT(QCA_HSUART_CS_RX_BUSY_SHIFT)
+
+/* UART_CLOCK register (UART clock) */
+#define QCA_HSUART_CLK_STEP_SHIFT 0
+#define QCA_HSUART_CLK_STEP_MASK BITS(QCA_HSUART_CLK_STEP_SHIFT, 16)
+#define QCA_HSUART_CLK_STEP_MAX_VAL 0x3333
+#define QCA_HSUART_CLK_SCALE_SHIFT 16
+#define QCA_HSUART_CLK_SCALE_MASK BITS(QCA_HSUART_CLK_SCALE_SHIFT, 8)
+#define QCA_HSUART_CLK_SCALE_MAX_VAL 0xFF
+
+/* UART_INT register (UART interrupt/control status) */
+#define QCA_HSUART_INT_RX_VALID_SHIFT 0
+#define QCA_HSUART_INT_RX_VALID_MASK BIT(QCA_HSUART_INT_RX_VALID_SHIFT)
+#define QCA_HSUART_INT_TX_READY_SHIFT 1
+#define QCA_HSUART_INT_TX_READY_MASK BIT(QCA_HSUART_INT_TX_READY_SHIFT)
+#define QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT 2
+#define QCA_HSUART_INT_RX_FRAMING_ERR_MASK BIT(QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT)
+#define QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT 3
+#define QCA_HSUART_INT_RX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT)
+#define QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT 4
+#define QCA_HSUART_INT_TX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT)
+#define QCA_HSUART_INT_RX_PARITY_ERR_SHIFT 5
+#define QCA_HSUART_INT_RX_PARITY_ERR_MASK BIT(QCA_HSUART_INT_RX_PARITY_ERR_SHIFT)
+#define QCA_HSUART_INT_RX_BREAK_ON_SHIFT 6
+#define QCA_HSUART_INT_RX_BREAK_ON_MASK BIT(QCA_HSUART_INT_RX_BREAK_ON_SHIFT)
+#define QCA_HSUART_INT_RX_BREAK_OFF_SHIFT 7
+#define QCA_HSUART_INT_RX_BREAK_OFF_MASK BIT(QCA_HSUART_INT_RX_BREAK_OFF_SHIFT)
+#define QCA_HSUART_INT_RX_FULL_SHIFT 8
+#define QCA_HSUART_INT_RX_FULL_MASK BIT(QCA_HSUART_INT_RX_FULL_SHIFT)
+#define QCA_HSUART_INT_TX_EMPTY_SHIFT 9
+#define QCA_HSUART_INT_TX_EMPTY_MASK BIT(QCA_HSUART_INT_TX_EMPTY_SHIFT)
+
+/* UART_INT_EN register (UART interrupt enable) */
+#define QCA_HSUART_INT_EN_RX_VALID_SHIFT 0
+#define QCA_HSUART_INT_EN_RX_VALID_MASK BIT(QCA_HSUART_INT_EN_RX_VALID_SHIFT)
+#define QCA_HSUART_INT_EN_TX_READY_SHIFT 1
+#define QCA_HSUART_INT_EN_TX_READY_MASK BIT(QCA_HSUART_INT_EN_TX_READY_SHIFT)
+#define QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT 2
+#define QCA_HSUART_INT_EN_RX_FRAMING_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT)
+#define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT 3
+#define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT)
+#define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT 4
+#define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT)
+#define QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT 5
+#define QCA_HSUART_INT_EN_RX_PARITY_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT)
+#define QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT 6
+#define QCA_HSUART_INT_EN_RX_BREAK_ON_MASK BIT(QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT)
+#define QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT 7
+#define QCA_HSUART_INT_EN_RX_BREAK_OFF_MASK BIT(QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT)
+#define QCA_HSUART_INT_EN_RX_FULL_SHIFT 8
+#define QCA_HSUART_INT_EN_RX_FULL_MASK BIT(QCA_HSUART_INT_EN_RX_FULL_SHIFT)
+#define QCA_HSUART_INT_EN_TX_EMPTY_SHIFT 9
+#define QCA_HSUART_INT_EN_TX_EMPTY_MASK BIT(QCA_HSUART_INT_EN_TX_EMPTY_SHIFT)
+
+
+/*
+ * GPIO registers
+ */
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_GPIO_COUNT 30
+#elif (SOC_TYPE & QCA_AR934X_SOC)
+ #define QCA_GPIO_COUNT 23
+#elif (SOC_TYPE & QCA_QCA953X_SOC)
+ #define QCA_GPIO_COUNT 18
+#elif (SOC_TYPE & QCA_QCA955X_SOC)
+ #define QCA_GPIO_COUNT 24
+#endif
+
+#define QCA_GPIO_OE_REG QCA_GPIO_BASE_REG + 0x00
+#define QCA_GPIO_IN_REG QCA_GPIO_BASE_REG + 0x04
+#define QCA_GPIO_OUT_REG QCA_GPIO_BASE_REG + 0x08
+#define QCA_GPIO_SET_REG QCA_GPIO_BASE_REG + 0x0C
+#define QCA_GPIO_CLEAR_REG QCA_GPIO_BASE_REG + 0x10
+#define QCA_GPIO_INT_EN_REG QCA_GPIO_BASE_REG + 0x14
+#define QCA_GPIO_INT_TYPE_REG QCA_GPIO_BASE_REG + 0x18
+#define QCA_GPIO_INT_POLARITY_REG QCA_GPIO_BASE_REG + 0x1C
+#define QCA_GPIO_INT_PENDING_REG QCA_GPIO_BASE_REG + 0x20
+#define QCA_GPIO_INT_MASK_REG QCA_GPIO_BASE_REG + 0x24
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_GPIO_FUNC_1_REG QCA_GPIO_BASE_REG + 0x28
+ #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x2C
+ #define QCA_GPIO_FUNC_2_REG QCA_GPIO_BASE_REG + 0x30
+ #define QCA_GPIO_WLAN_MUX_SET0_REG QCA_GPIO_BASE_REG + 0x34
+ #define QCA_GPIO_WLAN_MUX_SET1_REG QCA_GPIO_BASE_REG + 0x38
+ #define QCA_GPIO_WLAN_MUX_SET2_REG QCA_GPIO_BASE_REG + 0x3C
+ #define QCA_GPIO_WLAN_MUX_SET3_REG QCA_GPIO_BASE_REG + 0x40
+#else
+ #if (SOC_TYPE & QCA_QCA955X_SOC)
+ #define QCA_GPIO_SPARE_BITS_REG QCA_GPIO_BASE_REG + 0x28
+ #else
+ #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x28
+ #endif
+
+ #define QCA_GPIO_OUT_FUNC0_REG QCA_GPIO_BASE_REG + 0x2C
+ #define QCA_GPIO_OUT_FUNC1_REG QCA_GPIO_BASE_REG + 0x30
+ #define QCA_GPIO_OUT_FUNC2_REG QCA_GPIO_BASE_REG + 0x34
+ #define QCA_GPIO_OUT_FUNC3_REG QCA_GPIO_BASE_REG + 0x38
+ #define QCA_GPIO_OUT_FUNC4_REG QCA_GPIO_BASE_REG + 0x3C
+ #define QCA_GPIO_OUT_FUNC5_REG QCA_GPIO_BASE_REG + 0x40
+ #define QCA_GPIO_IN_EN0_REG QCA_GPIO_BASE_REG + 0x44
+ #define QCA_GPIO_IN_EN1_REG QCA_GPIO_BASE_REG + 0x48
+ #define QCA_GPIO_IN_EN2_REG QCA_GPIO_BASE_REG + 0x4C
+ #define QCA_GPIO_IN_EN3_REG QCA_GPIO_BASE_REG + 0x50
+ #define QCA_GPIO_IN_EN4_REG QCA_GPIO_BASE_REG + 0x54
+ #define QCA_GPIO_IN_EN9_REG QCA_GPIO_BASE_REG + 0x68
+ #define QCA_GPIO_FUNC_REG QCA_GPIO_BASE_REG + 0x6C
+#endif
+
+/*
+ * GPIO registers BIT fields
+ */
+
+/* GPIO_FUNCTION_1/2 register (GPIO function) */
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT 0
+ #define QCA_GPIO_FUNC_1_JTAG_DIS_MASK BIT(QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT)
+ #define QCA_GPIO_FUNC_1_UART_EN_SHIFT 1
+ #define QCA_GPIO_FUNC_1_UART_EN_MASK BIT(QCA_GPIO_FUNC_1_UART_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT 2
+ #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_MASK BIT(QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT 3
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT 4
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT 5
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT 6
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT 7
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT 13
+ #define QCA_GPIO_FUNC_1_SPI_CS_EN1_MASK BIT(QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT)
+ #define QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT 14
+ #define QCA_GPIO_FUNC_1_SPI_CS_EN2_MASK BIT(QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT)
+ #define QCA_GPIO_FUNC_1_SPI_EN_SHIFT 18
+ #define QCA_GPIO_FUNC_1_SPI_EN_MASK BIT(QCA_GPIO_FUNC_1_SPI_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT 23
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT)
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT 24
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT)
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT 25
+ #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT)
+ #define QCA_GPIO_FUNC_1_I2S_EN_SHIFT 26
+ #define QCA_GPIO_FUNC_1_I2S_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT 27
+ #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT 29
+ #define QCA_GPIO_FUNC_1_I2S_22_18_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT 30
+ #define QCA_GPIO_FUNC_1_SPDIF_EN_MASK BIT(QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT)
+ #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT 31
+ #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_MASK BIT(QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT)
+
+ #define QCA_GPIO_FUNC_2_MIC_DIS_SHIFT 0
+ #define QCA_GPIO_FUNC_2_MIC_DIS_MASK BIT(QCA_GPIO_FUNC_2_MIC_DIS_SHIFT)
+ #define QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT 1
+ #define QCA_GPIO_FUNC_2_I2S_ON_LED_MASK BIT(QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT)
+ #define QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT 2
+ #define QCA_GPIO_FUNC_2_SPDIF_ON23_MASK BIT(QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT)
+ #define QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT 3
+ #define QCA_GPIO_FUNC_2_I2SCK_ON1_MASK BIT(QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT)
+ #define QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT 4
+ #define QCA_GPIO_FUNC_2_I2SWS_ON0_MASK BIT(QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT)
+ #define QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT 5
+ #define QCA_GPIO_FUNC_2_I2SSD_ON12_MASK BIT(QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT)
+ #define QCA_GPIO_FUNC_2_WPS_DIS_SHIFT 8
+ #define QCA_GPIO_FUNC_2_WPS_DIS_MASK BIT(QCA_GPIO_FUNC_2_WPS_DIS_SHIFT)
+ #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT 9
+ #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_MASK BIT(QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT)
+ #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT 10
+ #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_MASK BIT(QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT)
+ #define QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT 11
+ #define QCA_GPIO_FUNC_2_USB_LED_ON1_MASK BIT(QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT)
+ #define QCA_GPIO_FUNC_2_LNA_ON28_SHIFT 12
+ #define QCA_GPIO_FUNC_2_LNA_ON28_MASK BIT(QCA_GPIO_FUNC_2_LNA_ON28_SHIFT)
+ #define QCA_GPIO_FUNC_2_SLIC_EN_SHIFT 13
+ #define QCA_GPIO_FUNC_2_SLIC_EN_MASK BIT(QCA_GPIO_FUNC_2_SLIC_EN_SHIFT)
+ #define QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT 14
+ #define QCA_GPIO_FUNC_2_SLIC_ON18_22_MASK BIT(QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT)
+ #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT 15
+ #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_MASK BIT(QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT)
+ #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT 16
+ #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_MASK BITS(QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT, 3)
+#endif
+
+/*
+ * GPIO MUX
+ */
+#define QCA_GPIO_OUT_FUNCX_GPIOX_EN_SHIFT(_gpio) ((_gpio % 4) * 8)
+#define QCA_GPIO_OUT_FUNCX_GPIOX_EN_MASK(_gpio) BIT(((_gpio % 4) * 8), 8)
+
+#define QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT 0
+#define QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT 0
+#define QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT 0
+#define QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT 0
+#define QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT 0
+#define QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT 0
+#define QCA_GPIO_OUT_FUNCX_GPIO0_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO4_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO8_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO12_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO16_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO20_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT, 8)
+
+#define QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT 8
+#define QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT 8
+#define QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT 8
+#define QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT 8
+#define QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT 8
+#define QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT 8
+#define QCA_GPIO_OUT_FUNCX_GPIO1_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO5_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO9_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO13_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO17_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO21_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT, 8)
+
+#define QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT 16
+#define QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT 16
+#define QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT 16
+#define QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT 16
+#define QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT 16
+#define QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT 16
+#define QCA_GPIO_OUT_FUNCX_GPIO2_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO6_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO10_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO14_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO18_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO22_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT, 8)
+
+#define QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT 24
+#define QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT 24
+#define QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT 24
+#define QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT 24
+#define QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT 24
+#define QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT 24
+#define QCA_GPIO_OUT_FUNCX_GPIO3_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO7_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO11_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO15_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO19_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT, 8)
+#define QCA_GPIO_OUT_FUNCX_GPIO23_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT, 8)
+
+/* GPIO output select values (for MUX) */
+#define QCA_GPIO_OUT_MUX_GPIO_VAL 0
+#define QCA_GPIO_OUT_MUX_MII_EXT_MDI_VAL 1
+#define QCA_GPIO_OUT_MUX_SYS_RST_L_VAL 1
+#define QCA_GPIO_OUT_MUX_NAND_CS0_VAL 1
+#define QCA_GPIO_OUT_MUX_BOOT_RXT_MDI_VAL 2
+#define QCA_GPIO_OUT_MUX_SPI_CS0_VAL 9
+
+/* 5-port ethernet switch activity LEDs */
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN1_VAL 26
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN2_VAL 27
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN3_VAL 28
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN4_VAL 29
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN5_VAL 30
+
+/* 5-port ethernet switch collision detect LEDs */
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN1_VAL 31
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN2_VAL 32
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN3_VAL 33
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN4_VAL 34
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN5_VAL 35
+
+/* 5-port ethernet switch full/half duplex LEDs */
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN1_VAL 36
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN2_VAL 37
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN3_VAL 38
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN4_VAL 39
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN5_VAL 40
+
+/* 5-port ethernet switch link indicator LEDs */
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK1_VAL 41
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK2_VAL 42
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK3_VAL 43
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK4_VAL 44
+#define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK5_VAL 45
+
+#if (SOC_TYPE & QCA_AR934X_SOC)
+ #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL 4
+ #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL 5
+ #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL 6
+ #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL 7
+ #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL 8
+ #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL 10
+ #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL 11
+ #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL 12
+ #define QCA_GPIO_OUT_MUX_I2S_WS_VAL 13
+ #define QCA_GPIO_OUT_MUX_I2S_SD_VAL 14
+ #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL 15
+ #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 16
+ #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 17
+ #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 18
+ #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 19
+ #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 20
+ #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 21
+ #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL 22
+ #define QCA_GPIO_OUT_MUX_CLK_OBS7_VAL 23
+ #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL 24
+ #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL 25
+ #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 46
+ #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 47
+ #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 48
+ #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL 49
+ #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 50
+ #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 51
+ #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL 72
+ #define QCA_GPIO_OUT_MUX_BT_ANT_VAL 73
+ #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 74
+ #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL 78
+ #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL_VAL 79
+ #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL_VAL 80
+ #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 84
+ #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 87
+#else
+ #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL 3
+ #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL 4
+ #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL 5
+ #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL 8
+ #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL 10
+ #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL 11
+ #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL 12
+ #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL 13
+ #define QCA_GPIO_OUT_MUX_I2S_WS_VAL 14
+ #define QCA_GPIO_OUT_MUX_I2S_SD_VAL 15
+ #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL 16
+ #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL 17
+ #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL 18
+ #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL 19
+ #define QCA_GPIO_OUT_MUX_HSUART_RXD_VAL 20 /* TODO: RXD is INPUT, mistake in QCA9558 datasheet? */
+ #define QCA_GPIO_OUT_MUX_HSUART_CTS_VAL 21 /* TODO: CTS is INPUT, mistake in QCA9558 datasheet? */
+ #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL 22
+ #define QCA_GPIO_OUT_MUX_SRIF_OUT_VAL 23
+
+ #if (SOC_TYPE & QCA_QCA955X_SOC)
+ #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_VAL 24
+ #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_VAL 25
+ #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_VAL 26
+ #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_VAL 27
+ #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_INV_VAL 28
+ #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_INV_VAL 29
+ #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_INV_VAL 30
+ #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_INV_VAL 31
+ #define QCA_GPIO_OUT_MUX_GE1_MII_MDO_VAL 32
+ #define QCA_GPIO_OUT_MUX_GE1_MII_MDC_VAL 33
+ #define QCA_GPIO_OUT_MUX_SWCOM2_VAL 38
+ #define QCA_GPIO_OUT_MUX_SWCOM3_VAL 39
+ #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL 40
+ #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL 41
+ #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 42
+ #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 43
+ #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 44
+ #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL 45
+ #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 46
+ #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 47
+ #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL 68
+ #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 70
+ #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_STROBE_VAL 71
+ #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_DATA_VAL 72
+ #define QCA_GPIO_OUT_MUX_NAND_CS1_VAL 73
+ #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 74
+ #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL 75
+ #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 76
+ #define QCA_GPIO_OUT_MUX_CLK_REQ_N_EP_VAL 77
+ #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL 78
+ #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 79
+ #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 80
+ #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 81
+ #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 82
+ #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 83
+ #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 84
+ #endif
+
+ #if (SOC_TYPE & QCA_QCA953X_SOC)
+ #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL 48
+ #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL 49
+ #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 50
+ #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 51
+ #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 52
+ #define QCA_GPIO_OUT_MUX_RX_CLEAR_INT_VAL 53
+ #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 54
+ #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 55
+ #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 78
+ #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 86
+ #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 88
+ #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL 89
+ #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 90
+ #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 91
+ #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 92
+ #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 93
+ #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 94
+ #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 95
+ #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL 96
+ #endif
+#endif
+
+/* GPIO_IN_ENABLE0 register (GPIO in signals 0) */
+#define QCA_GPIO_IN_EN0_SPI_MISO_SHIFT 0
+#define QCA_GPIO_IN_EN0_SPI_MISO_MASK BITS(QCA_GPIO_IN_EN0_SPI_MISO_SHIFT, 8)
+#define QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT 8
+#define QCA_GPIO_IN_EN0_LSUART_RXD_MASK BITS(QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT ,8)
+
+/* GPIO_IN_ENABLE1 register (GPIO in signals 1) */
+#define QCA_GPIO_IN_EN1_I2S_WS_SHIFT 0
+#define QCA_GPIO_IN_EN1_I2S_WS_MASK BITS(QCA_GPIO_IN_EN1_I2S_WS_SHIFT ,8)
+#define QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT 8
+#define QCA_GPIO_IN_EN1_I2S_MIC_SD_MASK BITS(QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT ,8)
+#define QCA_GPIO_IN_EN1_I2S_CLK_SHIFT 16
+#define QCA_GPIO_IN_EN1_I2S_CLK_MASK BITS(QCA_GPIO_IN_EN1_I2S_CLK_SHIFT ,8)
+#define QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT 24
+#define QCA_GPIO_IN_EN1_I2S_MCLK_MASK BITS(QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT ,8)
+
+/* GPIO_IN_ENABLE9 register (GPIO in signals 9) */
+#define QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT 16
+#define QCA_GPIO_IN_EN9_HSUART_RXD_MASK BITS(QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT ,8)
+#define QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT 24
+#define QCA_GPIO_IN_EN9_HSUART_CTS_MASK BITS(QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT ,8)
+
+/* GPIO_FUNCTION register (GPIO function) */
+#define QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT 0
+#define QCA_GPIO_FUNC_GPIO_SRIF_EN_MASK BIT(QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT)
+#define QCA_GPIO_FUNC_JTAG_DIS_SHIFT 1
+#define QCA_GPIO_FUNC_JTAG_DIS_MASK BIT(QCA_GPIO_FUNC_JTAG_DIS_SHIFT)
+#define QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT 2
+#define QCA_GPIO_FUNC_CLK_OBS0_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT)
+#define QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT 3
+#define QCA_GPIO_FUNC_CLK_OBS1_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT)
+#define QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT 4
+#define QCA_GPIO_FUNC_CLK_OBS2_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT)
+#define QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT 5
+#define QCA_GPIO_FUNC_CLK_OBS3_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT)
+#define QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT 6
+#define QCA_GPIO_FUNC_CLK_OBS4_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT)
+#define QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT 7
+#define QCA_GPIO_FUNC_CLK_OBS5_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT)
+#define QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT 8
+#define QCA_GPIO_FUNC_CLK_OBS6_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT)
+#define QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT 9
+#define QCA_GPIO_FUNC_CLK_OBS7_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT)
+
+/*
+ * PLL control registers
+ */
+#define QCA_PLL_CPU_PLL_CFG_REG QCA_PLL_BASE_REG + 0x00
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_PLL_CPU_PLL_CFG2_REG QCA_PLL_BASE_REG + 0x04
+ #define QCA_PLL_CPU_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG QCA_PLL_BASE_REG + 0x10
+ #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x14
+ #define QCA_PLL_ETHSW_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24
+ #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C
+ #define QCA_PLL_USB_SUSPEND_REG QCA_PLL_BASE_REG + 0x40
+ #define QCA_PLL_WLAN_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x44
+#else
+ #define QCA_PLL_DDR_PLL_CFG_REG QCA_PLL_BASE_REG + 0x04
+ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08
+
+ #if (SOC_TYPE & QCA_QCA955X_SOC)
+ #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x0C
+ #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x10
+ #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x14
+ #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x18
+ #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x1C
+ #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x20
+ #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x24
+ #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x28
+ #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x2C
+ #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x30
+ #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x34
+ #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x38
+ #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x40
+ #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44
+ #define QCA_PLL_ETH_SGMII_CTRL_REG QCA_PLL_BASE_REG + 0x48
+ #define QCA_PLL_ETH_SGMII_SERDES_REG QCA_PLL_BASE_REG + 0x4C
+ #define QCA_PLL_SLIC_PWM_DIV_REG QCA_PLL_BASE_REG + 0x50
+ #else
+ #define QCA_PLL_CPU_SYNC_REG QCA_PLL_BASE_REG + 0x0C
+ #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x10
+ #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x14
+ #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x18
+ #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x1C
+ #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x20
+ #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24
+
+ #if (SOC_TYPE & QCA_AR9344_SOC)
+ #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28
+ #else
+ #define QCA_PLL_CURR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28
+ #endif
+
+ #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C
+ #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x30
+ #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x34
+ #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x38
+ #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x3C
+ #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x40
+ #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44
+ #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x48
+ #endif
+#endif
+
+/*
+ * PLL control registers BIT fields
+ */
+
+/* CPU_PLL_CONFIG register (CPU phase lock loop configuration) */
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0
+ #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 10)
+ #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 10
+ #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
+ #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 16
+ #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
+ #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 21
+ #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK BIT(QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)
+ #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 23
+ #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
+#else
+ #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0
+ #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 6)
+ #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 6
+ #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
+ #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 12
+ #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
+ #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 17
+ #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK BITS(QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT, 2)
+ #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 19
+ #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
+#endif
+
+#define QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT 30
+#define QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK BIT(QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT)
+#define QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT 31
+#define QCA_PLL_CPU_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT)
+
+/* CPU_PLL_CONFIG2 register (CPU phase lock loop configuration, AR933x only) */
+#define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT 0
+#define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_MASK BITS(QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT, 12)
+
+/* CPU_CLOCK_CONTROL register (CPU clock control, AR933x only) */
+#define QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT 2
+#define QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK BIT(QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT)
+#define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT, 2)
+#define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT, 2)
+#define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT, 2)
+
+/* ETHSW_CLOCK_CONTROL register (Ethernet switch clock control, AR933x only) */
+#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT 3
+#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_MASK BIT(QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT)
+#define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT 4
+#define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_MASK BIT(QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT)
+
+/* ETH_XMII_CONTROL register (Ethernet XMII control) */
+#define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT 0
+#define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT, 8)
+#define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT 8
+#define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT, 8)
+#define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT 16
+#define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT, 8)
+#define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT 24
+#define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_MASK BIT(QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT)
+#define QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT 25
+#define QCA_PLL_ETH_XMII_CTRL_GIGE_MASK BIT(QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT)
+#define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT 26
+#define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT, 2)
+#define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT 28
+#define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT, 2)
+#define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT 30
+#define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_MASK BIT(QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT)
+#define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT 31
+#define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_MASK BIT(QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT)
+
+/* SUSPEND register (USB suspend, AR933x only) */
+#define QCA_PLL_USB_SUSPEND_EN_SHIFT 0
+#define QCA_PLL_USB_SUSPEND_EN_MASK BIT(QCA_PLL_USB_SUSPEND_EN_SHIFT)
+#define QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT 8
+#define QCA_PLL_USB_SUSPEND_RESTART_TIME_MASK BITS(QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT, 20)
+
+/* WLAN_CLOCK_CONTROL register (WLAN clock control, AR933x only) */
+#define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT 0
+#define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT)
+#define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT 1
+#define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT)
+#define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT 2
+#define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT)
+#define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT 3
+#define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT)
+#define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT 4
+#define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT)
+#define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT 8
+#define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT)
+#define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT 9
+#define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT)
+#define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT 10
+#define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT)
+#define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT 12
+#define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT)
+
+/* DDR_PLL_CONFIG register (DDR PLL configuration) */
+#define QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT 0
+#define QCA_PLL_DDR_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT, 10)
+#define QCA_PLL_DDR_PLL_CFG_NINT_SHIFT 10
+#define QCA_PLL_DDR_PLL_CFG_NINT_MASK BITS(QCA_PLL_DDR_PLL_CFG_NINT_SHIFT, 6)
+#define QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT 16
+#define QCA_PLL_DDR_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT, 5)
+#define QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT 21
+#define QCA_PLL_DDR_PLL_CFG_RANGE_MASK BITS(QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT, 2)
+#define QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT 23
+#define QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT, 3)
+#define QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT 30
+#define QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK BIT(QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT)
+#define QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT 31
+#define QCA_PLL_DDR_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT)
+
+/* CPU_DDR_CLOCK_CONTROL register (CPU DDR clock control) */
+#define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT 1
+#define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT 2
+#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT 3
+#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT 4
+#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT, 5)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT, 5)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT, 5)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT 20
+#define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT 21
+#define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT 22
+#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT 23
+#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT)
+#define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT 24
+#define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT)
+
+/* SWITCH_CLOCK_CONTROL */
+#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT 0
+#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT)
+#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT 1
+#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT)
+#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT 2
+#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT)
+#define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT 3
+#define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT)
+#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT 4
+#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT)
+#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT 5
+#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT)
+
+#if (SOC_TYPE & QCA_AR934X_SOC) |\
+ (SOC_TYPE & QCA_QCA953X_SOC)
+ #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT 6
+ #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT)
+#else
+ #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT 6
+ #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT)
+ #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT 12
+ #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT)
+ #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT 13
+ #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT)
+ #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT 14
+ #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT)
+ #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT 15
+ #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT)
+#endif
+
+#define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT 7
+#define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT)
+#define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT 8
+#define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_MASK BITS(QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT, 4)
+
+/* DDR_PLL_DITHER register (DDR PLL dither parameter) */
+#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT 0
+#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT, 10)
+#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT 10
+#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 10)
+#define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_SHIFT 20
+#define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 7)
+#define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT 27
+#define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT, 4)
+#define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT 31
+#define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT)
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ /* PLL_DITHER_FRAC register (CPU PLL dither FRAC) */
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT 0
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT, 10)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT 10
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT, 10)
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT 20
+ #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT, 10)
+
+ /* PLL_DITHER register (CPU PLL dither) */
+ #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 0
+ #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 14)
+ #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31
+ #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT)
+#else
+ /* CPU_PLL_DITHER register (CPU PLL dither parameter) */
+ #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT 0
+ #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 6)
+ #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT 6
+ #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
+ #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 12
+ #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
+ #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 18
+ #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6)
+ #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31
+ #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT)
+#endif
+
+/*
+ * PLL SRIF registers (not available in AR933x)
+ */
+#define QCA_PLL_SRIF_CPU_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x1C0
+#define QCA_PLL_SRIF_CPU_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x1C4
+#define QCA_PLL_SRIF_CPU_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x1C8
+#define QCA_PLL_SRIF_AUD_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x200
+#define QCA_PLL_SRIF_AUD_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x204
+#define QCA_PLL_SRIF_AUD_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x208
+#define QCA_PLL_SRIF_DDR_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x240
+#define QCA_PLL_SRIF_DDR_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x244
+#define QCA_PLL_SRIF_DDR_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x248
+#define QCA_PLL_SRIF_PCIE_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0xC00
+#define QCA_PLL_SRIF_PCIE_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0xC04
+#define QCA_PLL_SRIF_PCIE_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0xC08
+
+/*
+ * PLL SRIF registers BIT fields (not available in AR933x)
+ */
+
+/* DPLL1 (common for CPU, AUD, DDR and PCIE) */
+#define QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT 0
+#define QCA_PLL_SRIF_DPLL1_NFRAC_MASK BITS(QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT, 18)
+#define QCA_PLL_SRIF_DPLL1_NINT_SHIFT 18
+#define QCA_PLL_SRIF_DPLL1_NINT_MASK BITS(QCA_PLL_SRIF_DPLL1_NINT_SHIFT, 9)
+#define QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT 27
+#define QCA_PLL_SRIF_DPLL1_REFDIV_MASK BITS(QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT, 5)
+
+/* DPLL2 (common for CPU, AUD, DDR and PCIE) */
+#if (SOC_TYPE & QCA_QCA953X_SOC)
+ #define QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT 0
+ #define QCA_PLL_SRIF_DPLL2_RST_TEST_MASK BIT(QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT)
+ #define QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT 1
+ #define QCA_PLL_SRIF_DPLL2_SEL_CNT_MASK BIT(QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT)
+ #define QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT 2
+ #define QCA_PLL_SRIF_DPLL2_TEST_IN_MASK BITS(QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT, 10)
+ #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT 12
+ #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_MASK BITS(QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT, 7)
+ #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 19
+ #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 3)
+ #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 22
+ #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK BIT(QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
+ #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT 23
+ #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_MASK BIT(QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT)
+ #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT 24
+ #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_MASK BIT(QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT)
+ #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 25
+ #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 4)
+ #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 29
+ #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 2)
+ #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 31
+ #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK BIT(QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
+#else
+ #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 13
+ #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2)
+ #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 16
+ #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK BIT(QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
+ #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 19
+ #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7)
+ #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 26
+ #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KI_SHIFT, 4)
+ #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 30
+ #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK BIT(QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
+ #define QCA_PLL_SRIF_DPLL2_RANGE_SHIFT 31
+ #define QCA_PLL_SRIF_DPLL2_RANGE_MASK BIT(QCA_PLL_SRIF_DPLL2_RANGE_SHIFT)
+#endif
+
+/* DPLL3 (common for CPU, AUD, DDR and PCIE) */
+#define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT 23
+#define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_MASK BITS(QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT, 7)
+
+/*
+ * Reset control registers
+ */
+#define QCA_RST_GENERAL_TIMER1_REG QCA_RST_BASE_REG + 0x00
+#define QCA_RST_GENERAL_TIMER1_RELOAD_REG QCA_RST_BASE_REG + 0x04
+#define QCA_RST_WATCHDOG_TIMER_CTRL_REG QCA_RST_BASE_REG + 0x08
+#define QCA_RST_WATCHDOG_TIMER_REG QCA_RST_BASE_REG + 0x0C
+#define QCA_RST_MISC_INTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x10
+#define QCA_RST_MISC_INTERRUPT_MASK_REG QCA_RST_BASE_REG + 0x14
+#define QCA_RST_GLOBALINTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x18
+#define QCA_RST_RESET_REG QCA_RST_BASE_REG + 0x1C
+#define QCA_RST_REVISION_ID_REG QCA_RST_BASE_REG + 0x90
+#define QCA_RST_GENERAL_TIMER2_REG QCA_RST_BASE_REG + 0x94
+#define QCA_RST_GENERAL_TIMER2_RELOAD_REG QCA_RST_BASE_REG + 0x98
+#define QCA_RST_GENERAL_TIMER3_REG QCA_RST_BASE_REG + 0x9C
+#define QCA_RST_GENERAL_TIMER3_RELOAD_REG QCA_RST_BASE_REG + 0xA0
+#define QCA_RST_GENERAL_TIMER4_REG QCA_RST_BASE_REG + 0xA4
+#define QCA_RST_GENERAL_TIMER4_RELOAD_REG QCA_RST_BASE_REG + 0xA8
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xAC
+#else
+ #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xB0
+#endif
+
+/*
+ * Reset control registers BIT fields
+ */
+
+/* RST_BOOTSTRAP (Reset bootstrap) */
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 0
+#else
+ #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 4
+#endif
+#define QCA_RST_BOOTSTRAP_REF_CLK_MASK BIT(QCA_RST_BOOTSTRAP_REF_CLK_SHIFT)
+#define QCA_RST_BOOTSTRAP_REF_CLK_25M_VAL 0x0
+#define QCA_RST_BOOTSTRAP_REF_CLK_40M_VAL 0x1
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT 3
+ #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK BIT(QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT)
+ #define QCA_RST_BOOTSTRAP_EEPBUSY_SHIFT 4
+ #define QCA_RST_BOOTSTRAP_EEPBUSY_MASK BIT(QCA_RST_BOOTSTRAP_EEPBUSY_SHIFT)
+ #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 12
+ #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
+ #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT 16
+ #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK BIT(QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT)
+ #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT 17
+ #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_MASK BIT(QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT)
+ #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT 18
+ #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_MASK BIT(QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT)
+
+ #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 0
+ #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1
+ #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 2
+#else
+ #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 0
+
+ /* v2 does not support SDR, but we can read reserved bit and make it universal */
+ #if (SOC_TYPE & QCA_QCA953X_SOC)
+ #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
+ #else
+ #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BIT(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT)
+ #endif
+
+ #define QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT 2
+ #define QCA_RST_BOOTSTRAP_BOOT_SEL_MASK BIT(QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT)
+ #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT 3
+ #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_MASK BIT(QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT)
+ #define QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT 5
+ #define QCA_RST_BOOTSTRAP_JTAG_MODE_MASK BIT(QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT)
+ #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT 7
+ #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK BIT(QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT)
+
+ #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 3
+ #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1
+ #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 0
+#endif
+
+/* RST_RESET */
+#define QCA_RST_RESET_I2C_RST_SHIFT 0
+#define QCA_RST_RESET_I2C_RST_MASK BIT(QCA_RST_RESET_I2C_RST_SHIFT)
+#define QCA_RST_RESET_MBOX_RST_SHIFT 1
+#define QCA_RST_RESET_MBOX_RST_MASK BIT(QCA_RST_RESET_MBOX_RST_SHIFT)
+#define QCA_RST_RESET_LUT_RST_SHIFT 2
+#define QCA_RST_RESET_LUT_RST_MASK BIT(QCA_RST_RESET_LUT_RST_SHIFT)
+#define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT 3
+#define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_MASK BIT(QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT)
+#define QCA_RST_RESET_USB_PHY_RST_SHIFT 4
+#define QCA_RST_RESET_USB_PHY_RST_MASK BIT(QCA_RST_RESET_USB_PHY_RST_SHIFT)
+#define QCA_RST_RESET_USB_HOST_RST_SHIFT 5
+#define QCA_RST_RESET_USB_HOST_RST_MASK BIT(QCA_RST_RESET_USB_HOST_RST_SHIFT)
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_RST_RESET_SLIC_RST_SHIFT 6
+ #define QCA_RST_RESET_SLIC_RST_MASK BIT(QCA_RST_RESET_SLIC_RST_SHIFT)
+#else
+ #define QCA_RST_RESET_PCIE_RST_SHIFT 6
+ #define QCA_RST_RESET_PCIE_RST_MASK BIT(QCA_RST_RESET_PCIE_RST_SHIFT)
+ #define QCA_RST_RESET_SLIC_RST_SHIFT 30
+ #define QCA_RST_RESET_SLIC_RST_MASK BIT(QCA_RST_RESET_SLIC_RST_SHIFT)
+#endif
+
+#define QCA_RST_RESET_PCIE_PHY_RST_SHIFT 7
+#define QCA_RST_RESET_PCIE_PHY_RST_MASK BIT(QCA_RST_RESET_PCIE_PHY_RST_SHIFT)
+
+#if (SOC_TYPE & QCA_QCA955X_SOC)
+ #define QCA_RST_RESET_ETH_SGMII_RST_SHIFT 8
+ #define QCA_RST_RESET_ETH_SGMII_RST_MASK BIT(QCA_RST_RESET_ETH_SGMII_RST_SHIFT)
+#else
+ #define QCA_RST_RESET_ETH_SWITCH_RST_SHIFT 8
+ #define QCA_RST_RESET_ETH_SWITCH_RST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_RST_SHIFT)
+#endif
+
+#define QCA_RST_RESET_GE0_MAC_RST_SHIFT 9
+#define QCA_RST_RESET_GE0_MAC_RST_MASK BIT(QCA_RST_RESET_GE0_MAC_RST_SHIFT)
+#define QCA_RST_RESET_HOST_DMA_INT_SHIFT 10
+#define QCA_RST_RESET_HOST_DMA_INT_MASK BIT(QCA_RST_RESET_HOST_DMA_INT_SHIFT)
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_RST_RESET_WLAN_RST_SHIFT 11
+ #define QCA_RST_RESET_WLAN_RST_MASK BIT(QCA_RST_RESET_WLAN_RST_SHIFT)
+#else
+ #define QCA_RST_RESET_USB_PHY_ARST_SHIFT 11
+ #define QCA_RST_RESET_USB_PHY_ARST_MASK BIT(QCA_RST_RESET_USB_PHY_ARST_SHIFT)
+#endif
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 14
+ #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
+#else
+ #if (SOC_TYPE & QCA_QCA955X_SOC)
+ #define QCA_RST_RESET_ETH_SGMII_ARST_SHIFT 12
+ #define QCA_RST_RESET_ETH_SGMII_ARST_MASK BIT(QCA_RST_RESET_ETH_SGMII_ARST_SHIFT)
+ #else
+ #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 12
+ #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
+ #endif
+
+ #define QCA_RST_RESET_NANDF_RST_SHIFT 14
+ #define QCA_RST_RESET_NANDF_RST_MASK BIT(QCA_RST_RESET_NANDF_RST_SHIFT)
+#endif
+
+#define QCA_RST_RESET_GE1_MAC_RST_SHIFT 13
+#define QCA_RST_RESET_GE1_MAC_RST_MASK BIT(QCA_RST_RESET_GE1_MAC_RST_SHIFT)
+#define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT 15
+#define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_MASK BIT(QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT)
+#define QCA_RST_RESET_DDR_RST_SHIFT 16
+#define QCA_RST_RESET_DDR_RST_MASK BIT(QCA_RST_RESET_DDR_RST_SHIFT)
+#define QCA_RST_RESET_HSUART_RST_SHIFT 17
+#define QCA_RST_RESET_HSUART_RST_MASK BIT(QCA_RST_RESET_HSUART_RST_SHIFT)
+#define QCA_RST_RESET_PCIEEP_RST_SHIFT 18
+#define QCA_RST_RESET_PCIEEP_RST_MASK BIT(QCA_RST_RESET_PCIEEP_RST_SHIFT)
+#define QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT 19
+#define QCA_RST_RESET_HOST_DMA_RST_INT_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT)
+#define QCA_RST_RESET_CPU_COLD_RST_SHIFT 20
+#define QCA_RST_RESET_CPU_COLD_RST_MASK BIT(QCA_RST_RESET_CPU_COLD_RST_SHIFT)
+#define QCA_RST_RESET_CPU_NMI_SHIFT 21
+#define QCA_RST_RESET_CPU_NMI_MASK BIT(QCA_RST_RESET_CPU_NMI_SHIFT)
+#define QCA_RST_RESET_GE0_MDIO_RST_SHIFT 22
+#define QCA_RST_RESET_GE0_MDIO_RST_MASK BIT(QCA_RST_RESET_GE0_MDIO_RST_SHIFT)
+#define QCA_RST_RESET_GE1_MDIO_RST_SHIFT 23
+#define QCA_RST_RESET_GE1_MDIO_RST_MASK BIT(QCA_RST_RESET_GE1_MDIO_RST_SHIFT)
+#define QCA_RST_RESET_FULL_CHIP_RST_SHIFT 24
+#define QCA_RST_RESET_FULL_CHIP_RST_MASK BIT(QCA_RST_RESET_FULL_CHIP_RST_SHIFT)
+#define QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT 25
+#define QCA_RST_RESET_CHECKSUM_ACC_RST_MASK BIT(QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT)
+#define QCA_RST_RESET_PCIEEP_RST_INT_SHIFT 26
+#define QCA_RST_RESET_PCIEEP_RST_INT_MASK BIT(QCA_RST_RESET_PCIEEP_RST_INT_SHIFT)
+#define QCA_RST_RESET_RTC_RST_SHIFT 27
+#define QCA_RST_RESET_RTC_RST_MASK BIT(QCA_RST_RESET_RTC_RST_SHIFT)
+#define QCA_RST_RESET_EXT_RST_SHIFT 28
+#define QCA_RST_RESET_EXT_RST_MASK BIT(QCA_RST_RESET_EXT_RST_SHIFT)
+
+#if (SOC_TYPE & QCA_AR934X_SOC) |\
+ (SOC_TYPE & QCA_QCA955X_SOC)
+ #define QCA_RST_RESET_HOST_DMA_RST_SHIFT 29
+ #define QCA_RST_RESET_HOST_DMA_RST_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_SHIFT)
+#else
+ #define QCA_RST_RESET_USB_EXT_PWR_SHIFT 29
+ #define QCA_RST_RESET_USB_EXT_PWR_MASK BIT(QCA_RST_RESET_USB_EXT_PWR_SHIFT)
+#endif
+
+#define QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT 31
+#define QCA_RST_RESET_HOST_DMA_RST_STATUS_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT)
+
+/* RST_REVISION_ID (Chip revision ID) */
+#define QCA_RST_REVISION_ID_MAJOR_SHIFT 4
+#define QCA_RST_REVISION_ID_MAJOR_MASK BITS(QCA_RST_REVISION_ID_MAJOR_SHIFT, 12)
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+ #define QCA_RST_REVISION_ID_REV_SHIFT 0
+ #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 2)
+#else
+ #define QCA_RST_REVISION_ID_REV_SHIFT 0
+ #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 4)
+#endif
+
+#define QCA_RST_REVISION_ID_MAJOR_AR9330_VAL 0x0110
+#define QCA_RST_REVISION_ID_MAJOR_AR9331_VAL 0x1110
+#define QCA_RST_REVISION_ID_MAJOR_AR9341_VAL 0x0120
+#define QCA_RST_REVISION_ID_MAJOR_AR9344_VAL 0x2120
+#define QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL 0x0140
+#define QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL 0x0160
+#define QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL 0x1130
+
+/*
+ * RTC registers
+ */
+#define QCA_RTC_RST_CTRL_REG QCA_RTC_BASE_REG + 0x00
+#define QCA_RTC_XTAL_CTRL_REG QCA_RTC_BASE_REG + 0x04
+#define QCA_RTC_WLAN_PLL_CTRL_REG QCA_RTC_BASE_REG + 0x14
+#define QCA_RTC_PLL_SETTLE_REG QCA_RTC_BASE_REG + 0x18
+#define QCA_RTC_XTAL_SETTLE_REG QCA_RTC_BASE_REG + 0x1C
+#define QCA_RTC_CLK_OUT_REG QCA_RTC_BASE_REG + 0x20
+#define QCA_RTC_RST_CAUSE_REG QCA_RTC_BASE_REG + 0x28
+#define QCA_RTC_SYS_SLEEP_REG QCA_RTC_BASE_REG + 0x2C
+#define QCA_RTC_KEEP_AWAKE_REG QCA_RTC_BASE_REG + 0x34
+#define QCA_RTC_DERIVED_RTC_CLK_REG QCA_RTC_BASE_REG + 0x38
+#define QCA_RTC_PLL_CTRL2_REG QCA_RTC_BASE_REG + 0x3C
+#define QCA_RTC_SYNC_RST_REG QCA_RTC_BASE_REG + 0x40
+#define QCA_RTC_SYNC_STATUS_REG QCA_RTC_BASE_REG + 0x44
+#define QCA_RTC_SYNC_DERIVED_REG QCA_RTC_BASE_REG + 0x48
+#define QCA_RTC_SYNC_FORCE_WAKE_REG QCA_RTC_BASE_REG + 0x4C
+#define QCA_RTC_INTERRUPT_CAUSE_REG QCA_RTC_BASE_REG + 0x50
+#define QCA_RTC_INTERRUPT_EN_REG QCA_RTC_BASE_REG + 0x54
+#define QCA_RTC_INTERRUPT_MASK_REG QCA_RTC_BASE_REG + 0x58
+
+/*
+ * RTC registers BIT fields
+ */
+
+/* RESET_CONTROL register (RTC reset control) */
+#define QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT 0
+#define QCA_RTC_RST_CTRL_MAC_WARM_RST_MASK BIT(QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT)
+#define QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT 1
+#define QCA_RTC_RST_CTRL_MAC_COLD_RST_MASK BIT(QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT)
+#define QCA_RTC_RST_CTRL_WARM_RST_SHIFT 2
+#define QCA_RTC_RST_CTRL_WARM_RST_MASK BIT(QCA_RTC_RST_CTRL_WARM_RST_SHIFT)
+#define QCA_RTC_RST_CTRL_COLD_RST_SHIFT 3
+#define QCA_RTC_RST_CTRL_COLD_RST_MASK BIT(QCA_RTC_RST_CTRL_COLD_RST_SHIFT)
+
+/* RESET_CAUSE register (Reset cause) */
+#define QCA_RTC_RST_CAUSE_LAST_SHIFT 0
+#define QCA_RTC_RST_CAUSE_LAST_MASK BITS(QCA_RTC_RST_CAUSE_LAST_SHIFT, 2)
+
+#define QCA_RTC_RST_CAUSE_LAST_HARD_VAL 0
+#define QCA_RTC_RST_CAUSE_LAST_COLD_VAL 1
+#define QCA_RTC_RST_CAUSE_LAST_WARM_VAL 2
+
+/* RTC_SYNC_REGISTER register (RTC reset, force sleep and force wakeup) */
+#define QCA_RTC_SYNC_RST_RESET_SHIFT 0
+#define QCA_RTC_SYNC_RST_RESET_MASK BIT(QCA_RTC_SYNC_RST_RESET_SHIFT)
+
+/* RTC_SYNC_STATUS register (RTC sync/sleep status) */
+#define QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT 0
+#define QCA_RTC_SYNC_STATUS_SHUTDOWN_MASK BIT(QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT)
+#define QCA_RTC_SYNC_STATUS_ON_SHIFT 1
+#define QCA_RTC_SYNC_STATUS_ON_MASK BIT(QCA_RTC_SYNC_STATUS_ON_SHIFT)
+#define QCA_RTC_SYNC_STATUS_SLEEP_SHIFT 2
+#define QCA_RTC_SYNC_STATUS_SLEEP_MASK BIT(QCA_RTC_SYNC_STATUS_SLEEP_SHIFT)
+#define QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT 3
+#define QCA_RTC_SYNC_STATUS_WAKEUP_MASK BIT(QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT)
+#define QCA_RTC_SYNC_STATUS_WRESET_SHIFT 4
+#define QCA_RTC_SYNC_STATUS_WRESET_MASK BIT(QCA_RTC_SYNC_STATUS_WRESET_SHIFT)
+#define QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT 5
+#define QCA_RTC_SYNC_STATUS_PLL_CHANGING_MASK BIT(QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT)
+
+/* RTC_SYNC_FORCE_WAKE register (RTC force wake) */
+#define QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT 0
+#define QCA_RTC_SYNC_FORCE_WAKE_EN_MASK BIT(QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT)
+#define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT 1
+#define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_MASK BIT(QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT)
+
+/*
+ * SPI serial flash registers
+ */
+#define QCA_SPI_FUNC_SEL_REG QCA_FLASH_BASE_REG + 0x00
+#define QCA_SPI_CTRL_REG QCA_FLASH_BASE_REG + 0x04
+#define QCA_SPI_IO_CTRL_REG QCA_FLASH_BASE_REG + 0x08
+#define QCA_SPI_READ_DATA_REG QCA_FLASH_BASE_REG + 0x0C
+#define QCA_SPI_SHIFT_DATAOUT_REG QCA_FLASH_BASE_REG + 0x10
+#define QCA_SPI_SHIFT_CNT_REG QCA_FLASH_BASE_REG + 0x14
+#define QCA_SPI_SHIFT_DATAIN_REG QCA_FLASH_BASE_REG + 0x18
+
+/*
+ * SPI serial flash registers BIT fields
+ */
+
+/* SPI_FUNC_SELECT register (SPI function select) */
+#define QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT 0
+#define QCA_SPI_FUNC_SEL_FUNC_SEL_MASK BIT(QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT)
+
+/* SPI_CONTROL register (SPI control) */
+#define QCA_SPI_CTRL_CLK_DIV_SHIFT 0
+#define QCA_SPI_CTRL_CLK_DIV_MASK BITS(QCA_SPI_CTRL_CLK_DIV_SHIFT, 6)
+#define QCA_SPI_CTRL_REMAP_DIS_SHIFT 6
+#define QCA_SPI_CTRL_REMAP_DIS_MASK BIT(QCA_SPI_CTRL_REMAP_DIS_SHIFT)
+#define QCA_SPI_CTRL_SPI_RELOCATE_SHIFT 7
+#define QCA_SPI_CTRL_SPI_RELOCATE_MASK BIT(QCA_SPI_CTRL_SPI_RELOCATE_SHIFT)
+#define QCA_SPI_CTRL_TSHSL_CNT_SHIFT 8
+#define QCA_SPI_CTRL_TSHSL_CNT_MASK BITS(QCA_SPI_CTRL_TSHSL_CNT_SHIFT, 6)
+
+/* SPI_IO_CONTROL register (SPI I/O control) */
+#define QCA_SPI_IO_CTRL_IO_DO_SHIFT 0
+#define QCA_SPI_IO_CTRL_IO_DO_MASK BIT(QCA_SPI_IO_CTRL_IO_DO_SHIFT)
+#define QCA_SPI_IO_CTRL_IO_CLK_SHIFT 8
+#define QCA_SPI_IO_CTRL_IO_CLK_MASK BIT(QCA_SPI_IO_CTRL_IO_CLK_SHIFT)
+#define QCA_SPI_IO_CTRL_IO_CS0_SHIFT 16
+#define QCA_SPI_IO_CTRL_IO_CS0_MASK BIT(QCA_SPI_IO_CTRL_IO_CS0_SHIFT)
+#define QCA_SPI_IO_CTRL_IO_CS1_SHIFT 17
+#define QCA_SPI_IO_CTRL_IO_CS1_MASK BIT(QCA_SPI_IO_CTRL_IO_CS1_SHIFT)
+#define QCA_SPI_IO_CTRL_IO_CS2_SHIFT 18
+#define QCA_SPI_IO_CTRL_IO_CS2_MASK BIT(QCA_SPI_IO_CTRL_IO_CS2_SHIFT)
+
+/* SPI_SHIFT_CNT_ADDR register (SPI content to shift out or in) */
+#define QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT 0
+#define QCA_SPI_SHIFT_CNT_BITS_CNT_MASK BITS(QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT, 7)
+#define QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT 26
+#define QCA_SPI_SHIFT_CNT_TERMINATE_MASK BIT(QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT)
+#define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT 27
+#define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_MASK BIT(QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT)
+#define QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT 28
+#define QCA_SPI_SHIFT_CNT_CHNL_CS0_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT)
+#define QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT 29
+#define QCA_SPI_SHIFT_CNT_CHNL_CS1_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT)
+#define QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT 30
+#define QCA_SPI_SHIFT_CNT_CHNL_CS2_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT)
+#define QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT 31
+#define QCA_SPI_SHIFT_CNT_SHIFT_EN_MASK BIT(QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT)
+
+/*
+ * Other useful defines
+ */
+
+/* Magic flag for indication that PLL/clocks config is stored in FLASH */
+#define QCA_PLL_IN_FLASH_MAGIC 0x504C4C73
+
+/* Maximum DRAM size: 256 MB */
+#define QCA_DRAM_MAX_SIZE_VAL (256 * 1024 * 1024)
+
+/*
+ * Functions
+ */
+#ifndef __ASSEMBLY__
+inline u32 qca_xtal_is_40mhz(void);
+void qca_soc_name_rev(char *buf);
+void qca_full_chip_reset(void);
+void qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk, u32 *spi_clk, u32 *ref_clk);
+void qca_sf_bulk_erase(u32 bank);
+void qca_sf_write_page(u32 bank, u32 address, u32 length, u8 *data);
+u32 qca_sf_sect_erase(u32 bank, u32 address, u32 sect_size, u8 erase_cmd);
+u32 qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_cmd);
+u32 qca_sf_jedec_id(u32 bank);
+u32 qca_dram_type(void);
+u32 qca_dram_size(void);
+u32 qca_dram_ddr_width(void);
+void qca_dram_init(void);
+inline u32 qca_dram_cas_lat(void);
+inline u32 qca_dram_trcd_lat(void);
+inline u32 qca_dram_trp_lat(void);
+inline u32 qca_dram_tras_lat(void);
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Read, write, set and clear macros
+ */
+#define qca_soc_reg_read(_addr) *(volatile unsigned int *)(KSEG1ADDR(_addr))
+#define qca_soc_reg_write(_addr, _val) ((*(volatile unsigned int *)KSEG1ADDR(_addr)) = (_val))
+
+#define qca_soc_reg_read_set(_addr, _mask) \
+ qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) | (_mask)))
+
+#define qca_soc_reg_read_clear(_addr, _mask) \
+ qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) & ~(_mask)))
+
+#endif /* _QCA_SOC_COMMON_H_ */
--- /dev/null
+/*
+ * SOC common registers and helper function/macro definitions
+ *
+ * Copyright (C) 2014 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOC_COMMON_H_
+#define _SOC_COMMON_H_
+
+#include <linux/bitops.h>
+
+#ifndef SOC_TYPE
+ #error "SOC_TYPE is not defined!"
+#endif
+
+/*
+ * GPIO registers BIT fields
+ */
+#define GPIO_X_MASK(_gpio) (1 << _gpio)
+#define GPIO0 GPIO_X_MASK(0)
+#define GPIO1 GPIO_X_MASK(1)
+#define GPIO2 GPIO_X_MASK(2)
+#define GPIO3 GPIO_X_MASK(3)
+#define GPIO4 GPIO_X_MASK(4)
+#define GPIO5 GPIO_X_MASK(5)
+#define GPIO6 GPIO_X_MASK(6)
+#define GPIO7 GPIO_X_MASK(7)
+#define GPIO8 GPIO_X_MASK(8)
+#define GPIO9 GPIO_X_MASK(9)
+#define GPIO10 GPIO_X_MASK(10)
+#define GPIO11 GPIO_X_MASK(11)
+#define GPIO12 GPIO_X_MASK(12)
+#define GPIO13 GPIO_X_MASK(13)
+#define GPIO14 GPIO_X_MASK(14)
+#define GPIO15 GPIO_X_MASK(15)
+#define GPIO16 GPIO_X_MASK(16)
+#define GPIO17 GPIO_X_MASK(17)
+#define GPIO18 GPIO_X_MASK(18)
+#define GPIO19 GPIO_X_MASK(19)
+#define GPIO20 GPIO_X_MASK(20)
+#define GPIO21 GPIO_X_MASK(21)
+#define GPIO22 GPIO_X_MASK(22)
+#define GPIO23 GPIO_X_MASK(23)
+#define GPIO24 GPIO_X_MASK(24)
+#define GPIO25 GPIO_X_MASK(25)
+#define GPIO26 GPIO_X_MASK(26)
+#define GPIO27 GPIO_X_MASK(27)
+#define GPIO28 GPIO_X_MASK(28)
+#define GPIO29 GPIO_X_MASK(29)
+#define GPIO30 GPIO_X_MASK(30)
+#define GPIO31 GPIO_X_MASK(31)
+#define GPIO32 GPIO_X_MASK(32)
+#define GPIO33 GPIO_X_MASK(33)
+#define GPIO34 GPIO_X_MASK(34)
+#define GPIO35 GPIO_X_MASK(35)
+#define GPIO36 GPIO_X_MASK(36)
+#define GPIO37 GPIO_X_MASK(37)
+#define GPIO38 GPIO_X_MASK(38)
+#define GPIO39 GPIO_X_MASK(39)
+#define GPIO40 GPIO_X_MASK(40)
+#define GPIO41 GPIO_X_MASK(41)
+#define GPIO42 GPIO_X_MASK(42)
+#define GPIO43 GPIO_X_MASK(43)
+#define GPIO44 GPIO_X_MASK(44)
+#define GPIO45 GPIO_X_MASK(45)
+#define GPIO46 GPIO_X_MASK(46)
+#define GPIO47 GPIO_X_MASK(47)
+#define GPIO48 GPIO_X_MASK(48)
+#define GPIO49 GPIO_X_MASK(49)
+#define GPIO50 GPIO_X_MASK(50)
+
+/*
+ * Memory types
+ */
+#define RAM_MEMORY_TYPE_DDR1 1
+#define RAM_MEMORY_TYPE_DDR2 2
+#define RAM_MEMORY_TYPE_DDR3 3
+#define RAM_MEMORY_TYPE_SDR 4
+#define RAM_MEMORY_TYPE_UNKNOWN 5
+
+/*
+ * Useful clock variables
+ */
+#define VAL_40MHz (40 * 1000 * 1000)
+#define VAL_25MHz (25 * 1000 * 1000)
+
+#endif /* _SOC_COMMON_H_ */
--- /dev/null
+/*
+ * tinf - tiny inflate library (inflate, gzip, zlib)
+ *
+ * version 1.00
+ *
+ * Copyright (c) 2003 by Joergen Ibsen / Jibz
+ * All Rights Reserved
+ *
+ * http://www.ibsensoftware.com/
+ */
+
+#ifndef TINF_H_INCLUDED
+#define TINF_H_INCLUDED
+
+/* calling convention */
+#ifndef TINFCC
+ #ifdef __WATCOMC__
+ #define TINFCC __cdecl
+ #else
+ #define TINFCC
+ #endif
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define TINF_OK 0
+#define TINF_DATA_ERROR (-3)
+
+/* function prototypes */
+
+void TINFCC tinf_init(void);
+
+int TINFCC tinf_uncompress(void *dest, unsigned int *destLen,
+ const void *source, unsigned int sourceLen);
+
+int TINFCC tinf_gzip_uncompress(void *dest, unsigned int *destLen,
+ const void *source, unsigned int sourceLen);
+
+int TINFCC tinf_zlib_uncompress(void *dest, unsigned int *destLen,
+ const void *source, unsigned int sourceLen);
+
+unsigned int TINFCC tinf_adler32(const void *data, unsigned int length);
+
+unsigned int TINFCC tinf_crc32(const void *data, unsigned int length);
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* TINF_H_INCLUDED */
+++ /dev/null
-/*
- * This file is derived from zlib.h and zconf.h from the zlib-0.95
- * distribution by Jean-loup Gailly and Mark Adler, with some additions
- * by Paul Mackerras to aid in implementing Deflate compression and
- * decompression for PPP packets.
- */
-
-/*
- * ==FILEVERSION 960122==
- *
- * This marker is used by the Linux installation script to determine
- * whether an up-to-date version of this file is already installed.
- */
-
-/* zlib.h -- interface of the 'zlib' general purpose compression library
- version 0.95, Aug 16th, 1995.
-
- Copyright (C) 1995 Jean-loup Gailly and Mark Adler
-
- This software is provided 'as-is', without any express or implied
- warranty. In no event will the authors be held liable for any damages
- arising from the use of this software.
-
- Permission is granted to anyone to use this software for any purpose,
- including commercial applications, and to alter it and redistribute it
- freely, subject to the following restrictions:
-
- 1. The origin of this software must not be misrepresented; you must not
- claim that you wrote the original software. If you use this software
- in a product, an acknowledgment in the product documentation would be
- appreciated but is not required.
- 2. Altered source versions must be plainly marked as such, and must not be
- misrepresented as being the original software.
- 3. This notice may not be removed or altered from any source distribution.
-
- Jean-loup Gailly Mark Adler
- gzip@prep.ai.mit.edu madler@alumni.caltech.edu
- */
-
-#ifndef _ZLIB_H
-#define _ZLIB_H
-
-/* #include "zconf.h" */ /* included directly here */
-
-/* zconf.h -- configuration of the zlib compression library
- * Copyright (C) 1995 Jean-loup Gailly.
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-/* From: zconf.h,v 1.12 1995/05/03 17:27:12 jloup Exp */
-
-/*
- The library does not install any signal handler. It is recommended to
- add at least a handler for SIGSEGV when decompressing; the library checks
- the consistency of the input data whenever possible but may go nuts
- for some forms of corrupted input.
- */
-
-/*
- * Compile with -DMAXSEG_64K if the alloc function cannot allocate more
- * than 64k bytes at a time (needed on systems with 16-bit int).
- * Compile with -DUNALIGNED_OK if it is OK to access shorts or ints
- * at addresses which are not a multiple of their size.
- * Under DOS, -DFAR=far or -DFAR=__far may be needed.
- */
-
-#ifndef STDC
-# if defined(MSDOS) || defined(__STDC__) || defined(__cplusplus)
-# define STDC
-# endif
-#endif
-
-#ifdef __MWERKS__ /* Metrowerks CodeWarrior declares fileno() in unix.h */
-# include <unix.h>
-#endif
-
-/* Maximum value for memLevel in deflateInit2 */
-#ifndef MAX_MEM_LEVEL
-# ifdef MAXSEG_64K
-# define MAX_MEM_LEVEL 8
-# else
-# define MAX_MEM_LEVEL 9
-# endif
-#endif
-
-#ifndef FAR
-# define FAR
-#endif
-
-/* Maximum value for windowBits in deflateInit2 and inflateInit2 */
-#ifndef MAX_WBITS
-# define MAX_WBITS 15 /* 32K LZ77 window */
-#endif
-
-/* The memory requirements for deflate are (in bytes):
- 1 << (windowBits+2) + 1 << (memLevel+9)
- that is: 128K for windowBits=15 + 128K for memLevel = 8 (default values)
- plus a few kilobytes for small objects. For example, if you want to reduce
- the default memory requirements from 256K to 128K, compile with
- make CFLAGS="-O -DMAX_WBITS=14 -DMAX_MEM_LEVEL=7"
- Of course this will generally degrade compression (there's no free lunch).
-
- The memory requirements for inflate are (in bytes) 1 << windowBits
- that is, 32K for windowBits=15 (default value) plus a few kilobytes
- for small objects.
-*/
-
- /* Type declarations */
-
-#ifndef OF /* function prototypes */
-# ifdef STDC
-# define OF(args) args
-# else
-# define OF(args) ()
-# endif
-#endif
-
-typedef unsigned char Byte; /* 8 bits */
-typedef unsigned int uInt; /* 16 bits or more */
-typedef unsigned long uLong; /* 32 bits or more */
-
-typedef Byte FAR Bytef;
-typedef char FAR charf;
-typedef int FAR intf;
-typedef uInt FAR uIntf;
-typedef uLong FAR uLongf;
-
-#ifdef STDC
- typedef void FAR *voidpf;
- typedef void *voidp;
-#else
- typedef Byte FAR *voidpf;
- typedef Byte *voidp;
-#endif
-
-/* end of original zconf.h */
-
-#define ZLIB_VERSION "0.95P"
-
-/*
- The 'zlib' compression library provides in-memory compression and
- decompression functions, including integrity checks of the uncompressed
- data. This version of the library supports only one compression method
- (deflation) but other algorithms may be added later and will have the same
- stream interface.
-
- For compression the application must provide the output buffer and
- may optionally provide the input buffer for optimization. For decompression,
- the application must provide the input buffer and may optionally provide
- the output buffer for optimization.
-
- Compression can be done in a single step if the buffers are large
- enough (for example if an input file is mmap'ed), or can be done by
- repeated calls of the compression function. In the latter case, the
- application must provide more input and/or consume the output
- (providing more output space) before each call.
-*/
-
-typedef voidpf (*alloc_func) OF((voidpf opaque, uInt items, uInt size));
-typedef void (*free_func) OF((voidpf opaque, voidpf address, uInt nbytes));
-
-typedef void (*cb_func) OF((Bytef *buf, uInt len));
-
-struct internal_state;
-
-typedef struct z_stream_s {
- Bytef *next_in; /* next input byte */
- uInt avail_in; /* number of bytes available at next_in */
- uLong total_in; /* total nb of input bytes read so far */
-
- Bytef *next_out; /* next output byte should be put there */
- uInt avail_out; /* remaining free space at next_out */
- uLong total_out; /* total nb of bytes output so far */
-
- char *msg; /* last error message, NULL if no error */
- struct internal_state FAR *state; /* not visible by applications */
-
- alloc_func zalloc; /* used to allocate the internal state */
- free_func zfree; /* used to free the internal state */
- voidp opaque; /* private data object passed to zalloc and zfree */
-
- Byte data_type; /* best guess about the data type: ascii or binary */
-
- cb_func outcb; /* called regularly just before blocks of output */
-
-} z_stream;
-
-/*
- The application must update next_in and avail_in when avail_in has
- dropped to zero. It must update next_out and avail_out when avail_out
- has dropped to zero. The application must initialize zalloc, zfree and
- opaque before calling the init function. All other fields are set by the
- compression library and must not be updated by the application.
-
- The opaque value provided by the application will be passed as the first
- parameter for calls of zalloc and zfree. This can be useful for custom
- memory management. The compression library attaches no meaning to the
- opaque value.
-
- zalloc must return Z_NULL if there is not enough memory for the object.
- On 16-bit systems, the functions zalloc and zfree must be able to allocate
- exactly 65536 bytes, but will not be required to allocate more than this
- if the symbol MAXSEG_64K is defined (see zconf.h). WARNING: On MSDOS,
- pointers returned by zalloc for objects of exactly 65536 bytes *must*
- have their offset normalized to zero. The default allocation function
- provided by this library ensures this (see zutil.c). To reduce memory
- requirements and avoid any allocation of 64K objects, at the expense of
- compression ratio, compile the library with -DMAX_WBITS=14 (see zconf.h).
-
- The fields total_in and total_out can be used for statistics or
- progress reports. After compression, total_in holds the total size of
- the uncompressed data and may be saved for use in the decompressor
- (particularly if the decompressor wants to decompress everything in
- a single step).
-*/
-
- /* constants */
-
-#define Z_NO_FLUSH 0
-#define Z_PARTIAL_FLUSH 1
-#define Z_FULL_FLUSH 2
-#define Z_SYNC_FLUSH 3 /* experimental: partial_flush + byte align */
-#define Z_FINISH 4
-#define Z_PACKET_FLUSH 5
-/* See deflate() below for the usage of these constants */
-
-#define Z_OK 0
-#define Z_STREAM_END 1
-#define Z_ERRNO (-1)
-#define Z_STREAM_ERROR (-2)
-#define Z_DATA_ERROR (-3)
-#define Z_MEM_ERROR (-4)
-#define Z_BUF_ERROR (-5)
-/* error codes for the compression/decompression functions */
-
-#define Z_BEST_SPEED 1
-#define Z_BEST_COMPRESSION 9
-#define Z_DEFAULT_COMPRESSION (-1)
-/* compression levels */
-
-#define Z_FILTERED 1
-#define Z_HUFFMAN_ONLY 2
-#define Z_DEFAULT_STRATEGY 0
-
-#define Z_BINARY 0
-#define Z_ASCII 1
-#define Z_UNKNOWN 2
-/* Used to set the data_type field */
-
-#define Z_NULL 0 /* for initializing zalloc, zfree, opaque */
-
-extern char *zlib_version;
-/* The application can compare zlib_version and ZLIB_VERSION for consistency.
- If the first character differs, the library code actually used is
- not compatible with the zlib.h header file used by the application.
- */
-
- /* basic functions */
-
-extern int inflateInit OF((z_stream *strm));
-/*
- Initializes the internal stream state for decompression. The fields
- zalloc and zfree must be initialized before by the caller. If zalloc and
- zfree are set to Z_NULL, inflateInit updates them to use default allocation
- functions.
-
- inflateInit returns Z_OK if success, Z_MEM_ERROR if there was not
- enough memory. msg is set to null if there is no error message.
- inflateInit does not perform any decompression: this will be done by
- inflate().
-*/
-
-
-extern int inflate OF((z_stream *strm, int flush));
-/*
- Performs one or both of the following actions:
-
- - Decompress more input starting at next_in and update next_in and avail_in
- accordingly. If not all input can be processed (because there is not
- enough room in the output buffer), next_in is updated and processing
- will resume at this point for the next call of inflate().
-
- - Provide more output starting at next_out and update next_out and avail_out
- accordingly. inflate() always provides as much output as possible
- (until there is no more input data or no more space in the output buffer).
-
- Before the call of inflate(), the application should ensure that at least
- one of the actions is possible, by providing more input and/or consuming
- more output, and updating the next_* and avail_* values accordingly.
- The application can consume the uncompressed output when it wants, for
- example when the output buffer is full (avail_out == 0), or after each
- call of inflate().
-
- If the parameter flush is set to Z_PARTIAL_FLUSH or Z_PACKET_FLUSH,
- inflate flushes as much output as possible to the output buffer. The
- flushing behavior of inflate is not specified for values of the flush
- parameter other than Z_PARTIAL_FLUSH, Z_PACKET_FLUSH or Z_FINISH, but the
- current implementation actually flushes as much output as possible
- anyway. For Z_PACKET_FLUSH, inflate checks that once all the input data
- has been consumed, it is expecting to see the length field of a stored
- block; if not, it returns Z_DATA_ERROR.
-
- inflate() should normally be called until it returns Z_STREAM_END or an
- error. However if all decompression is to be performed in a single step
- (a single call of inflate), the parameter flush should be set to
- Z_FINISH. In this case all pending input is processed and all pending
- output is flushed; avail_out must be large enough to hold all the
- uncompressed data. (The size of the uncompressed data may have been saved
- by the compressor for this purpose.) The next operation on this stream must
- be inflateEnd to deallocate the decompression state. The use of Z_FINISH
- is never required, but can be used to inform inflate that a faster routine
- may be used for the single inflate() call.
-
- inflate() returns Z_OK if some progress has been made (more input
- processed or more output produced), Z_STREAM_END if the end of the
- compressed data has been reached and all uncompressed output has been
- produced, Z_DATA_ERROR if the input data was corrupted, Z_STREAM_ERROR if
- the stream structure was inconsistent (for example if next_in or next_out
- was NULL), Z_MEM_ERROR if there was not enough memory, Z_BUF_ERROR if no
- progress is possible or if there was not enough room in the output buffer
- when Z_FINISH is used. In the Z_DATA_ERROR case, the application may then
- call inflateSync to look for a good compression block. */
-
-
-extern int inflateEnd OF((z_stream *strm));
-/*
- All dynamically allocated data structures for this stream are freed.
- This function discards any unprocessed input and does not flush any
- pending output.
-
- inflateEnd returns Z_OK if success, Z_STREAM_ERROR if the stream state
- was inconsistent. In the error case, msg may be set but then points to a
- static string (which must not be deallocated).
-*/
-
- /* advanced functions */
-
-extern int inflateInit2 OF((z_stream *strm,
- int windowBits));
-/*
- This is another version of inflateInit with more compression options. The
- fields next_out, zalloc and zfree must be initialized before by the caller.
-
- The windowBits parameter is the base two logarithm of the maximum window
- size (the size of the history buffer). It should be in the range 8..15 for
- this version of the library (the value 16 will be allowed soon). The
- default value is 15 if inflateInit is used instead. If a compressed stream
- with a larger window size is given as input, inflate() will return with
- the error code Z_DATA_ERROR instead of trying to allocate a larger window.
-
- If next_out is not null, the library will use this buffer for the history
- buffer; the buffer must either be large enough to hold the entire output
- data, or have at least 1<<windowBits bytes. If next_out is null, the
- library will allocate its own buffer (and leave next_out null). next_in
- need not be provided here but must be provided by the application for the
- next call of inflate().
-
- If the history buffer is provided by the application, next_out must
- never be changed by the application since the decompressor maintains
- history information inside this buffer from call to call; the application
- can only reset next_out to the beginning of the history buffer when
- avail_out is zero and all output has been consumed.
-
- inflateInit2 returns Z_OK if success, Z_MEM_ERROR if there was
- not enough memory, Z_STREAM_ERROR if a parameter is invalid (such as
- windowBits < 8). msg is set to null if there is no error message.
- inflateInit2 does not perform any decompression: this will be done by
- inflate().
-*/
-
-extern int inflateSync OF((z_stream *strm));
-/*
- Skips invalid compressed data until the special marker (see deflate()
- above) can be found, or until all available input is skipped. No output
- is provided.
-
- inflateSync returns Z_OK if the special marker has been found, Z_BUF_ERROR
- if no more input was provided, Z_DATA_ERROR if no marker has been found,
- or Z_STREAM_ERROR if the stream structure was inconsistent. In the success
- case, the application may save the current current value of total_in which
- indicates where valid compressed data was found. In the error case, the
- application may repeatedly call inflateSync, providing more input each time,
- until success or end of the input data.
-*/
-
-extern int inflateReset OF((z_stream *strm));
-/*
- This function is equivalent to inflateEnd followed by inflateInit,
- but does not free and reallocate all the internal decompression state.
- The stream will keep attributes that may have been set by inflateInit2.
-
- inflateReset returns Z_OK if success, or Z_STREAM_ERROR if the source
- stream state was inconsistent (such as zalloc or state being NULL).
-*/
-
-extern int inflateIncomp OF((z_stream *strm));
-/*
- This function adds the data at next_in (avail_in bytes) to the output
- history without performing any output. There must be no pending output,
- and the decompressor must be expecting to see the start of a block.
- Calling this function is equivalent to decompressing a stored block
- containing the data at next_in (except that the data is not output).
-*/
-
- /* checksum functions */
-
-/*
- This function is not related to compression but is exported
- anyway because it might be useful in applications using the
- compression library.
-*/
-
-extern uLong adler32 OF((uLong adler, Bytef *buf, uInt len));
-
-/*
- Update a running Adler-32 checksum with the bytes buf[0..len-1] and
- return the updated checksum. If buf is NULL, this function returns
- the required initial value for the checksum.
- An Adler-32 checksum is almost as reliable as a CRC32 but can be computed
- much faster. Usage example:
-
- uLong adler = adler32(0L, Z_NULL, 0);
-
- while (read_buffer(buffer, length) != EOF) {
- adler = adler32(adler, buffer, length);
- }
- if (adler != original_adler) error();
-*/
-
-#ifndef _Z_UTIL_H
- struct internal_state {int dummy;}; /* hack for buggy compilers */
-#endif
-
-#endif /* _ZLIB_H */
LIB = libbootstrap.a
-OBJS = bootstrap_board.o LzmaDecode.o string.o crc32.o LzmaWrapper.o time.o
+OBJS = bootstrap_board.o LzmaDecode.o string.o crc32.o LzmaWrapper.o
CFLAGS += -DCONFIG_LZMA=1
#include <version.h>
#include <net.h>
#include <environment.h>
+#include <tinf.h>
#include "LzmaWrapper.h"
-//#define DEBUG_ENABLE_BOOTSTRAP_PRINTF
+/*#define DEBUG_ENABLE_BOOTSTRAP_PRINTF*/
DECLARE_GLOBAL_DATA_PTR;
-#if (((CFG_ENV_ADDR+CFG_ENV_SIZE) < BOOTSTRAP_CFG_MONITOR_BASE) || (CFG_ENV_ADDR >= (BOOTSTRAP_CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || defined(CFG_ENV_IS_IN_NVRAM)
-#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE)
+#if (((CFG_ENV_ADDR+CFG_ENV_SIZE) < BOOTSTRAP_CFG_MONITOR_BASE) || \
+ (CFG_ENV_ADDR >= (BOOTSTRAP_CFG_MONITOR_BASE + CFG_MONITOR_LEN))) \
+ || defined(CFG_ENV_IS_IN_NVRAM)
+ #define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE)
#else
-#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
+ #define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
#endif
#undef DEBUG
/*
* The Malloc area is immediately below the monitor copy in DRAM
*/
-static void mem_malloc_init(ulong dest_addr){
-// ulong dest_addr = BOOTSTRAP_CFG_MONITOR_BASE + gd->reloc_off;
-
+static void mem_malloc_init(ulong dest_addr)
+{
+ /* ulong dest_addr = BOOTSTRAP_CFG_MONITOR_BASE + gd->reloc_off; */
mem_malloc_end = dest_addr;
mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_brk = mem_malloc_start;
memset((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start);
}
-void *malloc(unsigned int size){
- if(size < (mem_malloc_end - mem_malloc_start)){
+void *malloc(unsigned int size)
+{
+ if (size < (mem_malloc_end - mem_malloc_start)) {
mem_malloc_start += size;
-
- return((void *)(mem_malloc_start - size));
+ return (void *)(mem_malloc_start - size);
}
- return(NULL);
+ return NULL;
}
-void *realloc(void *src, unsigned int size){
- return(NULL);
+void *realloc(void *src, unsigned int size)
+{
+ return NULL;
}
-void free(void *src){
+void free(void *src)
+{
return;
}
-static int init_func_ram(void){
- if((gd->ram_size = initdram()) > 0){
- return(0);
- }
- return(1);
+static int init_func_ram(void)
+{
+ if ((gd->ram_size = dram_init()) > 0)
+ return 0;
+
+ return 1;
}
/*
*/
typedef int(init_fnc_t)(void);
-init_fnc_t *init_sequence[] = { timer_init,
- init_func_ram,
- NULL, };
+init_fnc_t *init_sequence[] = { init_func_ram,
+ NULL, };
-void bootstrap_board_init_f(ulong bootflag){
+void bootstrap_board_init_f(ulong bootflag)
+{
gd_t gd_data, *id;
bd_t *bd;
init_fnc_t **init_fnc_ptr;
ulong addr, addr_sp, len = (ulong)&uboot_end_bootstrap - BOOTSTRAP_CFG_MONITOR_BASE;
ulong *s;
- /* Pointer is writable since we allocated a register for it.
- */
+ /* Pointer is writable since we allocated a register for it */
gd = &gd_data;
- /* compiler optimization barrier needed for GCC >= 3.4 */
+ /* Compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
memset((void *)gd, 0, sizeof(gd_t));
- for(init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr){
- if((*init_fnc_ptr)() != 0){
+ for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0)
hang();
- }
}
/*
* Now that we have DRAM mapped and working, we can
- * relocate the code and continue running from DRAM.
+ * relocate the code and continue running from DRAM
*/
addr = CFG_SDRAM_BASE + gd->ram_size;
/*
- * We can reserve some RAM "on top" here.
- * round down to next 4 kB limit.
+ * We can reserve some RAM "on top" here,
+ * round down to next 4 kB limit
*/
addr &= ~(4096 - 1);
/*
- * Reserve memory for U-Boot code, data & bss
+ * Reserve memory for U-Boot code, data & bss,
* round down to next 16 kB limit
*/
addr -= len;
addr &= ~(16 * 1024 - 1);
- /*
- * Reserve memory for malloc() arena.
- */
+ /* Reserve memory for malloc() arena */
addr_sp = addr - TOTAL_MALLOC_LEN;
/*
addr_sp -= sizeof(gd_t);
id = (gd_t *)addr_sp;
- /*
- * Reserve memory for boot params.
- */
+ /* Reserve memory for boot params */
addr_sp -= CFG_BOOTPARAMS_LEN;
bd->bi_boot_params = addr_sp;
/*
- * Finally, we set up a new (bigger) stack.
+ * Finally, we set up a new (bigger) stack
*
- * Leave some safety gap for SP, force alignment on 16 byte boundary
- * Clear initial stack frame
+ * Leave some safety gap for SP, force alignment on 16 byte boundary,
+ * clear initial stack frame
*/
addr_sp -= 16;
addr_sp &= ~0xF;
addr_sp = (ulong)s;
/*
- * Save local variables to board info struct
+ * Save local variables to board info struct:
+ * - start of DRAM memory
+ * - size of DRAM memory in bytes
*/
- bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */
- bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
+ bd->bi_memstart = CFG_SDRAM_BASE;
+ bd->bi_memsize = gd->ram_size;
memcpy(id, (void *)gd, sizeof(gd_t));
bootstrap_relocate_code(addr_sp, id, addr);
-
/* NOTREACHED - relocate_code() does not return */
}
*
************************************************************************
*/
-void bootstrap_board_init_r(gd_t *id, ulong dest_addr){
+void bootstrap_board_init_r(gd_t *id, ulong dest_addr)
+{
int i;
ulong addr;
ulong data, len, checksum;
unsigned int destLen;
int (*fn)(int);
- /* initialize malloc() area */
+ /* Initialize malloc() area */
mem_malloc_init(dest_addr);
addr = (ulong)((char *)(BOOTSTRAP_CFG_MONITOR_BASE + ((ulong)&uboot_end_data_bootstrap - dest_addr)));
memmove(&header, (char *)addr, sizeof(image_header_t));
- if(ntohl(hdr->ih_magic) != IH_MAGIC){
+ if (ntohl(hdr->ih_magic) != IH_MAGIC)
return;
- }
data = (ulong)&header;
len = sizeof(image_header_t);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if(crc32(0, (unsigned char *)data, len) != checksum){
+ if (tinf_crc32((unsigned char *)data, len) != checksum)
return;
- }
data = addr + sizeof(image_header_t);
len = ntohl(hdr->ih_size);
#ifdef CONFIG_LZMA
i = lzma_inflate((unsigned char *)data, len, (unsigned char*)ntohl(hdr->ih_load), (int *)&destLen);
- if(i != LZMA_RESULT_OK){
- //do_reset(cmdtp, flag, argc, argv);
+ if (i != LZMA_RESULT_OK)
return;
- }
#endif
fn = (void *)ntohl(hdr->ih_load);
hang();
}
-void hang(void){
- for(;;);
+void hang(void)
+{
+ for (;;)
+ ;
}
/*
- * This file is derived from crc32.c from the zlib-1.1.3 distribution
- * by Jean-loup Gailly and Mark Adler.
+ * CRC32 checksum
+ *
+ * Copyright (c) 1998-2003 by Joergen Ibsen / Jibz
+ * All Rights Reserved
+ *
+ * http://www.ibsensoftware.com/
+ *
+ * This software is provided 'as-is', without any express
+ * or implied warranty. In no event will the authors be
+ * held liable for any damages arising from the use of
+ * this software.
+ *
+ * Permission is granted to anyone to use this software
+ * for any purpose, including commercial applications,
+ * and to alter it and redistribute it freely, subject to
+ * the following restrictions:
+ *
+ * 1. The origin of this software must not be
+ * misrepresented; you must not claim that you
+ * wrote the original software. If you use this
+ * software in a product, an acknowledgment in
+ * the product documentation would be appreciated
+ * but is not required.
+ *
+ * 2. Altered source versions must be plainly marked
+ * as such, and must not be misrepresented as
+ * being the original software.
+ *
+ * 3. This notice may not be removed or altered from
+ * any source distribution.
*/
-/* crc32.c -- compute the CRC-32 of a data stream
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-#ifndef USE_HOSTCC /* Shut down "ANSI does not permit..." warnings */
-#include <common.h> /* to get command definitions like CFG_CMD_JFFS2 */
-#endif
-
-#include "zlib.h"
-
-#define local static
-#define ZEXPORT /* empty */
-unsigned long crc32 (unsigned long, const unsigned char *, unsigned int);
-
-#ifdef DYNAMIC_CRC_TABLE
-
-local int crc_table_empty = 1;
-local uLongf crc_table[256];
-local void make_crc_table OF((void));
-
/*
- Generate a table for a byte-wise 32-bit CRC calculation on the polynomial:
- x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1.
-
- Polynomials over GF(2) are represented in binary, one bit per coefficient,
- with the lowest powers in the most significant bit. Then adding polynomials
- is just exclusive-or, and multiplying a polynomial by x is a right shift by
- one. If we call the above polynomial p, and represent a byte as the
- polynomial q, also with the lowest power in the most significant bit (so the
- byte 0xb1 is the polynomial x^7+x^3+x+1), then the CRC is (q*x^32) mod p,
- where a mod b means the remainder after dividing a by b.
+ * CRC32 algorithm taken from the zlib source, which is
+ * Copyright (C) 1995-1998 Jean-loup Gailly and Mark Adler
+ */
- This calculation is done using the shift-register method of multiplying and
- taking the remainder. The register is initialized to zero, and for each
- incoming bit, x^32 is added mod p to the register if the bit is a one (where
- x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by
- x (which is shifting right by one and adding x^32 mod p if the bit shifted
- out is a one). We start with the highest power (least significant bit) of
- q and repeat for all eight bits of q.
+#include "tinf.h"
- The table is simply the CRC of all possible eight bit values. This is all
- the information needed to generate CRC's on data a byte at a time for all
- combinations of CRC register values and incoming bytes.
-*/
-local void make_crc_table(){
- uLong c;
- int n, k;
- uLong poly; /* polynomial exclusive-or pattern */
- /* terms of polynomial defining this crc (except x^32): */
- static const Byte p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26};
+static const unsigned int tinf_crc32tab[16] = {
+ 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, 0x76dc4190,
+ 0x6b6b51f4, 0x4db26158, 0x5005713c, 0xedb88320, 0xf00f9344,
+ 0xd6d6a3e8, 0xcb61b38c, 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278,
+ 0xbdbdf21c
+};
- /* make exclusive-or pattern from polynomial (0xedb88320L) */
- poly = 0L;
- for (n = 0; n < sizeof(p)/sizeof(Byte); n++)
- poly |= 1L << (31 - p[n]);
+unsigned int tinf_crc32(const void *data, unsigned int length)
+{
+ const unsigned char *buf = (const unsigned char *)data;
+ unsigned int crc = 0xffffffff;
+ unsigned int i;
- for (n = 0; n < 256; n++)
- {
- c = (uLong)n;
- for (k = 0; k < 8; k++)
- c = c & 1 ? poly ^ (c >> 1) : c >> 1;
- crc_table[n] = c;
- }
- crc_table_empty = 0;
-}
-#else
-/* ========================================================================
- * Table of CRC-32's of all single-byte values (made by make_crc_table)
- */
-local const uLongf crc_table[256] = {
- 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
- 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
- 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
- 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
- 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
- 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
- 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
- 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
- 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
- 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
- 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
- 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
- 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
- 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
- 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
- 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
- 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
- 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
- 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
- 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
- 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
- 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
- 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
- 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
- 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
- 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
- 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
- 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
- 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
- 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
- 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
- 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
- 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
- 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
- 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
- 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
- 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
- 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
- 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
- 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
- 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
- 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
- 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
- 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
- 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
- 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
- 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
- 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
- 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
- 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
- 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
- 0x2d02ef8dL
-};
-#endif
+ if (length == 0) return 0;
-/* ========================================================================= */
-#define DO1(buf) crc = crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
-#define DO2(buf) DO1(buf); DO1(buf);
-#define DO4(buf) DO2(buf); DO2(buf);
-#define DO8(buf) DO4(buf); DO4(buf);
+ for (i = 0; i < length; ++i)
+ {
+ crc ^= buf[i];
+ crc = tinf_crc32tab[crc & 0x0f] ^ (crc >> 4);
+ crc = tinf_crc32tab[crc & 0x0f] ^ (crc >> 4);
+ }
-/* ========================================================================= */
-uLong ZEXPORT crc32(crc, buf, len)
- uLong crc;
- const Bytef *buf;
- uInt len;
-{
-#ifdef DYNAMIC_CRC_TABLE
- if (crc_table_empty)
- make_crc_table();
-#endif
- crc = crc ^ 0xffffffffL;
- while (len >= 8)
- {
- DO8(buf);
- len -= 8;
- }
- if (len) do {
- DO1(buf);
- } while (--len);
- return crc ^ 0xffffffffL;
+ return crc ^ 0xffffffff;
}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static inline void mips_compare_set(u32 v){
- asm volatile ("mtc0 %0, $11" : : "r" (v));
-}
-
-static inline void mips_count_set(u32 v){
- asm volatile ("mtc0 %0, $9" : : "r" (v));
-}
-
-static inline u32 mips_count_get(void){
- u32 count;
-
- asm volatile ("mfc0 %0, $9" : "=r" (count) :);
- return(count);
-}
-
-/*
- * timer without interrupts
- */
-int timer_init(void){
- mips_compare_set(0);
- mips_count_set(0);
-
- return(0);
-}
-
-ulong get_timer(ulong base){
- return(mips_count_get() - base);
-}
-
-void udelay(unsigned long usec){
- ulong tmo;
- ulong start = get_timer(0);
- bd_t *bd = gd->bd;
-
- /*
- * We don't have filled the bd->bi_cfg_hz
- * before relocation to RAM (bd is read only before that),
- */
- if((gd->flags & GD_FLG_RELOC) == 0){
- tmo = usec * (CFG_HZ_FALLBACK / 1000000);
- } else {
- tmo = usec * (CFG_HZ / 1000000);
- }
-
- while ((ulong)((mips_count_get() - start)) < tmo)
- /*NOP*/;
-}
/*
- * This file is derived from crc32.c from the zlib-1.1.3 distribution
- * by Jean-loup Gailly and Mark Adler.
+ * CRC32 checksum
+ *
+ * Copyright (c) 1998-2003 by Joergen Ibsen / Jibz
+ * All Rights Reserved
+ *
+ * http://www.ibsensoftware.com/
+ *
+ * This software is provided 'as-is', without any express
+ * or implied warranty. In no event will the authors be
+ * held liable for any damages arising from the use of
+ * this software.
+ *
+ * Permission is granted to anyone to use this software
+ * for any purpose, including commercial applications,
+ * and to alter it and redistribute it freely, subject to
+ * the following restrictions:
+ *
+ * 1. The origin of this software must not be
+ * misrepresented; you must not claim that you
+ * wrote the original software. If you use this
+ * software in a product, an acknowledgment in
+ * the product documentation would be appreciated
+ * but is not required.
+ *
+ * 2. Altered source versions must be plainly marked
+ * as such, and must not be misrepresented as
+ * being the original software.
+ *
+ * 3. This notice may not be removed or altered from
+ * any source distribution.
*/
-/* crc32.c -- compute the CRC-32 of a data stream
- * Copyright (C) 1995-1998 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
- */
-
-#ifndef USE_HOSTCC /* Shut down "ANSI does not permit..." warnings */
-#include <common.h> /* to get command definitions like CFG_CMD_JFFS2 */
-#endif
-
-#include "zlib.h"
-
-#define local static
-#define ZEXPORT /* empty */
-unsigned long crc32 (unsigned long, const unsigned char *, unsigned int);
-
-#ifdef DYNAMIC_CRC_TABLE
-
-local int crc_table_empty = 1;
-local uLongf crc_table[256];
-local void make_crc_table OF((void));
-
/*
- Generate a table for a byte-wise 32-bit CRC calculation on the polynomial:
- x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1.
-
- Polynomials over GF(2) are represented in binary, one bit per coefficient,
- with the lowest powers in the most significant bit. Then adding polynomials
- is just exclusive-or, and multiplying a polynomial by x is a right shift by
- one. If we call the above polynomial p, and represent a byte as the
- polynomial q, also with the lowest power in the most significant bit (so the
- byte 0xb1 is the polynomial x^7+x^3+x+1), then the CRC is (q*x^32) mod p,
- where a mod b means the remainder after dividing a by b.
-
- This calculation is done using the shift-register method of multiplying and
- taking the remainder. The register is initialized to zero, and for each
- incoming bit, x^32 is added mod p to the register if the bit is a one (where
- x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by
- x (which is shifting right by one and adding x^32 mod p if the bit shifted
- out is a one). We start with the highest power (least significant bit) of
- q and repeat for all eight bits of q.
-
- The table is simply the CRC of all possible eight bit values. This is all
- the information needed to generate CRC's on data a byte at a time for all
- combinations of CRC register values and incoming bytes.
-*/
-local void make_crc_table()
-{
- uLong c;
- int n, k;
- uLong poly; /* polynomial exclusive-or pattern */
- /* terms of polynomial defining this crc (except x^32): */
- static const Byte p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26};
+ * CRC32 algorithm taken from the zlib source, which is
+ * Copyright (C) 1995-1998 Jean-loup Gailly and Mark Adler
+ */
- /* make exclusive-or pattern from polynomial (0xedb88320L) */
- poly = 0L;
- for (n = 0; n < sizeof(p)/sizeof(Byte); n++)
- poly |= 1L << (31 - p[n]);
+#include "tinf.h"
- for (n = 0; n < 256; n++)
- {
- c = (uLong)n;
- for (k = 0; k < 8; k++)
- c = c & 1 ? poly ^ (c >> 1) : c >> 1;
- crc_table[n] = c;
- }
- crc_table_empty = 0;
-}
-#else
-/* ========================================================================
- * Table of CRC-32's of all single-byte values (made by make_crc_table)
- */
-local const uLongf crc_table[256] = {
- 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
- 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
- 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
- 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
- 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
- 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
- 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
- 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
- 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
- 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
- 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
- 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
- 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
- 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
- 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
- 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
- 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
- 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
- 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
- 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
- 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
- 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
- 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
- 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
- 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
- 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
- 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
- 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
- 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
- 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
- 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
- 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
- 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
- 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
- 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
- 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
- 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
- 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
- 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
- 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
- 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
- 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
- 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
- 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
- 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
- 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
- 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
- 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
- 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
- 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
- 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
- 0x2d02ef8dL
+static const unsigned int tinf_crc32tab[16] = {
+ 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, 0x76dc4190,
+ 0x6b6b51f4, 0x4db26158, 0x5005713c, 0xedb88320, 0xf00f9344,
+ 0xd6d6a3e8, 0xcb61b38c, 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278,
+ 0xbdbdf21c
};
-#endif
-#if 0
-/* =========================================================================
- * This function can be used by asm versions of crc32()
- */
-const uLongf * ZEXPORT get_crc_table()
+unsigned int tinf_crc32(const void *data, unsigned int length)
{
-#ifdef DYNAMIC_CRC_TABLE
- if (crc_table_empty) make_crc_table();
-#endif
- return (const uLongf *)crc_table;
-}
-#endif
+ const unsigned char *buf = (const unsigned char *)data;
+ unsigned int crc = 0xffffffff;
+ unsigned int i;
-/* ========================================================================= */
-#define DO1(buf) crc = crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
-#define DO2(buf) DO1(buf); DO1(buf);
-#define DO4(buf) DO2(buf); DO2(buf);
-#define DO8(buf) DO4(buf); DO4(buf);
+ if (length == 0) return 0;
-/* ========================================================================= */
-uLong ZEXPORT crc32(crc, buf, len)
- uLong crc;
- const Bytef *buf;
- uInt len;
-{
-#ifdef DYNAMIC_CRC_TABLE
- if (crc_table_empty)
- make_crc_table();
-#endif
- crc = crc ^ 0xffffffffL;
- while (len >= 8)
- {
- DO8(buf);
- len -= 8;
- }
- if (len) do {
- DO1(buf);
- } while (--len);
- return crc ^ 0xffffffffL;
+ for (i = 0; i < length; ++i)
+ {
+ crc ^= buf[i];
+ crc = tinf_crc32tab[crc & 0x0f] ^ (crc >> 4);
+ crc = tinf_crc32tab[crc & 0x0f] ^ (crc >> 4);
+ }
+
+ return crc ^ 0xffffffff;
}
--- /dev/null
+/*
+ * CRC32 checksum
+ *
+ * Copyright (c) 1998-2003 by Joergen Ibsen / Jibz
+ * All Rights Reserved
+ *
+ * http://www.ibsensoftware.com/
+ *
+ * This software is provided 'as-is', without any express
+ * or implied warranty. In no event will the authors be
+ * held liable for any damages arising from the use of
+ * this software.
+ *
+ * Permission is granted to anyone to use this software
+ * for any purpose, including commercial applications,
+ * and to alter it and redistribute it freely, subject to
+ * the following restrictions:
+ *
+ * 1. The origin of this software must not be
+ * misrepresented; you must not claim that you
+ * wrote the original software. If you use this
+ * software in a product, an acknowledgment in
+ * the product documentation would be appreciated
+ * but is not required.
+ *
+ * 2. Altered source versions must be plainly marked
+ * as such, and must not be misrepresented as
+ * being the original software.
+ *
+ * 3. This notice may not be removed or altered from
+ * any source distribution.
+ */
+
+/*
+ * CRC32 algorithm taken from the zlib source, which is
+ * Copyright (C) 1995-1998 Jean-loup Gailly and Mark Adler
+ */
+
+#include "tinf.h"
+
+static const unsigned int tinf_crc32tab[16] = {
+ 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, 0x76dc4190,
+ 0x6b6b51f4, 0x4db26158, 0x5005713c, 0xedb88320, 0xf00f9344,
+ 0xd6d6a3e8, 0xcb61b38c, 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278,
+ 0xbdbdf21c
+};
+
+unsigned int tinf_crc32(const void *data, unsigned int length)
+{
+ const unsigned char *buf = (const unsigned char *)data;
+ unsigned int crc = 0xffffffff;
+ unsigned int i;
+
+ if (length == 0) return 0;
+
+ for (i = 0; i < length; ++i)
+ {
+ crc ^= buf[i];
+ crc = tinf_crc32tab[crc & 0x0f] ^ (crc >> 4);
+ crc = tinf_crc32tab[crc & 0x0f] ^ (crc >> 4);
+ }
+
+ return crc ^ 0xffffffff;
+}
--- /dev/null
+/*
+ * tinfgzip - tiny gzip decompressor
+ *
+ * Copyright (c) 2003 by Joergen Ibsen / Jibz
+ * All Rights Reserved
+ *
+ * http://www.ibsensoftware.com/
+ *
+ * This software is provided 'as-is', without any express
+ * or implied warranty. In no event will the authors be
+ * held liable for any damages arising from the use of
+ * this software.
+ *
+ * Permission is granted to anyone to use this software
+ * for any purpose, including commercial applications,
+ * and to alter it and redistribute it freely, subject to
+ * the following restrictions:
+ *
+ * 1. The origin of this software must not be
+ * misrepresented; you must not claim that you
+ * wrote the original software. If you use this
+ * software in a product, an acknowledgment in
+ * the product documentation would be appreciated
+ * but is not required.
+ *
+ * 2. Altered source versions must be plainly marked
+ * as such, and must not be misrepresented as
+ * being the original software.
+ *
+ * 3. This notice may not be removed or altered from
+ * any source distribution.
+ */
+
+#include "tinf.h"
+
+#define FTEXT 1
+#define FHCRC 2
+#define FEXTRA 4
+#define FNAME 8
+#define FCOMMENT 16
+
+int tinf_gzip_uncompress(void *dest, unsigned int *destLen,
+ const void *source, unsigned int sourceLen)
+{
+ unsigned char *src = (unsigned char *)source;
+ unsigned char *dst = (unsigned char *)dest;
+ unsigned char *start;
+ unsigned int dlen, crc32;
+ int res;
+ unsigned char flg;
+
+ /* -- check format -- */
+
+ /* check id bytes */
+ if (src[0] != 0x1f || src[1] != 0x8b) return TINF_DATA_ERROR;
+
+ /* check method is deflate */
+ if (src[2] != 8) return TINF_DATA_ERROR;
+
+ /* get flag byte */
+ flg = src[3];
+
+ /* check that reserved bits are zero */
+ if (flg & 0xe0) return TINF_DATA_ERROR;
+
+ /* -- find start of compressed data -- */
+
+ /* skip base header of 10 bytes */
+ start = src + 10;
+
+ /* skip extra data if present */
+ if (flg & FEXTRA)
+ {
+ unsigned int xlen = start[1];
+ xlen = 256*xlen + start[0];
+ start += xlen + 2;
+ }
+
+ /* skip file name if present */
+ if (flg & FNAME) { while (*start) ++start; ++start; }
+
+ /* skip file comment if present */
+ if (flg & FCOMMENT) { while (*start) ++start; ++start; }
+
+ /* check header crc if present */
+ if (flg & FHCRC)
+ {
+ unsigned int hcrc = start[1];
+ hcrc = 256*hcrc + start[0];
+
+ if (hcrc != (tinf_crc32(src, start - src) & 0x0000ffff))
+ return TINF_DATA_ERROR;
+
+ start += 2;
+ }
+
+ /* -- get decompressed length -- */
+
+ dlen = src[sourceLen - 1];
+ dlen = 256*dlen + src[sourceLen - 2];
+ dlen = 256*dlen + src[sourceLen - 3];
+ dlen = 256*dlen + src[sourceLen - 4];
+
+ /* -- get crc32 of decompressed data -- */
+
+ crc32 = src[sourceLen - 5];
+ crc32 = 256*crc32 + src[sourceLen - 6];
+ crc32 = 256*crc32 + src[sourceLen - 7];
+ crc32 = 256*crc32 + src[sourceLen - 8];
+
+ /* -- decompress data -- */
+
+ res = tinf_uncompress(dst, destLen, start, src + sourceLen - start - 8);
+
+ if (res != TINF_OK) return TINF_DATA_ERROR;
+
+ if (*destLen != dlen) return TINF_DATA_ERROR;
+
+ /* -- check CRC32 checksum -- */
+
+ if (crc32 != tinf_crc32(dst, dlen)) return TINF_DATA_ERROR;
+
+ return TINF_OK;
+}
--- /dev/null
+/*
+ * tinflate - tiny inflate
+ *
+ * Copyright (c) 2003 by Joergen Ibsen / Jibz
+ * All Rights Reserved
+ *
+ * http://www.ibsensoftware.com/
+ *
+ * This software is provided 'as-is', without any express
+ * or implied warranty. In no event will the authors be
+ * held liable for any damages arising from the use of
+ * this software.
+ *
+ * Permission is granted to anyone to use this software
+ * for any purpose, including commercial applications,
+ * and to alter it and redistribute it freely, subject to
+ * the following restrictions:
+ *
+ * 1. The origin of this software must not be
+ * misrepresented; you must not claim that you
+ * wrote the original software. If you use this
+ * software in a product, an acknowledgment in
+ * the product documentation would be appreciated
+ * but is not required.
+ *
+ * 2. Altered source versions must be plainly marked
+ * as such, and must not be misrepresented as
+ * being the original software.
+ *
+ * 3. This notice may not be removed or altered from
+ * any source distribution.
+ */
+
+#include "tinf.h"
+
+/* ------------------------------ *
+ * -- internal data structures -- *
+ * ------------------------------ */
+
+typedef struct {
+ unsigned short table[16]; /* table of code length counts */
+ unsigned short trans[288]; /* code -> symbol translation table */
+} TINF_TREE;
+
+typedef struct {
+ const unsigned char *source;
+ unsigned int tag;
+ unsigned int bitcount;
+
+ unsigned char *dest;
+ unsigned int *destLen;
+
+ TINF_TREE ltree; /* dynamic length/symbol tree */
+ TINF_TREE dtree; /* dynamic distance tree */
+} TINF_DATA;
+
+/* --------------------------------------------------- *
+ * -- uninitialized global data (static structures) -- *
+ * --------------------------------------------------- */
+
+TINF_TREE sltree; /* fixed length/symbol tree */
+TINF_TREE sdtree; /* fixed distance tree */
+
+/* extra bits and base tables for length codes */
+unsigned char length_bits[30];
+unsigned short length_base[30];
+
+/* extra bits and base tables for distance codes */
+unsigned char dist_bits[30];
+unsigned short dist_base[30];
+
+/* special ordering of code length codes */
+const unsigned char clcidx[] = {
+ 16, 17, 18, 0, 8, 7, 9, 6,
+ 10, 5, 11, 4, 12, 3, 13, 2,
+ 14, 1, 15
+};
+
+/* ----------------------- *
+ * -- utility functions -- *
+ * ----------------------- */
+
+/* build extra bits and base tables */
+static void tinf_build_bits_base(unsigned char *bits, unsigned short *base, int delta, int first)
+{
+ int i, sum;
+
+ /* build bits table */
+ for (i = 0; i < delta; ++i) bits[i] = 0;
+ for (i = 0; i < 30 - delta; ++i) bits[i + delta] = i / delta;
+
+ /* build base table */
+ for (sum = first, i = 0; i < 30; ++i)
+ {
+ base[i] = sum;
+ sum += 1 << bits[i];
+ }
+}
+
+/* build the fixed huffman trees */
+static void tinf_build_fixed_trees(TINF_TREE *lt, TINF_TREE *dt)
+{
+ int i;
+
+ /* build fixed length tree */
+ for (i = 0; i < 7; ++i) lt->table[i] = 0;
+
+ lt->table[7] = 24;
+ lt->table[8] = 152;
+ lt->table[9] = 112;
+
+ for (i = 0; i < 24; ++i) lt->trans[i] = 256 + i;
+ for (i = 0; i < 144; ++i) lt->trans[24 + i] = i;
+ for (i = 0; i < 8; ++i) lt->trans[24 + 144 + i] = 280 + i;
+ for (i = 0; i < 112; ++i) lt->trans[24 + 144 + 8 + i] = 144 + i;
+
+ /* build fixed distance tree */
+ for (i = 0; i < 5; ++i) dt->table[i] = 0;
+
+ dt->table[5] = 32;
+
+ for (i = 0; i < 32; ++i) dt->trans[i] = i;
+}
+
+/* given an array of code lengths, build a tree */
+static void tinf_build_tree(TINF_TREE *t, const unsigned char *lengths, unsigned int num)
+{
+ unsigned short offs[16];
+ unsigned int i, sum;
+
+ /* clear code length count table */
+ for (i = 0; i < 16; ++i) t->table[i] = 0;
+
+ /* scan symbol lengths, and sum code length counts */
+ for (i = 0; i < num; ++i) t->table[lengths[i]]++;
+
+ t->table[0] = 0;
+
+ /* compute offset table for distribution sort */
+ for (sum = 0, i = 0; i < 16; ++i)
+ {
+ offs[i] = sum;
+ sum += t->table[i];
+ }
+
+ /* create code->symbol translation table (symbols sorted by code) */
+ for (i = 0; i < num; ++i)
+ {
+ if (lengths[i]) t->trans[offs[lengths[i]]++] = i;
+ }
+}
+
+/* ---------------------- *
+ * -- decode functions -- *
+ * ---------------------- */
+
+/* get one bit from source stream */
+static int tinf_getbit(TINF_DATA *d)
+{
+ unsigned int bit;
+
+ /* check if tag is empty */
+ if (!d->bitcount--)
+ {
+ /* load next tag */
+ d->tag = *d->source++;
+ d->bitcount = 7;
+ }
+
+ /* shift bit out of tag */
+ bit = d->tag & 0x01;
+ d->tag >>= 1;
+
+ return bit;
+}
+
+/* read a num bit value from a stream and add base */
+static unsigned int tinf_read_bits(TINF_DATA *d, int num, int base)
+{
+ unsigned int val = 0;
+
+ /* read num bits */
+ if (num)
+ {
+ unsigned int limit = 1 << (num);
+ unsigned int mask;
+
+ for (mask = 1; mask < limit; mask *= 2)
+ if (tinf_getbit(d)) val += mask;
+ }
+
+ return val + base;
+}
+
+/* given a data stream and a tree, decode a symbol */
+static int tinf_decode_symbol(TINF_DATA *d, TINF_TREE *t)
+{
+ int sum = 0, cur = 0, len = 0;
+
+ /* get more bits while code value is above sum */
+ do {
+
+ cur = 2*cur + tinf_getbit(d);
+
+ ++len;
+
+ sum += t->table[len];
+ cur -= t->table[len];
+
+ } while (cur >= 0);
+
+ return t->trans[sum + cur];
+}
+
+/* given a data stream, decode dynamic trees from it */
+static void tinf_decode_trees(TINF_DATA *d, TINF_TREE *lt, TINF_TREE *dt)
+{
+ TINF_TREE code_tree;
+ unsigned char lengths[288+32];
+ unsigned int hlit, hdist, hclen;
+ unsigned int i, num, length;
+
+ /* get 5 bits HLIT (257-286) */
+ hlit = tinf_read_bits(d, 5, 257);
+
+ /* get 5 bits HDIST (1-32) */
+ hdist = tinf_read_bits(d, 5, 1);
+
+ /* get 4 bits HCLEN (4-19) */
+ hclen = tinf_read_bits(d, 4, 4);
+
+ for (i = 0; i < 19; ++i) lengths[i] = 0;
+
+ /* read code lengths for code length alphabet */
+ for (i = 0; i < hclen; ++i)
+ {
+ /* get 3 bits code length (0-7) */
+ unsigned int clen = tinf_read_bits(d, 3, 0);
+
+ lengths[clcidx[i]] = clen;
+ }
+
+ /* build code length tree */
+ tinf_build_tree(&code_tree, lengths, 19);
+
+ /* decode code lengths for the dynamic trees */
+ for (num = 0; num < hlit + hdist; )
+ {
+ int sym = tinf_decode_symbol(d, &code_tree);
+
+ switch (sym)
+ {
+ case 16:
+ /* copy previous code length 3-6 times (read 2 bits) */
+ {
+ unsigned char prev = lengths[num - 1];
+ for (length = tinf_read_bits(d, 2, 3); length; --length)
+ {
+ lengths[num++] = prev;
+ }
+ }
+ break;
+ case 17:
+ /* repeat code length 0 for 3-10 times (read 3 bits) */
+ for (length = tinf_read_bits(d, 3, 3); length; --length)
+ {
+ lengths[num++] = 0;
+ }
+ break;
+ case 18:
+ /* repeat code length 0 for 11-138 times (read 7 bits) */
+ for (length = tinf_read_bits(d, 7, 11); length; --length)
+ {
+ lengths[num++] = 0;
+ }
+ break;
+ default:
+ /* values 0-15 represent the actual code lengths */
+ lengths[num++] = sym;
+ break;
+ }
+ }
+
+ /* build dynamic trees */
+ tinf_build_tree(lt, lengths, hlit);
+ tinf_build_tree(dt, lengths + hlit, hdist);
+}
+
+/* ----------------------------- *
+ * -- block inflate functions -- *
+ * ----------------------------- */
+
+/* given a stream and two trees, inflate a block of data */
+static int tinf_inflate_block_data(TINF_DATA *d, TINF_TREE *lt, TINF_TREE *dt)
+{
+ /* remember current output position */
+ unsigned char *start = d->dest;
+
+ while (1)
+ {
+ int sym = tinf_decode_symbol(d, lt);
+
+ /* check for end of block */
+ if (sym == 256)
+ {
+ *d->destLen += d->dest - start;
+ return TINF_OK;
+ }
+
+ if (sym < 256)
+ {
+ *d->dest++ = sym;
+
+ } else {
+
+ int length, dist, offs;
+ int i;
+
+ sym -= 257;
+
+ /* possibly get more bits from length code */
+ length = tinf_read_bits(d, length_bits[sym], length_base[sym]);
+
+ dist = tinf_decode_symbol(d, dt);
+
+ /* possibly get more bits from distance code */
+ offs = tinf_read_bits(d, dist_bits[dist], dist_base[dist]);
+
+ /* copy match */
+ for (i = 0; i < length; ++i)
+ {
+ d->dest[i] = d->dest[i - offs];
+ }
+
+ d->dest += length;
+ }
+ }
+}
+
+/* inflate an uncompressed block of data */
+static int tinf_inflate_uncompressed_block(TINF_DATA *d)
+{
+ unsigned int length, invlength;
+ unsigned int i;
+
+ /* get length */
+ length = d->source[1];
+ length = 256*length + d->source[0];
+
+ /* get one's complement of length */
+ invlength = d->source[3];
+ invlength = 256*invlength + d->source[2];
+
+ /* check length */
+ if (length != (~invlength & 0x0000ffff)) return TINF_DATA_ERROR;
+
+ d->source += 4;
+
+ /* copy block */
+ for (i = length; i; --i) *d->dest++ = *d->source++;
+
+ /* make sure we start next block on a byte boundary */
+ d->bitcount = 0;
+
+ *d->destLen += length;
+
+ return TINF_OK;
+}
+
+/* inflate a block of data compressed with fixed huffman trees */
+static int tinf_inflate_fixed_block(TINF_DATA *d)
+{
+ /* decode block using fixed trees */
+ return tinf_inflate_block_data(d, &sltree, &sdtree);
+}
+
+/* inflate a block of data compressed with dynamic huffman trees */
+static int tinf_inflate_dynamic_block(TINF_DATA *d)
+{
+ /* decode trees from stream */
+ tinf_decode_trees(d, &d->ltree, &d->dtree);
+
+ /* decode block using decoded trees */
+ return tinf_inflate_block_data(d, &d->ltree, &d->dtree);
+}
+
+/* ---------------------- *
+ * -- public functions -- *
+ * ---------------------- */
+
+/* initialize global (static) data */
+void tinf_init()
+{
+ /* build fixed huffman trees */
+ tinf_build_fixed_trees(&sltree, &sdtree);
+
+ /* build extra bits and base tables */
+ tinf_build_bits_base(length_bits, length_base, 4, 3);
+ tinf_build_bits_base(dist_bits, dist_base, 2, 1);
+
+ /* fix a special case */
+ length_bits[28] = 0;
+ length_base[28] = 258;
+}
+
+/* inflate stream from source to dest */
+int tinf_uncompress(void *dest, unsigned int *destLen,
+ const void *source, unsigned int sourceLen)
+{
+ TINF_DATA d;
+ int bfinal;
+
+ /* initialise data */
+ d.source = (const unsigned char *)source;
+ d.bitcount = 0;
+
+ d.dest = (unsigned char *)dest;
+ d.destLen = destLen;
+
+ *destLen = 0;
+
+ do {
+
+ unsigned int btype;
+ int res;
+
+ /* read final block flag */
+ bfinal = tinf_getbit(&d);
+
+ /* read block type (2 bits) */
+ btype = tinf_read_bits(&d, 2, 0);
+
+ /* decompress block */
+ switch (btype)
+ {
+ case 0:
+ /* decompress uncompressed block */
+ res = tinf_inflate_uncompressed_block(&d);
+ break;
+ case 1:
+ /* decompress block with fixed huffman trees */
+ res = tinf_inflate_fixed_block(&d);
+ break;
+ case 2:
+ /* decompress block with dynamic huffman trees */
+ res = tinf_inflate_dynamic_block(&d);
+ break;
+ default:
+ return TINF_DATA_ERROR;
+ }
+
+ if (res != TINF_OK) return TINF_DATA_ERROR;
+
+ } while (!bfinal);
+
+ return TINF_OK;
+}
#include <version.h>
#include <net.h>
#include <environment.h>
-#include "ar7240_soc.h"
-#include "../board/ar7240/common/ar7240_flash.h"
DECLARE_GLOBAL_DATA_PTR;
-//#define BOARD_DEBUG
+/*#define BOARD_DEBUG*/
-#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || defined(CFG_ENV_IS_IN_NVRAM)
-#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE)
+#if (((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
+ (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN))) \
+ || defined(CFG_ENV_IS_IN_NVRAM)
+ #define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE)
#else
-#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
+ #define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
#endif
-#define CHECK_BIT(var,pos) ((var) & (1<<(pos)))
-
extern ulong uboot_end_data;
extern ulong uboot_end;
-extern int timer_init(void);
-
-extern void all_led_on(void);
-extern void all_led_off(void);
-extern const char* print_mem_type(void);
-#ifdef CONFIG_WASP
-extern void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq);
-#else
-extern void ar933x_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq);
-#endif
-
ulong monitor_flash_len;
-const char version_string[] = U_BOOT_VERSION" (" __DATE__ ", " __TIME__ ")";
+const char version_string[] = U_BOOT_VERSION;
-// Begin and End of memory area for malloc(), and current "brk"
+/* Begin and end of memory area for malloc(), and current "brk" */
static ulong mem_malloc_start;
static ulong mem_malloc_end;
static ulong mem_malloc_brk;
-// The Malloc area is immediately below the monitor copy in DRAM
-static void mem_malloc_init(void){
+/* The Malloc area is immediately below the monitor copy in DRAM */
+static void mem_malloc_init(void)
+{
ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off;
mem_malloc_end = dest_addr;
memset((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start);
}
-void *sbrk(ptrdiff_t increment){
+void *sbrk(ptrdiff_t increment)
+{
ulong old = mem_malloc_brk;
ulong new = old + increment;
- if((new < mem_malloc_start) || (new > mem_malloc_end)){
- return(NULL);
+ if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
+ printf("## Error: sbrk: out of memory (%d requested > %d available)\n",
+ increment, mem_malloc_end - old);
+
+ return (void*)MORECORE_FAILURE;
}
+
mem_malloc_brk = new;
- return((void *)old);
+
+ return (void *)old;
}
-static int display_banner(void){
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- printf("\n\n*********************************************\n* %s *\n*********************************************\n\n", version_string);
-#else
- printf("\n\n*********************************************\n");
- printf("* *\n");
- printf("* RAM VERSION *\n");
- printf("* *\n");
- printf("*********************************************\n* %s *\n*********************************************\n\n", version_string);
+static int display_banner(void)
+{
+ puts("\n");
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+ puts("\n***************************************"
+ "\n* *"
+ "\n* RAM VERSION *"
+ "\n* *");
#endif
- return(0);
+
+ printf("\n***************************************"
+ "\n* %s *"
+ "\n* " __DATE__ ", " __TIME__ " *"
+ "\n***************************************\n\n",
+ version_string);
+
+ return 0;
}
-static int init_baudrate(void){
+static int baudrate_init(void)
+{
char *s;
- if((s = getenv("baudrate")) != NULL){
+ if ((s = getenv("baudrate")) != NULL) {
gd->baudrate = simple_strtoul(s, NULL, 10);
} else {
gd->baudrate = CONFIG_BAUDRATE;
}
- return(0);
+
+ return 0;
}
#ifndef COMPRESSED_UBOOT
-static int init_func_ram(void){
- puts("DRAM: ");
-
- if((gd->ram_size = initdram()) > 0){
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- print_size(gd->ram_size, print_mem_type());
-#else
- // TODO: fix me!
- print_size(gd->ram_size + 1024*1024, print_mem_type());
-#endif
- puts("\n");
- return(0);
- }
+static int init_func_ram(void)
+{
+ if ((gd->ram_size = dram_init()) > 0)
+ return 0;
puts("## Error on RAM initialization!\n");
- return(1);
+ return 1;
}
#endif
#ifndef COMPRESSED_UBOOT
init_fnc_t *init_sequence[] = { timer_init,
- env_init, /* initialize environment */
- init_baudrate, /* initialze baudrate settings */
- serial_init, /* serial communications setup */
- console_init_f,
- display_banner, /* say that we are here */
- checkboard,
- init_func_ram,
- NULL, };
+ env_init,
+ baudrate_init,
+ serial_init,
+ console_init_f,
+ display_banner,
+ init_func_ram,
+ NULL, };
#else
-init_fnc_t *init_sequence[] = { env_init, /* initialize environment */
- init_baudrate, /* initialze baudrate settings */
- serial_init, /* serial communications setup */
- console_init_f, /* initialize console */
- display_banner, /* say that we are here -> print baner */
- NULL, };
+init_fnc_t *init_sequence[] = { env_init,
+ baudrate_init,
+ serial_init,
+ console_init_f,
+ display_banner,
+ NULL, };
#endif
/*
* BOARD INITIALIZATION
*
*/
-void board_init_f(ulong bootflag){
+void board_init_f(ulong bootflag)
+{
gd_t gd_data, *id;
bd_t *bd;
init_fnc_t **init_fnc_ptr;
ulong addr, addr_sp, len = (ulong)&uboot_end - CFG_MONITOR_BASE;
ulong *s;
- // Pointer is writable since we allocated a register for it.
+ /* Pointer is writable since we allocated a register for it */
gd = &gd_data;
- /* compiler optimization barrier needed for GCC >= 3.4 */
+ /* Compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
memset((void *)gd, 0, sizeof(gd_t));
- // loop trough init_sequence
- for(init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr){
- if((*init_fnc_ptr)() != 0){
+ /* Loop trough init_sequence */
+ for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0)
hang();
- }
}
#ifdef COMPRESSED_UBOOT
- // print BOARD_CUSTOM_STRING
- puts(BOARD_CUSTOM_STRING"\n\n");
-
- // count ram size and print it
gd->ram_size = bootflag;
- puts("DRAM: ");
- print_size(gd->ram_size, print_mem_type());
- puts("\n");
#endif
/*
* Now that we have DRAM mapped and working, we can
- * relocate the code and continue running from DRAM.
+ * relocate the code and continue running from DRAM
*/
addr = CFG_SDRAM_BASE + gd->ram_size;
/*
- * We can reserve some RAM "on top" here.
- */
-
- /*
- * round down to next 4 kB limit.
+ * We can reserve some RAM "on top" here,
+ * round down to next 4 kB limit
*/
addr &= ~(4096 - 1);
#endif
/*
- * Reserve memory for U-Boot code, data & bss
+ * Reserve memory for U-Boot code, data & bss,
* round down to next 16 kB limit
*/
addr -= len;
printf("Reserving %ldk for U-Boot at: %08lX\n", len >> 10, addr);
#endif
- /*
- * Reserve memory for malloc() arena.
- */
+ /* Reserve memory for malloc() arena */
addr_sp = addr - TOTAL_MALLOC_LEN;
#ifdef BOARD_DEBUG
printf("Reserving %d Bytes for Global Data at: %08lX\n", sizeof(gd_t), addr_sp);
#endif
- /* Reserve memory for boot params.
- */
+ /* Reserve memory for boot params */
addr_sp -= CFG_BOOTPARAMS_LEN;
bd->bi_boot_params = addr_sp;
#endif
/*
- * Finally, we set up a new (bigger) stack.
+ * Finally, we set up a new (bigger) stack
*
- * Leave some safety gap for SP, force alignment on 16 byte boundary
- * Clear initial stack frame
+ * Leave some safety gap for SP, force alignment on 16 byte boundary,
+ * clear initial stack frame
*/
addr_sp -= 16;
addr_sp &= ~0xF;
#endif
/*
- * Save local variables to board info struct
+ * Save local variables to board info struct:
+ * - start of DRAM memory
+ * - size of DRAM memory in bytes
+ * - console baudrate
*/
- bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */
- bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
- bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
+ bd->bi_memstart = CFG_SDRAM_BASE;
+ bd->bi_memsize = gd->ram_size;
+ bd->bi_baudrate = gd->baudrate;
memcpy(id, (void *)gd, sizeof(gd_t));
*
************************************************************************
*/
-void board_init_r(gd_t *id, ulong dest_addr){
+void board_init_r(gd_t *id, ulong dest_addr)
+{
cmd_tbl_t *cmdtp;
- ulong size;
extern void malloc_bin_reloc(void);
#ifndef CFG_ENV_IS_NOWHERE
- extern char * env_name_spec;
+ extern char *env_name_spec;
#endif
bd_t *bd;
char *s;
-#if defined(OFFSET_MAC_ADDRESS)
- unsigned char buffer[6];
-#endif
- unsigned int ahb_freq, ddr_freq, cpu_freq, spi_freq;
gd = id;
- gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
+
+ /* Tell others: relocation done */
+ gd->flags |= GD_FLG_RELOC;
/* bd -> board data */
bd = gd->bd;
- /* get CPU/RAM/AHB clocks */
-#ifdef CONFIG_WASP
- ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
-#else
- ar933x_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
-#endif
-
- /* set bi_cfg_hz */
- bd->bi_cfg_hz = (unsigned long)(cpu_freq >> 1);
-
#ifdef BOARD_DEBUG
printf("Now running in RAM - U-Boot at: %08lX\n", dest_addr);
#endif
+ /* We need (half of the) main CPU clock for udelay */
+ bd->bi_cfg_hz = (u32)(main_cpu_clk() >> 1);
+
gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
monitor_flash_len = (ulong)&uboot_end_data - dest_addr;
- /*
- * We have to relocate the command table manually
- */
- for(cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++){
+ /* We have to relocate the command table manually */
+ for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
ulong addr;
addr = (ulong)(cmdtp->cmd) + gd->reloc_off;
addr = (ulong)(cmdtp->name) + gd->reloc_off;
cmdtp->name = (char *)addr;
- if(cmdtp->usage){
+ if (cmdtp->usage) {
addr = (ulong)(cmdtp->usage) + gd->reloc_off;
cmdtp->usage = (char *)addr;
}
+
#ifdef CFG_LONGHELP
- if(cmdtp->help){
+ if (cmdtp->help) {
addr = (ulong)(cmdtp->help) + gd->reloc_off;
cmdtp->help = (char *)addr;
}
#endif
}
- /* there are some other pointer constants we must deal with */
+ /* There are some other pointer constants we must deal with */
#ifndef CFG_ENV_IS_NOWHERE
env_name_spec += gd->reloc_off;
#endif
- /* configure available FLASH banks */
- size = flash_init();
-
+ /* Configure available FLASH banks */
bd->bi_flashstart = CFG_FLASH_BASE;
- bd->bi_flashsize = size;
-
- // calculate SPI clock (we need to set bit 0 to 1 in SPI_FUNC_SELECT to access SPI registers)
- ar7240_reg_wr(AR7240_SPI_FS, 0x01);
- spi_freq = ahb_freq / (((ar7240_reg_rd(AR7240_SPI_CLOCK) & 0x3F) + 1) * 2);
- ar7240_reg_wr(AR7240_SPI_FS, 0x0);
-
- // make MHz from Hz
- cpu_freq /= 1000000;
- ddr_freq /= 1000000;
- ahb_freq /= 1000000;
- spi_freq /= 1000000;
-
- printf("CLOCKS: %d/%d/%d/%d MHz (CPU/RAM/AHB/SPI)\n", cpu_freq, ddr_freq, ahb_freq, spi_freq);
- puts("\n");
+ bd->bi_flashsize = flash_init();
#if CFG_MONITOR_BASE == CFG_FLASH_BASE
- bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */
+ /* Reserved area for U-Boot */
+ bd->bi_flashoffset = monitor_flash_len;
#else
bd->bi_flashoffset = 0;
#endif
- /* initialize malloc() area */
+ /* Initialize malloc() area */
mem_malloc_init();
malloc_bin_reloc();
- /* relocate environment function pointers etc. */
+ /* Relocate environment function pointers etc. */
env_relocate();
- /* board MAC address */
-#if defined(OFFSET_MAC_ADDRESS)
- memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6);
-
- /*
- * check first LSBit (I/G bit) and second LSBit (U/L bit) in MSByte of vendor part
- * both of them should be 0:
- * I/G bit == 0 -> Individual MAC address (unicast address)
- * U/L bit == 0 -> Burned-In-Address (BIA) MAC address
- */
- if(CHECK_BIT((buffer[0] & 0xFF), 0) != 0 || CHECK_BIT((buffer[0] & 0xFF), 1) != 0){
- // 00-03-7F (Atheros Communications, Inc.)
- bd->bi_enetaddr[0] = 0x00;
- bd->bi_enetaddr[1] = 0x03;
- bd->bi_enetaddr[2] = 0x7f;
- bd->bi_enetaddr[3] = 0x09;
- bd->bi_enetaddr[4] = 0x0b;
- bd->bi_enetaddr[5] = 0xad;
-
- printf("## Error: MAC is invalid, using fixed!\n\n");
- }
-#else
- // fake MAC
- // 00-03-7F (Atheros Communications, Inc.)
- bd->bi_enetaddr[0] = 0x00;
- bd->bi_enetaddr[1] = 0x03;
- bd->bi_enetaddr[2] = 0x7f;
- bd->bi_enetaddr[3] = 0x09;
- bd->bi_enetaddr[4] = 0x0b;
- bd->bi_enetaddr[5] = 0xad;
-
- printf("** Warning: using fixed MAC address!\n\n");
-#endif
-
- /* IP Address */
+ /* Local device IP address */
bd->bi_ip_addr = getenv_IPaddr("ipaddr");
#if defined(CONFIG_PCI)
- /*
- * Do pci configuration
- */
+ /* Do pci configuration */
pci_init();
#endif
- /** leave this here (after malloc(), environment and PCI are working) **/
+ /* Leave this here (after malloc(), environment and PCI are working) */
/* Initialize devices */
devices_init();
/* Initialize the console (after the relocation and devices init) */
console_init_r();
- /** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/
/* Initialize from environment */
- if((s = getenv("loadaddr")) != NULL){
+ if ((s = getenv("loadaddr")) != NULL)
load_addr = simple_strtoul(s, NULL, 16);
- }
#if (CONFIG_COMMANDS & CFG_CMD_NET)
- if((s = getenv("bootfile")) != NULL){
+ if ((s = getenv("bootfile")) != NULL)
copy_filename(BootFile, s, sizeof(BootFile));
- }
-#endif /* CFG_CMD_NET */
+#endif
- /* blink all available LEDs */
- printf("LED on during eth initialization...\n\n");
- all_led_on();
+ /* Init MAC address in board data info */
+ macaddr_init(bd->bi_enetaddr);
+
+ /* Print some information about board */
+ print_board_info();
#if (CONFIG_COMMANDS & CFG_CMD_NET)
+ all_led_on();
eth_initialize(gd->bd);
-#endif
-
all_led_off();
+#endif
- /* main_loop() can return to retry autoboot, if so just run it again. */
- for(;;){
+ /* main_loop() can return to retry autoboot, if so just run it again */
+ for (;;)
main_loop();
- }
/* NOTREACHED - no way out of command loop except booting */
}
-void hang(void){
+void hang(void)
+{
puts("## ERROR ##\n");
- for(;;);
+
+ for (;;)
+ ;
}
#include <common.h>
#include <command.h>
#include <image.h>
-#include <zlib.h>
#include <asm/byteorder.h>
#include <asm/addrspace.h>
+#include <ar7240_soc.h>
//#define DEBUG
-#ifdef CONFIG_AR7240
-#include <ar7240_soc.h>
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
#define LINUX_MAX_ENVS 512 // was 256
void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
//ulong initrd_start = 0, initrd_end = 0;
-#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240)
int flash_size_mbytes;
void(*theKernel)(int, char **, char **, int);
-#else
- void(*theKernel)(int, char **, char **, int *);
-#endif
image_header_t *hdr = &header;
char *commandline = getenv("bootargs");
char env_buf[12];
-#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240)
theKernel = (void (*)(int, char **, char **, int))ntohl(hdr->ih_ep);
-#else
- theKernel = (void (*)(int, char **, char **, int *))ntohl(hdr->ih_ep);
-#endif
#ifdef DEBUG
printf("## Bootargs: %s\n", commandline);
ar7240_reg_wr(AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | 0x88));
#endif
-#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240)
// Pass the flash size as expected by current Linux kernel for AR7100
flash_size_mbytes = gd->bd->bi_flashsize/(1024 * 1024);
theKernel(linux_argc, linux_argv, linux_env, flash_size_mbytes);
-#else
- theKernel(linux_argc, linux_argv, linux_env, 0);
-#endif
}
static void linux_params_init(ulong start, char *line){
linux_argv[linux_argc] = argp;
memcpy(argp, line, next - line);
argp[next - line] = 0;
-#if defined(CONFIG_AR7240)
-#define REVSTR "REVISIONID"
-#define PYTHON "python"
-#define VIRIAN "virian"
- if(strcmp(argp, REVSTR) == 0){
- if(is_ar7241() || is_ar7242()){
- strcpy(argp, VIRIAN);
- } else {
- strcpy(argp, PYTHON);
- }
- }
-#endif
argp += next - line + 1;
linux_argc++;
line = next;
}
-#if defined(CONFIG_AR9100) || defined(CONFIG_AR7240)
/* Add mem size to command line */
if(memstr[0]){
sprintf(memstr, "mem=%luM", gd->ram_size >> 20);
linux_argc++;
argp += strlen(memstr) + 1;
}
-#endif
linux_env = (char **)(((ulong)argp + 15) & ~15);
linux_env[0] = 0;
/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:GPL-2.0
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
-static inline void mips_compare_set(u32 v){
+static inline void mips_compare_set(u32 v)
+{
asm volatile ("mtc0 %0, $11" : : "r" (v));
}
-static inline void mips_count_set(u32 v){
+static inline void mips_count_set(u32 v)
+{
asm volatile ("mtc0 %0, $9" : : "r" (v));
}
-static inline u32 mips_count_get(void){
+static inline u32 mips_count_get(void)
+{
u32 count;
asm volatile ("mfc0 %0, $9" : "=r" (count) :);
- return(count);
+
+ return count;
}
/*
- * timer without interrupts
+ * Timer without interrupts
*/
-int timer_init(void){
+int timer_init(void)
+{
mips_compare_set(0);
mips_count_set(0);
- return(0);
+ return 0;
}
-ulong get_timer(ulong base){
- return(mips_count_get() - base);
+ulong get_timer(ulong base)
+{
+ return mips_count_get() - base;
}
-void udelay(unsigned long usec){
+void udelay(unsigned long usec)
+{
ulong tmo;
ulong start = get_timer(0);
bd_t *bd = gd->bd;
- /*
- * We don't have filled the bd->bi_cfg_hz
- * before relocation to RAM (bd is read only before that),
- */
- if((gd->flags & GD_FLG_RELOC) == 0){
- tmo = usec * (CFG_HZ_FALLBACK / 1000000);
- } else {
- tmo = usec * (CFG_HZ / 1000000);
- }
+ tmo = usec * (CFG_HZ / 1000000);
while ((ulong)((mips_count_get() - start)) < tmo)
- /*NOP*/;
+ /* NOP */;
}
#include <miiphy.h>
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
-extern int ag7240_enet_initialize(bd_t * bis);
+#if defined(CONFIG_ATHEROS)
+ extern int ath_gmac_enet_initialize(bd_t * bis);
+#else
+ extern int ag7240_enet_initialize(bd_t * bis);
+#endif
/*
static struct eth_device *eth_devices, *eth_current;
#endif
// ag7240 initialization
+#if defined(CONFIG_ATHEROS)
+ ath_gmac_enet_initialize(bis);
+#else
ag7240_enet_initialize(bis);
+#endif
if(!eth_devices){
puts("## Error: no ethernet found\n");
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
+#include <tinf.h>
#ifndef __ASSEMBLY__
#define __ASSEMBLY__ /* Dirty trick to get only #defines */
#define ENV_SIZE (CFG_ENV_SIZE - ENV_HEADER_SIZE)
-extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned int);
-
#ifdef ENV_IS_EMBEDDED
extern unsigned int env_size;
extern unsigned char environment;
*dataptr = envptr + ENV_HEADER_SIZE;
unsigned int datasize = ENV_SIZE;
- crc = crc32 (0, dataptr, datasize);
+ crc = tinf_crc32 (dataptr, datasize);
/* Check if verbose mode is activated passing a parameter to the program */
if (argc > 1) {
#include <sys/stat.h>
#include <time.h>
#include <unistd.h>
+#include <tinf.h>
#if defined(__BEOS__) || defined(__NetBSD__) || defined(__APPLE__)
#include <inttypes.h>
char *cmdname;
-extern unsigned long crc32 (unsigned long crc, const char *buf, unsigned int len);
-
typedef struct table_entry {
int val; /* as defined in image.h */
char *sname; /* short (input) name */
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = htonl(0); /* clear for re-calculation */
- if (crc32 (0, data, len) != checksum) {
+ if (tinf_crc32 (data, len) != checksum) {
fprintf (stderr,
"*** Warning: \"%s\" has bad header checksum!\n",
imagefile);
data = (char *)(ptr + sizeof(image_header_t));
len = sbuf.st_size - sizeof(image_header_t) ;
- if (crc32 (0, data, len) != ntohl(hdr->ih_dcrc)) {
+ if (tinf_crc32 (data, len) != ntohl(hdr->ih_dcrc)) {
fprintf (stderr,
"*** Warning: \"%s\" has corrupted data!\n",
imagefile);
hdr = (image_header_t *)ptr;
- checksum = crc32 (0,
+ checksum = tinf_crc32 (
(const char *)(ptr + sizeof(image_header_t)),
sbuf.st_size - sizeof(image_header_t)
);
strncpy((char *)hdr->ih_name, name, IH_NMLEN);
- checksum = crc32(0,(const char *)hdr,sizeof(image_header_t));
+ checksum = tinf_crc32((const char *)hdr,sizeof(image_header_t));
hdr->ih_hcrc = htonl(checksum);
projects / oweals / u-boot_mod.git / commitdiff