sh: Add support SH7710/SH7712

SH7710/SH7712 of SH3 CPU are supported.
SH771X is called SH-Ether, and has the Ether controller in CPU.
The driver of Ether is not included in this patch.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index afba2d21b454ae5b1e9e2c3a9540f783736e7053..00a9b39195184a6f5eb2232235136b1dc3b278b7 100644 (file)
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -30,25 +30,20 @@
 #error "Default SCIF doesn't set....."
 #endif
 
-#if defined(CONFIG_SH3)
-/* There are SH7720's register */
-#define SCSMR  (volatile unsigned short *)(SCIF_BASE + 0x0)
-#define SCBRR  (volatile unsigned char  *)(SCIF_BASE + 0x4)
-#define SCSCR  (volatile unsigned short *)(SCIF_BASE + 0x8)
-#define SCFSR  (volatile unsigned short *)(SCIF_BASE + 0x14)   /* SCSSR */
-#define SCFCR  (volatile unsigned short *)(SCIF_BASE + 0x18)
-#define SCFDR  (volatile unsigned short *)(SCIF_BASE + 0x1C)
-#define SCFTDR (volatile unsigned char  *)(SCIF_BASE + 0x20)
-#define SCFRDR (volatile unsigned char  *)(SCIF_BASE + 0x24)
+/* Base register */
+#define SCSMR  (vu_short *)(SCIF_BASE + 0x0)
+#define SCBRR  (vu_char  *)(SCIF_BASE + 0x4)
+#define SCSCR  (vu_short *)(SCIF_BASE + 0x8)
+#define SCFCR  (vu_short *)(SCIF_BASE + 0x18)
+#define SCFDR  (vu_short *)(SCIF_BASE + 0x1C)
+#ifdef CONFIG_SH7720 /* SH7720 specific */
+#define SCFSR  (vu_short *)(SCIF_BASE + 0x14)   /* SCSSR */
+#define SCFTDR (vu_char  *)(SCIF_BASE + 0x20)
+#define SCFRDR (vu_char  *)(SCIF_BASE + 0x24)
 #else
-#define SCSMR  (vu_short *)(SCIF_BASE + 0x0)
-#define SCBRR  (vu_char  *)(SCIF_BASE + 0x4)
-#define SCSCR  (vu_short *)(SCIF_BASE + 0x8)
 #define SCFTDR         (vu_char  *)(SCIF_BASE + 0xC)
 #define SCFSR  (vu_short *)(SCIF_BASE + 0x10)
 #define SCFRDR         (vu_char  *)(SCIF_BASE + 0x14)
-#define SCFCR  (vu_short *)(SCIF_BASE + 0x18)
-#define SCFDR  (vu_short *)(SCIF_BASE + 0x1C)
 #endif
 
 #if defined(CONFIG_SH4A)
@@ -62,7 +57,11 @@
 #define SCLSR  (vu_short *)(SCIF_BASE + 0x24)
 #define LSR_ORER       1
 #elif defined (CONFIG_SH3)
-#define SCLSR  SCFSR   /* SCSSR */
+#ifdef CONFIG_SH7720 /* SH7720 specific */
+# define SCLSR SCFSR   /* SCSSR */
+#else
+# define SCLSR   (vu_short *)(SCIF_BASE + 0x24)
+#endif
 #define LSR_ORER       0x0200
 #endif
 

diff --git a/include/asm-sh/cpu_sh3.h b/include/asm-sh/cpu_sh3.h
index 68679c0da3df0931a697dd5d89b705c9b819786f..6db38a2f84ed61806e0913211fa3e54fdc9a8c8c 100644 (file)
--- a/include/asm-sh/cpu_sh3.h
+++ b/include/asm-sh/cpu_sh3.h
@@ -31,7 +31,9 @@
 #define CACHE_OC_NUM_ENTRIES   256
 #define CACHE_OC_ENTRY_SHIFT   4
 
-#if defined(CONFIG_CPU_SH7720)
+#if defined(CONFIG_CPU_SH7710)
+#include <asm/cpu_sh7710.h>
+#elif defined(CONFIG_CPU_SH7720)
 #include <asm/cpu_sh7720.h>
 #else
 #error "Unknown SH3 variant"

diff --git a/include/asm-sh/cpu_sh7710.h b/include/asm-sh/cpu_sh7710.h
new file mode 100644 (file)
index 0000000..e223f1c
--- /dev/null
+++ b/include/asm-sh/cpu_sh7710.h
@@ -0,0 +1,64 @@
+#ifndef _ASM_CPU_SH7710_H_
+#define _ASM_CPU_SH7710_H_
+
+#define CACHE_OC_NUM_WAYS      4
+#define CCR_CACHE_INIT 0x0000000D
+
+/* MMU and Cache control */
+#define MMUCR          0xFFFFFFE0
+#define CCR            0xFFFFFFEC
+
+/* PFC */
+#define PACR           0xA4050100
+#define PBCR           0xA4050102
+#define PCCR           0xA4050104
+#define PETCR          0xA4050106
+
+/* Port Data Registers */
+#define PADR           0xA4050120
+#define PBDR           0xA4050122
+#define PCDR           0xA4050124
+
+/* BSC */
+#define CMNCR          0xA4FD0000
+#define CS0BCR         0xA4FD0004
+#define CS2BCR         0xA4FD0008
+#define CS3BCR         0xA4FD000C
+#define CS4BCR         0xA4FD0010
+#define CS5ABCR                0xA4FD0014
+#define CS5BBCR                0xA4FD0018
+#define CS6ABCR                0xA4FD001C
+#define CS6BBCR                0xA4FD0020
+#define CS0WCR         0xA4FD0024
+#define CS2WCR         0xA4FD0028
+#define CS3WCR         0xA4FD002C
+#define CS4WCR         0xA4FD0030
+#define CS5AWCR                0xA4FD0034
+#define CS5BWCR                0xA4FD0038
+#define CS6AWCR                0xA4FD003C
+#define CS6BWCR                0xA4FD0040
+
+/* SDRAM controller */
+#define SDCR           0xA4FD0044
+#define RTCSR          0xA4FD0048
+#define RTCNT          0xA4FD004C
+#define RTCOR          0xA4FD0050
+
+/* SCIF */
+#define SCSMR_0                0xA4400000
+#define SCIF0_BASE     SCSMR_0
+#define SCSMR_0                0xA4410000
+#define SCIF1_BASE     SCSMR_1
+
+/* Timer */
+#define TSTR0          0xA412FE92
+#define TSTR           TSTR0
+#define TCNT0          0xa412FE98
+#define TCR0           0xa412FE9C
+
+/* On chip oscillator circuits */
+#define FRQCR          0xA415FF80
+#define WTCNT          0xA415FF84
+#define WTCSR          0xA415FF86
+
+#endif /* _ASM_CPU_SH7710_H_ */