powerpc/mpc85xx:Add BSC9131 RDB Support
authorPrabhakar Kushwaha <prabhakar@freescale.com>
Tue, 24 Apr 2012 20:17:15 +0000 (20:17 +0000)
committerAndy Fleming <afleming@freescale.com>
Fri, 6 Jul 2012 22:30:29 +0000 (17:30 -0500)
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC
 is an integrated device that targets Femto base station market. It combines
 Power Architecture e500v2 and DSP StarCore SC3850 core technologies with
 MAPLE-B2F baseband acceleration processing elements

  BSC9131RDB Overview
   -----------------
     -1Gbyte DDR3 (on board DDR)
     -128Mbyte 2K page size NAND Flash
     -256 Kbit M24256 I2C EEPROM
     -128 Mbit SPI Flash memory
     -USB-ULPI
     -eTSEC1: Connected to RGMII PHY
     -eTSEC2: Connected to RGMII PHY
     -DUART interface: supports one UARTs up to 115200 bps for console display
Apart from the above it also consists various peripherals to support DSP
functionalities.

This patch adds support for mainly Power side functionalities and peripherals

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
MAINTAINERS
board/freescale/bsc9131rdb/Makefile [new file with mode: 0644]
board/freescale/bsc9131rdb/README [new file with mode: 0644]
board/freescale/bsc9131rdb/bsc9131rdb.c [new file with mode: 0644]
board/freescale/bsc9131rdb/ddr.c [new file with mode: 0644]
board/freescale/bsc9131rdb/law.c [new file with mode: 0644]
board/freescale/bsc9131rdb/tlb.c [new file with mode: 0644]
boards.cfg
include/configs/BSC9131RDB.h [new file with mode: 0644]

index e55893b52ce163edd9afcfe9eefd66f604c39c87..d6e7377e66eb70fa4111e4654cd2b168ed7a4768 100644 (file)
@@ -21,6 +21,8 @@ Poonam Aggrwal <poonam.aggrwal@freescale.com>
 
        P2020RDB        P2020
 
+       BSC9131RDB      BSC9131
+
 Greg Allen <gallen@arlut.utexas.edu>
 
        UTX8245         MPC8245
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
new file mode 100644 (file)
index 0000000..6f4cb26
--- /dev/null
@@ -0,0 +1,53 @@
+#
+# Copyright 2011-2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS-y        += $(BOARD).o
+COBJS-y        += ddr.o
+COBJS-y        += law.o
+COBJS-y        += tlb.o
+#COBJS-y               += bsc9131rdb_mux.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):                $(obj).depend $(OBJS) $(SOBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+clean:
+       rm -f $(OBJS) $(SOBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/bsc9131rdb/README b/board/freescale/bsc9131rdb/README
new file mode 100644 (file)
index 0000000..065faa3
--- /dev/null
@@ -0,0 +1,137 @@
+Overview
+--------
+- BSC9131 is integrated device that targets Femto base station market.
+ It combines Power Architecture e500v2 and DSP StarCore SC3850 core
+ technologies with MAPLE-B2F baseband acceleration processing elements.
+- It's MAPLE disabled personality is called 9231.
+
+The BSC9131 SoC includes the following function and features:
+. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
+  L2 cache
+. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
+. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
+  Processing (MAPLE-B2F)
+. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
+ Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
+ and CRC algorithms
+. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
+ Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
+ operations
+. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
+ ECC, up to 400-MHz clock/800 MHz data rate
+. Dedicated security engine featuring trusted boot
+. DMA controller
+. OCNDMA with four bidirectional channels
+. Interfaces
+. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
+  including IEEE 1588. v2 hardware support and virtualization (eTSEC)
+. eTSEC 1 supports RGMII/RMII
+. eTSEC 2 supports RGMII
+. High-speed USB 2.0 host and device controller with ULPI interface
+. Enhanced secure digital (SD/MMC) host controller (eSDHC)
+. Antenna interface controller (AIC), supporting three industry standard
+  JESD207/three custom ADI RF interfaces (two dual port and one single port)
+  and three MAXIM's MaxPHY serial interfaces
+. ADI lanes support both full duplex FDD support and half duplex TDD support
+. Universal Subscriber Identity Module (USIM) interface that facilitates
+  communication to SIM cards or Eurochip pre-paid phone cards
+. TDM with one TDM port
+. Two DUART, four eSPI, and two I2C controllers
+. Integrated Flash memory controller (IFC)
+. TDM with 256 channels
+. GPIO
+. Sixteen 32-bit timers
+
+The e500 core subsystem within the Power Architecture consists of the following:
+. 32-Kbyte L1 instruction cache
+. 32-Kbyte L1 data cache
+. 256-Kbyte L2 cache/L2 memory/L2 stash
+. programmable interrupt controller (PIC)
+. Debug support
+. Timers
+
+The SC3850 core subsystem consists of the following:
+. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
+. 32 Kbyte 8-way level 1 data cache (L1 DCache)
+. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
+. Memory management unit (MMU)
+. Enhanced programmable interrupt controller (EPIC)
+. Debug and profiling unit (DPU)
+. Two 32-bit timers
+
+BSC9131RDB board Overview
+-------------------------
+ 1Gbyte DDR3 (on board DDR)
+ 128Mbyte 2K page size NAND Flash
+ 256 Kbit M24256 I2C EEPROM
+ 128 Mbit SPI Flash memory
+ USB-ULPI
+ eTSEC1: Connected to RGMII PHY
+ eTSEC2: Connected to RGMII PHY
+ DUART interface: supports one UARTs up to 115200 bps for console display
+ USIM connector
+
+Frequency Combinations Supported
+--------------------------------
+Core MHz/CCB MHz/DDR(MT/s)
+1. 1000/500/800
+2. 800/400/667
+
+Boot Methods Supported
+-----------------------
+1. NAND Flash
+2. SPI Flash
+
+Default Boot Method
+--------------------
+NAND boot
+
+Building U-boot
+--------------
+To build the u-boot for BSC9131RDB:
+1. NAND Flash
+       make BSC9131RDB_NAND
+2. SPI Flash
+       make BSC9131RDB_SPIFLASH
+
+Memory map
+-----------
+ 0x0000_0000   0x7FFF_FFFF     DDR                     1G cacheable
+ 0xA0000000    0xBFFFFFFF      Shared DSP core L2/M2 space     512M
+ 0xC100_0000   0xC13F_FFFF     MAPLE-2F                4M
+ 0xC1F0_0000   0xC1F3_FFFF     PA SRAM Region 0        256K
+ 0xC1F8_0000   0xC1F9_FFFF     PA SRAM Region 1        128K
+ 0xFED0_0000   0xFED0_3FFF     SEC Secured RAM         16K
+ 0xFEE0_0000   0xFEE0_0FFF     DSP Boot ROM            4K
+ 0xFF60_0000   0xFF6F_FFFF     DSP CCSR                1M
+ 0xFF70_0000   0xFF7F_FFFF     PA CCSR                 1M
+ 0xFF80_0000   0xFFFF_FFFF     Boot Page & NAND Buffer 8M
+
+Flashing Images
+---------------
+To place a new u-boot image in the NAND flash and then boot
+with that new image temporarily, use this:
+       tftp 1000000 u-boot-nand.bin
+       nand erase 0 100000
+       nand write 1000000 0 100000
+       reset
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+       dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
+
+Likely, that .dts file will come from here;
+
+       linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
+
+Booting Linux
+-------------
+Place a linux uImage in the TFTP disk area.
+
+       tftp 1000000 uImage
+       tftp 2000000 rootfs.ext2.gz.uboot
+       tftp c00000 bsc9131rdb.dtb
+       bootm 1000000 2000000 c00000
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
new file mode 100644 (file)
index 0000000..2e0e55f
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <netdev.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+       clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
+       setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
+
+       clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
+       setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
+                       MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
+       setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
+       clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
+                       MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
+                       MPC85xx_PMUXCR_IFC_AD_GPIO |
+                       MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       struct cpu_type *cpu;
+
+       cpu = gd->cpu;
+       printf("Board: %sRDB\n", cpu->name);
+
+       return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+       phys_addr_t base;
+       phys_size_t size;
+
+       ft_cpu_setup(blob, bd);
+
+       base = getenv_bootm_low();
+       size = getenv_bootm_size();
+
+       fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+       fdt_fixup_dr_usb(blob, bd);
+}
+#endif
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
new file mode 100644 (file)
index 0000000..c753edf
--- /dev/null
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_DRAM_SIZE   1024
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+       .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+       .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+       .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+       .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+       .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+       .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+       .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+       .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+       .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+       .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+       .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+       .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+       .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+       .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+       .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+       .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+       .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+       .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+       .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+       .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+       .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
+       .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+       .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+       .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+       {750, 850, &ddr_cfg_regs_800},
+       {0, 0, NULL}
+};
+
+unsigned long get_sdram_size(void)
+{
+       return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
+}
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+phys_size_t fixed_sdram(void)
+{
+       int i;
+       char buf[32];
+       fsl_ddr_cfg_regs_t ddr_cfg_regs;
+       phys_size_t ddr_size;
+       ulong ddr_freq, ddr_freq_mhz;
+
+       ddr_freq = get_ddr_freq(0);
+       ddr_freq_mhz = ddr_freq / 1000000;
+
+       printf("Configuring DDR for %s MT/s data rate\n",
+                               strmhz(buf, ddr_freq));
+
+       for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+               if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+                  (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+                       memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
+                                                       sizeof(ddr_cfg_regs));
+                       break;
+               }
+       }
+
+       if (fixed_ddr_parm_0[i].max_freq == 0) {
+               panic("Unsupported DDR data rate %s MT/s data rate\n",
+                                       strmhz(buf, ddr_freq));
+       }
+
+       ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+       fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+       if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
+                                       LAW_TRGT_IF_DDR_1) < 0) {
+               printf("ERROR setting Local Access Windows for DDR\n");
+               return 0;
+       }
+
+       return ddr_size;
+}
+
+#else /* CONFIG_SYS_DDR_RAW_TIMING */
+/* Micron MT41J256M8HX-15E */
+dimm_params_t ddr_raw_timing = {
+       .n_ranks = 1,
+       .rank_density = 1073741824u,
+       .capacity = 1073741824u,
+       .primary_sdram_width = 32,
+       .ec_sdram_width = 0,
+       .registered_dimm = 0,
+       .mirrored_dimm = 0,
+       .n_row_addr = 15,
+       .n_col_addr = 10,
+       .n_banks_per_sdram_device = 8,
+       .edc_config = 0,
+       .burst_lengths_bitmask = 0x0c,
+
+       .tCKmin_X_ps = 1870,
+       .caslat_X = 0x1e << 4,  /* 5,6,7,8 */
+       .tAA_ps = 13125,
+       .tWR_ps = 15000,
+       .tRCD_ps = 13125,
+       .tRRD_ps = 7500,
+       .tRP_ps = 13125,
+       .tRAS_ps = 37500,
+       .tRC_ps = 50625,
+       .tRFC_ps = 160000,
+       .tWTR_ps = 7500,
+       .tRTP_ps = 7500,
+       .refresh_rate_ps = 7800000,
+       .tFAW_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+               unsigned int controller_number,
+               unsigned int dimm_number)
+{
+       const char dimm_model[] = "Fixed DDR on board";
+
+       if ((controller_number == 0) && (dimm_number == 0)) {
+               memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+               memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+               memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+       }
+
+       return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+                               dimm_params_t *pdimm,
+                               unsigned int ctrl_num)
+{
+       int i;
+       popts->clk_adjust = 6;
+       popts->cpo_override = 0x1f;
+       popts->write_data_delay = 2;
+       popts->half_strength_driver_enable = 1;
+       /* Write leveling override */
+       popts->wrlvl_en = 1;
+       popts->wrlvl_override = 1;
+       popts->wrlvl_sample = 0xf;
+       popts->wrlvl_start = 0x8;
+       popts->trwt_override = 1;
+       popts->trwt = 0;
+
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+               popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+       }
+}
+
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c
new file mode 100644 (file)
index 0000000..201c147
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+       SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
new file mode 100644 (file)
index 0000000..5b68f4a
--- /dev/null
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+       /* TLB 0 - for temp stack in cache */
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+                       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+                       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+                       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+
+       /* TLB 1 */
+       /* *I*** - Covers boot page */
+       SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 0, BOOKE_PAGESZ_4K, 1),
+
+       /* *I*G* - CCSRBAR (PA) */
+       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 1, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT)
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 3, BOOKE_PAGESZ_1M, 1)
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
index a723f67eb1432fb02aa14959d8cbede9d07759ab..a6b030fe5bdc2115ae8719e17d86471aeb6c9ce2 100644 (file)
@@ -775,6 +775,7 @@ P5020DS_SECURE_BOOT          powerpc     mpc85xx     corenet_ds          freesca
 P5020DS_SPIFLASH            powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 P5020DS_SRIOBOOT_MASTER                     powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:SRIOBOOT_MASTER
 P5020DS_SRIOBOOT_SLAVE          powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
+BSC9131RDB_SPIFLASH          powerpc     mpc85xx     bsc9131rdb          freescale      -           BSC9131RDB:BSC9131RDB,SPIFLASH
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
new file mode 100644 (file)
index 0000000..fd076e0
--- /dev/null
@@ -0,0 +1,428 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * BSC9131 RDB board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_BSC9131RDB
+#define CONFIG_BSC9131
+#define CONFIG_NAND_FSL_IFC
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE           0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS    0x1107fffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE                   /* BOOKE */
+#define CONFIG_E500                    /* BOOKE e500 family */
+#define CONFIG_MPC85xx         /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/
+#define CONFIG_FSL_IFC                 /* Enable IFC Support */
+
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_TSEC_ENET
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ    66666666 /* DDRCLK on 9131 RDB */
+#define CONFIG_SYS_CLK_FREQ    66666666 /* SYSCLK for 9131 RDB */
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE                        /* toggle L2 cache */
+#define CONFIG_BTB                     /* enable branch predition */
+
+#define CONFIG_SYS_MEMTEST_START       0x01000000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END         0x01ffffff
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#undef CONFIG_SYS_DDR_RAW_TIMING
+#undef CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM         0
+#define SPD_EEPROM_ADDRESS             0x52 /* I2C access */
+
+#define CONFIG_MEM_INIT_VALUE          0xDeadBeef
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_sdram_size(void);
+#endif
+#define CONFIG_SYS_SDRAM_SIZE          get_sdram_size() /* DDR size */
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   1
+
+#define CONFIG_SYS_DDR_CS0_BNDS                0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG      0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2    0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT       0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR       0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR   0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL    0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL      0x89080600
+#define CONFIG_SYS_DDR_SR_CNTR         0x00000000
+#define CONFIG_SYS_DDR_RCW_1           0x00000000
+#define CONFIG_SYS_DDR_RCW_2           0x00000000
+#define CONFIG_SYS_DDR_CONTROL         0xC70C0000      /* Type = DDR3  */
+#define CONFIG_SYS_DDR_CONTROL_2       0x24401000
+#define CONFIG_SYS_DDR_TIMING_4                0x00000001
+#define CONFIG_SYS_DDR_TIMING_5                0x02401400
+
+#define CONFIG_SYS_DDR_TIMING_3_800            0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_800            0x00110104
+#define CONFIG_SYS_DDR_TIMING_1_800            0x6f6b8644
+#define CONFIG_SYS_DDR_TIMING_2_800            0x0fa888cf
+#define CONFIG_SYS_DDR_CLK_CTRL_800            0x03000000
+#define CONFIG_SYS_DDR_MODE_1_800              0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800              0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL_800            0x0c300100
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800       0x8675f608
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR     CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR_DEFAULT
+
+#define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses */
+                                                       /* CONFIG_SYS_IMMR */
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x3FFF_FFFF     DDR                     1G cacheable
+ * 0x8800_0000 0x8810_0000     IFC internal SRAM               1M
+ * 0xC100_0000 0xC13F_FFFF     MAPLE-2F                4M
+ * 0xC1F0_0000 0xC1F3_FFFF     PA L2 SRAM Region 0     256K
+ * 0xC1F8_0000 0xC1F9_FFFF     PA L2 SRAM Region 1     128K
+ * 0xFED0_0000 0xFED0_3FFF     SEC Secured RAM         16K
+ * 0xFF70_0000 0xFF7F_FFFF     PA CCSR                 1M
+ * 0xFF80_0000 0xFFFF_FFFF     Boot Page & NAND flash buffer   8M
+ *
+ */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND Flash on IFC */
+#define CONFIG_SYS_NAND_BASE           0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+                               | CSPR_PORT_SIZE_8      /* Port Size = 8 bit*/ \
+                               | CSPR_MSEL_NAND        /* MSEL = NAND */ \
+                               | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK  IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+                               | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+                               | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+                               | CSOR_NAND_RAL_2       /* RAL = 2Byes */ \
+                               | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
+                               | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
+                               | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
+
+/* NAND Flash Timing Params */
+#define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x08)  \
+                                       | FTIM0_NAND_TWP(0x06)   \
+                                       | FTIM0_NAND_TWCHT(0x03) \
+                                       | FTIM0_NAND_TWH(0x04))
+#define CONFIG_SYS_NAND_FTIM1          (FTIM1_NAND_TADLE(0x18) \
+                                       | FTIM1_NAND_TWBE(0x23) \
+                                       | FTIM1_NAND_TRR(0x08)  \
+                                       | FTIM1_NAND_TRP(0x05))
+#define CONFIG_SYS_NAND_FTIM2          (FTIM2_NAND_TRAD(0x08)  \
+                                       | FTIM2_NAND_TREH(0x04) \
+                                       | FTIM2_NAND_TWHRE(0x3f))
+#define CONFIG_SYS_NAND_FTIM3          FTIM3_NAND_TWW(0x22)
+
+#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+
+#define CONFIG_SYS_NAND_DDR_LAW                11
+
+/* Set up IFC registers for boot location NAND */
+#define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0              CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0               CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0           CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_BOARD_EARLY_INIT_F      /* Call board_pre_init */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR       0xffd00000      /* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_END                0x00004000/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END \
+                                               - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MALLOC_LEN          (1024 * 1024)   /* Reserved for malloc*/
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX      1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         get_bus_freq(0)
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV   /* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE     /* enable fit_format_{error,warning}() */
+
+#define CONFIG_FSL_I2C                 /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C                        /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C                 /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED           400000 /* I2C speed and slave address*/
+#define CONFIG_SYS_I2C_OFFSET          0x3000
+
+/* I2C EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_CMD_I2C
+
+
+#define CONFIG_FSL_ESPI
+/* eSPI - Enhanced SPI */
+#ifdef CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED                10000000
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII                     /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC        1       /* Allow unregistered phys */
+#define CONFIG_TSEC1   1
+#define CONFIG_TSEC1_NAME      "eTSEC1"
+#define CONFIG_TSEC2   1
+#define CONFIG_TSEC2_NAME      "eTSEC2"
+
+#define TSEC1_PHY_ADDR         0
+#define TSEC2_PHY_ADDR         3
+
+#define TSEC1_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX           0
+
+#define TSEC2_PHYIDX           0
+
+#define CONFIG_ETHPRIME                "eTSEC1"
+
+#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS     0
+#define CONFIG_ENV_SPI_CS      0
+#define CONFIG_ENV_SPI_MAX_HZ  10000000
+#define CONFIG_ENV_SPI_MODE    0
+#define CONFIG_ENV_OFFSET      0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE   0x10000
+#define CONFIG_ENV_SIZE                0x2000
+#else
+#define CONFIG_ENV_IS_NOWHERE          /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR                        (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE                        0x2000
+#endif
+#else
+#define CONFIG_ENV_IS_NOWHERE  1       /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE                0x400
+#endif
+
+#define CONFIG_LOADS_ECHO              /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE           /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING                 /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE                   /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "=> "           /* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+                                               /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS     16              /* max number of command args */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ          1000    /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ   (64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE   230400  /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX  2       /* which serial port to use */
+#endif
+
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_HOSTNAME                BSC9131rdb
+#define CONFIG_ROOTPATH                "/opt/nfsroot"
+#define CONFIG_BOOTFILE                "uImage"
+#define CONFIG_UBOOTPATH       "u-boot.bin" /* U-Boot image on TFTP server */
+
+#define CONFIG_BAUDRATE                115200
+
+#define        CONFIG_EXTRA_ENV_SETTINGS                               \
+       "netdev=eth0\0"                                         \
+       "uboot=" CONFIG_UBOOTPATH "\0"                          \
+       "loadaddr=1000000\0"                    \
+       "bootfile=uImage\0"     \
+       "consoledev=ttyS0\0"                            \
+       "ramdiskaddr=2000000\0"                 \
+       "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
+       "fdtaddr=c00000\0"                              \
+       "fdtfile=bsc9131rdb.dtb\0"              \
+       "bdev=sda1\0"   \
+       "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
+       "othbootargs=ramdisk_size=600000 \0" \
+       "usbext2boot=setenv bootargs root=/dev/ram rw " \
+       "console=$consoledev,$baudrate $othbootargs; "  \
+       "usb start;"                    \
+       "ext2load usb 0:4 $loadaddr $bootfile;"         \
+       "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
+       "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
+       "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
+
+#define CONFIG_RAMBOOTCOMMAND          \
+       "setenv bootargs root=/dev/ram rw "     \
+       "console=$consoledev,$baudrate $othbootargs; "  \
+       "tftp $ramdiskaddr $ramdiskfile;"       \
+       "tftp $loadaddr $bootfile;"             \
+       "tftp $fdtaddr $fdtfile;"               \
+       "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif /* __CONFIG_H */