arm64: zynqmp: Make chip_id routine to handle based on el.
authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Tue, 25 Jul 2017 06:21:37 +0000 (11:51 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 2 Aug 2017 07:11:52 +0000 (09:11 +0200)
Modify chip_id() routine such that to handle based on
the current el. Also make it available even if FPGA is
not enabled in system such it can be used always.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/include/asm/arch-zynqmp/hardware.h
board/xilinx/zynqmp/zynqmp.c

index 1228c7acb8c4174ec59f548e219119dd3ecf288f..cab29ba036911ab9d56fd49756fdb99d14777e7d 100644 (file)
@@ -144,4 +144,7 @@ struct pmu_regs {
 
 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
 
+#define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040
+#define ZYNQMP_CSU_VER_ADDR    0xFFCA0044
+
 #endif /* _ASM_ARCH_HARDWARE_H */
index ae69615bfdbb9af352c8d72b6863c0a6052d94bd..07e048681783effe4d789c4f6b46afa961ab489c 100644 (file)
@@ -75,44 +75,65 @@ static const struct {
                .name = "17eg",
        },
 };
+#endif
 
 int chip_id(unsigned char id)
 {
        struct pt_regs regs;
-       regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
-       regs.regs[1] = 0;
-       regs.regs[2] = 0;
-       regs.regs[3] = 0;
        int val = -EINVAL;
 
-       smc_call(&regs);
-
-       /*
-        * SMC returns:
-        * regs[0][31:0]  = status of the operation
-        * regs[0][63:32] = CSU.IDCODE register
-        * regs[1][31:0]  = CSU.version register
-        */
-       switch (id) {
-       case IDCODE:
-               regs.regs[0] = upper_32_bits(regs.regs[0]);
-               regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
-                               ZYNQMP_CSU_IDCODE_SVD_MASK;
-               regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
-               val = regs.regs[0];
-               break;
-       case VERSION:
-               regs.regs[1] = lower_32_bits(regs.regs[1]);
-               regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
-               val = regs.regs[1];
-               break;
-       default:
-               printf("%s, Invalid Req:0x%x\n", __func__, id);
+       if (current_el() != 3) {
+               regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
+               regs.regs[1] = 0;
+               regs.regs[2] = 0;
+               regs.regs[3] = 0;
+
+               smc_call(&regs);
+
+               /*
+                * SMC returns:
+                * regs[0][31:0]  = status of the operation
+                * regs[0][63:32] = CSU.IDCODE register
+                * regs[1][31:0]  = CSU.version register
+                */
+               switch (id) {
+               case IDCODE:
+                       regs.regs[0] = upper_32_bits(regs.regs[0]);
+                       regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
+                                       ZYNQMP_CSU_IDCODE_SVD_MASK;
+                       regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
+                       val = regs.regs[0];
+                       break;
+               case VERSION:
+                       regs.regs[1] = lower_32_bits(regs.regs[1]);
+                       regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
+                       val = regs.regs[1];
+                       break;
+               default:
+                       printf("%s, Invalid Req:0x%x\n", __func__, id);
+               }
+       } else {
+               switch (id) {
+               case IDCODE:
+                       val = readl(ZYNQMP_CSU_IDCODE_ADDR);
+                       val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
+                              ZYNQMP_CSU_IDCODE_SVD_MASK;
+                       val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
+                       break;
+               case VERSION:
+                       val = readl(ZYNQMP_CSU_VER_ADDR);
+                       val &= ZYNQMP_CSU_SILICON_VER_MASK;
+                       break;
+               default:
+                       printf("%s, Invalid Req:0x%x\n", __func__, id);
+               }
        }
 
        return val;
 }
 
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
+       !defined(CONFIG_SPL_BUILD)
 static char *zynqmp_get_silicon_idcode_name(void)
 {
        uint32_t i, id;