*/
#include <asm/arch/omap.h>
+#include <linux/linkage.h>
-.global save_boot_params
-save_boot_params:
+ENTRY(save_boot_params)
/*
* See if the rom code passed pointer is valid:
* It is not valid if it is not in non-secure SRAM
strb r2, [r3, #CH_FLAGS_OFFSET]
1:
bx lr
+ENDPROC(save_boot_params)
-
-.globl lowlevel_init
-lowlevel_init:
+ENTRY(lowlevel_init)
/*
* Setup a temporary stack
*/
*/
bl s_init
pop {ip, pc}
+ENDPROC(lowlevel_init)
-.globl set_pl310_ctrl_reg
-set_pl310_ctrl_reg:
+ENTRY(set_pl310_ctrl_reg)
PUSH {r4-r11, lr} @ save registers - ROM code may pollute
@ our registers
LDR r12, =0x102 @ Set PL310 control register - value in R0
.word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
@ call ROM Code API to set control register
POP {r4-r11, pc}
+ENDPROC(set_pl310_ctrl_reg)
#include <version.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks_omap3.h>
+#include <linux/linkage.h>
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
#ifdef CONFIG_SPL_BUILD
-.global save_boot_params
-save_boot_params:
+ENTRY(save_boot_params)
ldr r4, =omap3_boot_device
ldr r5, [r0, #0x4]
and r5, r5, #0xff
str r5, [r4]
bx lr
+ENDPROC(save_boot_params)
#endif
-.global omap3_gp_romcode_call
-omap3_gp_romcode_call:
+ENTRY(omap3_gp_romcode_call)
PUSH {r4-r12, lr} @ Save all registers from ROM code!
MOV r12, r0 @ Copy the Service ID in R12
MOV r0, r1 @ Copy parameter to R0
.word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
@ because we use -march=armv5
POP {r4-r12, pc}
+ENDPROC(omap3_gp_romcode_call)
/*
* Funtion for making PPA HAL API calls in secure devices
* R0 - Service ID
* R1 - paramer list
*/
-.global do_omap3_emu_romcode_call
-do_omap3_emu_romcode_call:
+ENTRY(do_omap3_emu_romcode_call)
PUSH {r4-r12, lr} @ Save all registers from ROM code!
MOV r12, r0 @ Copy the Secure Service ID in R12
MOV r3, r1 @ Copy the pointer to va_list in R3
.word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
@ because we use -march=armv5
POP {r4-r12, pc}
+ENDPROC(do_omap3_emu_romcode_call)
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
/**************************************************************************
* cpy_clk_code: relocates clock code into SRAM where its safer to execute
* R1 = SRAM destination address.
*************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
+ENTRY(cpy_clk_code)
/* Copy DPLL code into SRAM */
adr r0, go_to_speed /* get addr of clock setting code */
mov r2, #384 /* r2 size to copy (div by 32 bytes) */
cmp r0, r2 /* until source end address [r2] */
bne next2
mov pc, lr /* back to caller */
+ENDPROC(cpy_clk_code)
/* ***************************************************************************
* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
* L3 when its not in self refresh seems bad for it. Normally, this
* code runs from flash before SDR is init so that should be ok.
****************************************************************************/
-.global go_to_speed
- go_to_speed:
+ENTRY(go_to_speed)
stmfd sp!, {r4 - r6}
/* move into fast relock bypass */
nop
ldmfd sp!, {r4 - r6}
mov pc, lr /* back to caller, locked */
+ENDPROC(go_to_speed)
_go_to_speed: .word go_to_speed
#endif
-.globl lowlevel_init
-lowlevel_init:
+ENTRY(lowlevel_init)
ldr sp, SRAM_STACK
str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
/* back to arch calling code */
mov pc, lr
+ENDPROC(lowlevel_init)
/* the literal pools origin */
.ltorg
.word 26000, 432, 12, 9, 16, 9, 4, 3, 1
.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
-.globl get_36x_mpu_dpll_param
-get_36x_mpu_dpll_param:
+ENTRY(get_36x_mpu_dpll_param)
adr r0, mpu_36x_dpll_param
mov pc, lr
+ENDPROC(get_36x_mpu_dpll_param)
-.globl get_36x_iva_dpll_param
-get_36x_iva_dpll_param:
+ENTRY(get_36x_iva_dpll_param)
adr r0, iva_36x_dpll_param
mov pc, lr
+ENDPROC(get_36x_iva_dpll_param)
-.globl get_36x_core_dpll_param
-get_36x_core_dpll_param:
+ENTRY(get_36x_core_dpll_param)
adr r0, core_36x_dpll_param
mov pc, lr
+ENDPROC(get_36x_core_dpll_param)
-.globl get_36x_per_dpll_param
-get_36x_per_dpll_param:
+ENTRY(get_36x_per_dpll_param)
adr r0, per_36x_dpll_param
mov pc, lr
+ENDPROC(get_36x_per_dpll_param)
.align 5
+#include <linux/linkage.h>
+
#ifndef CONFIG_SYS_L2CACHE_OFF
-.global v7_outer_cache_enable
-v7_outer_cache_enable:
+ENTRY(v7_outer_cache_enable)
push {r0, r1, r2, lr}
mrc 15, 0, r3, cr1, cr0, 1
orr r3, r3, #2
mcr 15, 0, r3, cr1, cr0, 1
pop {r1, r2, r3, pc}
+ENDPROC(v7_outer_cache_enable)
-.global v7_outer_cache_disable
-v7_outer_cache_disable:
+ENTRY(v7_outer_cache_disable)
push {r0, r1, r2, lr}
mrc 15, 0, r3, cr1, cr0, 1
bic r3, r3, #2
mcr 15, 0, r3, cr1, cr0, 1
pop {r1, r2, r3, pc}
+ENDPROC(v7_outer_cache_disable)
#endif
#include <config.h>
#include <version.h>
#include <asm/system.h>
+#include <linux/linkage.h>
.globl _start
_start: b reset
* after relocating the monitor code.
*
*/
- .globl relocate_code
-relocate_code:
+ENTRY(relocate_code)
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
_board_init_r_ofs:
.word board_init_r - _start
+ENDPROC(relocate_code)
/*************************************************************************
*
* CONFIG_SYS_ICACHE_OFF is defined.
*
*************************************************************************/
-.globl cpu_init_cp15
-cpu_init_cp15:
+ENTRY(cpu_init_cp15)
/*
* Invalidate L1 I/D
*/
#endif
mcr p15, 0, r0, c1, c0, 0
mov pc, lr @ back to my caller
-
+ENDPROC(cpu_init_cp15)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*************************************************************************
* setup memory timing
*
*************************************************************************/
-cpu_init_crit:
+ENTRY(cpu_init_crit)
/*
* Jump to board specific initialization...
* The Mask ROM will have already initialized
bl lowlevel_init @ go setup pll,mux,memory
mov lr, ip @ restore link
mov pc, lr @ back to my caller
+ENDPROC(cpu_init_crit)
#endif
#ifndef CONFIG_SPL_BUILD
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