arm: socfpga: gen5: add reset & sdr node to SPL devicetrees

The SPL for socfpga gen5 currently takes all peripherals out of reset
unconditionally. To implement proper reset handling for peripherals,
the reset node has to be provided with the SPL dts.

In preparation to move the DDR driver to DM, the sdr node is required
in SPL, too.

This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon
files so that the reset manager and SDR driver correctly probe in SPL.
It centralizes these settings into a common file since in contrast to
boot-type specific nodes, "soc", "rst" and "sdr" are always needed.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
new file mode 100644 (file)
index 0000000..322c858
--- /dev/null
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (c) 2019 Simon Goldschmidt
+ */
+/{
+       soc {
+               u-boot,dm-pre-reloc;
+       };
+};
+
+&rst {
+       u-boot,dm-pre-reloc;
+};
+
+&sdr {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
index e75f2902c54be3f4bfefba01f1d883ee30f526b3..dfaff4c0f7bb8e2a1e20de4ad6aa40b3f8022191 100644 (file)
--- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
@@ -6,15 +6,13 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
        aliases {
                spi0 = "/soc/spi@ff705000";
                udc0 = &usb1;
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &watchdog0 {

diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
index a3870716740f03edc0c1f9ab1667be074e48e34a..6439daa525d9ec4a315fec9b3eaa96d3234380e4 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
@@ -4,6 +4,7 @@
  */
 
 #include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
 
 / {
        model = "Devboards.de DBM-SoC1";
@@ -24,10 +25,6 @@
                device_type = "memory";
                reg = <0x0 0x40000000>; /* 1GB */
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &gmac1 {

diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
index 08d81da16907f18d79b808fe539251442b659329..0219c6948d4f4a600a0756db3b69aa72564d8a13 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
@@ -6,14 +6,12 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
        aliases {
                udc0 = &usb1;
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &watchdog0 {

diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
index e9105743ea039f376a5902f7ce4c7bdb5dbbdd1a..b620dd8dda560823c9a507d652c092844a9d2409 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -6,6 +6,7 @@
  */
 
 #include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
 
 / {
        model = "Terasic DE10-Nano";
@@ -26,10 +27,6 @@
                device_type = "memory";
                reg = <0x0 0x40000000>; /* 1GB */
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &gmac1 {

diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
index 4f076bce93ebd8c1e9b2e71c1bfef312f120516b..ff1e61e0cbe9ed87b1231137deb6595af987ea36 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -4,6 +4,7 @@
  */
 
 #include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
 
 / {
        model = "Terasic DE1-SoC";
@@ -24,10 +25,6 @@
                device_type = "memory";
                reg = <0x0 0x40000000>; /* 1GB */
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &gmac1 {

diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
index 93e4d45ad2b7edb0f67abc67ee92af56e81f9a37..2d314129230cf5e9082ae12eb5891c082c4a8406 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -4,6 +4,7 @@
  */
 
 #include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
 
 / {
        model = "SoCFPGA Cyclone V IS1";
@@ -31,10 +32,6 @@
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &gmac1 {

diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
index 2fafd7e399d3eb86854b645144ff005fd4a3dce0..7d9874cafa0bc63d7c6ebad28fab9d5fceabe199 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
@@ -6,15 +6,13 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
        aliases {
                spi0 = "/soc/spi@ff705000";
                udc0 = &usb1;
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &can0 {

diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
index 7ef30531f4a62687018e1de13d50694d41b8cd2b..85cc396a701586521a9a2e85e52d8bfef848263f 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
@@ -6,15 +6,13 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
        aliases {
                spi0 = "/soc/spi@ff705000";
                udc0 = &usb1;
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &watchdog0 {

diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
index 1003115ceadb8bf3d0c7510ae1b4fce81238e1f8..0a4d54e30479f9f5854a362c3c0f06b2c8d4283c 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
@@ -6,15 +6,13 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
        aliases {
                spi0 = "/soc/spi@ff705000";
                udc0 = &usb1;
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &watchdog0 {

diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
index 1a18c4f3baf6f913193dd5668189e78e2dc08875..bb29da6d6c926c24138bf3aa5b9e69f015a4b288 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -4,6 +4,7 @@
  */
 
 #include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
 
 / {
        model = "SoCFPGA Cyclone V SR1500";
@@ -27,10 +28,6 @@
                device_type = "memory";
                reg = <0x0 0x40000000>; /* 1GB */
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &gmac1 {

diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
index e05ca8279a9eef942e5542827cce5f723e9bea59..db55a4ecadbc8666146c0515630851b09ba36291 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
@@ -6,15 +6,13 @@
  * Copyright (c) 2018 Simon Goldschmidt
  */
 
+#include "socfpga-common-u-boot.dtsi"
+
 /{
        aliases {
                spi0 = "/soc/spi@ff705000";
                udc0 = &usb0;
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &watchdog0 {