Origen: Select SCLKMPLL as FIMD0 parent clock

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
index 0eebbfc24487e349e22a035aa8fe9b3ff6adf914..928320120160a63fc1e18e7cdf0888ad000a1e48 100644 (file)
--- a/board/samsung/origen/lowlevel_init.S
+++ b/board/samsung/origen/lowlevel_init.S
@@ -158,6 +158,11 @@ system_clock_init:
        ldr     r2, =CLK_SRC_PERIL0_OFFSET
        str     r1, [r0, r2]
 
+       /* FIMD0 */
+       ldr     r1, =CLK_SRC_LCD0_VAL
+       ldr     r2, =CLK_SRC_LCD0_OFFSET
+       str     r1, [r0, r2]
+
        /* wait ?us */
        mov     r1, #0x10000
 3:     subs    r1, r1, #1

diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
index d949ad27b848220b341f3c39430eaf7a189e967f..94cccca52c1b0e855f8fe08ea9d14e77b4f14b33 100644 (file)
--- a/board/samsung/origen/origen_setup.h
+++ b/board/samsung/origen/origen_setup.h
@@ -56,6 +56,8 @@
 #define CLK_SRC_PERIL0_OFFSET  0xC250
 #define CLK_DIV_PERIL0_OFFSET  0xC550
 
+#define CLK_SRC_LCD0_OFFSET    0xC234
+
 #define APLL_LOCK_OFFSET       0x14000
 #define MPLL_LOCK_OFFSET       0x14008
 #define APLL_CON0_OFFSET       0x14100
@@ -351,6 +353,16 @@
                                | (UART1_RATIO << 4) \
                                | (UART0_RATIO << 0))
 
+/* CLK_SRC_LCD0 */
+#define FIMD_SEL_SCLKMPLL      6
+#define MDNIE0_SEL_XUSBXTI     1
+#define MDNIE_PWM0_SEL_XUSBXTI 1
+#define MIPI0_SEL_XUSBXTI      1
+#define CLK_SRC_LCD0_VAL       ((MIPI0_SEL_XUSBXTI << 12) \
+                               | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
+                               | (MDNIE0_SEL_XUSBXTI << 4) \
+                               | (FIMD_SEL_SCLKMPLL << 0))
+
 /* Required period to generate a stable clock output */
 /* PLL_LOCK_TIME */
 #define PLL_LOCKTIME           0x1C20