rockchip: rk3036: update clock driver for ddr

After the MASK MACRO update, we need to update the driver at the same time.
This is a fix to:
37943aa rockchip: rk3036: clean mask definition for cru reg

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 1d3fc1a62285007edeb7523ea597e8f3962cd4a3..a06ef7bde0a440987fb4fd671353219776854480 100644 (file)
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -330,29 +330,26 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv)
        struct rk3036_pll *pll = &priv->cru->pll[1];
 
        /* pll enter slow-mode */
-       rk_clrsetreg(&priv->cru->cru_mode_con,
-                    DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+       rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
                     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 
        /* use integer mode */
        rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
 
        rk_clrsetreg(&pll->con0,
-                    PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
+                    PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
                     (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) |
                        dpll_init_cfg.fbdiv);
-       rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
-                       PLL_REFDIV_MASK << PLL_REFDIV_SHIFT,
-                       (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
-                        dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
+       rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
+                    (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
+                     dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
 
        /* waiting for pll lock */
        while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
                rockchip_udelay(1);
 
        /* PLL enter normal-mode */
-       rk_clrsetreg(&priv->cru->cru_mode_con,
-                    DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+       rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
                     DPLL_MODE_NORM << DPLL_MODE_SHIFT);
 }